Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
General Description
Features
The MAX13037/MAX13038 contact monitor and level
shifters monitor and debounce eight remote mechanical
switches and assert an interrupt (INT) if a switch
changes state. The state of each switch is sampled
through an SPI interface by reading the status register.
Any switch can be prohibited from asserting an interrupt
by writing to the command register. Four of the switch
inputs are intended for ground-connected switches
(IN0–IN3) and the other four inputs (IN4–IN7) are programmable in groups of two for either ground-connected or battery-connected switches. Two switch inputs
(IN0, IN1) have direct level-shifted outputs (DO0, DO1)
to be used for PWM or other timing-based signals.
Switch input thresholds are set to 50% of the voltage
applied to BATREF. The threshold hysteresis is set by
connecting an external resistor from HYST to ground.
The MAX13037/MAX13038 supply an adjustable wetting current to each closed switch to clean mechanical
switch contacts that are exposed to adverse conditions.
•
•
•
•
•
The MAX13037/MAX13038 feature a low dropout (LDO)
linear regulator capable of supplying up to 150mA of
current. The MAX13037 LDO has an output voltage of
+5V, whereas the MAX13038 has an output voltage of
+3.3V. The MAX13037/MAX13038 also feature a watchdog timer and an open-drain reset output with
adjustable timing.
The MAX13037/MAX13038 operate with a +6V to +26V
battery voltage applied to BAT. The MAX13037/
MAX13038 are available in a 6mm x 6mm, 36-pin TQFN
package and operate over the automotive -40°C to
+125°C temperature range.
•
•
•
•
•
•
•
•
•
•
+6V to +26V Operating Voltage Range
+42V Compatibility on BAT
Switch Inputs Withstand Reverse Battery
150mA LDO, +5V (MAX13037) or +3.3V (MAX13038)
Ultra-Low Operating Current 28µA (typ) in 64ms
Scan Mode with LDO ON
Resistor Adjustable Switching Hysteresis
Watchdog and Reset
Built-In Switch Debouncing
Interrupt Output
Immunity to Transients
High Modularity
Thermal Protection
±8kV HBM ESD Protection on IN0–IN7 Without
External Components
Two Inputs (IN0, IN1) Programmable as Direct
Outputs
Four Inputs (IN4–IN7) Programmable for BAT or
GND Related Switches
Ordering Information
PART
LDO
OUTPUT
VOLTAGE
TEMP
RANGE
PINPACKAGE
MAX13037ATX+
+5V
-40°C to
+125°C
36 TQFN-EP*
(6mm x 6mm)
MAX13038ATX+
+3.3V
-40°C to
+125°C
36 TQFN-EP*
(6mm x 6mm)
Applications
Body Computers
Window Lifters
Seat Movers
+Denotes a lead(Pb)-free/RoHS-compliant package package.
*EP = Exposed pad.
Electric Sunroofs
Other Control ECUs
Pin Configuration and Typical Application Circuit appear at end of data sheet.
19-1084; Rev 1; 5/15
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Absolute Maximum Ratings
(All voltages referenced to GND, unless otherwise noted.)
VLO ........................................................................-0.3V to +6.0V
BAT.........................................................................-0.3V to +42V
IN_ , BATREF...........................................................-45V to +45V
IN_ to BAT ...............................................................-45V to +45V
SD, REGON. ...........................................................-0.3V to +45V
HYST, WET, TD, TDEB, THRESH, OT, INT, RST......-0.3V to 6.0V
CS, CLK, SDI, SDO, WDI,
DO0, DO1, REGOFF.......................................-0.3V to (VLO + 0.3V)
Continuous Current (CS, CLK, SDI, SDO, WDI, DO0,
DO1, REGOFF) .............................................................±20mA
Continuous Power Dissipation (TA = +70°C)
36-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Package Thermal Characteristics (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (θJA) ...........28°C/W
Junction-to-Case Thermal Resistance (θJC) ...................1.4°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a 4-layer
board. For detailed information on package thermal considerations see www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
(BAT = +6V to +26V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at BAT = +14V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
26
V
POWER SUPPLY
BAT Supply Range
BAT Supply Current with
Regulator On
BAT Supply Current with
Regulator Off
BAT Supply Current in Scan
Mode with Regulator On
VBAT
6
ISUP_REG
VBAT = +14V, continuous scan (SC2 = 1,
SC1 = 1, SC0 = 0), programmable
hysteresis off (M0 = M1 = 1),
IN0–IN7 = unconnected, regulator on
(REGON = REGOFF = GND).
57
110
µA
ISUP
VBAT = +14V, continuous scan (SC2 = 1,
SC1 = 1, SC0 = 0), programmable
hysteresis off (M0 = M1 = 1),
IN0–IN7 = unconnected, regulator off
(REGON = BAT, REGOFF = GND).
46
80
µA
VBAT = +14V, scan mode (SC0 = 0,
ISCAN_REG SC1 = 0, SC2 = 0), regulator on
(REGON = REGOFF = GND).
28
48
µA
17
35
µA
BAT Supply Current in Scan
Mode with Regulator Off
ISCAN
VBAT = +14V, scan mode (SC0 = 0,
SC1 = 0, SC2 = 0), regulator off
(REGON = BAT, REGOFF = GND).
BAT Supply Current in Shutdown
Mode
ISHDN
VSD = 0V, VBAT = +14V,
REGON = BAT
BATREF Input Resistance
RBATREF
VBATREF = +14V
BATREF Input Leakage Current in
Shutdown
IL_BATREF
VSD = 0V, VBATREF = +14V
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TA = +25°C
3
5
TA = +125°C
4
7
1
2.7
µA
MΩ
1
µA
Maxim Integrated | 2
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Electrical Characteristics (continued)
(BAT = +6V to +26V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at BAT = +14V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCH INPUTS (IN0–IN7)
Input Voltage Threshold Center
(Note 3)
Input Voltage Threshold
Hysteresis (Note 4)
VTH_C
VTH_HYS
RHYST = ∞ or programmable hysteresis
disabled
0.425 x
0.5 x
0.575 x
VBATREF VBATREF VBATREF
0.4 x
RHYST = 90kΩ
0.5 x
0.63 x
VBATREF VBATREF VBATREF
RHYST = ∞ or programmable hysteresis
disabled
0.133 x 0.166 x 0.22 x
VBATREF VBATREF VBATREF
RHYST = 90kΩ
0. 26 x 0.361 x 0. 48 x
VBATREF VBATREF VBATREF
Wetting Current Rise/Fall Time
(Note 5)
RSENSE
IWET_RISE_
FALL
11
RWET = 61kΩ
IWET
Rise
6
1
RWET = 30kΩ
VSD = 0V, VIN_ = +14V
ESD Protection IN0–IN7
Human Body Model (HBM)
22
kΩ
µs
22
28
RWET = 330kΩ
IN0–IN7 Input Impedance in
Shutdown
16
Fall
RWET = 61kΩ
Wetting Current
V
0.5 x
VBATREF
RHYST = 0Ω
Switch-State Sense Resistor
V
40
51
mA
7.5
5.5
8.5
MΩ
8
kV
LOGIC-LEVELS (CS, CLK, SDI , SDI, DO0, DO1, INT, OT, RST, SD, REGON, REGOFF)
SDO, DO1, DO2
Output Voltage High
VOH
Source current = 2mA
SDO, DO1, DO2
Output Voltage Low
VOL
Sink current = 4mA
INT, OT, RST Output Voltage Low
VINTL
Sink current = 4mA
SD Input Leakage Current
IL_SD
VSD = VBAT = +14V
SD, REGON Input Voltage Low
VIH_SD
REGON Pullup Current
IREGON
CS, CLK, SDI, REGOFF, WDI
Input Voltage Low
VIL
CS, CLK, SDI, REGOFF, WDI
Input Voltage High
VIH
CS, CLK, WDI, REGOFF Input
Leakage Current
IIL
SDI Pulldown Resistor
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V
0.2 x VLO
VIL_SD
SD, REGON Input Voltage High
INT, OT, RST Leakage Current
0.8 x VLO
0.4
V
1
µA
0.8
V
3.0
µA
2.4
REGON = 0
0.4
V
1
0.33 x VLO
0.66 x VLO
IOL
-1
65
V
V
-1
RSDI
V
+1
100
µA
+1
µA
145
kΩ
Maxim Integrated | 3
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Electrical Characteristics (continued)
(BAT = +6V to +26V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at BAT = +14V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LINEAR REGULATOR
Output Voltage
VLO
MAX13037, VBAT = +14V, ILOAD = 1mA
4.92
5.00
5.08
MAX13038, VBAT = +14V, ILOAD = 1mA
3.234
3.300
3.366
VLO = +5V
(MAX13037)
0.53
1
VLO = +3.3V
(MAX13038)
0.53
1
VLO = +5V
(MAX13037)
1
1.85
VLO = +3.3V
(MAX13038)
1
1.85
ILOAD = 1mA to 50mA,
VBAT = +14V
Load Regulation
LOAD_REG
ILOAD = 1mA to 150mA,
VBAT = +14V
Line Regulation
Dropout Voltage
LINE_REG VBAT = +6V to +26V
VDROP
%
-0.9
+0.9
VLO = +5V, ILO = 50mA (MAX13037)
330
VLO = +5V, ILO = 150mA (MAX13037)
1000
VLO = +3.3V, ILO = 150mA (MAX13038)
Output Current Limit
ILIM
Power-Supply Rejection Ratio
PSRR
Start-Up Time
tSTART
VBAT = +14V
V
mV/V
mV
1300
150
ILO = 10mA, f = 100Hz, 500mVP-P,
AC-coupled into VBAT
mA
68
dB
1
ms
RESET, WATCHDOG
Reset Reference Voltage
VRST
THRESH from high to low
1.20
1.24
1.28
V
THERMAL SHUTDOWN
Thermal Shutdown Temperature
TSHDN
(Note 6)
165
°C
Thermal Shutdown Temperature
for Wetting Currents Only
TWARN
(Note 7)
135
°C
Thermal Shutdown Hysteresis
THYST
15
°C
Timing Characteristics
(BAT = +6V to +26V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at BAT = +14V, TA = +25°C.) (Note 2)
PARAMETER
IN0 to DO0 Propagation Delay,
IN1 to DO1 Propagation Delay
SYMBOL
tPROP
TYP
MAX
VBAT = +6V
CONDITIONS
MIN
22
35
VBAT = +14V
22
µs
CLK Frequency
fCLK
Input rise/fall time < 2ns
Falling Edge of CS to Rising
Edge of CLK
Required Setup Time
tLEAD
Input rise/fall time < 2ns, Figure 1
110
ns
Falling Edge of CLK to Rising
Edge of CS
Required Setup Time
tLAG
Input rise/fall time < 2ns, Figure 1
50
ns
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5
UNITS
MHz
Maxim Integrated | 4
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Timing Characteristics (continued)
(BAT = +6V to +26V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at BAT = +14V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDI to Falling Edge of CLK
Required Setup Time
tSI(SU)
Input rise/fall time < 2ns, Figure 1
30
ns
Falling Edge of CLK to SDI
Required Hold Time
tSI(HOLD)
Input rise/fall time < 2ns, Figure 1
20
ns
Time from Falling Edge of CS to
SDO Low Impedance
tSO(EN)
Input rise/fall time < 2ns, Figure 1
55
ns
Time from Rising Edge of CS to
SDO High Impedance
tSO(DIS)
Figures 1 and 2
55
ns
Time from Rising Edge of CLK to
SDO Data Valid
tVALID
CSDO =15pF, Figure 1
70
ms
Debounce Time
tDEB
Scanning Time Pulse
tSCAN
Scanning Time Period
tSCAN-P
Wetting Time Pulse
tWETT
CTDEB = 500pF
CTDEB = 10nF
3.18
5.9
9.42
ms
63
120
188
ms
130
250
400
µs
SC0 = 0, SC1 = 1, SC2 = 1
4
8
14
ms
WTOFF = 0
10
21
35
ms
tSD
SD low-to-high transition to input monitoring
enabled
200
µs
Time from SCAN Mode to Normal
Operation
tSM
(Note 8)
500
µs
Reset Output Pulse Width
tRST
CTD = 10nF (Figure 3)
10
21
36
ms
Watchdog Timeout Period 1
tWD1
CTD = 10nF, time before INT goes low
(Figure 3)
40
84
144
ms
Watchdog Timeout Period 2
tWD2
CTD = 10nF, time before RST goes low
(Figure 3)
Minimum Watchdog Timeout
Reset on WDI
tWDI
Time from Shutdown to Normal
Operation
2 x tWD1
300
ms
ns
Note 2: All units are 100% production tested at TA = 125°C. Limits over the operating temperature range are guaranteed by design and
not production tested.
Note 3: VTH_C = (VTH_HIGH + VTH_LOW) / 2.
Note 4: VTH_HYS = (VTH_HIGH - VTH_LOW).
Note 5: Wetting current rise/fall time is measured as the time it takes to go from 20% to 80% of the maximum wetting current.
Note 6: TSHDN is the temperature at which the wetting currents and LDO are disabled.
Note 7: TWARN is the temperature at which only the wetting currents are disabled.
Note 8: When exiting SCAN mode to enter Normal Mode (through SPI) any input change is ignored for 500µs (typ) to allow correct
wake-up of input comparators. After this time elapses, the inputs are monitored in continuous mode.
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Maxim Integrated | 5
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
CS
tLEAD
tLAG
CLK
tSI(SU)
SDI
tSI(HOLD)
MSB IN
tSO(EN)
tSO(DIS)
tVALID
MSB OUT
SDO
LSB OUT
Figure 1. SPI Timing Characteristics
VL
CS
1kΩ
CS
MAX13037
MAX13038
tSO(EN)
tSO(DIS)
SDO
15pF
SDO
1/3VL
VOL + 0.1VL
Figure 2. SDO Enable/Disable Test Circuit and Timing Diagram
WDI
tWD1
tWD1
INT
RST
NORMAL OPERATION
(NO SWITCHES ACTIVE)
tWD2
tRST
Figure 3. Watchdog Interrupt/Reset Timing Diagram
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Maxim Integrated | 6
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Typical Operating Characteristics
(BAT = +14V, SD = VBAT, RWET = 61kΩ, RHYST = 90kΩ, CTDEB = 4700pF, CTD = 4700pF, TA = +25°C, unless otherwise noted.)
10
GND-CONNECTED SWITCH
0
-10
BAT-CONNECTED SWITCH
MAX13037/8toc02
40
30
GND-CONNECTED SWITCH
20
10
INT
2V/div
0
-10
-20
BAT-CONNECTED SWITCH
IIN_
20mA/div
-30
-20
-40
-30
-50
14
18
22
130
180
230
280
RWET (kΩ)
BAT CURRENT vs. TEMPERATURE
(NORMAL MODE)
BAT CURRENT vs. TEMPERATURE
(NORMAL MODE)
SD = LOW
7
6
70
5
IBAT (μA)
80
60
ADJUSTABLE HYSTERESIS OFF
BAT CURRENT vs. TEMPERATURE
(SCANNING MODE)
4
40
3
30
2
20ms/div
45
LDO = ON
SCANNING PERIOD = 2ms
40
IBAT (μA)
ADJUSTABLE HYSTERESIS ON
8
330
MAX13037/8toc05
100
50
80
VBAT (V)
110
35
SCANNING PERIOD = 64ms
30
25
20
1
10
0
0
20
-40 -25 -10 5
-40 -25 -10 5 20 35 50 65 80 95 110 125
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TYPICAL IN0 DRIVING
(NORMAL MODE, WTOFF = WEN = WEND = 0)
TYPICAL IN0 DRIVING
(NORMAL MODE, WTOFF = WEN = WEND = 0)
MAX13037/8toc07
TEMPERATURE (°C)
f = 5kHz
VIN0
5V/div
TEMPERATURE (°C)
HYSTERESIS vs. RHYST
8
ADJUSTABLE HYSTERESIS ON
7
6
HYSTERESIS (V)
VIN0
5V/div
f = 100Hz
ADJUSTABLE HYSTERESIS OFF
-40 -25 -10 5 20 35 50 65 80 95 110 125
MAX13037/8 toc08
IBAT (μA)
30
26
MAX13037/8toc06
10
MAX13037/8toc04
6
90
VIN_
10V/div
VDO0
2V/div
VDO0
2V/div
MAX13037/8toc09
WETTING CURRENT (mA)
20
50
WETTING CURRENT (mA)
MAX13037/8toc01
30
WETTING CURRENT PULSE (NORMAL MODE,
WTOFF = 0, WEN = WEND = 1)
WETTING CURRENT vs. RWET
MAX13037/8toc03
WETTING CURRENT vs. VBAT
5
4
3
2
1
40μs/div
2ms/div
0
0
200
400
600
800
1000
RHYST (kΩ)
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Maxim Integrated | 7
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Typical Operating Characteristics (continued)
(BAT = +14V, SD = VBAT, RWET = 61kΩ, RHYST = 90kΩ, CTDEB = 4700pF, CTD = 4700pF, TA = +25°C, unless otherwise noted.)
8
VIN_ RISING
7
VIN_ FALLING
6
ADJUSTABLE HYSTERESIS OFF
15
SCANNING PERIOD = 2ms
INPUT SWITCH OPEN
VIN_
5V/div
VIN_ RISING
10
5
VIN_ FALLING
0
5
6
-40 -25 -10 5 20 35 50 65 80 95 110 125
10
14
400μs/div
DEBOUNCE TIME vs. CTDEB
DEBOUNCE TIME vs. BAT VOLTAGE
54
52
50
48
46
MAX13037/8toc14
120
50
100
DEBOUNCE TIME (ms)
DEBOUNCE TIME (ms)
56
26
51
MAX13037/8toc13
58
22
49
MAX13037/8toc15
DEBOUNCE TIME vs. TEMPERATURE
60
18
VBAT (V)
TEMPERATURE (°C)
DEBOUNCE TIME (ms)
MAX13037/8toc12
9
20
MAX13037/8toc11
SWITCHING THRESHOLD (V)
ADJUSTABLE HYSTERESIS OFF
SWITCHING THRESHOLD (V)
MAX13037/8toc10
10
INPUT WAVEFORM IN SCAN MODE
(SCAN MODE, WTOFF = WEN = 0, WEND = 1)
SWITCHING THRESHOLD vs. VBAT
SWITCHING THRESHOLD vs. TEMPERATURE
80
60
40
48
44
20
42
40
0
47
-40 -25 -10 5 20 35 50 65 80 95 110 125
6
10
14
0
26
2000
4000
VLO OUTPUT VOLTAGE vs. TEMPERATURE
4.5
4.0
8000
10,000
VLO OUTPUT VOLTAGE vs. LOAD CURRENT
5.5
5.0
VLO OUTPUT VOLTAGE (V)
MAX13037/8toc16
5.0
6000
CTDEB (pF)
VBAT (V)
5.5
VLO OUTPUT VOLTAGE (V)
22
MAX13037/8toc17
TEMPERATURE (°C)
18
4.5
MAX13037
4.0
3.5
3.0
MAX13038
3.5
2.5
2.0
3.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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0
50
100
150
200
LOAD CURRENT (mA)
Maxim Integrated | 8
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Typical Operating Characteristics (continued)
(BAT = +14V, SD = VBAT, RWET = 61kΩ, RHYST = 90kΩ, CTDEB = 4700pF, CTD = 4700pF, TA = +25°C, unless otherwise noted.)
WATCHDOG INTERRUPT AND RESET
PERIOD vs. TEMPERATURE
VLO
-COUPLED)
50mV/div
125
PERIOD (ms)
90
PERIOD (ms)
ILO
50mA/div
150
MAX13037/8toc19
MAX13037/8toc18
100
WATCHDOG INTERRUPT AND RESET
PERIOD vs. CTD
80
70
MAX13037/8toc20
VLO TRANSIENT LOAD REGULATION
100
75
50
60
25
50
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
1ms/div
0
2000
TEMPERATURE (°C)
4000
6000
8000
10,000
CTD (pF)
Pin Description
PIN
NAME
1, 15, 31
GND
2
IN0
Switch Input Channel 0. Connect IN0 to a switch connected to GND. IN0 can be programmed as a
direct input with a level-shifted output on DO0 (see the Mechanical Switch Inputs (IN0–IN7) section).
3
IN1
Switch Input Channel 1. Connect IN1 to a switch connected to GND. IN1 can be programmed as a
direct input with a level-shifted output on DO1 (see the Mechanical Switch Inputs (IN0–IN7) section).
4
IN2
Switch Input Channel 2. Connect IN2 to a switch connected to GND.
5
IN3
Switch Input Channel 3. Connect IN3 to a switch connected to GND.
6
IN4
Switch Input Channel 4. Connect IN4 to a switch connected to GND or BAT.
7
IN5
Switch Input Channel 5. Connect IN5 to a switch connected to GND or BAT.
8
IN6
Switch Input Channel 6. Connect IN6 to a switch connected to GND or BAT.
9
IN7
Switch Input Channel 7. Connect IN7 to a switch connected to GND or BAT.
10, 11, 34
N.C.
No Connection. Not internally connected.
12
HYST
Hysteresis Input. Connect HYST to GND with a 0Ω to 900kΩ resistor to set the input voltage
hysteresis on IN0–IN7.
13
WET
Wetting Current Input. Connect a 30kΩ to 330kΩ resistor from WET to GND to set the wetting current
on IN0–IN7.
14
TDEB
Switch Debounce Time Input. Connect a 500pF to 10nF capacitor from TDEB to GND to set the
switch debounce time.
16
OT
Overtemperature Warning Output. OT is an open-drain output that asserts low when the thermal
warning threshold is exceeded.
17
INT
Interrupt Output. INT is an open-drain output that asserts low when one or more of the IN0–IN7 inputs
change state and are enabled for interrupts or when the watchdog times out.
18
TD
Reset and Watchdog Timeout Input. Connect TD to GND with a 500pF to 10nF capacitor to set the
timeout period for the reset and watchdog.
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FUNCTION
Ground
Maxim Integrated | 9
MAX13037/MAX13038
Contact Monitor and Level
Shifters with LDO Regulator
Pin Description (continued)
PIN
NAME
19
SD
Shutdown Input. Drive SD low to place the MAX13037/MAX13038 into shutdown mode and disable
the linear regulator. Drive SD high for normal operation. SD is compatible with voltages up to VBAT.
20
REGON
Linear Regulator Enable Input (Active Low). Connect REGON to INT to enable a wake-up when a
switch status change is detected. Drive REGON using an open-drain logic output to control the
regulator directly. REGON is internally pulled up to an internal bias voltage of approximately +4.8V.
21
REGOFF
Linear Regulator Disable Input (Active Low). REGOFF is used in conjunction with REGON when the
internal regulator is enabled by an interrupt (see the Low-Dropout Linear Regulator (VLO) section).
22
CS
SPI Chip-Select Input. Drive CS low to enable the clocking of data into and out of the
MAX13037/MAX13038. SPI data is latched into the MAX13037/MAX13038 on the rising edge of CS.
23
SDO
SPI Serial-Data Output. SPI data is output on SDO on the rising edges of CLK while CS is held low.
SDO is three-state when CS is high.
24
SDI
SPI Serial-Data Input. SPI data is latched into the internal shift register on the falling edges of CLK
while CS is held low. SDI has an internal 100kΩ pulldown resistor.
25
CLK
SPI Serial-Clock Input
26
RST
Reset Output. RST is an open-drain output that asserts low when VLO is below the threshold
determined by the THRESH input. RST also asserts low when the watchdog times out.
27
DO1
Data Output Channel 1. DO1 is the level-shifted output of IN1 when WEND = 0.
28
DO0
Data Output Channel 0. DO0 is the level-shifted output of IN0 when WEND = 0.
29
THRESH
30
WDI
32
BATREF
Battery Reference Input. Switch thresholds are set to 50% of the voltage applied to BATREF. Connect
BATREF to the system’s battery supply voltage.
33
VLO
Linear Regulator Output. VLO is the output of an internal linear regulator and is the reference voltage
for all digital I/O. Bypass VLO with a 2.2µF or greater ceramic capacitor. Alternatively, a 10µF
electrolytic capacitor can be used in parallel with a 0.1µF ceramic capacitor.
35, 36
BAT
Battery Supply Input. Connect BAT to a positive +6V to +26V battery supply voltage. Bypass BAT to
ground with a 0.1µF ceramic capacitor and a 10µF electrolytic capacitor placed as close as possible
to BAT.
—
EP
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FUNCTION
Reset Threshold Level Input. Connect THRESH to a resistor divider between VLO and GND to set the
reset reference level.
Watchdog Timer Input. The watchdog timer is reset at every transition on the WDI input.
Exposed Paddle. Connect EP to GND.
Maxim Integrated | 10
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Functional Diagram
SD
BAT
LINEAR
REGULATOR
MAX13037
MAX13038
VLO
WDI
RESET +
WATCHDOG
REGON
REGOFF
THRESH
TD
WAKE-UP
LOGIC
DO0
DO1
BATREF
DIGITAL
INTERFACE
CS
IN0
SPI
INTERFACE
IN1
IN2
IN3
IN4
WETTING
CURRENT
CONTROL
LEVEL
TRANSLATORS
SDI
SDO
SHIFT
REGISTER
IN5
INT
INTERRUPT
LOGIC
IN6
IN7
RST
OT
WET
HYST
TDEB
Detailed Description
The MAX13037/MAX13038 contact monitor and level
shifters monitor and debounce eight remote mechanical switches and assert an interrupt (INT) if a switch
changes state. Any of the switch inputs can be prohibited from asserting an interrupt. The switch threshold levels are set to 50% of the voltage applied to BATREF
and all switch inputs feature a common adjustable hysteresis, debounce time, and wetting current. Two
switch inputs (IN0, IN1) are programmable to have
direct outputs (DO0, DO1), useable for PWM or other
timing-based signals.
The MAX13037/MAX13038 feature an SPI interface to
monitor individual switch inputs and to configure interrupt masking, hysteresis, and wetting current
enable/disable, switch configuration (batteryconnected or ground-connected), and scanning period.
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CLK
GND
The MAX13037/MAX13038 provide an internal low
dropout (LDO) linear regulator capable of supplying up
to 150mA. The LDO can be enabled or disabled
through two digital control inputs: REGON and REGOFF.
A watchdog timer and power-on reset circuitry is provided on the MAX13037/MAX13038 to supervise external
microcontrollers (µC).
The MAX13037/MAX13038 feature three modes of
operation: normal mode, scanning mode, and shutdown mode. In normal mode, the part is fully functional
and internal sensing resistors are connected to all
switch inputs. In scanning mode, the sensing resistors
are connected for a finite duration to reduce power
consumption. In shutdown mode, all switch inputs are
high impedance and the internal LDO is switched off to
further reduce power consumption.
Maxim Integrated | 11
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
BAT
Linear Regulator Wake-Up
BAT is the main power-supply input. Bypass BAT to
ground with a 0.1µF ceramic capacitor placed as close
as possible to BAT. In addition, bypass BAT with a
10µF or greater capacitor. BAT can withstand DC voltages up to +42V.
Low-Dropout Linear Regulator (VLO)
The MAX13037/MAX13038 contain an internal LDO linear regulator supplied by the BAT input. The LDO output voltage is present on V LO and is capable of
supplying up to 150mA of current. The MAX13037 output voltage is set to +5V and the MAX13038 output
voltage is set to +3.3V.
The LDO regulator is controlled through the REGON
and REGOFF inputs as shown in Figure 4. REGON is
an input able to withstand voltages up to VBAT. The
LDO startup time is 1ms (typ).
There are two options for controlling the linear regulator:
• Wake-Up on Interrupt: In this case, REGON is connected to INT and when the MAX13037/MAX13038
generate an interrupt, the linear regulator is turned
on, thus providing power to the local µCs. The µC
pulls REGOFF high to keep the regulator on before
making an SPI read (which causes INT and REGON
to go high). The linear regulator can then be turned
off by pulling REGOFF low.
• Direct Control: In this case, the regulator is
enabled/disabled by some other signal in the system which must be connected to REGON. If
REGOFF is not used, it must be connected to GND
to allow the turnoff of the LDO.
REGOFF = 1
LDO ON
REGON = 0
REGOFF = 0
REGON = 1
REGOFF = 0
REGON = 0
LDO ON
REGON = 0
REGOFF = 1
REGON = 0
REGON = 1
Regulator wake-up can be controlled with the INT output by connecting it to REGON. REGON is a TTL input
with an internal pullup to a low-voltage internal reference of +4.8V (typ). With this control scheme, any
change of the input switches (enabled for interrupt generation) causes the regulator to turn on, thus providing
power to any external circuitry connected to VLO. If an
external microcontroller is supplied from V LO , the
microcontroller can keep the LDO on by forcing
REGOFF high. Reading from the MAX13037/MAX13038
over the SPI interface causes the INT output to go into
high-impedance so that both INT and REGON are
pulled high. After this phase, the microcontroller can
turn off the regulator again by driving REGOFF low.
Note that it is also possible to tie multiple open-drain
active-low outputs in an ORing configuration, allowing
the wakeup of the regulator from other devices.
If the INT output is not used to control the regulator,
connect the REGOFF input to ground and use REGON
to enable or disable the regulator as shown in Figure 4.
Watchdog Timer (WDI)
The MAX13037/MAX13038 feature a watchdog timer
that is reset on every transition on the WDI input. If
there is no transition on WDI before the first timeout
period (tWD1) the INT output asserts low. If there is still
no transition on WDI after the second timeout period
(tWD2), the RST output is pulsed low for tRST and the
INT output deasserts (see Figure 3). The watchdog
timeout period can be adjusted by changing the
capacitor value on the TD input.
tRST (ms) = 2 x CTD (nF)
tWD1 = 4 x tRST (ms)
tWD2 = 8 x tRST (ms)
Note that WDI can be tied to the CS input to allow a
watchdog reset for every read/write operation over the
SPI interface. To avoid any corruption of the internal
command register, it is necessary to transmit the full programming word (16 bits) for every CS negative pulse.
Reset Output (R S T)
LDO OFF
REGON = 1
REGOFF = 0
LDO ON
REGOFF = 0
REGOFF = 1 IS NOT ALLOWED
BECAUSE VLO IS ABSENT.
REGON = 1
REGOFF = 1
The RST output asserts low when a watchdog timeout
occurs or when the LDO output voltage drops below a
certain threshold. The threshold voltage is set by connecting an external voltage divider on the THRESH
input between VLO and GND. The voltage on THRESH
is compared with an internal reference voltage of
+1.24V and if it is lower, the RST output asserts low
for tRST and remains low if VLO does not rise above
the threshold.
Figure 4. Linear Regulator State Diagram
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Maxim Integrated | 12
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Mechanical Switch Inputs (IN0–IN7)
IN0–IN7 are the inputs for remote mechanical switches.
The status of each switch input is indicated by the SW0
through SW7 bits in the status register, and each switch
input can be programmed to not assert an interrupt
(INT) by writing to the P0–P7 bits in the command register. All switch inputs are configured to assert an interrupt upon power-up.
The first four inputs (IN0–IN3) are intended for groundconnected switches. The remaining four inputs (IN4–IN7)
can be programmed in sets of two for either ground-connected or battery-connected switches by writing to the
M0 and M1 bits (see Table 5). The default state after
power-up is IN2–IN7 configured for ground-connected
switches, and IN0/IN1 configured for direct inputs.
All switch inputs have internal 16kΩ sense resistors to
detect switch transitions. Inputs configured for groundconnected switches are pulled up to BAT and inputs configured for battery-connected switches are pulled down to
GND. Figure 5 shows the switch input structure for IN0
and IN1. IN0 and IN1 can be programmed as direct
inputs with level-shifted outputs (DO0 and DO1) by clearing the WEND bit in the command register (normal mode
only). When programmed as direct inputs, IN0 and IN1
can be used for PWM or other signaling. Clearing the
WEND bit disables the sense resistors and wetting currents on IN0 and IN1. When programmed as direct inputs,
the status of IN0 and IN1 is not reflected in the status register, and interrupts are not allowed on these inputs.
VBAT
MAX13037
MAX13038
Switch Threshold Levels and
Hysteresis (BATREF, HYST)
Input thresholds for the remote switches are 50% of the
voltage applied to BATREF. The BATREF input is typically connected to the battery voltage before the reversebattery protection diode. The MAX13037/MAX13038
feature adjustable hysteresis on the switch inputs by
connecting an external 0 to 900kΩ resistor from HYST to
ground (normal mode only). Short HYST to ground to
obtain the maximum hysteresis of (0.5 x VBATREF). The
approximate formula for hysteresis is given below:
⎡
⎤
43
VHYST = ⎢0.166 +
⎥ (VBATREF )
(123 + (RHYST(kΩ) ) ⎥⎦
⎢⎣
To reduce power consumption, the adjustable hysteresis can be disabled by setting [SC2:SC1:SC0 = 1:1:0]
in the command register. When the adjustable hysteresis is disabled, the hysteresis is set to 0.166 x VBATREF.
Switch Debounce and Deglitch
The switch inputs IN0–IN7 share a common programmable debounce timer to increase the noise immunity
of the system in normal and scan mode. The switch
debounce time is set by connecting a capacitor
between the t DEB input and ground. The minimum
value of this capacitor is 500pF and the maximum value
is 10nF, corresponding to a debounce time of 5ms to
100ms respectively. To calculate other debounce times
the following formula should be used:
C(nF) = tDEB(ms) / 10
All switch input glitches of less than 20µs in duration are
automatically rejected by the MAX13037/MAX13038.
Debounce in Normal Mode
CONTROL
LOGIC
WETTING*
CURRENT
16kΩ*
IN0, IN1
NOTES:
*WETTING CURRENT AND PULLUP/DOWN RESISTORS ARE
CONTROLLED BY THE WEN AND WEND BITS IN THE COMMAND
REGISTER (SEE TABLE 4).
Figure 5. Input Structure of IN0 and IN1
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When a change of state occurs at the switch input the
debounce timer starts. If the new state is stable for at least
tDEB, the status register is updated and an interrupt is
generated (if enabled). If the input returns to its previous
state before the debounce time has elapsed, an interrupt
is not generated and the status register is not updated.
Debounce in Scan Mode
A change of state at the switch input causes the device to
automatically enter normal mode and the debounce timing
to start. The device remains in normal mode as long as the
input state differs from the previous state. As soon as the
debounce time ends, the status register is updated, an
interrupt is generated, and the device re-enters scan mode.
If the input returns to its previous state before the end
of the debounce time, the device re-enters scan mode,
an interrupt is not generated, and the status register is
not updated.
Maxim Integrated | 13
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Wetting Current (WET)
The MAX13037/MAX13038 feature adjustable wetting
current to any closed switch to clean switch contacts
that are exposed to adverse conditions. The wetting
current is set by connecting a 30kΩ to 330kΩ resistor
from WET to ground. A 30kΩ resistor corresponds to a
wetting current of 40mA (typ) and a 330kΩ resistor corresponds to a 4mA (typ) wetting current. See the
Typical Operating Characteristics section for the relationship between the wetting current and RWET.
The WEN and WEND bits in the command register
enable and disable the wetting currents and the
WTOFF bit allows the wetting current to be activated for
a duration of 20ms (typ) (see the Command Register
section). Disabling wetting currents, or limiting the
active wetting current time reduces power consumption. The default state upon power-up is all wetting currents disabled.
Wetting current is activated on closed switches just
after the debounce time. The wetting current pulse
starts after the debounce time. A wetting current pulse
is provided to all closed switches when a valid input
change is detected. Wetting current rise and fall times
are controlled to enhance EMC performance. There is
one wetting current timer for all switch inputs.
Therefore, it is possible to observe wetting pulses
longer than expected whenever two switches turn on in
sequence and are spaced out less than tWET. In scan
mode, the wetting current is enabled during the polling
pulse only.
When using wetting currents, special care must be
taken to avoid exceeding the maximum power dissipation of the MAX13037/MAX13038 (see the Applications
Information section).
Switch Outputs (DO0, DO1)
DO0 and DO1 are direct level-shifted outputs of the
switch inputs IN0 and IN1 when the WEND bit of the
command register is cleared and when operating in
normal mode. When configured as direct inputs, the
wetting currents and sensing resistors are disabled on
IN0 and IN1. DO0 and DO1 are three-stated when the
WEND bit is set or when operating in scan mode.
asserts when the first watchdog timeout period elapses
(tWD1). A pullup resistor to VLO is needed on INT. INT is
cleared when CS is driven low for a read/write operation.
The INT output still asserts when VLO is disabled provided that it is pulled up to a different supply voltage.
Thermal Protection (O T)
The MAX13037/MAX13038 feature a two-level thermal
protection strategy that prevents the device from being
damaged by overheating. At the initial warning temperature of +135°C (typ), only wetting currents are disabled. The MAX13037/MAX13038 return to normal
operation after the internal temperature decreases
below +120°C (typ). This protection feature is disabled
when WEN = 0 or when all inputs are open. At the second thermal warning temperature of +170°C (typ), the
LDO is shut down. Because a µC is often supplied by
the LDO, an overheating event caused by excessive
power dissipation related to I/O wetting currents is normally resolved without affecting the µC status.
An open-drain, active-low output (OT) asserts low when
the internal temperature of the device rises above the
thermal warning threshold. OT is immediately cleared
when the CS input is driven low for read/write operations, regardless of whether the temperature is above
the threshold, or not. The overtemperature status of the
MAX13037/MAX13038 can also be monitored by reading the OT bit in the status register. The OT bit is set
when the internal temperature rises above the temperature threshold, and it is cleared when the temperature
falls below the temperature hysteresis level. This allows
a µC to monitor the overtemperature status, even if the
OT output has been cleared. See Figure 6 for an example timing diagram of the overtemperature alerts.
If desired, the OT and INT outputs can be connected
to the same µC GPIO in a wired-OR configuration to
save a µC pin. The OT output still asserts when VL is
absent provided that it is pulled up to a different supply voltage.
TEMPERATURE
When programmed as direct inputs, the status of IN0
and IN1 are not reflected in the status register and
interrupts are not allowed on these inputs.
OT
Interrupt Output (I N T)
CS
INT is an active-low, open-drain output that asserts
when any of the switch inputs change state, as long as
the particular input is enabled for interrupts (set by
clearing P7–P0 in the command register). INT also
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OT BIT
Figure 6. Example Timing Diagram of the Overtemperature Alerts
Maxim Integrated | 14
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
STATUS REGISTER
IS COPIED TO
SHIFT REGISTER
SHIFT REGISTER IS
COPIED TO COMMAND
REGISTER
CS
15
CLK
SDI
14
WTOFF SC2
SW7
SDO
SW6
13
12
SC1
SC0
SW5
11
10
WEN WEND
SW4
SW3
9
8
7
6
5
4
3
2
1
0
M1
M0
P7
P6
P5
P4
P3
P2
P1
P0
SW2
SW1
SW0
OT
*
*
*
*
*
*
*
* = UNUSED.
Figure 7. SPI Read/Write Example
Status Register
Serial Peripheral Interface
(C S, SD0, SDI, CLK)
The status register contains the status of the switches
connected to IN7 through IN0 and it also contains an
overtemperature warning bit (see Table 1). The status
register is accessed through an SPI-compatible master.
The MAX13037/MAX13038 operate as a Serial Peripheral
Interface (SPI) slave devices. An SPI master accesses
the MAX13037/MAX13038 by reading from a status register and writing to a command register. Both registers
are 16 bits long and are accessed most significant bit
(MSB) first.
On the falling edge of CS, the status register is immediately loaded to an internal shift register and the contents are transferred out of the SDO output on the rising
edge of CLK. Serial data on the SDI input is latched
into the shift register on the falling edge of CLK. On the
rising edge of CS, the contents of the shift register are
copied to the command register (see Figure 7). The
status and command registers are 16 bits wide, so it is
essential to clock a total of 16 bits while CS is low for
the input and output data to be valid. When CS is high,
the SDO output is high-impedance and any transitions
on CLK and SDI are ignored. The INT and OT flags are
cleared on the CS falling edge. Input status changes
occurring during the CS reading/writing operation are
allowed. If a switch status changes when CS is low, the
interrupt is asserted as usual. This allows the part to be
used even if VLO is disabled provided that the INT output is pulled up to another supply voltage.
Notes:
Bits 15–8: Switch 7 Through 0 Status (SW7–SW0)
SW7 through SW0 reflect the status of the switches
connected to inputs IN7 through IN0, respectively.
Open switches are returned as a [0] and closed switches are returned as a [1].
Bit 7: Overtemperature Warning (OT)
The OT bit returns a [1] when the internal temperature of
the MAX13037/MAX13038 is above the temperature
warning threshold of +135°C (typ). The OT bit returns a
[0] when the MAX13037/MAX13038 is either below the
temperature threshold, or it has fallen below the temperature hysteresis level following an overtemperature event.
Bits 6–0: Unused
Bits 6 through 0 are unused and should be ignored.
Command Register
The command register is used to configure the
MAX13037/MAX13038 for various modes of operation
and is accessed by an SPI-compatible master (see
Table 2). The power-on reset (POR) value of the command register is 0x00.
Table 1. Status Register
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
SW7
SW6
SW5
SW4
SW3
SW2
SW1
SW0
OT
—
—
—
—
—
—
—
Table 2. Command Register
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NAME
WTOFF
SC2
SC1
SC0
WEN
WEND
M1
M0
P7
P6
P5
P4
P3
P2
P1
P0
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Maxim Integrated | 15
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Notes:
Bit 15: Wetting Current Mode (WTOFF)
Set the WTOFF bit to configure the wetting currents as
continuous on closed switches. Clear the WTOFF bit to
configure the wetting current as a pulse where the wetting current is turned on for a set duration of 20ms after
a switch closes (and the debounce is timed out). After
20ms elapses, the wetting current is turned off. Either
wetting current mode is only applicable to switches that
have wetting currents enabled (see WEN and WEND
bits). In scan mode, the wetting currents are on for the
polling time of 250µs (typ) and are pulsed at the programmed scanning period. When WTOFF is set, the
wetting current continuously pulses at the programmed
scanning period. When WTOFF is cleared, the wetting
current pulses at the programmed scanning period, but
turns off after 20ms elapses.
Bits 14, 13, 12: Scanning Period (SC2, SC1, SC0)
The SC2, SC1, and SC0 bits are used to program the
scanning period as depicted in Table 3. Switch inputs
are simultaneously polled for a finite duration of 250µs
(typ), and polling occurs at a period selected through
the SC2, SC1, and SC0 inputs. Figure 8 shows a timing
diagram of switch scanning and sampling. When the
inputs are not being polled, the sense resistors are disconnected, reducing the current consumption caused
from polling closed switches. For a continuous scanning
Table 3. Programmable Scanning
Period
SC2
SC1
SC0
SCANNING PERIOD (ms)
0
0
0
64
0
0
1
32
0
1
0
16
0
1
1
8
1
0
0
4
1
0
1
2
period ([SC2:SC1:SC0] = [1:1:1] or [1:1:0]), the switch
inputs are constantly being monitored and the sense
resistors are always connected. The state [SC2:SC1:SC0]
= [1:1:0] also disables adjustable hysteresis (normally set
by RHYST) and fixes hysteresis at 0.166 x VBATREF. When
adjustable hysteresis is not needed, it is recommended to
disable this feature to reduce power consumption.
Bit 11: Global Wetting Current Enable (WEN)
The WEN bit is a global enable for the wetting currents
on all the channels. Set the WEN bit to enable wetting
currents on all channels and clear the WEN bit to disable wetting currents. Even with wetting currents globally enabled, the wetting currents and sense resistors
on IN0 and IN1 can still be turned off with the WEND bit
(see Table 4).
Bit 10: IN0 and IN1 Wetting Current Enable (WEND)
The WEND bit is used to turn on wetting currents and
sense resistors on inputs IN0 and IN1. Set the WEND
bit to enable wetting currents on IN0 and IN1 and clear
the WEND bit to turn off the wetting current and sense
resistors on IN0 and IN1. When the wetting currents
and sense resistors are disabled (WEND = 0), IN0 and
IN1 are configured as direct inputs with level-shifted
outputs on DO0 and D01. DO0 and DO1 can only be
used as level-shifted outputs in normal mode and are
three-stated in scan mode (see the Scan Mode section). Note that both the WEN and WEND bits need to
be set for wetting currents to be enabled on IN0 and
tSCAN
SWITCHES ARE
POLLED FOR 250μs
GND-CONNECTED
SWITCH INPUT
tSCAN-P
SWITCH
DEBOUNCE
STARTS
tDEB
INT
1
1
0
Continuous/adjustable
hysteresis off
1
1
1
Continuous
SWITCH
CLOSES
STATUS REGISTERS AND
INT ARE UPDATED
AFTER tDEB
Figure 8. Switch Sampling in Scan Mode
Table 4. Truth Table for WEN and WEND
WEN
WEND
WETTING CURRENT
(IN0, IN1)
16kΩ SENSE RESISTOR
(IN0, IN1)
WETTING CURRENT
(IN2–IN7)
16kΩ SENSE RESISTOR
(IN2–IN7)
0
0
Off
Off
Off
On
0
1
Off
On
Off
On
1
0
Off
Off
On
On
1
1
On
On
On
On
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Maxim Integrated | 16
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Table 5. Switch Configuration Controlled by M1 and M0
M1
M0
IN7 AND IN6 SWITCH
CONFIGURATION
IN5 AND IN4 SWITCH
CONFIGURATION
IN3–IN0 SWITCH
CONFIGURATION
0
0
Ground
Ground
Ground
0
1
Ground
Battery
Ground
1
0
Battery
Ground
Ground
1
1
Battery
Battery
Ground
IN1 (see Table 4). The DO0 and DO1 outputs are threestated when WEND = 1. When programmed as direct
inputs (WEND = 0), any input changes on IN0 and IN1
are not reflected by the status register.
command register to ([SC2:SC1:SC0] = [1:1:0]). The
hysteresis is set to 0.166 x VBATREF when adjustable
hysteresis is disabled.
Bits 9 and 8: Switch Configuration for IN7–IN4 (M1, M0)
The M1 and M0 bits set the switch configuration in
groups of two for IN7 through IN4 (see Table 5). Set M1
to configure IN7 and IN6 for battery-connected switches
and clear M1 for ground-connected switches. Set M0 to
configure IN5 and IN4 for battery-connected switches
and clear M0 for ground-connected switches.
In scan mode, each sense resistor is connected for a
finite duration of 250µs (typ) and is repeated at a period
according to the scanning period bits SC2, SC1, and SC0
(see Table 3). All input resistors are connected simultaneously and the inputs are polled at the same time. When all
external switches are open and the scanning period is set
to 64ms the scanning mode reduces current consumption to typically 28µA (LDO on) and 17µA (LDO off).
Wetting currents (if enabled) are applied to closed
switches during the polling time of 250µs (typ) and are
pulsed at the programmed scanning period. When
WTOFF is set, the wetting current continuously pulses at
the programmed scanning period. When WTOFF is
cleared, the wetting current pulses at the programmed
scanning period, but turns off after 20ms elapses. Inputs
IN0 and IN1 cannot be used as direct inputs (WEND = 0)
in scan mode. When configured as direct inputs in scan
mode, the outputs DO0 and DO1 are high impedance.
The quiescent current for a given scan mode can be calculated by the following formula (LDO off):
Bits 7–0: Interrupt Enable for IN7–IN0 (P7–P0)
The P7 through P0 bits allow independent control of
whether inputs IN7 through IN0 generate an interrupt
(INT). Set any bit to disable interrupts on the corresponding input and clear the bit to enable interrupts on
the corresponding channel. An interrupt is asserted
when any input configured for interrupts changes state.
IN0 and IN1 do not generate an interrupt when configured as direct inputs (WEND = 0).
Operating Modes
The MAX13037/MAX13038 feature three modes of operation: normal mode, scan mode, and shutdown mode.
Normal mode is entered when the scanning period bits
in the command register are configured for continuous
scanning ([SC2:SC1:SC0] = [1:1:1] or [1:1:0]). Scan
mode is entered when the scanning period bits are set
for a periodic scanning time as shown in Table 3.
Shutdown mode is entered by driving the shutdown
input (SD) low. The default mode after power-up is scan
mode (when SD = high) with a scan period of 64ms.
Normal Mode (Continuous Scanning)
In normal mode, the input sense resistors are always
connected to the switch inputs to detect any input status
change (except IN0 and IN1 when WEND = [0]). Wetting
currents are enabled according to the WEN, WEND, and
WTOFF bits in the command register. If adjustable hysteresis is not required, this feature can be disabled to
reduce power consumption (see the Typical Operating
Characteristics) by setting the scanning period bits in the
www.maximintegrated.com
Scan Mode
⎛
⎞
1
IBAT(μA) = 16 × ⎜1 +
⎟
t SCAN _ P(ms) ⎠
⎝
Where V BAT = SD = +14V, I BAT is the BAT current
expressed in microamps and tSCAN_P is the scanning
period expressed in milliseconds.
Shutdown Mode
In shutdown mode, the LDO is disabled, all switch
inputs are high impedance and the external switches
are no longer monitored, reducing current consumption
on BAT to 2.85µA (typ). The MAX13037/MAX13038
reset upon entering shutdown mode and the contents
of the command register are lost. Exit shutdown mode
by bringing the voltage on SD above +2.4V. The SD
input is compatible with voltages up to V BAT . The
MAX13037/MAX13038 take 200µs (typ) to exit shutdown
Maxim Integrated | 17
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
at which point the command register is restored to its
power-up default (0x00) and the MAX13037/
MAX13038 enter scan mode. Note that SD is compatible with both logic and BAT voltage levels. Having SD
compatible to VBAT allows the MAX13037/MAX13038 to
retain the settings in the command register as well as
input monitoring even when VLO is disabled, provided
that SD = VBAT.
ESD Protection
Applications Information
Human Body Model
Considerations for Reverse-Battery
Tolerance
The BATREF and IN0–IN7 inputs can withstand voltages
down to -45V without damage so that reverse battery is
not an issue. The BAT input should be protected with a
reverse-battery diode as shown in the Typical Application
Circuit. The shutdown (SD) and REGON inputs can be
controlled from a battery-level source, but should be protected against reverse battery in the application.
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electrostatic discharges encountered during handling and
assembly. The IN7–IN0 inputs have extra protection
against static electricity. Maxim’s engineers have
developed state-of-the-art structures to protect these
pins against ESD of ±8kV without damage.
The MAX13037/MAX13038 IN7–IN0 pins are characterized for ±8kV ESD protection using the Human
Body Model. Figure 7a shows the Human Body Model,
and Figure 7b shows the current waveform it generates when discharged into a low impedance. This
model consists of a 100pF capacitor charged to the
ESD voltage of interest, which is then discharged into
the device through a 1.5kΩ resistor.
RC 1MΩ
RD 1500Ω
Power Dissipation
Wetting currents and the LDO output current can result in
overheating the MAX13037/MAX13038. At the early thermal warning threshold of +135°C (typ), wetting currents
are disabled. This allows the LDO output to remain
enabled if overheating is caused by the wetting currents.
At temperatures above +170°C, the LDO is also turned
off to avoid damage to the device.
It is important to consider the effects of wetting currents
on the power dissipated by the MAX13037/MAX13038.
For example, assume all inputs are configured for a
continuous wetting current of 25mA, all external switches have an on-resistance of 1Ω and the battery voltage
is +16V. If all switches are simultaneously closed, the
corresponding power dissipated due to wetting currents
only is (16V - (25mA x 1Ω)) x 25mA x 8 = 3.12W, which
is higher than the absolute maximum power dissipation
of 2857mW at +70°C.
The LDO is a second source of power dissipation. For
example, if VLO = +3.3V, ILO = 100mA and VBAT =
+16V, the power dissipated by the LDO is (16V - 3.3V)
+ (0.1) = 1.27W. Both the LDO and wetting currents
should be taken into account for correct use of the
MAX13037/MAX13038.
www.maximintegrated.com
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
DISCHARGE
RESISTANCE
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
Figure 7a. Human Body ESD Test Model
IP 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 7b. Human Body Model Current Waveform
Maxim Integrated | 18
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
DO0
DO1
RST
CLK
SDI
SD0
CS
REGOFF
REGON
SD
26
25
24
23
22
21
20
19
TOP VIEW
27
Pin Configuration
28
18
TD
*EP
THRESH
29
17
INT
WDI
30
16
OT
GND
31
15
GND
BATREF
32
14
TDEB
VLO
33
13
WET
N.C.
34
12
HYST
BAT
35
11
N.C.
10
N.C.
5
6
7
8
9
IN3
IN4
IN5
IN6
IN7
3
IN1
4
2
IN0
IN2
1
36
+
GND
BAT
MAX13037
MAX13038
TQFN
(6mm x 6mm)
*CONNECT EXPOSED PAD TO GROUND
www.maximintegrated.com
Maxim Integrated | 19
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Typical Operating Circuit
BATTERY
+6V TO +26V,
+42V LOAD
DUMP
ECU CONNECTOR
BATREF
BATREF
DO0
DO1
DO1
THRESH
BAT
BAT
47μF
4700pF
4700pF
0.1μF 0.1μF
TDEB
TDEB
MAX13037
MAX13038
MAX13036
4700pF
TD
90kΩ
HYST
WET
SDO
SDO
SDI
CLK
CLK
CS
CS
61kΩ
HYST
30kΩ
SD
RST
OT
VLO
VL
OT
INT
SD
0.1μF
INT
WDI
GND
REGOFF
SDI
REGON
30kΩ
GND
WET
VLO
IN7
IN6
IN5
IN4
IN3
IN2
IN0
IN7
IN6
IN5
IN4
IN3
IN2
IN1
IN0
DO0
IN1
0.01μF
0.01μF
4.7μF
μC
Chip Information
Package Information
PROCESS: BiCMOS
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
www.maximintegrated.com
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
36 TQFN-EP
T3666+3
21-0141
90-0050
Maxim Integrated | 20
Contact Monitor and Level
Shifters with LDO Regulator
MAX13037/MAX13038
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/07
1
5/15
PAGES
CHANGED
DESCRIPTION
Initial release
—
No /V OPNs; deleted automotive references in General Description and Applications
Information sections; added Package Thermal Characteristics, updated Package
Information, and added Revision History; rebranded to new Maxim logo
1, 2, 18,
21, 22
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2015 Maxim Integrated Products, Inc. | 21
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