19-3592; Rev 0; 2/05
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
Features
The MAX1319/MAX1323/MAX1327 are single-channel,
14-bit, 526ksps analog-to-digital converters (ADCs) with
±2 LSB INL and ±1 LSB DNL with no missing codes. The
MAX1323 has a ±5V input range with ±16.5V fault-tolerant inputs. The MAX1327 has a ±10V input range with
±16.5V fault-tolerant inputs and the MAX1319 has a 0 to
+5V input range with ±6.0V fault-tolerant inputs. Other
features include a 10MHz track/hold (T/H) input bandwidth, internal clock, internal (+2.5V) or external (+2.0V
to +3.0V) reference, and shutdown mode.
A 16.6MHz, 14-bit, parallel interface provides the conversion results and accepts digital configuration inputs.
These devices operate from a +4.75V to +5.25V analog
supply and a separate +2.7V to +5.25V digital supply,
and consume less than 35mA total supply current. For
multichannel applications, refer to the MAX1316–
MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
data sheet.
♦ 14-Bit ADCs
526ksps
±2 LSB INL, ±1 LSB DNL, No Missing Codes
90dBc SFDR, -86dBc THD, 76.5dB SINAD, 77dB
SNR at 100kHz Input
These devices come in a 48-pin TQFP package and
operate over the extended -40°C to +85°C temperature range.
♦ Fast 1.6µs Conversion Time
♦ Flexible Input Ranges
0 to +5V (MAX1319)
±5V (MAX1323)
±10V (MAX1327)
♦ No Calibration Needed
♦ 14-Bit High-Speed Parallel Interface
♦ Internal or External Clock
♦ +2.5V Internal Reference or +2.0V to +3.0V
External Reference
♦ +5V Analog Supply, +3V to +5V Digital Supply
32mA Analog Supply Current (typ)
550µA Digital Supply Current (typ)
Shutdown and Power-Saving Modes
♦ 48-Pin TQFP Package (7mm x 7mm Footprint)
Applications
Pin Configuration
Vibration and Waveform Analysis
Data-Acquisition Systems
DVDD
D13
38
37
EOC
DGND
39
40
41
42
43
44
45
46
ALLON
SHDN
CLK
CONVST
CS
I.C.2
RD
EOLC
I.C.
9
28
I.C.
I.C.
I.C.
10
27
11
26
D3
D2
12
25
D1
31
MAX1319
MAX1323
MAX1327
8
30
29
D7
D6
D5
D4
24
7
INTCLK/EXTCLK
AGND
AVDD
Typical Operating Circuits appear at end of data sheet.
47
6
13
±10
MAX1327ECM 48 TQFP
C48-6
Note: All devices operate over the -40°C to +85°C temperature
range.
32
MSV
I.C.
I.C.
23
C48-6
5
D10
D9
D8
22
±5
33
21
MAX1323ECM 48 TQFP
4
20
C48-6
34
19
0 to +5
3
18
MAX1319ECM 48 TQFP
D11
AGND
AIN
I.C.
17
PKG
CODE
D12
35
16
INPUT
RANGE (V)
36
2
15
PIN-PACKAGE
1
AGND
AVDD
REFMS
REF
REF+
COM
REFAGND
D0
PART
AVDD
AGND
14
Ordering Information/
Selector Guide
48
TOP VIEW
Industrial Process Control and Automation
TQFP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1319/MAX1323/MAX1327
General Description
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
ABSOLUTE MAXIMUM RATINGS
REF+, COM, REF- to AGND.....................-0.3V to (AVDD + 0.3V)
D0–D13 to DGND ....................................-0.3V to (DVDD + 0.3V)
Maximum Current into Any Pin Except AVDD, DVDD,
AGND, DGND ...............................................................±50mA
Continuous Power Dissipation (TA = +70°C)
TQFP (derate 22.7mW/°C above +70°C) ...................1818mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0, I.C. to AGND (MAX1319)..............................................±6.0V
CH0, I.C. to AGND (MAX1323/MAX1327)...........................±16.5V
INTCLK/EXTCLK to AGND .......................-0.3V to (AVDD + 0.3V)
EOC, EOLC, WR, I.C.2, RD,
CS to DGND.........................................-0.3V to (DVDD + 0.3V)
CONVST, CLK, SHDN,
ALLON to DGND..................................-0.3V to (DVDD + 0.3V)
MSV, REFMS, REF to AGND.....................-0.3V to (AVDD + 0.3V)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (MAX1319; unipolar device), MSV =
AGND (MAX1323/MAX1327; bipolar devices), fCLK = 10MHz 50% duty, tACQ = 200ns, tQUIET = 10ns, INTCLK/EXTCLK = AGND
(external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Note 1)
Resolution
N
14
Bits
Integral Nonlinearity
INL
(Note 2)
±0.8
±2
LSB
Differential Nonlinearity
DNL
No missing codes
±0.5
±1
LSB
Offset Error
Offset Drift
Gain Error
Unipolar device
±33
Bipolar devices
±33
Unipolar device
4
Bipolar devices
4
(Note 3)
±10
Gain Temperature Coefficient
LSB
ppm/°C
±49
3
LSB
ppm/°C
DYNAMIC PERFORMANCE (at fIN = 100kHz, -0.4dBFS)
Signal-to-Noise Ratio
SNR
Signal-to-Noise and Distortion
Ratio
SINAD
Spurious Free Dynamic Range
SFDR
Total Harmonic Distortion
THD
Unipolar
Bipolar
Unipolar
Bipolar
74.5
76
75
76.5
74.5
76.0
75
76.5
83
dB
dB
93
-90
dBc
-83
dBc
ANALOG INPUTS (CH0–CH7)
Input Voltage Range
2
MAX1319
0
+5
MAX1323
-5
+5
MAX1327
-10
+10
_______________________________________________________________________________________
V
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (MAX1319; unipolar device), MSV =
AGND (MAX1323/MAX1327; bipolar devices), fCLK = 10MHz 50% duty, tACQ = 200ns, tQUIET = 10ns, INTCLK/EXTCLK = AGND
(external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MAX1319
MAX1323
MAX
0.54
0.72
-0.157
-0.12
VIN = +5V
VIN = -5V
MAX1327
TYP
VIN = +5V
VIN = 0V
Input Current
MIN
0.29
-1.16
-0.87
-1.13
-0.85
VIN = +10V
VIN = -10V
0.56
MAX1319
Input Resistance
0.39
UNITS
mA
0.74
7.58
MAX1323
8.66
MAX1327
14.26
Input Capacitance
kΩ
15
pF
External Clock Throughput Rate
526
ksps
Internal Clock Throughput Rate
526
ksps
Small-Signal Bandwidth
10
MHz
Full-Power Bandwidth
10
MHz
Aperture Delay
16
ns
Aperture Jitter
50
psRMS
TRACK/HOLD
INTERNAL REFERENCE
REFMS Voltage
REF Voltage
VREFMS
2.475
2.500
2.525
V
VREF
2.475
2.500
2.525
V
REF Temperature Coefficient
30
ppm/°C
EXTERNAL REFERENCE (REFMS and REF externally driven)
Input Current
-250
REFMS Input Voltage Range
REF Input Voltage Range
VREFMS
VREF
Unipolar device
+250
µA
V
2.0
2.5
3.0
2.0
2.5
3.0
V
REF Input Capacitance
15
pF
REFMS Input Capacitance
15
pF
_______________________________________________________________________________________
3
MAX1319/MAX1323/MAX1327
ELECTRICAL CHARACTERISTICS (continued)
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), CREF = CREFMS = 0.1µF, CREF+ =
CREF- = 0.1µF, CREF+-to-REF- = 2.2µF || 0.1µF, CCOM = 2.2µF || 0.1µF, CMSV = 2.2µF || 0.1µF (MAX1319; unipolar device), MSV =
AGND (MAX1323/MAX1327; bipolar devices), fCLK = 10MHz 50% duty, tACQ = 200ns, tQUIET = 10ns, INTCLK/EXTCLK = AGND
(external clock), SHDN = DGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (D0–D7, RD, CS, CLK, SHDN, CONVST)
Input-Voltage High
VIH
Input-Voltage Low
VIL
0.7 x
DVDD
V
0.3 x
DVDD
Input Hysteresis
15
Input Capacitance
CIN
Input Current
IIN
mV
15
VIN = 0V or DVDD
V
pF
±1
µA
CLOCK-SELECT INPUT (INTCLK/EXTCLK)
0.7 x
AVDD
Input-Voltage High
V
0.3 x
AVDD
Input-Voltage Low
V
DIGITAL OUTPUTS (D0–D13, EOC, EOLC)
Output-Voltage High
VOH
ISOURCE = 0.8mA
Output-Voltage Low
VOL
ISINK = 1.6mA
DVDD 0.6
V
0.4
Tri-State Leakage Current
RD ≥ VIH or CS ≥ VIH
0.06
Tri-State Output Capacitance
RD ≥ VIH or CS ≥ VIH
15
1
V
µA
pF
POWER SUPPLIES
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.70
5.25
V
Analog Supply Current
IAVDD
Digital Supply Current
IDVDD
4
32
36
MAX1323/MAX1327
28
32
VSHDN = DVDD
Shutdown Current
Power-Supply Rejection Ratio
MAX1319
PSRR
VRD = DVDD, VSHDN = DVDD
0.1
AVDD = +4.75V to +5.75V (Note 5)
50
_______________________________________________________________________________________
mA
700
µA
10
µA
2
µA
dB
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
PARAMETER
SYMBOL
Conversion Time
tCONV
CONVST Pulse-Width Low
(Acquisition Time)
tACQ
CONDITIONS
TYP
MAX
UNITS
Internal clock
1.6
1.8
ns
External clock (Figure 4)
16
(Note 4)
MIN
0.16
Clock
cycles
100
µs
CS Pulse Width
t2
30
RD Pulse-Width Low
t3
30
ns
CS to RD Setup Time
t8
0
ns
RD to CS Hold Time
t9
0
ns
Data Access Time
(RD Low to Valid Data)
t10
Bus Relinquish Time (RD High)
t11
Internal clock
EOC Pulse Width
t12
External CLK Period
t16
External CLK High Period
t17
External CLK Low Period
t18
External Clock Frequency
t19
t20
ns
Clock
cycle
90
ns
20
ns
Logic sensitive to rising edges
20
(Note 6)
0.1
(Note 7)
30
ns
ns
12.5
10
EOC Low to RD
ns
1
Internal Clock Frequency
CONVST High to CLK Edge
30
80
External clock (Figure 4)
Logic sensitive to rising edges
ns
MHz
MHz
20
ns
0
ns
Note 1: For the MAX1319, VIN = 0 to +5V. For the MAX1323, VIN = -5V to +5V. For the MAX1327, VIN = -10V to +10V.
Note 2: INL is defined as the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: CONVST must remain low for at least the acquisition period.
Note 5: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
Note 6: Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
to the falling edge of EOLC to a maximum of 0.25ms.
Note 7: To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the rising
edge of CONVST and have a minimum clock frequency of 100kHz.
_______________________________________________________________________________________
5
MAX1319/MAX1323/MAX1327
TIMING CHARACTERISTICS (Figures 3, 4, 5, and 6) (Tables 1, 2)
Typical Operating Characteristics
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits,
fCLK = 10MHz 50% duty, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C.)
0.50
0.25
0.25
0
0
-0.25
-0.25
-0.50
-0.50
-0.75
-0.75
-1.00
-1.00
0
4096
8192
12,288
16,384
50
SUPPLY CURRENT (mA)
0.50
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX1319 toc02
0.75
DNL (LSB)
45
40
35
fSAMPLE = 250ksps
30
0
4096
8192
12,288
16,384
4.75
4.87
5.00
5.12
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. TEMPERATURE
40
35
0.8
SHUTDOWN CURRENT (µA)
SHUTDOWN CURRENT (µA)
45
ANALOG
SHUTDOWN
CURRENT
0.6
0.4
DIGITAL
SHUTDOWN
CURRENT
0.2
5.25
MAX1319 toc06
0.8
MAX1319 toc04
50
MAX1319 toc05
INL (LSB)
0.75
SUPPLY CURRENT (mA)
1.00
MAX1319 toc01
1.00
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX1319 toc03
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
ANALOG
SHUTDOWN
CURRENT
0.6
0.4
DIGITAL
SHUTDOWN
CURRENT
0.2
fSAMPLE = 250ksps
0
-15
10
35
60
0
2.5
3.5
5.5
4.5
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.503
2.502
2.5001
2.501
VREF (V)
2.5002
2.5000
2.500
-0.5
2.4997
2.497
-1.5
2.4996
2.496
-2.0
5.0
5.1
5.2
5.3
-40
-15
10
35
TEMPERATURE (°C)
85
0
2.498
AVDD (V)
60
0.5
2.4998
4.9
35
1.0
2.499
4.8
10
OFFSET ERROR vs. SUPPLY VOLTAGE
2.4999
4.7
-15
1.5
OFFSET ERROR (LSB)
2.5003
-40
TEMPERATURE (°C)
2.504
MAX1319 toc07
2.5004
6
85
MAX1319 toc08
-40
60
85
MAX1319 toc09
30
VREF (V)
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
-1.0
NORMALIZED AT TA = +25°C
4.75
4.85
4.95
5.05
AVDD (V)
_______________________________________________________________________________________
5.15
5.25
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
GAIN ERROR vs. SUPPLY VOLTAGE
15
GAIN ERROR (LSB)
0.01
0
-0.01
13
12
11
-0.02
NORMALIZED AT TA = +25°C
-15
10
60
85
0.04
0.01
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
AVDD (V)
TEMPERATURE (°C)
FFT
SIGNAL-TO-NOISE RATIO
vs. CLOCK FREQUENCY
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK FREQUENCY
-40
-60
80
78
78
77
-80
77
76
75
74
-100
-120
0.10
0.15
0.20
76
75
74
73
73
72
72
71
71
70
-140
70
8
0.25
fIN = 100kHz
79
10
12
14
16
18
20
8
10
12
14
16
18
FREQUENCY (MHz)
fCLK (MHz)
fCLK (MHz)
EFFECTIVE NUMBER OF BITS
vs. CLOCK FREQUENCY
TOTAL HARMONIC DISTORTION
vs. CLOCK FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
fIN = 100kHz
13.0
100
-75
20
MAX1319 toc17b
-70
MAX1319 toc16
13.5
85
MAX1319 toc15
fIN = 100kHz
79
SINAD (dB)
-20
80
MAX1319 toc14
fANALOG_IN = 103kHz
fSAMPLE = 490kHz
fCLK = 10MHz
SINAD = 76.7dB
SNR = 77.0dB
THD = -88.3dB
SFDR = 91.0dB
0.05
0.05
TEMPERATURE (°C)
0
0
0.06
0.02
9
35
SNR (dB)
-40
MAX1319 toc13
-0.04
0.07
0.03
10
-0.03
AMPLITUDE (dB)
14
MAX1319 toc17
OFFSET ERROR (%FSR)
0.02
0.08
GAIN ERROR (%FSR)
0.03
GAIN ERROR vs. TEMPERATURE
0.09
MAX1319 toc11
MAX1319 toc10
16
MAX1319 toc12
OFFSET ERROR vs. TEMPERATURE
0.04
95
12.0
SFDR (dB)
THD (dB)
ENOB (BITS)
90
-80
12.5
-85
11.5
-90
11.0
-95
85
80
75
70
65
-100
10.5
8
10
12
14
fCLK (MHz)
16
18
20
60
8
10
12
14
fCLK (MHz)
16
18
20
8
10
12
14
16
18
20
fCLK (MHz)
_______________________________________________________________________________________
7
MAX1319/MAX1323/MAX1327
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits,
fCLK = 10MHz 50% duty, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C.)
Typical Operating Characteristics (continued)
(AVDD = +5V, DVDD = +3V, AGND = DGND = 0V, VREF = VREFMS = +2.5V (external reference), see the Typical Operating Circuits,
fCLK = 10MHz 50% duty, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, TA = +25°C.)
1.2
1.0
0.8
0.6
1.6
4500
4000
3000
1.2
1.0
0.8
2500
0.2
0.2
500
0
0
5.000
5.125
5.250
1562
1500
0.6
1000
4.875
2306
2000
0.4
ANALOG SUPPLY VOLTAGE (V)
3815
3500
1.4
0.4
0
4.750
MAX1319 toc20
INTERNAL CLOCK
COUNTS
1.4
tCONV
1.8
CONVERSION TIME (µs)
1.6
2.0
MAX1319 toc19
INTERNAL CLOCK
tCONV
1.8
MAX1319 toc18
2.0
OUTPUT HISTOGRAM
(DC INPUT)
CONVERSION TIME
vs. TEMPERATURE
CONVERSION TIME
vs. ANALOG SUPPLY VOLTAGE
CONVERSION TIME (µs)
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
-40
-15
10
35
60
85
TEMPERATURE (°C)
341
0
13
154
1
0
8209 8210 8211 8212 8213 8214 8215 8216 8217
DIGITAL OUTPUT CODE
Pin Description
8
PIN
NAME
FUNCTION
1, 15, 17
AVDD
Analog Supply Input. AVDD is the power input for the analog section of the converter. Apply +5V to
AVDD. Bypass AVDD to AGND with a 0.1µF capacitor at each AVDD input.
2, 3, 14,
16, 23
AGND
Analog Ground. AGND is the power return for AVDD. Connect all AGNDs together.
4
AIN
Analog Input
5, 7–12
I.C.
Internally Connected. Connect I.C. to AGND.
6
MSV
Midscale Voltage Bypass. For the MAX1319, connect a 2.2µF and a 0.1µF capacitor from MSV to
AGND. For the MAX1323/MAX1327, connect MSV directly to AGND.
13
INTCLK/
EXTCLK
Clock-Mode Select Input. Use INTCLK/EXTCLK to select the internal or external conversion clock.
Connect INTCLK/EXTCLK to AVDD to select the internal clock. Connect INTCLK/EXTCLK to AGND to
use an external clock connected to CLK.
18
REFMS
Midscale Reference Bypass or Input. REFMS is the bypass point for an internally generated reference
voltage. For the MAX1319, connect a 0.1µF capacitor from REFMS to AGND. For the MAX1323/
MAX1327, connect REFMS directly to REF and bypass with a 0.1µF capacitor from REFMS to AGND.
19
REF
ADC Reference Bypass or Input. REF is the bypass point for an internally generated reference
voltage. Bypass REF with a 0.01µF capacitor to AGND. REF can be driven externally by a precision
external voltage reference.
20
REF+
Positive Reference Bypass. REF+ is the bypass point for an internally generated reference voltage. Bypass
REF+ with a 0.1µF capacitor to AGND. Also bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor.
21
COM
Reference Common Bypass. COM is the bypass point for an internally generated reference voltage.
Bypass COM to AGND with a 2.2µF and a 0.1µF capacitor.
_______________________________________________________________________________________
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
PIN
NAME
FUNCTION
22
REF-
24
D0
Digital Out Bit 0 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
25
D1
Digital Out Bit 1 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
26
D2
Digital Out Bit 2 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
27
D3
Digital Out Bit 3 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
28
D4
Digital Out Bit 4 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
29
D5
Digital Out Bit 5 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
30
D6
Digital Out Bit 6 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
31
D7
Digital Out Bit 7 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
32
D8
Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
33
D9
Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
34
D10
Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
35
D11
Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
36
D12
Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
37
D13
Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
38
DVDD
Digital Supply Input. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND with a 0.1µF capacitor.
39
DGND
Digital Supply GND. DGND is the power return for DVDD. Connect DGND to AGND at only one point
(see the Layout, Grounding, and Bypassing section).
40
EOC
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. EOC returns high after
one clock period.
41
EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the last conversion. EOLC
returns high when CONVST goes low for the next conversion sequence. For the MAX1319/MAX1323/
MAX1327, EOLC gives the same information as EOC.
42
RD
Read Input. Pulling RD low initiates a read command of the parallel data buses, D0–D13. D0–D13 are
high impedance while either RD or CS is high.
43
I.C.2
44
CS
Chip-Select Input. Pulling CS low activates the digital interface. D0–D13 are high impedance while
either CS or RD is high.
45
CONVST
Convert-Start Input. Driving CONVST high places the device in hold mode and initiates the
conversion process. The analog inputs are sampled on the rising edge of CONVST. When CONVST
is low the analog inputs are tracked.
46
CLK
External-Clock Input. CLK accepts an external clock signal up to 15MHz. Connect CLK to DGND for
internally clocked conversions. To select external clock mode, set INTCLK/EXTCLK = 0.
Negative Reference Bypass. REF- is the bypass point for an internally generated reference voltage. Bypass
REF- with a 0.1µF capacitor to AGND. Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor.
Internally Connected 2. Connect I.C.2 to DVDD.
47
SHDN
Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1 for shutdown mode.
48
ALLON
ALLON is not implemented. Connect ALLON to DGND.
_______________________________________________________________________________________
9
MAX1319/MAX1323/MAX1327
Pin Description (continued)
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
MAX1319
MAX1323
MAX1327
AVDD
DVDD
D13
AIN
14-BIT
ADC
S/H
14
SRAM
OUTPUT
DRIVERS
D0
MSV
REF+
COM
REF-
*
INTERFACE
AND
CONTROL
CS
RD
CONVST
SHDN
5kΩ
CLK
REF
ALLON
5kΩ
EOC
REFMS
EOLC
2.500V
DGND
INTCLK/EXTCLK
AGND
*SWITCH CLOSED ON UNIPOLAR DEVICE, OPEN ON BIPOLAR DEVICES
Figure 1. Functional Diagram
Detailed Description
Analog Inputs
The MAX1319/MAX1323/MAX1327 are 14-bit, 526ksps,
1.6µs conversion-time ADCs. These devices are available
with 0 to +5V, ±5V, and ±10V input ranges. The 0 to +5V
device features ±6V fault-tolerant inputs (see the Typical
Operating Circuits). The ±5V and ±10V devices feature
±16.5V fault-tolerant inputs (see the Typical Operating
Circuits). Internal or external reference, and clock capability offer great flexibility and ease of use. A 16.6MHz,
14-bit, parallel data bus outputs the conversion result.
Figure 1 shows the functional diagram of these devices.
T/H
The time required for the T/H to acquire an input signal
depends on the input source impedance. If the input signal’s source impedance is high, the acquisition time
lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the maximum
time the device takes to acquire the signal. Use the following formula to calculate the acquisition time:
tACQ = 10 (RS + RIN) x 6pF
where R IN = 2.2kΩ, R S = the input signal’s source
impedance, and t ACQ is never less than 180ns. A
source impedance of less than 100Ω does not significantly affect the ADC’s performance.
10
______________________________________________________________________________________
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
Input Bandwidth
The input tracking circuitry has a 10MHz small-signal
bandwidth, making it possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high frequency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Input Range and Protection
These devices provide ±10V, ±5V or 0 to +5V analog
input voltage ranges. Figure 2 shows the typical input circuit. Overvoltage protection circuitry at the analog input
provides ±16.5V fault protection for the bipolar input
devices and ±6.0V fault protection for the unipolar input
device. This fault protection circuit limits the current going
into or out of the device to less than 50mA, providing an
added layer of protection from momentary overvoltage or
undervoltage conditions at the analog input.
Power-Saving Modes
Shutdown Mode
During shutdown, the analog and digital circuits in the
device power down and the device draws less than
100µA from AVDD, and less than 100µA from DVDD.
Select shutdown mode using the SHDN input. Set
SHDN high to enter shutdown mode. After coming out
of shutdown, allow the 1ms wake-up before making the
first conversion. When using an external clock, apply at
least 20 clock cycles with CONVST high before making
the first conversion. When using internal clock mode,
wait at least 2µs before making the first conversion.
Clock Modes
These devices provide an internal clock of 10MHz
(typ). Alternatively, an external clock can be used.
Internal Clock
Internal clock mode frees the microprocessor from the
burden of running the ADC conversion clock. For internal clock operation, connect INTCLK/EXTCLK to AVDD
and connect CLK to DGND.
External Clock
For external clock operation, connect INTCLK/EXTCLK
to AGND and connect an external clock source to CLK.
Note that INTCLK/EXTCLK is referenced to the analog
power supply, AVDD. The external clock frequency can
be up to 15MHz, with a duty cycle between 30% and
70%. Clock frequencies of 100kHz and lower can be
used, but the droop in the T/H circuits reduces linearity.
Selecting an Input Buffer
MAX1319
MAX1323
MAX1327
5pF
R1
AIN
R2
CPAR
1pF
VBIAS
INPUT RANGE (V) R1 (kΩ) R2 (kΩ)
0 TO +5
3.33
5.00
±5
6.67
2.86
±10
13.33
2.35
Most applications require an input buffer to achieve 14bit accuracy. Although slew rate and bandwidth are
important, the most critical specification is settling time.
The sampling requires a relatively brief sampling interval of 150ns. At the beginning of the acquisition, the
internal sampling capacitor array connects to the
amplifier output, causing some output disturbance.
Ensure the amplifier is capable of settling to at least 14bit accuracy during this interval. Use a low-noise, lowdistortion, wideband amplifier (such as the MAX4330 or
MAX4265), which settles quickly and is stable with the
ADC’s capacitive load (in parallel with any bypass
capacitors on the analog inputs).
Figure 2. Typical Input Circuit
______________________________________________________________________________________
11
MAX1319/MAX1323/MAX1327
To improve the input signal bandwidth under AC conditions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance and settle
quickly. For example, the MAX4265 can be used for +5V
unipolar devices, or the MAX4350 can be used for ±5V
bipolar inputs.
The T/H aperture delay is typically 13ns. Figure 2 shows
a simplified equivalent input circuit, illustrating the ADC’s
sampling architecture.
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
face. The parallel interface goes high impedance when
RD = 1 or CS = 1.
Applications Information
Digital Interface
Starting a Conversion
The parallel digital interface outputs the 14-bit conversion result. The interface includes the following control
signals: chip select (CS), read (RD), end of conversion
(EOC), end of last conversion (EOLC), convert start
(CONVST), shutdown (SHDN), all on (ALLON), internal
clock select (INTCLK /EXTCLK), and external clock
input (CLK). Figures 3 and 4, Table 1, and the Timing
Characteristics table show the operation of the inter-
To start a conversion using internal clock mode, pull
CONVST low for at least the acquisition time (tACQ). The
T/H acquires the signal while CONVST is low, and conversion begins on the rising edge of CONVST. The endof-conversion signal (EOC) or the end-of-last-conversion
signal (EOLC) pulses low when the conversion result is
available (Figure 3).
SAMPLE
t13
tACQ
CONVST
HOLD
TRACK
TRACK
tEOC1
t12
EOC
t3
RD
t10
D0–D13
CH0
t11
Figure 3. Reading a Conversion—Internal Clock
Table 1. Reference Bypass Capacitors
LOCATION
INPUT VOLTAGE RANGE
UNIPOLAR (µF)
BIPOLAR (µF)
2.2 || 0.1
NA
REFMS Bypass Capacitor to AGND
0.01
0.01
REF Bypass Capacitor to AGND
0.01
0.01
REF+ Bypass Capacitor to AGND
0.1
0.1
2.2 || 0.1
2.2 || 0.1
MSV Bypass Capacitor to AGND
REF+ to REF- Capacitor
REF- Bypass Capacitor to AGND
0.1
0.1
COM Bypass Capacitor to AGND
2.2 || 0.1
2.2 || 0.1
NA = Not applicable (connect MSV directly to AGND).
12
______________________________________________________________________________________
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
It is necessary to have a period of inactivity on the digital bus during signal aquisition. tQUIET is the period
between the RD rising edge and the falling edge of
CONVST shown in Figure 4. Allow a minimum of 50ns
for tQUIET.
Reading a Conversion Result
Reading During a Conversion
Figures 3 and 4 show the interface signals for initiating
a read operation during a conversion cycle. CS can be
low at all times; it can be low during the RD cycles, or it
can be the same as RD.
After initiating a conversion by bringing CONVST high,
wait for EOC or EOLC to go low (about 1.6µs in internal
clock mode or 17 clock cycles in external clock mode)
before reading the first conversion result. Read the
conversion result by bringing RD low and latching the
data to the parallel digital-output bus. Bring RD high to
release the digital bus.
Power-Up Reset
After applying power, allow the 1.0ms wake-up time to
elapse before initiating the first conversion. If using an
external clock, apply 20 clock pulses to CLK with
CONVST high before initiating the first conversion. If
using an internal clock, hold CONVST high for at least
2.0µs after the wake-up time is complete.
Reference
Internal Reference
The internal reference circuits provide for analog input
voltages of 0 to +5V unipolar (MAX1319), ±5V bipolar
(MAX1323) or ±10V bipolar (MAX1327). Install external
capacitors for reference stability, as indicated in Table 1,
and as shown in the Typical Operating Circuits.
SAMPLE
SAMPLE
t13
tACQ
CONVST
HOLD
TRACK
t19
t16
t17
1
TRACK
2
3
16
17
18
19
20
1
CLK
t18
tQUIET
EOC
t12
t20
CS
t2
t8
t3
RD
t9
t10
D0–D13
t11
Figure 4. Reading a Conversion—External Clock
______________________________________________________________________________________
13
MAX1319/MAX1323/MAX1327
To start a conversion using external clock mode, pull
CONVST low for at least the acquisition time (tACQ). The
T/H acquires the signal while CONVST is low, and conversion begins on the rising edge of CONVST. Apply an
external clock to the CLK pin. To avoid T/H droop
degrading the sampled analog input signals, the first
clock pulse should occur within 10µs from the rising
edge of CONVST, and have a minimum clock frequency
of 100kHz. The conversion result is available for read on
the rising edge of the 17th clock cycle (Figure 4).
In both internal and external clock modes, CONVST
must be held high until the last conversion result is
read. For best operation, the rising edge of CONVST
must be a clean, high-speed, low-jitter digital signal.
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
power supply is very noisy, a ferrite bead can be connected as a lowpass filter, as shown in Figure 5.
Transfer Functions
SUPPLIES
+5V
RETURN
+3V TO +5V
RETURN
OPTIONAL
FERRITE
BEAD
Bipolar ±10V Device
Table 2 and Figure 6 show the two’s complement transfer function for the MAX1327 with a ±10V input range.
The full-scale input range (FSR) is eight times the voltage at REF. The internal +2.500V reference gives a
+20V FSR, while an external +2V to +3V reference
allows an FSR of +16V to +24V, respectively. Calculate
the LSB size using the following equation:
1 LSB =
AVDD
AGND
MAX1319
MAX1323
MAX1327
DVDD
DGND
VDD
GND
DIGITAL
CIRCUITRY
Figure 5. Power-Supply Grounding and Bypassing
External Reference
Connect a +2.0V to +3.0V external reference at REFMS
and/or REF. When connecting an external reference,
the input impedance is typically 5kΩ. The external reference must be able to drive 200µA of current and be
less than 3Ω output impedance. For more information
about using external references see the Transfer
Functions section.
Layout, Grounding, and Bypassing
For best performance use PC boards. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital lines parallel to one another (especially clock lines),
or do not run digital lines underneath the ADC package. Figure 5 shows the recommended system ground
connections. A single-point analog ground (star ground
point) should be established at AGND, separate from
the logic ground. All other analog grounds and DGND
should be connected to this ground. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply
for this ground should be low impedance and as short
as possible for noise-free operation. High-frequency
noise in the VDD power supply may affect the highspeed comparator in the ADC. Bypass these supplies
to the single-point analog ground with 0.1µF and 2.2µF
bypass capacitors close to the device. If the +5V
14
8 × VREFADC
214
This equals 1.2207mV with a +2.5V internal reference.
The input range is centered about VMSV. Normally, MSV
= AGND, and the input is symmetrical at about zero. For
a custom midscale voltage, drive MSV with an external
voltage source. Noise present on MSV directly couples
into the ADC result. Use a precision, low-drift voltage reference with adequate bypassing to prevent MSV from
degrading ADC performance. For maximum full-scale
range, be careful not to violate the absolute maximum
voltage ratings of the analog inputs when choosing MSV.
Determine the input voltage as a function of V REF ,
VMSV, and the output code in decimal using the following equation:
VCH _ = LSB × CODE10 + VMSV
Bipolar ±5V Device
Table 3 and Figure 7 show the two’s complement transfer
function for the MAX1323 with a ±5V input range. The
FSR is four times the voltage at REF. The internal +2.500V
reference gives a +10V FSR, while an external +2V to
+3V reference allows an FSR of +8V to +12V, respectively. Calculate the LSB size using the following equation:
1 LSB =
4 × VREFADC
214
This equals 0.6104mV when using the internal reference.
The input range is centered about V MSV. Normally,
MSV = AGND, and the input is symmetrical at about
zero. For a custom midscale voltage, drive MSV with an
external voltage source. Noise present on MSV directly
couples into the ADC result. Use a precision, low-drift
voltage reference with adequate bypassing to prevent
MSV from degrading ADC performance. For maximum
full-scale range, be careful not to violate the absolute
______________________________________________________________________________________
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
TWO'S COMPLEMENT BINARY OUTPUT CODE
0x1FFF
0x1FFE
0x1FFD
0x1FFC
0x0001
0x0000
0x3FFF
8 x VREFADC
0x2003
0x2002
0x2001
0x2000
1 LSB =
-8192 -8190
-1 0 +1
8 x VREFADC
214
+8189 +8191
(MSV)
INPUT VOLTAGE (VCH_ - VMSV IN LSBs)
Figure 6. ±10V Bipolar Transfer Function
TWO'S COMPLEMENT BINARY OUTPUT CODE
4 x VREFADC
0x0001
0x0000
0x3FFF
4 x VREFADC
1 LSB =
4 x VREFADC
2
-8192 -8190
-1 0 +1
DECIMAL
EQUIVALENT
OUTPUT
(CODE10)
INPUT
VOLTAGE (V)
(VREF = 2.5V,
VMSV = 0V)
01 1111 1111 1111 ➔
0x1FFF
8191
9.9988
01 1111 1111 1110 ➔
0x1FFE
8190
9.9976
00 0000 0000 0001 ➔
0x0001
1
0.0012
00 0000 0000 0000 ➔
0x0000
0
0
11 1111 1111 1111 ➔
0x3FFF
-1
-0.0012
10 0000 0000 0001 ➔
0x2001
-8191
-9.9988
10 0000 0000 0000 ➔
0x2000
-8192
-10.0000
Table 3. ±5V Bipolar Code Table
0x1FFF
0x1FFE
0x1FFD
0x1FFC
0x2003
0x2002
0x2001
0x2000
TWO’S COMPLEMENT
BINARY OUTPUT CODE
14
+8189 +8191
(MSV)
INPUT VOLTAGE (VCH_ - VMSV IN LSBs)
Figure 7. ±5V Bipolar Transfer Function
maximum voltage ratings of the analog inputs when
choosing MSV. Determine the input voltage as a function of VREF, VMSV, and the output code in decimal
using the following equation:
TWO’S COMPLEMENT
BINARY OUTPUT CODE
DECIMAL
EQUIVALENT
OUTPUT
(CODE10)
INPUT
VOLTAGE (V)
(VREF = 2.5V,
VMSV = 0V)
01 1111 1111 1111 ➔
0x1FFF
8191
4.9994
01 1111 1111 1110 ➔
0x1FFE
8190
4.9988
00 0000 0000 0001 ➔
0x0001
1
0.0006
00 0000 0000 0000 ➔
0x0000
0
0
11 1111 1111 1111 ➔
0x3FFF
-1
-0.0006
10 0000 0000 0001 ➔
0x2001
-8191
-4.9994
10 0000 0000 0000 ➔
0x2000
-8192
-5.0000
VCH _ = LSB × CODE10 + VMSV
______________________________________________________________________________________
15
MAX1319/MAX1323/MAX1327
Table 2. ±10V Bipolar Code Table
8 x VREFADC
Table 4. 0 to +5V Unipolar Code Table
BINARY OUTPUT CODE
11 1111 1111 1111 ➔
0x3FFF
16383
11 1111 1111 1110 ➔
0x3FFE
16382
4.9994
10 0000 0000 0001 ➔
0x2001
8193
2.5003
10 0000 0000 0000 ➔
0x2000
8192
2.5000
01 1111 1111 1111 ➔
0x1FFF
8191
00 0000 0000 0001 ➔
0x0001
1
00 0000 0000 0000 ➔
0x0000
0
4.9997
0x2001
0x2000
0x1FFF
2 x VREFADC
0x0003
0x0002
0x0001
0x0000
1 LSB =
0
0.0003
2 x VREFADC
214
2
8192
8190 8194
(MSV)
16,381 16,383
INPUT VOLTAGE (LSBs)
0
2 × VREFADC
214
This equals 0.3052mV when using the internal reference.
The input range is centered about VMSV, which is internally set to +2.500V. For a custom midscale voltage,
drive REFMS with an external voltage source and MSV
will follow REF MS. Noise present on MSV or REF MS
directly couples into the ADC result. Use a precision,
low-drift voltage reference with adequate bypassing to
prevent MSV from degrading ADC performance. For
maximum full-scale range, be careful not to violate the
absolute maximum voltage ratings of the analog inputs
when choosing MSV. Determine the input voltage as a
function of VREF, VMSV, and the output code in decimal
using the following equation:
16
0x3FFF
0x3FFE
0x3FFD
0x3FFC
2.4997
Unipolar 0 to +5V Device
Table 4 and Figure 8 show the offset binary transfer function for the MAX1319 with a 0 to +5V input range. The
FSR is two times the voltage at REF. The internal +2.500V
reference gives a +5V FSR, while an external +2V to +3V
reference allows an FSR of +4V to +6V, respectively.
Calculate the LSB size using the following equation:
1 LSB =
2 x VREFADC
INPUT
DECIMAL
EQUIVALENT VOLTAGE (V)
(VREF = VREFMS
OUTPUT
= 2.5V)
(CODE10)
BINARY OUTPUT CODE
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
Figure 8. 0 to +5V Unipolar Transfer Function
VCH _ = LSB × CODE10 + (VMSV - 2.500V)
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For these
devices this straight line is a line drawn between the
endpoints of the transfer function, once offset and gain
errors have been nullified.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification of less than ±1 LSB guarantees no missing codes
and a monotonic transfer function.
Unipolar Offset Error
For the unipolar MAX1319, the ideal midscale transition
from 0x1FFF to 0x2000 occurs at MSV (see Figure 8).
The unipolar offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
______________________________________________________________________________________
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Gain Error
The ideal full-scale transition from 0x1FFE to 0x1FFF
occurs at 1 LSB below full scale (see the Transfer
Functions section). The gain error is the amount of deviation between the measured full-scale transition point
and the ideal full-scale transition point, once offset error
has been nullified.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s resolution (N bits):
SNR = (6.02 × N + 1.76) dB
⎡
V22 + V32 + V4 2 + V52
THD = 20 × log ⎢⎢
V1
⎢⎣
⎤
⎥
⎥
⎥⎦
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest frequency component.
Aperature Delay
Aperture delay (tAD) is the time delay from the sampling
clock edge to the instant when an actual sample is taken.
Aperture Jitter
Aperture Jitter (tAJ) is the sample-to-sample variation in
aperture delay.
Small-Signal Bandwidth
where N = 14 bits.
In reality, there are other noise sources besides quantization noise; thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five harmonics, and the DC offset.
A small -20dBFS analog input signal is applied to an
ADC in a manner that ensures that the signal’s slew
rate does not limit the ADC’s performance. The input
frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased by -3dB.
Signal-to-Noise Plus Distortion
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
Full-Power Bandwidth
⎡
⎤
SignalRMS
SINAD(dB) = 20 × log ⎢
⎥
⎣ (Noise + Distortion)RMS ⎦
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB =
Chip Information
TRANSISTOR COUNT: 80,000
PROCESS: 0.6µm BiCMOS
SINAD - 1.76
6.02
______________________________________________________________________________________
17
MAX1319/MAX1323/MAX1327
Bipolar Offset Error
For the bipolar MAX1323/MAX1327, the ideal zero-point
transition from 0x3FFF to 0x0000 occurs at MSV, which
is usually connected to ground (see Figures 6 and 7).
The bipolar offset error is the amount of deviation
between the measured zero-point transition and the
ideal zero-point transition.
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
MAX1319/MAX1323/MAX1327
Typical Operating Circuits
I.C.2
13
DVDD
INTCLK/EXTCLK
38
+5V
+3V
0.1µF
0.1µF
1
MAX1319
AVDD
DGND
39
GND
0.1µF
15
0.1µF
17
AVDD
AVDD
CS
2.2µF
UNIPOLAR
CONFIGURATION
RD
6
0.1µF
MSV
0.01µF
SHDN
18
REFMS
0.01µF
19
REF
ALLON
CLK
EOC
0.1µF
20
REF+
EOLC
42
45
47
48
DIGITAL
INTERFACE
AND
CONTROL
46
40
41
0.1µF
2.2µF
22
REF0.1µF
D13
D12
2.2µF
D11
21
0.1µF
COM
GND
AGND
D8
I.C.
D7
I.C.
D6
I.C.
D5
I.C.
D4
I.C.
D3
I.C.
D2
I.C.
D1
CH0
D0
12
11
10
9
8
7
ANALOG
INPUTS
0 TO +5V
5
4
D10
D9
2, 3, 14, 16, 23
18
CONVST
44
37
36
35
34
33
32
31
30
PARALLEL
DIGITAL
OUTPUTS
29
28
27
26
25
24
______________________________________________________________________________________
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
I.C.2
13
DVDD
INTCLK/EXTCLK
38
+5V
+3V
0.1µF
0.1µF
1
AVDD
0.1µF
15
0.1µF
17
MAX1323
MAX1327
DGND
BIPOLAR
CONFIGURATION
0.01µF
18
19
AVDD
CS
MSV
REFMS
REF
CONVST
SHDN
ALLON
CLK
0.1µF
20
GND
AVDD
RD
6
39
EOC
REF+
EOLC
44
42
45
47
48
DIGITAL
INTERFACE
AND
CONTROL
46
40
41
0.1µF
2.2µF
22
REF0.1µF
D13
D12
2.2µF
D11
21
0.1µF
COM
D9
2, 3, 14, 16, 23
GND
AGND
12
I.C.
11
10
9
8
7
BIPOLAR
ANALOG
INPUTS
5
4
D10
D8
D7
I.C.
D6
I.C.
D5
I.C.
D4
I.C.
D3
I.C.
D2
I.C.
D1
CH0
D0
37
36
35
34
33
32
31
30
PARALLEL
DIGITAL
OUTPUTS
29
28
27
26
25
24
______________________________________________________________________________________
19
MAX1319/MAX1323/MAX1327
Typical Operating Circuits (continued)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
MAX1319/MAX1323/MAX1327
526ksps, Single-Channel,
14-Bit, Parallel-Interface ADCs
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
21-0054
E
1
2
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm
21-0054
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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