MAX157ACPA

19-1388; Rev 0; 11/98 +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX The MAX157/MAX159 low-power, 10-bit analog-to-digital converters (ADCs) are available in 8-pin µMAX and DIP packages. Both devices operate with a single +2.7V to +5.25V supply and feature a 7.4µs successive-approximation ADC, automatic power-down, fast wake-up (2.5µs), an on-chip clock, and a high-speed, 3-wire serial interface. Power consumption is only 3.2mW (VDD = +3.6V) at the maximum sampling rate of 108ksps. At slower throughput rates, the 0.2µA automatic shutdown further reduces power consumption. The MAX157 provides 2-channel, single-ended operation and accepts input signals from 0 to VREF. The MAX159 accepts pseudo-differential inputs ranging from 0 to V REF . An external clock accesses data through the 3-wire serial interface, which is SPI™, QSPI™, and MICROWIRE™ compatible. Excellent dynamic performance and low power, combined with ease of use and a small package size, make these converters ideal for battery-powered and data acquisition applications, or for other circuits with demanding power-consumption and space requirements. For pin-compatible 12-bit upgrades, see the MAX144/MAX145 data sheet. Applications Battery-Powered Systems Portable Data Logging Isolated Data Acquisition Process-Control Monitoring Instrumentation Test Equipment Medical Instruments System Supervision Pin Configuration TOP VIEW VDD 1 8 SCLK CH0 (CH+) 2 7 DOUT 6 CS/SHDN 5 REF CH1 (CH-) 3 MAX157 MAX159 GND 4 µMAX/DIP ( ) ARE FOR MAX159 ONLY. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Features ♦ Single-Supply Operation (+2.7V to +5.25V) ♦ Two Single-Ended Channels (MAX157) Single Pseudo-Differential Channel (MAX159) ♦ Low Power 0.9mA (at 108ksps, +3V) 100µA (at 10ksps, +3V) 10µA (at 1ksps, +3V) 2.17MHz) In internal clock mode, the MAX157/MAX159 run from an internal, laser-trimmed oscillator to within 20% of the 2MHz specified clock rate. This releases the system microprocessor from running the SAR conversion clock and allows the conversion results to be read back at the processor’s convenience, at any clock rate from 0 to 5MHz. Operating the MAX157/MAX159 in internal clock mode is necessary for serial interfaces operating with clock frequencies lower than 100kHz or greater than 2.17MHz. Select internal clock mode (Figure 5) by hold- VDD 4 VDD 2 SHDN OUT 5 8 CLK MAX7410 MAX7414 IN 7 2 0.1µF 1 VDD CH0 REF 5 EXTERNAL REFERENCE 470Ω MAX157 3 fCORNER = 15kHz CH1 DOUT 7 0.01µF 8 COM 1 OS 6 GND 3 SCLK GND 4 CS/SHDN 6 µP/µC 1.5MHz CLOCK 0.01µF Figure 4. Analog Input with Anti-Aliasing Filter Structure ACTIVE POWER DOWN tCS ACTIVE tWAKE tCONV (tACQ) CS/SHDN SCLK DOUT 1 EOC HIGH-Z 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 CHID MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 HIGH-Z SAMPLING INSTANT Figure 5. Internal Clock Mode Timing _______________________________________________________________________________________ 9 MAX157/MAX159 ing SCLK high during a high/low transition of CS/SHDN. The first SCLK falling edge samples the data and initiates a conversion using the integrated on-chip oscillator. After the conversion, the oscillator shuts off and DOUT goes high, signaling the end of conversion (EOC). Data can then be read out with SCLK. Selecting Clock Mode To start the conversion process on the MAX157/ MAX159, pull CS/SHDN low. At CS/SHDN’s falling edge, the part wakes up, the internal T/H enters track mode, and a conversion begins. In addition, the state of SCLK at CS/SHDN’s falling edge selects internal (SCLK = high) or external (SCLK = low) clock mode. MAX157/MAX159 +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX Output Data Format Automatic Power-Down Mode Table 1 illustrates the 16-bit, serial data-stream output format for both the MAX157 and MAX159. The first three bits are always logic high (including the EOC bit for internal clock mode), followed by the channel identification (CHID = 0 for CH0, CHID = 1 for CH1, CHID = 1 for MAX159), the 10 bits of data in MSB first format, and two sub-LSB bits (S1 and S0). After the last bit has been read out, additional SCLK pulses will clock out trailing zeros. DOUT transitions on the falling edge of SCLK. The output remains high impedance when CS/SHDN is high. Whenever the MAX157/MAX159 are not selected (CS/SHDN = VDD), the parts enter their shutdown mode. In shutdown all internal circuitry is turned off, which reduces the supply current to typically less than 0.2µA. With an external reference stable to within 1LSB, the wake-up time is 2.5µs. If the external reference is not stable within 1LSB, the wake-up time must be increased to allow the reference to stabilize. External Reference For a waveform perfectly reconstructed from digital samples, SNR is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): Applications Information Signal-to-Noise Ratio (SNR) An external reference is required for both the MAX157 and MAX159. At REF, the DC input resistance is a minimum of 18kΩ. During a conversion, a reference must be able to deliver 250µA of DC load current and have an output impedance of 10Ω or less. Use a 0.1µF bypass capacitor for best performance. The reference input structure allows a voltage range of 0 to (VDD + 50mV) although noise levels will decrease effective resolution at lower reference voltages. ACTIVE POWER DOWN SNR(MAX) = (6.02 · N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, ACTIVE tCS SAMPLING INSTANT tWAKE (tACQ) CS/SHDN SCLK 1 2 HIGH-Z DOUT 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CHID MSB D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 HIGH-Z Figure 6. External Clock Mode Timing ••• CS/SHDN tSCLKS tCL SCLK tCH tCS ••• tDV DOUT HIGH-Z tDO tTR ••• Figure 7. Detailed Serial-Interface Timing Sequence 10 ______________________________________________________________________________________ HIGH-Z +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX SCLK CYCLE 1 2 3 DOUT (Internal Clock) EOC 1 1 DOUT (External Clock) 1 1 1 4 5 6 7 8 9 10 11 12 13 14 15 16 CHID D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 CHID D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise (which includes all spectral components minus the fundamental), the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion (SINAD) Signal-to-noise plus distortion is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals: SINAD(dB) = 20 RMS ⋅ log  (Noise Signal + Distortion)    RMS  Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the full-scale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD = 20 ⋅   log    (V )  22 + V32 + V4 2 + V52  V12   where V1 is the fundamental amplitude and V2 through V5 are the amplitudes of the 2nd through 5th-order harmonics. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Connection to Standard Interfaces The MAX157/MAX159 interface is fully compatible with SPI/QSPI and MICROWIRE standard serial interfaces. If a serial interface is available, establish the CPU’s serial interface as master so that the CPU generates the serial clock for the MAX157/MAX159. Select a clock frequency from 100kHz to 2.17MHz (external clock mode). 1) Use a general-purpose I/O line on the CPU to pull CS/SHDN low while SCLK is low. 2) Wait for the minimum wake-up time (tWAKE) specified before activating SCLK. 3) Activate SCLK for a minimum of 16 clock cycles. The first falling clock edge will generate a serial datastream of three leading ones, followed by the channel identification, the MSB of the digitized input signal, and two sub-bits. DOUT transitions on SCLK’s falling edge and is available in MSB-first format. Observe the SCLK to DOUT valid timing characteristic. Data should be clocked into the µP on SCLK’s rising edge. 4) Pull CS/SHDN high at or after the 16th falling clock edge. If CS/SHDN remains low, trailing zeros will be clocked out after the sub-bits. 5) With CS/SHDN high, wait at least 60ns (tCS), before starting a new conversion by pulling CS/SHDN low. A conversion can be aborted by pulling CS/SHDN high before the conversion ends; wait at least 60ns before starting a new conversion. Data can be output either in two 8-bit sequences or continuously. The bytes will contain the result of the conversion padded with three leading ones, the channel identification before the MSB, and two trailing subbits. If the serial clock hasn’t been idled after the last sub-bit (S0) and CS/SHDN is kept low, DOUT sends trailing zeros. SPI and MICROWIRE Interface When using SPI (Figure 8a) or MICROWIRE (Figure 8b) interfaces, set CPOL = 0 and CPHA = 0. Conversion begins with a falling edge on CS/SHDN (Figure 8c). Two consecutive 8-bit readings are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock’s falling edge and is clocked into the µP on SCLK’s rising edge. The first 8-bit data stream contains three leading ones, followed by channel identification and the first four data bits starting with the MSB. The second 8-bit data stream contains the remaining bits, D5 through D0, and the sub-bits S1 and S0. ______________________________________________________________________________________ 11 MAX157/MAX159 Table 1. Serial Output Data Stream for Internal and External Clock Mode MAX157/MAX159 +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX CS/SHDN I/O CS/SHDN SCK SCLK SK SCLK MISO DOUT SI DOUT I/O VDD SPI MICROWIRE MAX157 MAX159 MAX157 MAX159 SS Figure 8a. SPI Connections Figure 8b. MICROWIRE Connections 1ST BYTE READ SCLK CS/SHDN 1 2 3 DOUT* SAMPLING INSTANT 4 5 CHID D9 MSB 2ND BYTE READ 6 D8 7 D7 8 9 D6 D5 10 D4 11 D3 12 D2 13 D1 14 D0 LSB 15 S1 16 S0 HIGH-Z *WHEN CS/SHDN IS HIGH, DOUT = HIGH -Z Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0) QSPI Interface Using the high-speed QSPI interface with CPOL = 0 and CPHA = 0, the MAX157/MAX159 supports a maximum fSCLK of 2.17MHz. The QSPI circuit in Figure 9a can be programmed to perform a conversion on each of the two channels for the MAX157. Figure 9b shows the QSPI interface timing. PIC16 with SSP Module and PIC17 Interface The MAX157/MAX159 are compatible with a PIC16/ PIC17 microcontroller (µC), using the synchronous serial port (SSP) module. To establish SPI communication, connect the controller as shown in Figure 10a and configure the PIC16/PIC17 as system master by initializing its synchronous serial port control register (SSPCON) and synchronous serial port status register (SSPSTAT) to the bit patterns shown in Tables 2 and 3. In SPI mode, the PIC16/PIC17 µCs allow eight bits of data to be synchronously transmitted and received simultaneously. Two consecutive 8-bit readings (Figure 10b) are necessary to obtain the entire 10-bit result from the ADC. DOUT data transitions on the serial clock’s falling edge and is clocked into the µC on SCLK’s rising edge. The first 8-bit data stream contains 12 CS CS/SHDN SCK SCLK MISO DOUT VDD QSPI SS MAX157 MAX159 Figure 9a. QSPI Connections three leading ones, the channel identification, and the first four data bits starting with the MSB. The second 8bit data stream contains the remaining bits, D5 through D0, and the two sub-bits S1 and S0. Layout, Grounding, and Bypassing For best performance use printed circuit boards (PCBs), wire-wrap configurations are not recommended, since the layout should ensure proper separation of analog and digital traces. Run analog and digital lines anti-parallel to each other, and don’t layout digital signal paths underneath the ADC package. Use separate analog and digital PCB ground sections with only one ______________________________________________________________________________________ +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 HIGH-Z CHID DOUT D9 SAMPLING INSTANT *WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 S1 S0 LSB Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0) VDD star-point (Figure 11) connecting the two ground systems (analog and digital). For lowest-noise operation, ensure the ground return to the star ground’s power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1µF and 1µF, located as close as possible to the power supply pin of the MAX157/MAX159. Minimize capacitor lead length for best supply-noise rejection and add an attenuation resistor (10Ω) if the power supply is extremely noisy. VDD SCLK SCK DOUT SDI CS/SHDN I/O MAX157 MAX159 PIC16/PIC17 GND GND Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller 1ST BYTE READ SCLK CS/SHDN 1 2 3 4 2ND BYTE READ 5 6 7 8 9 10 11 12 13 14 15 16 HIGH-Z DOUT* CHID SAMPLING INSTANT *WHEN CS/SHDN IS HIGH, DOUT = HIGH - Z D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0 LSB MSB Figure 10b. SPI Interface Timing Sequence with PIC16/17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001) POWER SUPPLIES +3V +3V GND +3V DGND R* = 10Ω 1µF 0.1µF VDD GND MAX157 MAX159 DIGITAL CIRCUITRY * OPTIONAL FILTER RESISTOR Figure 11. Power-Supply Bypassing and Grounding ______________________________________________________________________________________ 13 MAX157/MAX159 1 SCLK CS/SHDN MAX157/MAX159 +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX Table 2. Detailed SSPCON Register Content CONTROL BIT MAX157/MAX159 SETTINGS SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON) WCOL Bit 7 X Write Collision Detection Bit SSPOV Bit 6 X Receive Overflow Detect Bit SSPEN Bit 5 1 Synchronous Serial Port Enable Bit 0: Disables serial port and configures these pins as I/O port pins. 1: Enables serial port and configures SCK, SDO and SCI pins as serial port pins. Clock Polarity Select Bit. CKP = 0 for SPI master mode selection. CKP Bit 4 0 SSPM3 Bit 3 0 SSPM2 Bit 2 0 SSPM1 Bit 1 0 SSPM0 Bit 0 1 Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects fCLK = fOSC / 16. X = Don’t care Table 3. Detailed SSPSTAT Register Content CONTROL BIT MAX157/MAX159 SETTINGS SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT) 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time. Bit 6 1 SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock. Bit 5 X Data Address Bit P Bit 4 X Stop Bit S Bit 3 X Start Bit R/W Bit 2 X Read/Write Bit Information UA Bit 1 X Update Address BF Bit 0 X Buffer Full Status Bit SMP Bit 7 CKE D/A X = Don’t care 14 ______________________________________________________________________________________ +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX TRANSISTOR COUNT: 2,058 SUBSTRATE CONNECTED TO GND 8LUMAXD.EPS Package Information ______________________________________________________________________________________ 15 MAX157/MAX159 Chip Information +2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX PDIPN.EPS MAX157/MAX159 Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.