19-1755; Rev 1; 3/01
KIT
ATION
EVALU
E
L
B
AVAILA
Wide Brightness Range
CCFL Backlight Controllers
The MAX1739/MAX1839 fully integrated controllers are
optimized to drive cold-cathode fluorescent lamps
(CCFLs) using the industry-proven Royer oscillator
inverter architecture. The Royer architecture provides
near sinusoidal drive waveforms over the entire input
range to maximize the life of CCFLs. The MAX1739/
MAX1839 optimize this architecture to work over a wide
input voltage range, achieve high efficiency, and maximize the dimming range.
The MAX1739/MAX1839 monitor and limit the transformer center-tap voltage when required. This ensures
minimal voltage stress on the transformer, which
increases the operating life of the transformer and
eases its design requirements. These controllers also
provide protection against many other fault conditions,
including lamp-out and buck short faults.
These controllers achieve 50:1 dimming range by
simultaneously adjusting lamp current and “chopping”
the CCFL on and off using a digitally adjusted pulsewidth modulated (DPWM) method. CCFL brightness is
controlled by an analog voltage or is set with an
SMBusTM-compatible two-wire interface (MAX1739).
The MAX1739/MAX1839 drive an external high-side
N-channel power MOSFET and two low-side N-channel
power MOSFETs, all synchronized to the Royer oscillator. An internal 5.3V linear regulator powers the MOSFET drivers and most of the internal circuitry. The
MAX1739/MAX1839 are available in space-saving
20-pin QSOP packages and operate over the -40°C to
+85°C temperature range.
Features
♦ Fast Response to Input Change
♦ Wide Input Voltage Range (4.6V to 28V)
♦ High Power-to-Light Efficiency
♦ Minimizes Transformer Voltage Stress
♦ Lamp-Out Protection with 2s Timeout
♦ Buck Switch Short and Other Single-Point Fault
Protection
♦ Integrated Royer MOSFET Drivers Reduce
Transformer Pin Count
♦ Buck Operation Synchronized to Royer Oscillator
♦ Synchronizable DPWM Frequency
♦ Pin-Selectable Brightness Control Interface
♦ SMBus Serial Interface (MAX1739)
♦ Analog Interface (MAX1739/MAX1839)
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX1739EEP
-40°C to +85°C
20 QSOP
MAX1839EEP
-40°C to +85°C
20 QSOP
Pin Configuration
________________________Applications
Notebook/Laptop Computers
Car Navigation Displays
LCD Monitors
TOP VIEW
REF 1
20 BATT
MINDAC 2
19 DH
Point-of-Sale Terminals
CCI 3
18 LX
Portable Display Electronics
CCV 4
SH/SUS 5
†Pg
17 BST
MAX1739
16 VL
CRF/SDA 6
15 GND
CTL/SCL 7
14 CS
MODE 8
13 DL1
CSAV 9
12 DL2
CTFB 10
11 SYNC
QSOP
SMBus is a trademark of Intel Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
1
MAX1739/MAX1839†
General Description
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
ABSOLUTE MAXIMUM RATINGS
VBATT to GND ...........................................................-0.3V to 30V
VBST, VSYNC to GND.................................................-0.3V to 34V
VBST to VLX .................................................................-0.3V to 6V
VDH to VLX .................................................-0.3V to (VBST + 0.3V)
VLX to GND...................................................-6V to (VBST + 0.3V)
VL to GND...................................................................-0.3V to 6V
VCCV, VCCI, VREF, VDL1, VDL2 to GND .........-0.3V to (VL + 0.3V)
VMINDAC, VCTFB, VCSAV to GND ................................-0.3V to 6V
VCS to GND...................................................-0.6V to (VL + 0.3V)
VMODE to GND.............................................................-6V to 12V
VCRF/SDA, VCRF, VCTL/SCL, VCTL, V SH/SUS,
V SH to GND ............................................................-0.3V to 6V
Continuous Power Dissipation (TA = +70°C)
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
Operating Temperature .......................................-40°C to +85°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY AND REFERENCE
VBATT Input Voltage Range
VL = VBATT
4.6
5.5
VL = open
6
28
VBATT = 28V
3.2
6
VBATT = VL = 5V
3.2
6
V
VBATT Quiescent Current, Operation
with Full Duty Cycle on DH
DH = DL1 = DL2 = open
VBATT Quiescent Current, Shutdown
SH/SUS = SH = GND
6
20
μA
VL Output Voltage, Normal Operation
6V < VBATT < 28V, 0 < ILOAD < 15mA
5.0
5.35
5.5
V
SH/SUS = SH = GND, no load
3.5
4.5
5.5
V
VL Output Voltage, Shutdown
VL Undervoltage Lockout Threshold
VL rising (leaving lockout)
VL falling (entering lockout)
4.6
4.0
VL Undervoltage Lockout Hysteresis
REF Output Voltage, Normal
Operation
V
300
4.5V < VL < 5.5V, IREF = 40μA
VL POR Threshold
mA
1.96
2.00
0.9
mV
2.04
V
2.7
V
18
Ω
SWITCHING REGULATOR
DH Driver On-Resistance
18
Ω
49
56
64
kHz
250
375
500
ns
DL1, DL2 Driver On-Resistance
Minimum DH Switching Frequency
1/tDH, SYNC = CS or GND, not synchronized
DH Minimum Off-Time
DH Maximum Duty Cycle
%
Detect falling edges on SYNC
64
200
kHz
SYNC Input Current
0 < VSYNC < 30V
-2
2
μA
SYNC Input Threshold
SYNC falling, referred to CS
400
500
600
mV
SYNC Input Hysteresis
Referred to the SYNC input threshold
50
100
150
mV
SYNC Threshold Crossing to DL1,
DL2 Toggle Delay
VSYNC = 0 to 5V, CDL_1 and CDL_2 < 100pF,
50% point on SYNC to 50% point on DL1 or DL2
120
ns
492
mV
CS Overcurrent Threshold
2
98
SYNC Synchronization Range
408
450
_______________________________________________________________________________________
Wide Brightness Range
CCFL Backlight Controllers
(V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC AND ERROR AMPLIFIER
DAC Resolution
Guaranteed monotonic
MINDAC Input Voltage Range
MINDAC Input Bias Current
MINDAC Digital PWM Disable
Threshold
CSAV Input Voltage Range
CSAV Regulation Point
Bits
0
2
V
0 < VMINDAC < 2V
-1
1
μA
MINDAC = VL
2.4
4
V
0.8
V
2.9
0
VMINDAC = 0, DAC code = 11111 binary
188
194
VMINDAC = 0, DAC code = 00001 binary
2
6.25
16
VMINDAC = 1V, DAC code = 00000 binary
93
100
110
CSAV Input Bias Current
CSAV to CCI Transconductance
5
-1
1V < VCCI < 2.7V
200
1
0
CTFB Input Bias Current
2
V
1
μA
570
600
630
mV
-1
CTFB Regulation Point
μA
μmho
100
CTFB Input Voltage Range
mV
CTFB to CCV Transconductance
TIMERS AND FAULT DETECTION
1V < VCCV < 2.7V
30
40
50
μmho
Chopping Oscillator Frequency
No AC signal on MODE, not synchronized
24
28
32
kHz
No AC signal on MODE
205
220
235
Digital PWM Chop-Mode Frequency
MODE to DPWM Sync Ratio
Lamp-Out Detection Timeout Timer
(Center-Tap Voltage Stuck at
Maximum) (Note 1)
32kHz AC signal on MODE
250
100kHz AC signal on MODE
781
FMODE / FDPWM
VCSAV < CSAV
lamp-out
threshold
Hz
128
No AC signal on MODE
2.06
32kHz AC signal on MODE
(Note 2)
Shorted Buck-Switch Detection
Timeout Timer (UL1950 Protection)
(Note 3)
VCCV < faultdetection
threshold on CCV
Lamp Turn-On Delay
After SH/SUS or SH forces device on or SH rises
75
0.4
No AC signal on MODE
332
291
32kHz AC signal on MODE
256
100kHz AC signal on MODE
82
MODE Operating Voltage Range
s
0.66
50
Fault-Detection Threshold on CCV
2.73
2.05
100kHz AC signal on MODE
CSAV Lamp-Out Threshold
2.33
100
mV
1
V
259
ms
4
-5.5
ms
11
V
0.6
V
2.6
V
MODE = GND Threshold
(min Brightness = 0)
To sync DPWM oscillator, not in shutdown
(Note 4)
MODE = REF Threshold
(max Brightness = 0)
To sync DPWM oscillator, not in shutdown
(Note 4)
1.4
MODE = VL Threshold
(MAX1739 SMB Interface Mode)
To sync DPWM oscillator, not in shutdown
(Note 4)
VL - 0.6
V
MODE AC Signal Amplitude
Peak to peak (Note 5)
2
V
MODE AC Signal Synchronization
Range
Chopping oscillator synchronized to MODE AC
signal
32
100
kHz
_______________________________________________________________________________________
3
MAX1739/MAX1839†
ELECTRICAL CHARACTERISTICS (continued)
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
5.5
V
ANALOG INTERFACE BRIGHTNESS CONTROL (MODE connected to REF or GND )
CRF/SDA, CRF Input Range
2.7
20
µA
VCRF/SDA = VCRF = 5.5V, SH/SUS = SH = 0
-1
1
µA
CTL/SCL, Input Range
MAX1739
0
CRF/
SDA
V
CTL Input Range
MAX1839
0
CRF
V
CTL/SCL, CTL Input Current
MODE = REF or GND
-1
1
µA
ADC Resolution
Guaranteed monotonic
CRF/SDA, CRF Input Current
VCRF/SDA = VCRF = 5.5V
ADC Hysteresis
5
Bits
1
LSB
SH Input Low Voltage
0.8
SH Input High Voltage
2.1
SH/SUS Input Hysteresis when
Transitioning In and Out of Shutdown
V
150
SH Input Bias Current
V
-1
mV
1
µA
SYSTEM MANAGEMENT BUS BRIGHTNESS CONTROL (MAX1739, MODE connected to VL, see Figures 12 and 13)
CRF/SDA, CTL/SCL, SH/SUS Input
0.8
CRF/SDA, CTL/SCL, SH/SUS Input
2.1
CRFSDA, CTLSCL Input Hysteresis
V
300
CRF/SDA, CTL/SCL, SH/SUS Input
V
-1
mV
1
µA
CRF/SDA Output Low Sink Current
VCRF/SDA = 0.4V
4
CTL/SCL Serial Clock High Period
tHIGH
4
µs
CTL/SCL Serial Clock Low Period
tLOW
4.7
µs
Start Condition Setup Time
tSU:STA
4.7
µs
Start Condition Hold Time
tHD:STA
4
µs
CRF/SDA Valid to CTL/SCL Rising Edge
Setup Time, Slave Clocking in Data
tSU:DAT
250
ns
CTL/SCL Falling Edge to CRF/SDA
Transition
tHD:DAT
0
ns
CTL/SCL Falling Edge to CRF/SDA
Valid, Reading Out Data
tDV
4
_______________________________________________________________________________________
mA
1
µs
Wide Brightness Range
CCFL Backlight Controllers
(V+ = 8.2V, V SH/SUS = V SH = 5.5V, MINDAC = GND, TA = -40°C to +85°C, unless otherwise noted.) (Note 6)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY AND REFERENCE
VBATT Input Voltage Range
VL = VBATT
4.6
5.5
VL = open
6
28
VBATT Quiescent Current, Shutdown
SH/SUS = SH = GND
VL Output Voltage, Normal Operation
6V < VBATT < 28V,
0 < ILOAD < 15mA
VL Undervoltage Lockout Threshold
5.0
VL rising (leaving lockout)
V
20
µA
5.6
V
4.6
V
VL falling (entering lockout)
4.0
4.5V < VL < 5.5V, IREF = 40µA
1.95
2.05
V
0.9
2.7
V
DH Driver On-Resistance
18
Ω
DL1, DL2 Driver On-Resistance
18
Ω
REF Output Voltage, Normal
Operation
VL POR Threshold
SWITCHING REGULATOR
SYNC Synchronization Range
Detect falling edges on SYNC
CS Overcurrent Threshold
64
200
kHz
408
492
mV
186
202
mV
560
640
mV
30
50
µmho
0.8
V
DAC AND ERROR AMPLIFIER
CSAV Regulation Point
VMINDAC = 0, DAC code = 11111 binary
CTFB Regulation Point
CTFB to CCV Transconductance
1V < VCCV < 2.7V
ANALOG INTERFACE BRIGHTNESS CONTROL (MODE connected to REF or MODE connected to GND)
SH Input Low Voltage
SH Input High Voltage
2.1
V
SYSTEM MANAGEMENT BUS BRIGHTNESS CONTROL (MODE connected to VL)
CRF/SDA, CTL/SCL, SH/SUS Input
Low Voltage
0.8
CRF/SDA, CTL/SCL, SH/SUS Input
High Voltage
CRF/SDA Output Low Sink Current
VCRF/SDA = 0.4V
Note 1: Corresponds to 512 DPWM cycles or 65536 MODE
cycles.
Note 2: When the buck switch is shorted, VCTFB goes high
causing VCCV to go below the fault detection threshold.
Note 3: Corresponds to 64 DPWM cycles or 8192 MODE cycles.
Note 4: The MODE pin thresholds are only valid while the part is
operating. In shutdown, VREF = 0 and the part only
differentiates between SMB mode and ADC mode. In
shutdown with ADC mode selected, the CRF/SDA and
CTL/SCL pins are at high impedance and will not cause
extra supply current when their voltages are not at
GND or VL.
V
2.1
V
4
mA
Note 5: The amplitude is measured with the following circuit:
VAMPLITUDE > 2V
500pF
MODE
10k
Note 6: Specifications from -40°C to +85°C are guaranteed by
design, not production tested.
_______________________________________________________________________________________
5
MAX1739/MAX1839†
ELECTRICAL CHARACTERISTICS
Typical Operating Characteristics
(VIN = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, Circuit of Figure 8.)
WIDE INPUT RANGE
(VBATT = 20V)
MAX1739/1839 toc02
MAX1739/1839 toc01
WIDE INPUT RANGE
(VBATT = 8V)
VCTAP
5V/div
VCSAV
500mV/div
VDH
20V/div
VDH
20V/div
WIDE INPUT RANGE
(VBATT = 20V, DPWM = 9%, VCTL = 0)
MAX1739/1839 toc04
WIDE INPUT RANGE
(VBATT = 8V, DPWM = 9%, VCTL = 0)
MAX1739/1839 toc03
4μs/div
VCTAP
10V/div
VCCV
VCCV
VCCV, VCCI
200mV/div
VCCI
VCCI
VCCI
VCCV
VCCV
1.2V
VCCI
VCCI
VCCV
SWITCHING WAVEFORMS
FEED-FORWARD COMPENSATION
20V
VIN
10V
VCTAP
5mV/div
VCTAP
10V/div
VCSAV
500mV/div
VCSAV
500mV/div
VDH
20V/div
VDH
20V/div
6
1.2V
100μs/div
100μs/div
20μs/div
VCCV, VCCI
200mV/div
MAX1739/1839 toc08
VCCV
VCTAP
10V/div
VCSAV
500mV/div
VCSAV
500mV/div
VCCI
VCTAP
5V/div
VCSAV
500mV/div
4μs/div
MAX1739/1839 toc05
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
VDL
5V/div
4μs/div
_______________________________________________________________________________________
Wide Brightness Range
CCFL Backlight Controllers
(VIN = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, Circuit of Figure 8.)
SYNCHRONIZED DPWM
(fMODE = 32kHz, VCTL = VCRF/2)
MAX1739/1839 toc06
MAX1739/1839 toc07
SYNCHRONIZED DPWM
(fMODE = 100kHz, VCTL = VCRF/2)
VCTAP
5V/div
VCSAV
500mV/div
VCTAP
5V/div
VCSAV
500mV/div
VDH
20V/div
VDH
20V/div
1ms/div
1ms/div
STARTUP
(ADC SOFT-START, MODE = GND)
MAX1739/1839 toc10
MAX1739/1839 toc09
LAMP-OUT VOLTAGE LIMITING
12V
VBATT
0
VSECONDARY
2kV/div
VCTAP
10V/div
VCSAV
500mV/div
VCTAP
5V/div
IBATT
500mA/div
2ms/div
LAMP-OUT VOLTAGE LIMITING
INPUT CURRENT vs.
INPUT VOLTAGE
MAX1739/1839 toc12
900
VCTAP
5V/div
8
SHUTDOWN
700
7
600
6
500
5
MAXIMUM BRIGHTNESS
400
4
300
3
200
2
100
1
MINIMUM BRIGHTNESS
0
400ms/div
9
SHUTDOWN CURRENT (μA)
800
VSECONDARY
2kV/div
IBATT (mA)
MAX1739/1839 toc11
20ms/div
0
0
5
10
15
20
25
VBATT (V)
_______________________________________________________________________________________
7
MAX1739/MAX1839†
Typical Operating Characteristics (continued)
Typical Operating Characteristics (continued)
(VIN = 12V, VCTL = VCRF, VMINDAC = 1V, MODE = GND, Circuit of Figure 8.)
VL vs. BATT VOLTAGE
MAX1739/1839 toc13
4.6
6
4.5
5
NORMAL OPERATION
4.4
3
5.25
4.3
5.20
4.2
5.15
4.1
1
4.0
0
5.10
0.01
0.1
1
10
SHUTDOWN
4
VL (V)
SHUTDOWN
5.30
SHUTDOWN VL (V)
NORMAL OPERATION
5.35
2
0
100
5
10
15
20
VBATT (V)
IVL (mA)
VL vs. TEMPERATURE
MAX1739/1839 toc15
5.36
4.60
5.35
4.55
5.34
4.50
NORMAL OPERATION
5.33
4.45
5.32
4.40
5.31
SHUTDOWN VL (V)
VL (V)
SHUTDOWN
4.35
-40
-15
10
35
60
85
TEMPERATURE (°C)
8
MAX1739/1839 toc14
VL vs. IVL
5.40
VL (V)
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
_______________________________________________________________________________________
25
Wide Brightness Range
CCFL Backlight Controllers
PIN
NAME
FUNCTION
MAX1739
MAX1839
1
REF
REF
2V Reference Output. Bypass to GND with 0.1μF. Forced low during shutdown.
2
MINDAC
MINDAC
DAC Zero-Scale Input. VMINDAC sets the DAC’s minimum scale output voltage.
Disable DPWM by connecting MINDAC to VL.
3
CCI
CCI
GMI Output. Output of the current loop GMI amplifier that regulates the CCFL current.
Typically bypass to GND with 0.1μF .
4
CCV
CCV
GMV Output. Output of the voltage loop GMV amplifier that regulates the maximum
average primary transformer voltage. Typically bypass to GND with 3300p F .
5
SH/SUS
SH
Logic Low Shutdown Input in Analog Interface Mode. SMBus suspends input in SMBus
interface mode (MAX1739 only).
6
CRF/SDA
CRF
5-Bit ADC Reference Input in Analog Interface Mode. Bypass to GND with 0.1μF. SMBus serial
data input/open-drain output (MAX1739 only) in SMBus interface mode.
7
CTL/SCL
CTL
CCFL Brightness Control Input in Analog Interface Mode. SMBus serial clock input
(MAX1739 only) in SMBus interface mode.
8
MODE
MODE
Interface Selection Input and Sync Input for DPWM Chopping (see Synchronizing the
DPWM Frequency). The average voltage on the MODE pin selects one of three CCFL
brightness control interfaces:
1) MODE = VL, enables SMBus serial interface (MAX1739 only).
2) MODE = GND, enables the analog interface (positive scale analog interface mode);
VCTL/SCL = 0 means minimum brightness.
3) MODE = REF, enables the analog interface (negative scale analog interface mode);
VCTL/SCL = 0 means maximum brightness.
9
CSAV
CSAV
Current-Sense Input. Input to the GMI error amplifier that drives CCI.
10
CTFB
CTFB
Center-Tap Voltage Feedback Input. The average VCTFB is limited to 0.6V.
11
SYNC
SYNC
Royer Synchronization Input. Falling edges on SYNC force DH on and toggle the DL1
and DL2 drivers. Connect directly to the Royer center tap.
12
DL2
DL2
Low-Side N-Channel MOSFET 2 Gate Drive. Drives the Royer oscillator switch. DL1 and
DL2 have make-before-break switching, where at least one is always on. Falling edges
on SYNC toggle DL1 and DL2 and turn DH on.
13
DL1
DL1
Low-Side N-Channel MOSFET 1 Gate Drive
14
CS
CS
Current-Sense Input (Current Limit). The current-mode regulator terminates the switch
cycle when VCS exceeds (VREF - VCCI).
15
GND
GND
16
VL
VL
17
BST
BST
System Ground
5.3V Linear Regulator Output. Supply voltage for most of the internal circuits. Bypass
with 1μF capacitor to GND. Can be connected to VBATT if VBATT < 5.5V.
High-Side Driver Bootstrap Input. Connect through a diode to VL and bypass with 0.1μF
capacitor to LX.
18
LX
LX
High-Side Driver Ground Input
19
DH
DH
High-Side Gate Driver Output. Falling edges on SYNC turn on DH.
20
BATT
BATT
Supply Input. Input to the internal 5.3V linear regulator that powers the chip.
_______________________________________________________________________________________
_______________________________________________________________________________________
9
MAX1739/MAX1839†
Pin Description
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
Detailed Description
detect. Figure 1 shows the current and voltage waveforms for the three operating modes with the brightness
control set to 50% of full scale.
The MAX1739/MAX1839 regulate the brightness of a
CCFL in three ways:
The MAX1739/MAX1839 include a 5.3V linear regulator
to power most of the internal circuitry, drivers for the
buck and Royer switches, and the synchronizable
DPWM oscillator. The MAX1739/MAX1839 are very flexible and include a variety of operating modes, an analog interface, an SMBus interface (MAX1739 only), a
shutdown mode, lamp-out detection, and buck-switch
short detection.
1) Linearly controlling the lamp current.
2) Digitally pulse-width modulating (or chopping) the
lamp current (DPWM).
3) Using both methods simultaneously for widest dimming range.
DPWM is implemented by pulse-width modulating the
lamp current at a rate faster than the human eye can
DPWM CONTROL
VMINDAC = 0
VCTL = VCRF/2 or BRIGHT[4:0] = 10,000
(DAC SET TO MIDSCALE)
EFFECTIVE BRIGHTNESS IS:
50% IN CONTINUOUS AND DPWM CONTROL
25% IN COMBINED CONTROL
VCTAP
TRANSFORMER
VOLTAGE
VCSAV
LAMP CURRENT
CONTINUOUS CURRENT CONTROL
CURRENT + DPWM CONTROL
VCTAP
VCSAV
Figure 1. Brightness Control Methods
10
______________________________________________________________________________________
Wide Brightness Range
CCFL Backlight Controllers
With MINDAC between REF and GND, DPWM is
enabled and the MAX1739/MAX1839 begin pulsing the
lamp current. During the on-cycle, VCCV is at 150mV
above VCCI. After the on-cycle, VCCV is forced down to
1.2V to provide soft-start at the beginning of the next
on-cycle. Also, VCCI retains its value until the beginning
of the next on-cycle. When VCCV increases, it causes
the buck regulator duty cycle to increase and provides
soft-start. When VCCV crosses over VCCI, the current
control loop regains control and regulates the lamp current. V CCV is limited to 150mV above V CCI for the
remainder of the on-cycle.
In a lamp-out condition, VCCI increases the primary
voltage in an attempt to maintain lamp current regulation. As VCCI rises, VCCV rises with it until the primary
voltage reaches its set limit point. At this point, VCCV
stops rising and limits the primary voltage by limiting
the duty cycle. Because V CCV is limited to 150mV
above VCCI, the voltage control loop is quickly able to
limit the primary voltage. Without this clamping feature,
the transformer voltage would overshoot to dangerous
levels because VCCV would take more time to slew
down from its supply rail. Once the MAX1739/MAX1839
sense less than 1/6 the full-scale current through the
lamp for 2 seconds, it shuts down the Royer oscillator
(see Lamp-Out Detection).
See the Sense Resistors section for information about
setting the voltage and current control loop thresholds.
Feed-Forward Control
Both control loops are influenced by the input voltage
feed-forward (VBATT) control circuitry of the MAX1739/
MAX1839. Feed-forward control instantly adjusts the
buck regulator’s duty cycle when it detects a change in
input voltage. This provides immunity to changes in
input voltage at all brightness levels. This feature
makes compensation over wide input ranges easier,
makes startup transients less dependent on input voltage, and improves line regulation for short DPWM ontimes.
The MAX1739/MAX1839 feed-forward control is implemented by varying the amplitude of the buck-switch’s
PWM ramp amplitude. This has the effect of varying the
duty cycle as a function of input voltage while maintaining the same VCCI and VCCV. In other words, VBATT feed
forward has the effect of not requiring changes in errorsignal voltage (VCCI and VCCV) to respond to changes in
VBATT. Since the capacitors only need to change their
voltage minimally to respond to changes in VBATT, the
controller’s response is essentially instantaneous.
Transient Overvoltage Protection
from Dropout
The MAX1739/MAX1839 are designed to maintain tight
control of the transformer primary under all transient
conditions. This includes transients from dropout,
where VBATT is so low that the controller loses regulation and reaches maximum duty cycle. Backlight
designs will want to choose circuit component values to
minimize the transformer turns ratio in order to minimize
primary-side currents and I2R losses. To achieve this,
_______________________________________________________________________________________
11
MAX1739/MAX1839†
Voltage and Current Control Loops
The MAX1739/MAX1839 use two control loops. The current control loop regulates the average lamp current. The
voltage control loop limits the maximum average primaryside transformer voltage. The voltage control loop is
active during the beginning of DPWM on-cycles and in
some fault conditions. Limiting the transformer primary
voltage allows for a lower transformer secondary voltage
rating that can increase reliability and decrease cost of
the transformer. The voltage control loop acts to limit the
transformer voltage any time the current control loop
attempts to steer the transformer voltage above its limit as
set by VCTFB (see Sense Resistors).
The voltage control loop uses a transconductance
amplifier to create an error current based on the voltage between CTFB and the internal reference level
(600mV typ) (Figure 2). The error current is then used
to charge and discharge CCCV to create an error voltage VCCV. The current control loop produces a similar
signal based on the voltage between CSAV and its
internal reference level (see the Dimming Range section). This error voltage is called VCCI. The lower of
VCCV and VCCI is used with the buck regulator’s PWM
ramp generator to set the buck regulator’s duty cycle.
During DPWM, the two control loops work together to
limit the transformer voltage and to allow wide dimming
range with good line rejection. During the DPWM offcycle, VCCV is set to 1.2V and CCI is set to high impedance. VCCV is set to 1.2V to create soft-start at the
beginning of each DPWM on-cycle in order to avoid
overshoot on the transformer primary. V CCI is set to
high impedance to keep VCCI from changing during the
off-cycles. This allows the current control loop to regulate the average lamp current only during DPWM oncycles and not the overall average lamp current.
Upon power-up, VCCI slowly rises, increasing the duty
cycle, which provides soft-start. During this time, VCCV,
which is the faster control loop, is limited to 150mV
above VCCI by the CCV-CLAMP. Once the secondary
voltage reaches the strike voltage, the lamp current
begins to increase. When the lamp current reaches the
regulation point, VCCI reaches steady state. With MINDAC = VL (DPWM disabled), the current control loop
remains in control and regulates the lamp current.
12
REF
VL
VL
0.6V
SYNC
CS
CTFB
CCV
CCI
CSAV
MODE
GND
CTL/SCL
CRF/SDA
GMV
GMI
500mV
450mV
CCV CLAMP
PK_DET_CLAMP
SUPPLY
BUCK
ENABLE
MINDAC = VL?
Y = 1, N = 0
ROYER OSC
BUCK REGULATOR
PWM CONTROL
PWM
RAMP
GENERATOR
PEAK
DETECTOR
DPWM OSC
SMBus
LAMP CURRENT AND
DPWM CONTROL
CS
CS
DL2
DL1
LX
DH
BST
REF
SH/SUS
VL
BATT
MINDAC
REF
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
Figure 2. Functional Diagram
______________________________________________________________________________________
Wide Brightness Range
CCFL Backlight Controllers
Buck Regulator
The buck regulator uses the signals from the PWM
comparator, the current-limit detection on CS, and
DPWM signals to control the high-side MOSFET duty
cycle. The regulator uses voltage-mode PWM control
and is synchronized to the Royer oscillator. A falling
edge on SYNC turns on the high-side MOSFET after a
375ns minimum off-time delay. The PWM comparator or
the CS current limit ends the on-cycle.
Interface Selection
Table 1 lists the functionality of SH/SUS, CRF/SDA, and
CTL/SCL in each of the three interface modes of the
MAX1739/MAX1839. The MAX1739 features both an
SMBus digital interface and an analog interface, while
the MAX1839 features only the analog interface. Note
that MODE can also synchronize the DPWM frequency
(see Synchronizing the DPWM Frequency).
Dimming Range
Brightness is controlled by either the analog interface
(see Analog Interface) or the SMBus interface (see
SMBus Interface). CCFL brightness is adjusted in three
ways:
1) Lamp current control, where the magnitude of the
average lamp current is adjusted.
2) DPWM control, where the average lamp current is
pulsed to the lamp with a variable duty cycle.
3) A combination of the first two methods.
In each of the three methods, a 5-bit brightness code is
generated from the selected interface and is used to
set the lamp current and/or DPWM duty cycle.
The 5-bit brightness code defines the lamp current
level with ob00000 representing minimum lamp current
and ob11111 representing maximum lamp current. The
average lamp current is measured across an external
sense resistor (see Sense Resistors). The voltage on
the sense resistor is measured at CSAV. The brightness
code adjusts the regulation voltage at CSAV (VCSAV).
The minimum average VCSAV is VMINDAC/10, and the
maximum average is set by the following formula:
VCSAV = VREF ✕ 31 / 320 + VMINDAC / 320
which is between 193.75mV and 200mV.
Note that if VCSAV does not exceed 100mV peak (which
is about 32mV average) for over 2 seconds, the
MAX1739/MAX1839 will assume a lamp-out condition
and shut down (see Lamp-Out Detection).
The equation relating brightness code to CSAV regulation voltage is:
VCSAV = VREF ✕ n / 320 + VMINDAC ✕ (32 - n) / 320
where n is the brightness code.
To always use maximum average lamp current when
using DPWM control, set VMINDAC to VREF.
DPWM control works similar to lamp current control in
that it also responds to the 5-bit brightness code. A
Table 1. Interface Modes
DIGITAL
INTERFACE
ANALOG INTERFACE
PIN
MODE = VL
(MAX1739 only)
MODE = REF,
VCTL/SCL = 0 = maximum brightness
MODE = GND,
VCTL/SCL = 0 = minimum brightness
SH/SUS
SMBus suspend
Logic-level shutdown control input
CRF/SDA
SMBus data I/O
Reference input for minimum brightness
CTL/SCL
SMBus clock input
Analog control input to set brightness (range from 0 to CRF/SDA)
Reference input for maximum brightness
______________________________________________________________________________________
13
MAX1739/MAX1839†
allow the circuit to operate in dropout at extremely low
battery voltages where the backlight’s performance is
secondary. All backlight circuit designs can undergo a
transient overvoltage condition when the laptop is
plugged into the AC adapter and V BATT suddenly
increases. The MAX1739/MAX1839 contain a unique
clamp circuit on VCCI. Along with the feed-forward circuitry, it ensures that there is not a transient transformer
overvoltage when leaving dropout.
The PK_DET_CLAMP circuit limits VCCI to the peaks of
the buck-regulator’s PWM ramp generator. As the circuit reaches dropout, VCCI approaches the peaks of
the PWM ramp generator in order to reach maximum
duty cycle. If VBATT decreases further, the control loop
loses regulation and VCCI tries to reach its positive supply rail. The clamp circuit on VCCI keeps this from happening, and VCCI rides just above the peaks of the
PWM ramp. As VBATT decreases further, the feed-forward PWM ramp generator loses amplitude and the
clamp drags V CCI down with it to a voltage below
where VCCI would have been if the circuit was not in
dropout. When VBATT is suddenly increased out of
dropout, VCCI is still low and maintains the drive on the
transformer at the old dropout level. The circuit then
slowly corrects and increases VCCI to bring the circuit
back into regulation.
brightness code of ob00000 corresponds to a 9.375%
DPWM duty cycle, and a brightness code of ob11111
corresponds to a 100% DPWM duty cycle. The duty
cycle changes by 3.125% per step, except codes
ob00000 to ob00011 all produce 9.375% (Figure 3).
To disable DPWM and always use 100% duty cycle, set
VMINDAC to VL. Note that with DPWM disabled, the
equations above should assume VMINDAC = 0 instead
of VMINDAC = VL. Table 2 lists MINDAC’s functionality,
and Table 3 shows some typical settings for the brightness adjustment.
In normal operation, VMINDAC is set between 0 and
VREF, and the MAX1739/MAX1839 use both lamp current control and DPWM control to vary the lamp brightness (Figure 4). In this mode, lamp current control
regulates the average lamp current during a DPWM oncycle and not the overall average lamp current.
Analog Interface and Brightness Code
The MAX1739/MAX1839 analog interface uses an internal ADC with 1-bit hysteresis to generate the brightness
code used to dim the lamp (see Dimming Range).
CTL/SDA is the ADC’s input, and CRF/SCL is its reference voltage. The ADC can operate in either positivescale ADC mode or negative-scale ADC mode. In
positive-scale ADC mode, the brightness code increas-
es from 0 to 31 as VCTL increases from 0 to VCRF. In
negative-scale mode, the brightness scale decreases
from 31 to 0 as VCTL increases from 0 to VCRF (Figure 5).
The analog interface’s internal ADC uses 1-bit hysteresis to keep the lamp from flickering between two codes.
V CTL ’s positive threshold (V CTL(TH) ) is the voltage
required to transition the brightness code as V CTL
increases and can be calculated as follows:
VCTL(TH) = (n + 2) / 33 VCRF
(positive-scale ADC mode, MODE = GND)
VCTL(TH) = (33 - n) / 33 VCRF
(negative-scale ADC mode, MODE = REF)
where n is the current selected brightness code. VCTL’s
negative threshold is the voltage required to transition
the brightness code as VCTL decreases and can be
calculated as follows:
VCTL(TH) = n / 33 VCRF
(positive-scale ADC mode, MODE = GND)
VCTL(TH) = (31 - n) / 33 VCRF
(negative-scale ADC mode, MODE = REF)
Figure 5 shows a graphic representation of the thresholds. CRF/SDA’s and CTL/SCL’s input voltage range is
2.7V to 5.5V.
COMBINED POWER LEVEL
(BOTH DPWM AND
LAMP CONTROL CURRENT)
DPWM SETTINGS
100
100
90
90
80
80
COMBINED POWER LEVEL (%)
DPWM DUTY CYCLE (%)
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
70
60
50
40
30
20
10
70
60
50
40
30
20
10
0
0
0
4
8
12
16
20
24
28
32
0
BRIGHTNESS CODE
4
8
12
16
20
24
28
32
BRIGHTNESS CODE
Figure 4. Combined Power Level
Figure 3. DPWM Settings
Table 2. MINDAC Functionality
MINDAC = VL
DPWM disabled (always on 100% duty cycle). Operates in lamp current control only.
(Use VMINDAC = 0 in the equations.)
MINDAC = REF
DPWM control enabled, duty cycle ranges from 9% to 100%. Lamp current control is disabled
(always maximum current).
0 ≤ VMINDAC < VREF
The device uses both lamp current control and DPWM.
14
______________________________________________________________________________________
Wide Brightness Range
CCFL Backlight Controllers
BRIGHTNESS
POSITIVESCALE ADC
NEGATIVESCALE ADC
SMBus
DAC
OUTPUT
DPWM DUTY
CYCLE
(%)
COMBINED
POWER
LEVEL (%)
Maximum
Brightness
MODE = GND,
VCTL/SCL =
VCRF/SDA
MODE = REF,
VCTL/SCL = 0
Bright [4:0] =
ob11111
Full-scale
DAC OUTPUT =
195.83mV
100
100
Minimum
Brightness
MODE = GND,
VCTL/SCL = 0,
VMINDAC =
VREF / 3
MODE = REF,
VCTL/SCL = VCRF/SDA,
VMINDAC = VREF / 3
Bright [4:0] =
ob00000,
VMINDAC =
VREF / 3
Zero-scale
DAC OUTPUT =
VMINDAC / 10
9
3
Note: The current-level range is solely determined by the MINDAC-to-REF ratio and is externally set.
Synchronizing the DPWM Frequency
MODE has two functions: one is to select the interface
mode as described in Interface Selection, and the other
is to synchronize the DPWM “chopping” frequency to
an external signal to prevent unwanted effects in the
display screen.
To synchronize the DPWM frequency, connect MODE
to VL, REF, or GND through a 10kΩ resistor. Then connect a 500pF capacitor from an AC signal source to
MODE as shown in Figure 6. The synchronization range
is from 32kHz to 100kHz, which corresponds to a
DPWM frequency range of 250Hz to 781Hz (128 MODE
pulses per DPWM cycle). High DPWM frequencies limit
the dimming range. See Loop Compensation for more
information concerning high DPWM frequencies.
Royer Oscillator MOSFET Drivers
The MAX1739/MAX1839 directly drive the two external
MOSFETs used in the Royer oscillator. This has many
advantages over the traditional method that uses bipolar switching and an extra winding on the transformer.
Directly driving the MOSFET eliminates the need for an
extra winding on the transformer, which reduces cost
and minimizes the size of the transformer. Also, driving
the switches directly improves commutation efficiency
and commutation timing. Using MOSFETs for the
switches typically improves overall inverter efficiency
due to lower switch drops.
The Royer topology works as a zero voltage crossing
(ZVC) detector and switches currents between the two
sections of the transformer primary windings. The two
windings work alternately, each generating a half wave
that is transferred to the secondary to produce the full-
wave sinusoidal lamp voltage and current. The
MAX1739/MAX1839 detect the zero crossing through
the SYNC pin; the threshold is set at 500mV referred to
CS and has a typical delay of 50ns. The active switching forces commutation very close to the ZVC point and
has better performance than the traditional windingbased ZVC switchover. Commutation can be further
31
30
BRIGHTNESS CODE
See Digital Interface for instructions on using the
SMBus interface.
29
3
2
1
0
1
33
2
33
3
33
4
33
VCTL
VCRF
1
32
33
31
33
30
33
29
33
VCTL
VCRF
30
33
31
33
32
33
1
1
33
0
(MODE = GND)
3
33
2
33
(MODE = REF)
Figure 5. Brightness Code
______________________________________________________________________________________
15
MAX1739/MAX1839†
Table 3. Brightness Adjustment Ranges (for 33:1 Dimming)
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
VL
REF
T1
ADC-
L1
10k
MODE
LX
MAX1739
MAX1839
MAX1739
MAX1839
SMBus
ADC+
R14
SYNC
500pF
GND
DPWM
SYNCHRONIZATION
SIGNAL
R15
REF
R4
CTFB
Figure 6. DPWM Synchronization
GND
R5
optimized using R14 and R15 as shown in Figure 7.
The resistor-divider can be used to force commutation
as close to the zero-crossing point as possible.
POR and UVLO
The MAX1739/MAX1839 include power-on reset (POR)
and undervoltage lockout (UVLO) features. The POR
resets all internal registers, such as DAC output, fault
conditions, and all SMBus registers. POR occurs when
VL is below 1.5V. The SMBus input logic thresholds are
designed to meet electrical characteristic limits for VL
as low as 3.5V, but the interface will continue to function down to the POR threshold.
The UVLO threshold occurs when VL is below 4.2V
(typ) and disables the buck-switch driver.
Low-Power Shutdown
When the MAX1739/MAX1839 are placed in shutdown,
all IC functions are turned off except the 5V linear regulator that powers all internal registers and the SMBus
interface (MAX1739). The SMBus interface is accessible in shutdown. In shutdown, the linear regulator output voltage drops to about 4.5V and the supply current
is 6µA (typ), which is the required power to maintain all
internal register states. While in shutdown, lamp-out
detection and buck-switch short-circuit detection latches are reset. The device can be placed into shutdown
by either writing to the MODE register (MAX1739
SMBus mode only) or with SH/SUS.
Lamp-Out Detection
For safety, during a lamp-out condition, the MAX1739/
MAX1839 limit the maximum average primary-side
transformer voltage (see Sense Resistors) and shut
down the lamp after 2s.
16
Figure 7. Adjusting the ZVC Detection
The lamp-out detection circuitry monitors VCSAV and
shuts down the lamp if VCSAV does not exceed 75mV
(typ) within 2 seconds. This circuitry ignores most pulses under 200ns. However, in some cases, a small
capacitor is needed at CSAV to prevent noise from tripping the circuitry. This is especially true in noisy environments and in designs with marginal layout.
Ideally, the voltage at CSAV is a half-wave rectified sine
wave. In this case, the CSAV lamp-out threshold is as
follows:
IMIN = IMAX / 6
where IMIN is the CSAV lamp out threshold, and IMAX is
the maximum lamp current (see Sense Resistors). Note:
The formulas assume a worst-case CSAV lamp-out
threshold of 100mV and a maximum CSAV average
voltage of 200mV.
Use MINDAC or limit the brightness code to prevent
setting the lamp current below the CSAV lamp-out
threshold.
STATUS1 bit sets when the lamp-out detection circuit
shuts down the device.
Buck-Switch Short Fault Detection
and Protection
When the buck switch (N1) fails short, there is no voltage limiting on the transformer and the input forces
excessive voltage on the transformer secondary. This
______________________________________________________________________________________
Wide Brightness Range
CCFL Backlight Controllers
Both buck-switch short and lamp-out detection will
clear the STATUS1 bit in the SMBus interface. STATUS1 does not clear immediately but will clear about 2
seconds after the inverter has been forced off (see
Digital Interface).
Note that once the inverter board fuse has blown,
SMBus communications with the part will cease since
the MAX1739 will then be without power.
Applications Information
As shown in the standard application circuit (Figure 8),
the MAX1739/MAX1839 regulate the current of a 4.5W
CCFL. The IC’s analog voltage interface sets the lamp
brightness with a minimum 20:1 power adjustment
range. This circuit operates from a wide supply-voltage
range of 7V to 24V. Typical applications include notebook, desktop monitor, and car navigation displays.
CCFL Specifications
To select the correct component values for the
MAX1739/MAX1839 circuit, several CCFL parameters
(Table 4) and the minimum DC input voltage must be
specified.
Royer Oscillator
Components T1, C6, C7, N2A, and N2B form the Royer
oscillator. A Royer oscillator is a resonant tank circuit
that oscillates at a frequency dependent on C7, the primary magnetizing inductance of T1 (LP), and the
impedance seen by the T1 secondary. Figure 8 shows
VIN
(5V TO 28V)
BATT
CCV
C9
4.7μF
VL
C4
N1
DHI
C6
D2
C3
CCI
BST
C5
C2
MAX1739
MAX1839
L1
T1
LX
D1
REF
R4
C7
C1
VL
MINDAC
SYNC
MODE
CTFB
CRF/SDA
DL2
CTL/SCL
DL1
SH/SUS
GND
CS
R5
N2B
D5
DIMMING
ON/OFF
N2A
CSAV
R13
Figure 8. Standard Application Circuit
______________________________________________________________________________________
17
MAX1739/MAX1839†
increases the circuit’s demand for current but may not
be enough to blow the fuse. With the buck switch shorted, the center tap rises above its regulation point,
which causes the CCV amplifier’s output (VCCV) to go
low. To detect this, the MAX1739/MAX1839 check that
VCCV is below 1V at the end of every DPWM period. If
this condition persists for over 250ms (or 64 DPWM
pulses), the inverter switch commutation is stopped
with either DL1 or DL2 on. With the buck switch shorted, this will cause a short circuit with enough current to
blow the fuse. If the buck switch is not shorted, then the
inverter latches off as in a lamp-out condition.
MAX1739/MAX1839†
Wide Brightness Range
CCFL Backlight Controllers
a proven application that is useful for a wide range of
CCFL tubes and power ranges. Table 5 shows the recommended components for a 4.5W application.
MOSFETs
The MAX1739/MAX1839 require three external switches
to operate: N1, N2A, and N2B. N1 is the buck switch;
select a logic-level N-channel MOSFET with low RDSON
to minimize conduction losses (100mΩ, 30V typ). Also
select a comparable-power Schottky diode for D1.
N2A/N2B are the Royer oscillator switches that drive
the transformer primary; select a dual-logic-level Nchannel MOSFET with low RDSON to minimize conduction losses (100mΩ, 30V typ).
Sense Resistors
R4 and R5 sense the transformer’s primary voltage.
Figure 9 shows the relationship between the primary
and secondary voltage. To set the maximum average
secondary transformer voltage, set R5 = 10kΩ, and
select R5 according to the following formula:
⎛ 1.5VS(RMS) ⎞
R4 = R5 ⎜
− 1⎟
N
⎝
⎠
where VS is the maximum RMS secondary transformer
voltage (above the strike voltage), and N is the turns
ratio of the transformer.
Table 4. CCFL Specifications
SPECIFICATION
SYMBOL
UNITS
CCFL Minimum Strike
Voltage
(Kick-Off Voltage)
VS
VRMS
CCFL Typical Operating
Voltage
(Lamp Voltage)
VL
VRMS
CCFL Maximum Operating
Current (Lamp Current)
IL
mARMS
fL
kHz
CCFL Maximum Frequency
(Lamp Frequency)
DESCRIPTION
Although CCFLs typically operate at
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