MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
General Description
The MAX20743 is a fully integrated, highly efficient
switching regulator with PMBus™ for applications
operating from 4.5V to 16V and requiring up to 35A
maximum load. This single-chip regulator provides
extremely compact, high-efficiency power delivery
solutions with high-precision output voltages and excellent
transient response for networking, datacom and telecom
equipment.
The IC offers a broad range of programmable features
through either the PMBus or through a capacitor and
resistor connected to a dedicated programming pin.
Using this feature, the operation can be optimized for a
specific application, reducing the component count and/
or setting appropriate trade-offs between the regulator’s
performance and system cost. Ease of programming
enables using the same design for multiple applications.
The IC includes protection and telemetry features. Positive
and negative cycle-by-cycle overcurrent protection and
overtemperature protection ensure a rugged design. Input
undervoltage lockout shuts down the device to prevent
operation when the input voltage is out of specification.
A status pin provides an output signal to show that the
output voltage is within range and the system is regulating.
Benefits and Features
●● High-Power Density and Low Component Count
• Overall Solution Size 509mm2 Including Inductor
and Output Capacitors
• 90.8% Peak Efficiency with VDDH = 12V and
VOUT = 1V
• Fast Transient Response: Supports Up to 300A/μs
Load-Step Transients
●● Optimized Component Performance and Efficiency
with Reduced Design-In Time
• PMBus-Compliant Interface for Telemetry and
Power Management
• Voltage, Current and Temperature Reporting
through Digital Bus
●● Increased Power-Supply Reliability with System and
IC Self-Protection Features
• Differential Remote Sense with Open-Circuit
Detection
• Hiccup Overcurrent Protection
• Programmable Thermal Shutdown
Typical System Efficiency vs.
Load Current (VDDH = 12V)
Applications
95
Communication Equipment
Networking Equipment
Servers and Storage Equipment
Point-of-Load Voltage Regulators
μP Chipset
Memory VDDQ
I/O
DESCRIPTION
CURRENT
INPUT
RATING* VOLTAGE
90
85
EFFICIENCY (%)
●●
●●
●●
●●
●●
●●
●●
100
75
VOUT
Vout
= 5V= 5V
70
VOUT
= 3.3V
Vout
= 3.3V
VOUT
= 1.8V
Vout
= 1.8V
65
OUTPUT
VOLTAGE
Electrical Rating
35A
4.5V to 16V
0.6V to 5.5V
Thermal Rating
TA = 55°C, 200LFM
34A
12V
1V
Thermal Rating
TA = 85°C, 0LFM
22A
12V
1V
*For specific operating conditions, refer to the SOA curves in
the Typical Operating Characteristics section.
19-8582; Rev 1; 10/16
80
Vout
= 1.2V
VOUT
= 1.2V
Vout
= 1V= 1V
VOUT
60
Vout
= 0.8V
VOUT
= 0.8V
Vout
= 0.65V
VOUT
= 0.65V
55
50
0
5
10
15
20
IOUT (A)
25
30
35
Ordering Information appears at end of data sheet.
PMBus is a trademark of SMIF, Inc.
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Absolute Maximum Ratings
Input Pin Voltage (VDDH) (Note 1).........................-0.3V to +18V
VCC...........................................................................-0.3V to +2V
STAT, OE, CLK, DATA, and
SMALERT Pin Voltages........................................-0.3V to +4V
PGMA, PGMB, VSENSE+ and
VSENSE- Pin Voltages..........................................-0.3V to +2V
Switching Node Voltage (VX) DC...........................-0.3V to +18V
Switching Node Voltage (VX) 25ns (Note 2)...........-10V to +23V
(BST - VX) Pin Differential....................................-0.3V to +2.5V
Junction Temperature (TJ)................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Peak Reflow Temperature Lead-Free.............................. +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Operating Ratings
Input Voltage (VDDH)................................................. 4.5V to 16V
Junction Temperature (TJ)................................. -40°C to +125°C
Maximum Average Input Current (IVDDH) (Note 3)..................6A
Maximum Average Output Current (IOUT).............................35A
Peak Output Current (IPK)......................................................60A
Package Information
PACKAGE CODE
P154A8F+1
Outline Number
21-100031
Land Pattern Number
90-100022
THERMAL RESISTANCE, FOUR-LAYER BOARD
Junction to Ambient (θJA)
13°C/W
Junction to Case (θJC)
(Still Air, No Heatsink; Note 4)
0.47°C/W
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Note 1: As measured at the VDDH pin referenced to the GND pin immediatly adjacent using a high-frequency scope probe with ILOAD
at IMAX. A high-frequency input bypass capacitor must be located less than 60 mils from the VDDH pin per our design guidelines.
Note 2: The 25ns rating is the allowable voltage on the VX node in excess of the -0.3V to +18V DC ratings. The VX voltage can exceed
the DC rating in either the positive or negative direction for up to 25ns per cycle.
Note 3: See the Average Input Current Limit section.
Note 4: Data taken using the MAX20743 evaluation kit (MAX20743EVKIT#). The PCB has 4 layers of 2oz copper.
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Maxim Integrated │ 2
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics
(Circuit of Figure 6, VDDH = 4.5V to 16V, TA = +32°C, unless otherwise noted. Typical values are at TA = +32°C. All devices 100%
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16
V
5.5
V
SUPPLY VOLTAGE
Supply Voltage Range
VDDH
TJ = -40°C to +125°C
4.5
VOUT
(Note 6)
0.6
OUTPUT VOLTAGE (Note 5)
Output-Voltage Range
1
Default is 1mV/μs; other values are set
through PMBus; measured at VSENSE+/pins
Slew Rate when VOUT is
Changed through PMBus
2
mV/μs
4
VREF
0.6484
VBOOT Values
Selected by C_SELA (Note 7)
0.8984
V
1.0
VREF Tolerance
VREF
Values Available through PMBus
Command
Referred to
VSENSE+/- pins
(Notes 6, 8)
0.6484V VREF
-1.2
+1.2
0.8984V VREF
-1.0
+1.0
1V VREF
-1.0
+1.0
0.6016
1.0
See Table 8 for accuracy vs. VREF
(Note 7)
%
V
FEEDBACK LOOP
Integrator Recovery Time
Constant
Gain (see the Control Loop
section for details)
tREC
RGAIN
20
Selected by R_SELB or PMBus
(Notes 6, 7, 8, 9)
μs
0.72
0.9
1.1
1.4
1.8
2.2
2.9
3.6
4.4
mV/A
SWITCHING FREQUENCY
400
Switching Frequency
fSW
500
400kHz/600kHz/800kHz selected by C_
SELB; other values are set through PMBus
(Note 7)
600
kHz
700
800
900
Switching Frequency Accuracy
(Notes 6, 8, 9)
-15
+15
%
INPUT PROTECTION
VDDH UVLO Threshold (Rising)
VDDH UVLO Threshold (Falling)
Hysteresis
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VDDH_UVLO
(Note 6)
4.25
3.75
3.9
350
4.47
V
mV
Maxim Integrated │ 3
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics (continued)
(Circuit of Figure 6, VDDH = 4.5V to 16V, TA = +32°C, unless otherwise noted. Typical values are at TA = +32°C. All devices 100%
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
13
16
%
OUTPUT-VOLTAGE PROTECTION (OVP)
Overvoltage-Protection Threshold
(Rising)
OVP
Relative to programmed VOUT
OVP Deglitch Filter Time
8
Power-Good Protection Threshold
(Falling)
Power-Good Protection Threshold
(Rising)
Relative to programmed VOUT
PWRGD
µs
6
9
12
%
3
6
9
%
Power-Good Deglitch Filter Time
8
µs
OVERCURRENT PROTECTION (OCP)
Positive OCP Inception
Threshold (Inductor Valley
Current)
OCP Setting 0
11.8
18.9
26.0
Selected by R_SELB OCP Setting 1
or PMBus
(Notes 6, 7, 8, 9)
OCP Setting 2
16.0
24.1
32.2
19.8
29.2
38.6
OCP Setting 3
24.5
34.1
43.8
OCP
Negative OCP Inception
Threshold (Inductor Valley
Current)
Hysteresis
A
OCP Setting 0
-26.4
OCP Setting 1
Selected by R_SELB
or PMBus
OCP Setting 2
-31.3
OCP Setting 3
-40.8
A
-36.0
Hysteresis applies only to positive OCP
20
%
OVERTEMPERATURE PROTECTION (OTP)
OTP Inception Threshold
OTP
Default is 150°C; 130°C is set through
PMBus (Notes 7, 8, 9)
120
130
140
140
150
160
Hysteresis
°C
10
OE MAXIMUM VOLTAGE
OE Maximum Voltage
Rising Threshold
Hysteresis
OE
Full VCC supply range; measured at the
OE pin; keep OE ≤ VDDH – 2.5V and ≤
3.6V (Note 6)
OE Pin Input Resistance
OE Deglitch Filter Time
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3.6
0.83
0.97
V
350
kΩ
2.2
µs
0.2
200
(Note 9)
0.9
0.9
275
Maxim Integrated │ 4
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics (continued)
(Circuit of Figure 6, VDDH = 4.5V to 16V, TA = +32°C, unless otherwise noted. Typical values are at TA = +32°C. All devices 100%
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STARTUP TIMING
Enable Time from OE Rise to
Start of BST Charge
tOE
After tINIT
16
µs
0.75
Soft-Start Ramp Time
tSS
BST Charging Time
tBST
1.5
3ms or 1.5ms can be bet by R_SELA; any
value can be set by PMBus (Note 7)
ms
3
6
8
µs
STAT PIN
Pullup Voltage
Status Output Low
VOHSTAT
VOLSTAT
3.6
ISTAT = 2.5mA
0.4
ISTAT = 0.2mA, 0V < VCC < UVLO and
0V < VDDH < UVLO (Note 6)
0.65
ISTAT = 1.3mA, 0V < VCC < UVLO and
0V < VDDH < UVLO (Note 6)
0.75
Status Output High Leakage
Current
ISTAT
STAT pulled up to 3.3V through 20kΩ
(Note 6)
Time from VOUT Ramp
Completion to STAT Pin Released
tSTAT
STAT output low to high, default is 125;
2000 can be set through PMBus (Note 7)
7
125
V
V
µA
µs
2000
PGMA AND PGMB PINS (see Tables 2–5)
Allowable R_SEL Resistor Range
12 resistor values detected
R_SEL Resistor Required
Accuracy
EIA standard resistor values only
Allowable C_SEL Capacitor
Range
3 options (0pF, 220pF, or 1000pF)
C_SEL Capacitor Required
Accuracy
Use X7R or better
Allowable External Capacitance
Load and stray capacitance in addition to
C_SELA/B
1.78
162
±1
0
kΩ
%
1000
±20
pF
%
20
pF
PMBus TELEMETRY
Reading Range
Reading Update Interval
Reading Averaging Interval
Reading Error
Reading Resolution
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4.5
VDDH
Readback
TA = -40°C to TJ = 125°C (Notes 8, 9, 10)
16
V
5
ms
1
ms
-3
+3
28
%
mV
Maxim Integrated │ 5
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Electrical Characteristics (continued)
(Circuit of Figure 6, VDDH = 4.5V to 16V, TA = +32°C, unless otherwise noted. Typical values are at TA = +32°C. All devices 100%
tested at room temperature. Limits over temperature guaranteed by design.)
PARAMETER
SYMBOL
CONDITIONS
Reading Range
MIN
Reading Update Interval
Reading Averaging Interval
Reading Error Referred to SENSE
Pins (VOUT can be scaled by
divider in feedback)
Reading Error
TA = -40°C to TJ = +125°C (Notes 8, 9, 10)
Reading Error
ms
1
ms
+25
1.95
0
IOUT
Readback
TA = -40°C to TJ = +125°C (Notes 8, 9, 10)
Reading Range
Reading Averaging Interval
V
5
-25
Reading Resolution
Reading Update Interval
UNITS
1.25
mV
Reading Range
Reading Averaging Interval
MAX
VSENSE
Readback
Reading Resolution
Reading Update Interval
TYP
0
35
(Notes 6, 8, 9)
Reading Resolution
A
5
ms
1
ms
±3
A
0.07
A
-40
Temperature
Readback
mV
+125
°C
5
ms
1
ms
±8
°C
0.52
°C
PMBus PINS (CLK, DATA, SMALERT)
Input Rising Threshold
VT_RISE
0.83
0.9
0.97
V
Input Falling Threshold
VT_FALL
0.62
0.7
0.79
V
Hysteresis
VHYS
Output Low Voltage
PMBus Clock Frequency
VOL
0.2
Sinking 4mA
fPM_CLK
V
0.4
V
400
kHz
SYSTEM SPECIFICATIONS (Note 11)
Line Regulation
Load Regulation (Static)
Efficiency (VDDH = 12V,
VOUT = 1V)
VOUT
η
±0.2
IOUT = 0 - IMAX
±0.7
Peak
90.8
Full load (35A)
84
%
%
Note 5: For proper regulation, it is required that VDDH > (VOUT + 2V). If VOUT is set > (UVLO - 2V), the IC can come out of UVLO,
but regulation is not guaranteed while VDDH is below (VOUT + 2V). To avoid this condition, OE can be held low until VDDH >
(VOUT + 2V).
Note 6: Denotes specifications that apply over the temperature range of TJ = -40°C to +125°C.
Note 7: Denotes parameters that are programmable.
Note 8: Min/max limits are ≥ 4σ about the mean.
Note 9: Guaranteed by design; not production tested.
Note 10: A -40°C test condition is specified at a TA test condition, instead of TJ, to allow for self heating.
Note 11: These specifications refer to the operation of the system and are based on the circuit shown in the reference schematic.
Tolerance of external components can affect these parameters. System performance numbers are measured using the
Maxim evaluation board for this product with BOM as shown in the MAX20743 EV kit data sheet. If a different PCB layout
and different external components are used, these values can change.
www.maximintegrated.com
Maxim Integrated │ 6
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, VDDH = 12V, VOUT = 1V,
fSW = 400kHz, TA = +25°C, Still Air, and No Heatsink.)
STARTUP RESPONSE
TRANSIENT RESPONSE
toc01
toc02
IOUT (10A/div)
VX (20V/div)
VOUT (20mV/div)
STAT(2V/div)
VX (10V/div)
OE (2V/div)
VOUT (200mV/div)
TIME: 100µs/div
CONDITIONS: IOUT = 20A to 30A STEP at 1A/µs
TIME: 500µs/div
TYPICAL VOUT RIPPLE
toc03
VOUT (20mV/div)
VX (10V/div)
TIME: 2µs/div
CONDITIONS: IOUT = 35A
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Maxim Integrated │ 7
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics (continued)
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, VDDH = 12V, VOUT = 1V,
fSW = 400kHz, TA = +25°C, Still Air, and No Heatsink.)
SYSTEM EFFICIENCY vs. OUTPUT LOAD
100
LOAD REGULATION
toc04
VOUT = 5.5V
5.5V
95
VOUT = 1.8V
1.8V
0.2
LOAD REGULATION (%)
85
EFFICIENCY (%)
VOUT = 3.3V
3.3V
0.3
90
80
75
VOUT
Vout
= 5V= 5V
Vout
= 3.3V
VOUT
= 3.3V
70
60
-0.4
50
5
10
15
20
IOUT (A)
25
30
JUNCTION TEMPERATURE
vs. SYSTEM POWER DISSIPATION
0.0
-0.3
Vout
= 0.65V
VOUT
= 0.65V
0
VOUT = 0.65V
.65V
0.1
-0.2
Vout
= 1V= 1V
VOUT
Vout
= 0.8V
VOUT
= 0.8V
55
1VVOUT = 1V
-0.1
VOUT
= 1.8V
Vout
= 1.8V
Vout
= 1.2V
VOUT
= 1.2V
65
0
35
5
10
15
20
25
30
35
IOUT (A)
SYSTEM POWER DISSIPATION
toc06
120
toc07
9
8
SYSTEM POWER DISSIPATION (W)
100
JUNCTION TEMPERATURE (°C)
toc05
0.4
SLOPE = 13°C/W
80
60
40
20
VOUT
Vout
= 5V= 5V
Vout
= 3.3V
VOUT
= 3.3V
7
Vout
= 1.8V
VOUT
= 1.8V
Vout
= 1.2V
VOUT
= 1.2V
6
Vout
= 1V= 1V
VOUT
Vout
= 0.8V
VOUT
= 0.8V
5
Vout
= 0.65V
VOUT
= 0.65V
4
3
2
1
0
0
1
2
3
4
5
SYSTEM POWER DISSIPATION (W)
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6
0
0
5
10
15
20
25
30
35
IOUT (A)
Maxim Integrated │ 8
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics (continued)
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, VDDH = 12V, VOUT = 1V,
fSW = 400kHz, TA = +25°C, Still Air, and No Heatsink.)
SAFE OPERATING AREA (SOA)
35
35
30
30
25
25
20
20
15
15
Vout=0.8V
VOUT = 0.8V
Vout=1.2V
VOUT = 1.2V
10
5
VOUT = 5.0V
Vout=5.0V
0
30
40
30
60
70
80
90
100
TA (°C)
CONDITIONS: 200LFM
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX,
WHICHEVER HAPPENS FIRST
60
70
80
90
100
TA (°C)
CONDITIONS: 400LFM
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX,
WHICHEVER HAPPENS FIRST
40
VOUT = 5.0V
Vout=5.0V
0
50
SAFE OPERATING AREA (SOA)
Vout=0.8V
VOUT = 0.8V
Vout=1.2V
VOUT = 1.2V
Vout=3.3V
VOUT = 3.3V
10
VOUT = 3.3V
Vout=3.3V
5
toc10
40
50
SYSTEM EFFICIENCY
vs. OUTPUT LOAD (VDDH = 5V)
100
toc11
95
35
90
30
20
15
Vout=0.8V
VOUT = 0.8V
Vout=1.2V
VOUT = 1.2V
Vout=3.3V
VOUT = 3.3V
10
5
Vout=5.0V
VOUT = 5.0V
0
30
40
50
60
70
80
90
100
TA (°C)
CONDITIONS: STILL AIR / NO HEATSINK
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX,
WHICHEVER HAPPENS FIRST
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EFFICIENCY (%)
85
25
IOUT (A)
toc09
40
IOUT (A)
IOUT (A)
40
SAFE OPERATING AREA (SOA)
toc08
80
75
70
Vout
= 1.8V
VOUT
= 1.8V
Vout
= 1.2V
VOUT
= 1.2V
Vout
= 1V= 1V
VOUT
Vout
= 0.8V
VOUT
= 0.8V
Vout
= 0.65V
VOUT
= 0.65V
65
60
55
50
0
5
10
15
20
IOUT (A)
25
30
35
Maxim Integrated │ 9
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Typical Operating Characteristics (continued)
(Unless otherwise stated: Tested on the MAX20743EVKIT# EV kit with component values per Table 7, VDDH = 12V, VOUT = 1V,
fSW = 400kHz, TA = +25°C, Still Air, and No Heatsink.)
SYSTEM POWER DISSIPATION (VDDH = 5V)
7
toc13
40
35
6
Vout
= 1.8V
VOUT
= 1.8V
Vout
= 1.2V
VOUT
= 1.2V
Vout
= 1V
VOUT
= 1V
5
30
25
Vout
= 0.8V
VOUT
= 0.8V
Vout
= 0.65V
VOUT
= 0.65V
4
IOUT (A)
SYSTEM POWER DISSIPATION (W)
SAFE OPERATING AREA (SOA) (VDDH = 5V)
toc12
20
15
3
Vout=0.8V
VOUT = 0.8V
Vout=1.0V
VOUT = 1.0V
VOUT = 1.2V
Vout=1.2V
10
2
5
1
0
30
60
70
80
90
100
TA (°C)
CONDITIONS: 400LFM
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX,
WHICHEVER HAPPENS FIRST
0
0
5
10
15
20
25
30
35
IOUT (A)
SAFE OPERATING AREA (SOA) (VDDH = 5V)
50
SAFE OPERATING AREA (SOA) (VDDH = 5V)
toc14
40
35
35
30
30
25
25
IOUT (A)
IOUT (A)
40
40
20
15
Vout=0.8V
VOUT = 0.8V
Vout=1.0V
VOUT = 1.0V
VOUT = 1.2V
Vout=1.2V
10
5
toc15
20
15
Vout=0.8V
VOUT = 0.8V
Vout=1.0V
VOUT = 1.0V
VOUT = 1.2V
Vout=1.2V
10
5
0
0
30
40
50
60
70
80
90
100
TA (°C)
CONDITIONS: 200LFM
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX,
WHICHEVER HAPPENS FIRST
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30
40
50
60
70
80
90
100
TA (°C)
CONDITIONS: STILL AIR / NO HEATSINK
CURVE INDICATES TJ = 125°C, IOUT = IMAX, or IVDDH = IVDDH_MAX,
WHICHEVER HAPPENS FIRST
Maxim Integrated │ 10
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
PGMB
DATA
STAT
Pin Configuration
15
14
13
VSENSE+
1
12
CLK
VSENSE-
2
11
AGND
SMALERT
3
10
VCC
PGMA
4
9
OE
VDDH
5
8
BST
7
VX
GND
6
(TOP VIEW)
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Maxim Integrated │ 11
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Pin Description
PIN
NAME
FUNCTION
1
VSENSE+
Remote-Sense Positive Node. Connect this node to VOUT at the load. A resistive voltage divider can
be used to regulate the output above the reference voltage.
2
VSENSE-
Remote-Sense Negative Node. Connect this node to ground at the load using a Kelvin connection.
3
SMALERT
4
PGMA
Program Node. Connect this node to ground through a programming resistor and capacitor.
5
VDDH
Power Input Voltage. The high-side MOSFET switch is connected to this node. See the Input
Capacitor section for decoupling requirements.
6
GND
Power Ground Node. The low-side MOSFET switch is connected to this node.
7
VX
Power Switching Node. Connect this node to the inductor.
8
BST
Bootstrap for High-Side Switch. Connect a 0.22μF ceramic capacitor between BST and VX.
9
OE
Output-Enable Node. This node is used to enable the regulator and has a precise threshold to allow
sequencing of multiple regulators. There is an internal 275kΩ (typ) pulldown on this pin.
10
VCC
Analog/Gate-Drive Supply for the IC from Internal 1.85V (typ) LDO. This node must be connected
to three 10µF X5R or better decoupling capacitors with a very short, wide trace. VCC can be
connected to 20kΩ pullups for STAT and OE as shown in Figure 6. Do not connect VCC to other
external loads. Do not overdrive VCC from an external source.
11
AGND
SMALERT Pin
Analog/Signal Ground. See the PCB Layout section for layout information.
12
CLK
PMBus Clock
13
STAT
Open-Drain Power-Good/Fault-Status Indication. Connect a pullup resistor to 1.8V or 3.3V.
14
DATA
PMBus Data
15
PGMB
Program Node. Connect this node to ground through a programming resistor and capacitor.
www.maximintegrated.com
Maxim Integrated │ 12
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Block Diagram
VCC
tON
TIMER
STAT
LDO
VDDH
BST
R
OE
S
DIGITAL
CONTROL
POWER
SWITCHING
Q
VX
PGMA
CURRENT
SENSE
OCP
PGMB
GND
CLK
PMBus
INTERFACE
DATA
PWM
ERROR
AMP
VSENSE+
SMALERT
VCC
TELEMETRY
VCC
VCC
CURRENT DAC
VSENSE-
AGND
Operation
Control Architecture
The MAX20743 provides an extremely compact, highefficiency regulator solution with minimal external
components and circuit design required. The monolithic
solution includes the top and bottom power switches, gate
drives, precision DAC reference, PWM controller, fault
protections, and PMBus interface (see the Block Diagram).
An external bootstrap capacitor is used to provide the drive
voltage for the top switch. Other external components
include the input and output filter capacitors, buck
inductor, and a few resistors and capacitors to set the
operating mode.
The IC implements an advanced valley currentmode
control
algorithm
that
supports
all
multi-layer
ceramic chip (MLCC) output capacitors and fast
transient response. In steady-state, it operates
at a fixed switching frequency. When a positive load step is
applied to the output, the switching frequency speeds up to
minimize the output voltage undershoot. Similarly, when the
load step is removed, the switching frequency slows down to
minimize the output voltage overshoot.
www.maximintegrated.com
REFERENCE VOLTAGE AND SOFT-START
The switching frequency can be set to 400kHz, 600kHz,
or 800kHz through C_SELB and can be overridden
through PMBus to 400kHz, 500kHz, 600kHz, 700kHz,
800kHz, or 900kHz.
Voltage regulation is achieved by modulating the low-side
on-time, comparing the difference between the feedback
and reference voltages with the low-side current-sense
signal using Maxim’s proprietary integrated current-sense
technology. Once the PWM modulator forces a low-tohigh transition, the high-side switch is enabled for a fixed
time, after which the low-side switch is turned on again.
An error amplifier with an integrator is used to maintain
zero-droop operation. The integrator has a transient
recovery time constant of 20µs (typ).
During regulation, the differential voltage between the
VSENSE+ and VSENSE- pins tracks the reference voltage,
which is set by the DAC and can be set from 0.6016V
to 1V. The sense pins can be connected to the output
voltage through a voltage-divider, so VOUT can be higher
than 1V.
Maxim Integrated │ 13
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
The switching frequency is determined by the high-side
on-time, as shown in Equation 1.
Equation 1:
V
f SW =
x OUT
t H_ON
VDDH
1
where:
fSW = Switching frequency (MHz)
tH_ON = On-period for high-side switch (μs)
VOUT = Output voltage (V)
VDDH = Input voltage (V).
The tH_ON high-side on-time is controlled by the IC to
be proportional to the duty cycle so that the resulting
switching frequency is independent of supply voltage and
output voltage.
Equation 2:
t H_ON ∝
VOUT
VDDH
The tH_ON pulse width is clamped to a minimum of
50ns (after tSS) and a maximum of 2µs to prevent any
unexpected operation during extreme VOUT conditions.
Voltage-Regulator Enable and
Turn-On Sequencing
The startup timing is shown in Figure 1. After VDDH is
applied, the IC goes through an initialization time (tINIT)
that takes up to 308μs. After initialization, OE is read.
Once OE is high for more than the 16μs OE filter time
(tOE), BST charging starts and is performed for 8μs (tBST),
after which the soft-start ramp begins. The soft-start ramp
time (tSS) can be 0.75ms, 1.5ms, 3ms, or 6ms depending
on the user’s programmed value. VOUT ramps up linearly
during the soft-start ramp time. If there are no faults, the
STAT pin can transition high after the completion of the
soft-start ramp time, plus the STAT blanking time (tSTAT).
tSTAT is programmable with options of 125µs and 2ms. If
OE is pulled low, the IC shuts down.
Alternatively, the IC can be enabled by sending a PMBus
Operate command. This raises the internal Operate signal
that is OR’d with the OE pin to create an internal OE
signal. Therefore, when either the OE pin or the internal
Operate signal goes high, startup is initiated, but it takes
both to be low to shut the part down.
t INIT
VCC
SHUTDOWN
t OE
OE or OPERATE
t BST
VOUT
t SS
STAT
t STAT
t INIT : Initialization, 308µs
t OE
: OE enable f ilter time, 16µs. If OE enabled earlier than tINIT completion, it is ignored until tINIT completes.
t BST : BST charging time, 8µs
t SS
: Sof t-start time per user selection,
u 0.75ms – 6ms
t STAT : STAT blanking time, 2ms or 125µs through user selection
Figure 1. Startup Timing
www.maximintegrated.com
Maxim Integrated │ 14
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Soft-Start Control
The initial output voltage behavior is determined by a
linear ramp of the internal reference voltage from zero to
the final value (tSS in Figure 1). The ramp time (tSS) is
programmable from 0.75ms to 6ms.
If the regulator is enabled when the output voltage has
a residual voltage, the system does not regulate until
the reference voltage ramps above this residual value.
In this case, the tOE (OE valid to onset of regulation)
specification is extended by the time required for the
desired voltage startup ramp to reach the actual residual
output voltage, but the time to reach the steady-state
output voltage is unchanged.
If the residual voltage is higher than the set output
voltage, neither the high-side or low-side switch is turned
on by the end of tSS. Under these conditions, switching
begins after tSS.
The MAX20743 exhibits a 400mV (typ) non-linearity
during startup when RGAIN is set to 1.8mV/A or 3.6mV/A.
This behavior is normal and does not have an adverse
effect on system operation. For best startup linearity,
an RGAIN of 0.9mV/A is recommended. See Startup
Response in Typical Operating Characteristics.
Remote Output-Voltage Sensing
To ensure accurate sensing of the output
voltage, a differential voltage-sense topology is used,
with a negative remote-sense pin provided. Point-of-load
(PoL) sensing compensates for voltage drops between
the output of the regulator and its load and provides the
highest regulation accuracy. The voltage-sensing circuit
features excellent common-mode rejection to further
improve load voltage regulation.
Protection and Status Operation
Output-Voltage Protection
The feedback voltage is continuously monitored for both
undervoltage and overvoltage conditions. The typical
fault-detection threshold is 13% above and 9% below
the reference voltage (see the Electrical Characteristics
table). If the output voltage falls below the power-good
protection (PWRGD) threshold beyond the filter time,
the STAT output goes low but the system continues to
operate, attempting to maintain regulation.
If the output voltage rises above the overvoltageprotection (OVP) threshold beyond the filter time, the
STAT pin is lowered and the system shuts down until the
output voltage falls within the valid range.
Current-Limiting and Short-Circuit Protection
The regulator’s valley current-mode control architecture
provides inherent current limiting and short-circuit
protection. The bottom switch’s instantaneous current
is monitored using integrated current sensing and is
controlled on a cycle-by-cycle basis within the control
block.
Current clamping occurs when the minimum instantaneous
(“valley”) low-side switch current level exceeds the
OCP threshold current, as shown in Figure 2. In this
situation, turn-on of the high-side switch is prevented
until the current falls below the threshold level. Since
the inductor valley current is the controlled parameter,
the average current delivered during positive current
clamping remains a function of several system-level
parameters. Note that IOCP has hysteresis and the value
drops down to IOCP2 once it has been triggered, as
shown in Figure 2.
IOCP(AVG)
IOCP
IOCP2
I
L
IOCP(AVG) = IOCP2 +
1
2
( VDDH VOUT ) x
tH_ON
LOUT
where:
IOCP2 = IOCP - Hysteresis
Figure 2. Inductor Current During Current Limiting
www.maximintegrated.com
Maxim Integrated │ 15
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Undervoltage Lockout (UVLO)
Regulator Status (STAT)
Overtemperature Protection (OTP)
The STAT pin is low while the regulator is disabled and
goes high after the startup ramp is completed, plus the
programmed tSTAT blanking interval if the output voltage
is within the PWRGD/OVP regulation window. The STAT
pin is an open-drain output and is 3.3V tolerant. The pin
remains low when VDDH is not present.
Table 1. Summary of Fault Actions
Table 3. PGMA Pin C_SELA Capacitor
Values
The regulator internally monitors VDDH with a UVLO
circuit. When the input supply voltage is below the UVLO
threshold, the regulator stops switching, and the STAT
pin is driven low. For UVLO levels, see the Electrical
Characteristics table.
The OTP-level default is 150°C and can be set to 130°C
over PMBus. If the die temperature reaches the OTP level
during operation, the regulator is disabled and the STAT pin
is driven low. Overtemperature is a nonlatching fault, with
the hysteresis shown in the Electrical Characteristics table.
FAULT
ACTION
Power good
(output undervoltage)
STAT low
Output OVP
STAT low,
shut down and restart
Overtemperature
STAT low,
shut down and restart
Supply fault
(VDDH_UVLO; VCC_UVLO)
STAT low,
shut down and restart
BST fault
STAT low,
shut down and restart
Table 2. PGMA Pin R_SELA Values
The STAT signal provides an open-drain output,
consistent with CMOS logic levels, which indicates
whether the regulator is functioning properly. An external
pullup resistor is required for connecting STAT to VCC or
another 1.8V or 3.3V supply.
NO.
C (pF) ±20%
V BOOT (V)
1
Open
0.6484
2
220
0.8984
3
1000
1
Table 4. PGMB Pin R_SELB Values
NO.
R (kΩ) ±1%
R GAIN (mΩ)
OCP (A)
1
1.78
3.6
20
2
2.67
3.6
25
3
4.02
3.6
30
4
6.04
3.6
35
NO.
R (kΩ)
±1%
SOFT-START
TIME (mS)
PMBus SLAVE
ADDRESS (1010_xxx)
5
9.09
1.8
20
6
13.3
1.8
25
1
1.78
3
1010 000b
7
20
1.8
30
2
2.67
3
1010 001b
8
30.9
1.8
35
3
4.02
3
1010 010b
9
46.4
0.9
20
4
6.04
3
1010 011b
10
71.5
0.9
25
5
9.09
3
1010 100b
11
107
0.9
30
6
13.3
3
1010 101b
12
162
0.9
35
7
20
3
1010 110b
8
30.9
3
1010 111b
9
46.4
1.5
1010 000b
10
71.5
1.5
1010 001b
11
107
1.5
1010 010b
12
162
1.5
1010 011b
www.maximintegrated.com
Table 5. PGMB Pin C_SELB Capacitor
Values
NO.
C (pF) ±20%
fSW FREQUENCY (kHz)
1
Open
400
2
220
600
3
1000
800
Maxim Integrated │ 16
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
The STAT pin is driven low when one or more of the
following conditions exists:
●●
●●
●●
PWRGD fault (see the Output-Voltage Protection section).
VSENSE- pin is left unconnected or shorted to VDDH.
Die temperature exceeds the temperature shutdown
threshold shown in the Electrical Characteristics table.
●● OVP circuit detects that the output voltage is above
the tolerance limit.
●● Supply voltage drops below the UVLO threshold.
●● Fault is detected on the BST node, such as a
shorted or open bootstrap capacitor.
The ensuing startup follows the same timing shown in
Figure 1.
PGMA and PGMB Pin Functionality
The PGMA and PGMB pins are used to set up some of
the key programmable features of the regulator IC. A
resistor and capacitor are connected to the PGMA/B pins
and their values are read during power-up initialization.
Power must be cycled to re-read the values.
PMBus Commands
A summary of PMBus commands is shown in Table 6. For
more information, refer to AN6042: MAX20743 PMBus
Application Note.
PMBus Telemetry
The IC provides input voltage, output voltage, output
current, and junction temperature telemetry. Output
voltage is measured at the VSENSE+/- pins; therefore,
if there is a divider in the feedback, the measurement
is scaled by the divide ratio. For range and accuracy
specifications, see the Electrical Characteristics table.
For data format, refer to AN6042: MAX20743 PMBus
Application Note.
Table 6. PMBus Command List
COMMAND
CODE
COMMAND NAME
TYPE
NO. OF
DATA
BYTES
COMMAND
CODE
COMMAND NAME
TYPE
NO. OF
DATA
BYTES
01h
OPERATION
RW
1
7Dh
STATUS_TEMPERATURE
RO
1
02h
ON_OFF_CONFIG
RO
1
7Eh
STATUS_CML
RO
1
03h
CLEAR_FAULTS
WO
0
80h
STATUS_MFR_SPECIFIC
RO
1
10h
WRITE_PROTECT
RW
1
88h
READ_VIN
RO
2
1Bh
PMBALERT_MASK
RW
2
8Bh
READ_VOUT
RO
2
20h
VOUT_MODE
RO
1
8Ch
READ_IOUT
RO
2
21h
VOUT_COMMAND
RW
2
8Dh
READ_TEMPERATURE_1
RO
2
24h
VOUT_MAX
RW
2
99h
MFR_ID
BLK
4
78h
STATUS_BYTE
RO
1
9Bh
MFR_REVISION
BLK
1
79h
STATUS_WORD
RO
2
D1h
MFR_VOUT_MIN
RW
2
7Ah
STATUS_VOUT
RO
1
D2h
MFR_DEVSET1
RW
2
7Bh
STATUS_IOUT
RO
1
D3h
MFR_DEVSET2
RW
2
7Ch
STATUS_INPUT
RO
1
www.maximintegrated.com
Note: RW = Read/Write, WO = Write Only, RO = Read Only,
and BLK = Block.
Maxim Integrated │ 17
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Reference Design
Equation 3:
A typical application schematic is shown in Figure 3, while
Table 7 shows optimum component values for common
output voltages.
I VDDH =
VOUT × I OUT
VDDH × η
where:
Average Input Current Limit
VOUT = Output Voltage
The input current of VDDH is given by Equation 3. VOUT,
IOUT, and VDDH should be properly chosen so that the
IOUT = Output Current
VDDH = Input Voltage
average input current does not exceed 6A (IVDDH_MAX).
η = Efficiency (refer to the Typical Operating Characteristics
section.)
VDDH
CVCC
CIN
VCC
1.8V or 3.3V
U1
MAX20743
RSTAT
CBST
BST
STAT
1.8V or 3.3V
COMPLIANT I/O
VDDH
OE
STAT
OE
CLK
DATA
CLK
DATA
SMALERT
LOUT
VOUT
VX
SMALERT
RFB1
VSENSE+
VSENSE-
PGMA
PGMB
GND
AGND
R_SELA
C_SELA
COUT
RFB2
C_SELB
R_SELB
Figure 3: Typical Application Circuit
Table 7. Reference Design Component Values
VOUT
(V)
RFB1
(kΩ)
RFB2 R_SELA C_SELA R_SELB
(kΩ)
(kΩ)
(pF)
(kΩ)
C_SELB
(pF)
RGAIN
(mΩ)
VREF
(V)
fSW
(kHz)
LOUT
(nH)
COUT
0.6484
1
Open
1.78
Open
162
Open
0.9
0.6484
400
170
6 x 100μF + 2 x 470μF
0.8
1.37
5.9
1.78
Open
162
Open
0.9
0.6484
400
170
6 x 100μF + 2 x 470μF
1
1.87
3.48
1.78
Open
162
Open
0.9
0.6484
400
170
6 x 100μF + 2 x 470μF
1.2
1.74
2.05
1.78
Open
162
Open
0.9
0.6484
400
170
6 x 100μF + 2 x 470μF
1.8
3.09
1.74
1.78
Open
162
220
0.9
0.6484
600
170
6 x 100μF + 2 x 470μF
3.3
5.62
1.37
1.78
Open
71.5
220
0.9
0.6484
600
210
6 x 100μF + 2 x 470μF
5.0
7.15
1.07
1.78
Open
71.5
220
0.9
0.6484
600
210
6 x 100μF + 2 x 470μF
www.maximintegrated.com
Maxim Integrated │ 18
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Output-Voltage Setting
Equation 4:
If an output voltage not listed in Table 7 is required,
calculate new values for RFB1 and RFB2 (as discussed
below) and use the other circuit values of the closest
output voltage in Table 7, or calculate them as shown
below.
The output voltage is set by the VREF DAC and divider
ratio of resistors RFB1 and RFB2 per Equation 4. The
IC regulates the VSENSE+ pin to the reference voltage
(VREF), which is set by the DAC. Upon power-up, the DAC
voltage initializes to one of the user-selectable VBOOT
voltages. Using PMBus, the DAC can also be set to any
voltage from 0.6016V to 1V with 3.9mV resolution, as
shown in Table 8. The divider resistors are chosen to give
the correct output voltage and to have an approximate
parallel resistance of RPAR = 1kΩ for best commonmode rejection of the error amplifier. In applications
requiring less than 10mV peak-to-peak output voltage
ripple, setting a lower DAC reference voltage such as
0.6484V or less is recommended because the part will
have less DAC voltage noise.
R
VOUT VREF x 1 + FB1
=
R
FB2
where VREF = 0.6016V to 1V (set by DAC).
The divider resistors are then given by Equation 5.
Equation 5:
R
R FB1 = VOUT x PAR
VREF
R PAR
R FB2 = R FB1 x
R FB1 − R PAR
where:
RFB1 = Top divider resistor
RFB2 = Bottom divider resistor
RPAR = Desired parallel resistance of RFB1 and RFB2
VOUT = Output voltage
VREF = Reference voltage = 0.6016V to 1V (set by DAC).
Table 8. Voltage vs. PMBus VOUT_COMMAND
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
307
0.6016
1.3%
324
0.6328
1.2%
341
0.6680
1.2%
308
0.6016
1.3%
325
0.6367
1.2%
342
0.6680
1.2%
309
0.6055
1.3%
326
0.6367
1.2%
343
0.6719
1.2%
0.6406
1.2%
310
0.6055
1.3%
327
344
0.6719
1.2%
311
0.6094
1.3%
328
0.6406
1.2%
345
0.6758
1.2%
312
0.6094
1.3%
329
0.6445
1.2%
346
0.6758
1.2%
313
0.6133
1.3%
330
0.6445
1.2%
347
0.6797
1.2%
314
0.6133
1.3%
331
0.6484
1.2%
348
0.6797
1.2%
0.6484
1.2%
315
0.6172
1.3%
332
349
0.6836
1.2%
316
0.6172
1.3%
333
0.6523
1.2%
350
0.6836
1.2%
317
0.6211
1.3%
334
0.6523
1.2%
351
0.6875
1.1%
318
0.6211
1.3%
335
0.6563
1.2%
352
0.6875
1.1%
319
0.6250
1.3%
336
0.6563
1.2%
353
0.6914
1.1%
0.6602
1.2%
320
0.6250
1.3%
337
354
0.6914
1.1%
321
0.6289
1.2%
338
0.6602
1.2%
355
0.6953
1.1%
322
0.6289
1.2%
339
0.6641
1.2%
356
0.6953
1.1%
323
0.6328
1.2%
340
0.6641
1.2%
357
0.6992
1.1%
www.maximintegrated.com
Maxim Integrated │ 19
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Table 8. Voltage vs. PMBus VOUT_COMMAND (continued)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
358
0.6992
1.1%
393
0.7695
1.0%
428
0.8359
1.0%
359
0.7031
1.1%
394
0.7695
1.0%
429
0.8398
1.0%
360
0.7031
1.1%
395
0.7734
1.0%
430
0.8398
1.0%
361
0.7070
1.1%
396
0.7734
1.0%
431
0.8438
1.0%
362
0.7070
1.1%
397
0.7773
1.0%
432
0.8438
1.0%
363
0.7109
1.1%
398
0.7773
1.0%
433
0.8477
1.0%
364
0.7109
1.1%
399
0.7813
1.0%
434
0.8477
1.0%
365
0.7148
1.1%
400
0.7813
1.0%
435
0.8516
1.0%
366
0.7148
1.1%
401
0.7852
1.0%
436
0.8516
1.0%
367
0.7188
1.1%
402
0.7852
1.0%
437
0.8555
1.0%
368
0.7188
1.1%
403
0.7891
1.0%
438
0.8555
1.0%
369
0.7227
1.1%
404
0.7891
1.0%
439
0.8594
1.0%
370
0.7227
1.1%
405
0.7930
1.0%
440
0.8594
1.0%
371
0.7266
1.1%
406
0.7930
1.0%
441
0.8633
1.0%
372
0.7266
1.1%
407
0.7969
1.0%
442
0.8633
1.0%
373
0.7305
1.1%
408
0.7969
1.0%
443
0.8672
1.0%
374
0.7305
1.1%
409
0.8008
1.0%
444
0.8672
1.0%
375
0.7344
1.1%
410
0.8008
1.0%
445
0.8711
1.0%
376
0.7344
1.1%
411
0.8047
1.0%
446
0.8711
1.0%
377
0.7383
1.1%
412
0.8047
1.0%
447
0.8750
1.0%
378
0.7383
1.1%
413
0.8086
1.0%
448
0.8750
1.0%
379
0.7422
1.1%
414
0.8086
1.0%
449
0.8789
1.0%
380
0.7422
1.1%
415
0.8125
1.0%
450
0.8789
1.0%
381
0.7461
1.1%
416
0.8125
1.0%
451
0.8828
1.0%
382
0.7461
1.1%
417
0.8164
1.0%
452
0.8828
1.0%
383
0.7500
1.1%
418
0.8164
1.0%
453
0.8867
1.0%
384
0.7500
1.1%
419
0.8203
1.0%
454
0.8867
1.0%
385
0.7539
1.1%
420
0.8203
1.0%
455
0.8906
1.0%
386
0.7539
1.1%
421
0.8242
1.0%
456
0.8906
1.0%
387
0.7578
1.1%
422
0.8242
1.0%
457
0.8945
1.0%
388
0.7578
1.1%
423
0.8281
1.0%
458
0.8945
1.0%
389
0.7617
1.1%
424
0.8281
1.0%
459
0.8984
1.0%
390
0.7617
1.1%
425
0.8320
1.0%
460
0.8984
1.0%
391
0.7656
1.0%
426
0.8320
1.0%
461
0.9023
1.0%
392
0.7656
1.0%
427
0.8359
1.0%
462
0.9023
1.0%
www.maximintegrated.com
Maxim Integrated │ 20
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Table 8. Voltage vs. PMBus VOUT_COMMAND (continued)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
VOUT
COMMAND
[9:0]
(decimal)
VOLTAGE
(V)
ACCURACY
(+/-)
463
0.9063
1.0%
480
0.9375
1.0%
497
0.9727
1.0%
464
0.9063
1.0%
481
0.9414
1.0%
498
0.9727
1.0%
465
0.9102
1.0%
482
0.9414
1.0%
499
0.9766
1.0%
466
0.9102
1.0%
483
0.9453
1.0%
500
0.9766
1.0%
467
0.9141
1.0%
484
0.9453
1.0%
501
0.9805
1.0%
468
0.9141
1.0%
485
0.9492
1.0%
502
0.9805
1.0%
469
0.9180
1.0%
486
0.9492
1.0%
503
0.9844
1.0%
470
0.9180
1.0%
487
0.9531
1.0%
504
0.9844
1.0%
471
0.9219
1.0%
488
0.9531
1.0%
505
0.9883
1.0%
472
0.9219
1.0%
489
0.9570
1.0%
506
0.9883
1.0%
473
0.9258
1.0%
490
0.9570
1.0%
507
0.9922
1.0%
474
0.9258
1.0%
491
0.9609
1.0%
508
0.9922
1.0%
475
0.9297
1.0%
492
0.9609
1.0%
509
0.9961
1.0%
476
0.9297
1.0%
493
0.9648
1.0%
510
0.9961
1.0%
477
0.9336
1.0%
494
0.9648
1.0%
511
1.0000
1.0%
478
0.9336
1.0%
495
0.9688
1.0%
512
1.0000
1.0%
479
0.9375
1.0%
496
0.9688
1.0%
—
—
—
Note: The repeated voltage values in the table are due to ignoring the LSB in hardware. The available VBOOT values are highlighted
in gray. Voltages shown are referenced to the sense pins. Actual VOUT can be scaled by a voltage-divider in the feedback.
www.maximintegrated.com
Maxim Integrated │ 21
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Control-Loop Stability
The IC uses valley current-mode control which is stabilized
by selecting appropriate values of COUT and RGAIN. No
compensation network is required. For stability, the loop
bandwidth (BW) should be 100kHz or less. Consider the
case of using MLCC output capacitors that have nearly
ideal impedance characteristics in the frequency range of
interest with negligible ESR and ESL. The loop bandwidth
can be approximated by breaking the loop into gain terms
as outlined below.
The voltage-loop gain consists of the following terms:
1) The IC’s valley current-mode control scheme has an
effective transconductance gain of 1/RGAIN.
2) For MLCC capacitors, the output capacitors contribute
an impedance gain of 1/(2 x π x COUT x f).
3) The feedback-divider contributes an attenuation of
KDIV = RFB2/(RFB1 + RFB2).
4) An inherent high-frequency pole located at 150kHz
independent of switching frequency.
When the BW is 100kHz or less, the high-frequency pole
can be ignored and the approximate loop gain and BW are
given by Equation 6.
Equation 6:
K DIV
2 x π x R GAIN x C OUT x f
K DIV
BW =
2 x π x R GAIN x C OUT
LOOP_GAIN(f ) =
OR
BW =
significantly affect the loop BW calculation. The purpose
of the integrator is to improve load regulation. The
integrator adds a factor of (1/tREC + s)/s to the loop gain.
Step Response
RGAIN_EFF is important since it determines the smallsignal transient response of the regulator. When a
load step is applied that does not exceed the slew-rate
capability of the inductor current, the regulator responds
linearly and VOUT temporarily changes by the amount of
VOUT_ERROR (Equation 7).
Equation 7:
VOUT_ERROR = I STEP x R GAIN_EFF
The integrator causes VOUT to recover to the nominal
value with a time constant of tREC = 20μs. The regulator
can be modeled to a first-order by the averaged smallsignal equivalent circuit shown in Figure 4. Here, VEQ is
an ideal voltage source, REQ is an equivalent lossless
resistance created by the control-loop action, and LEQ is
an equivalent inductance. Note that LEQ is not the same
as the actual LOUT inductor that has been absorbed into
the model. COUT is the actual output capacitance.
Output-Capacitor ESR
The preceding control-loop discussion considered
the use of MLCC output capacitors. Another
application worth mentioning is the use of output
tREC RGAIN_EFF
1
2 x π x R GAIN_EFF x C OUT
LEQ
where:
RGAIN_EFF
RGAIN_EFF = RGAIN/KDIV.
For stability, RGAIN and COUT should be chosen so that
BW < 100kHz.
The available RGAIN settings are shown in Table 4. When
choosing which RGAIN setting to use, one should consider
that while higher RGAIN allows the loop to be stabilized
with less COUT; less COUT generally results in higher
ripple and larger transient overshoot and undershoot, so
there needs to be a balance.
Integrator
The IC has an integrator included in its error amplifier that
was ignored in the above equations for simplicity. The
integrator only adds gain at low frequencies, so it does not
www.maximintegrated.com
VOUT
REQ
COUT
VOUT
VEQ
GND
Figure 4. Averaged Small-Signal Equivalent Circuit of Regulator
Note: The large-signal transient response is approximately the
larger between the VOUT_ERROR and the Unloading Transient
(see Equation 16).
Maxim Integrated │ 22
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
capacitors with more significant ESR. This can be
considered as long as the capacitors are rated to handle
the inductor current ripple and expected surge currents.
Thus far, it has been assumed that COUT is comprised
of MLCCs and the net ESR is negligible compared to
RGAIN/KDIV. If the net ESR of the COUT bank is not
negligible compared to RGAIN/KDIV, the inductor current
ripple is effectively sensed by the ESR and adds to the
RGAIN_EFF, as shown in Equation 8.
Equation 8:
R GAIN_EFF
=
R GAIN
+ ESR
K DIV
The capacitor’s ESR also introduces a zero into the loop
gain. The inherent high-frequency pole helps to compensate
this zero. For a more in-depth view of the effect of
circuit values on regulator performance, the Maxim
Simplis model and the MAX20743 evaluation kit can
be used. It is recommended to simulate and/or test
regulator performance when using values other than the
recommended component values.
The performance data shown in the Typical Operating
Characteristics section was taken using the MAX20743
evaluation kit and component values in Table 7. For most
applications, these are the optimum values to use. Table 9,
Table 10, and Table 11 show suitable part numbers for
input and output capacitors and the inductor.
Table 9. Recommended Inductors
COMPANY
VALUE
(nH)
I SAT
(A)
R DC
(mΩ)
FOOTPRINT
(mm)
HEIGHT
(mm)
PART NUMBER
WEBSITE
Cooper
170
60
0.29
10.4 x 8.0
7.5
FP1007R3-R17-R
www.cooperindustries.com
Pulse
210
64
0.32
13.5 x 13.0
8.0
PA0513.211NLT
www.pulseelectronics.com
Pulse
260
55
0.32
13.5 x 13.0
8.0
PA0513.261NLT
www.pulseelectronics.com
Pulse
320
45
0.32
13.5 x 13.0
8.0
PA0513.321NLT
www.pulseelectronics.com
Pulse
440
30
0.32
13.5 x 13.0
8.0
PA0513.441NLT
www.pulseelectronics.com
Table 10. MLCC Input Capacitors
CASE SIZE
VALUE
(µF)
TEMPERATURE
RATING
VOLTAGE
RATING
Τ (Note 1)
(mm)
0603
1
X7S
X7R
16V
0.8
(Note 2)
Murata
TDK
GRM188C71C105KA12D
C1608X7R1C105K
0805
2.2
X7R
25V
16V
16V
1.25
1.25
1.25
Murata
TDK
AVX
GRM21BR71E225KA73L
C2012X7R1C225M
0805YC225MAT
0805
4.7
X7R
16V
1.25
Murata
GRM21BR71C475K
1206
4.7
X7R
16V
1.65
AVX
Murata
1206YC475MAT
GRM31CR71C475KA01L
1206
10
X7R
16V
1.65
Murata
TDK
AVX
GRM31CR71C106KAC7L
C3216X7R1C106M
1206YC106MAT
1210
10
X7R
16V
25V
2.0
2.5
Murata
TDK
GRM32DR71C106KA01L
C3225X7R1E106M
1210
22
X7R
16V
2.45
2.5
2.5
AVX
Murata
TDK
1210YC226MAT
GRM32ER71A476K
C3225X7R1C226M
COMPANY
PART NUMBER
Note 1: Τ indicates nominal thickness.
Note 2: Indicates capacitors with nominal thickness smaller than the minimum FCQFN package thickness.
www.maximintegrated.com
Maxim Integrated │ 23
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Table 11. Recommended Output Capacitors
COMPANY
VALUE
(ΜF)
PART NUMBER
TEMP.
VOLT. CASE
RATING RATING SIZE
Τ (NOTE 1)
(mm)
WEBSITE
AVX
22
22
08054D226MAT2A
12066D226MAT2A
X5R
X5R
4V
6.3V
0805
1206
1.3
1.65
www.avxcorp.com
Murata
22
22
22
GRM21BR60J226ME39L
GRM31CR60J226KE19L
GRM32DR60J226KA01L
X5R
X5R
X5R
6.3V
6.3V
6.3V
0805
1206
1210
1.25
1.6
2.0
www.murata.co.jp
Panasonic
22
22
22
ECJ3YB0J226M
ECJHVB0J226M
ECJ3Y70J226M
X5R
X5R
X7R
6.3V
6.3V
6.3V
1206
1206
1206
1.6
0.85
1.65
www.panasonic.com
Taiyo Yuden
22
22
22
AMK212BJ226MG JMK316BJ226ML
JMK325BJ226MY
X5R
X5R
X5R
4V
6.3V
6.3V
0805
1206
1210
1.25
1.6
1.9
www.taiyo-yuden.com
TDK
22
22
22
22
C2012X5R0J226M
C3216X5R0J226M
C3225X5R0J226M
C3216X6S0J226M
X5R
X5R
X5R
X6S
6.3V
6.3V
6.3V
6.3V
0805
1206
1210
1206
1.25
1.6
1.6
1.6
www.component.tdk.com
Note 1: Τ indicates nominal thickness.
Inductor Selection
The output inductor has an important influence on
the overall size, cost, and efficiency of the voltage
regulator. Since the inductor is typically one of the larger
components in the system, a minimum inductor value is
particularly important in space-constrained applications.
Smaller inductor values also permit faster transient
response, reducing the amount of output cap needed to
maintain transient tolerances.
sufficient charge to maintain regulation while the inductor
current ramps up to supply the load.
In contrast, smaller inductor values increase the
regulator’s maximum achievable slew rate and decrease
the necessary capacitance, at the expense of higher
ripple current. The peak-to-peak ripple current is given by
Equation 10.
Equation 10:
For any buck regulator, the maximum current slew rate
through the output inductor is given by Equation 9.
Equation 9:
dIL
VL
SlewRate
= =
dt
L OUT
where:
IL = Inductor current
LOUT = Output inductance
VL = VDDH - VOUT during high-side FET conduction and
-VOUT during low-side FET conduction.
Equation 9 shows that larger inductor values limit the
regulator’s ability to slew current through the output
inductor in response to step-load transients. Consequently,
more output capacitors are required to supply (or store)
www.maximintegrated.com
I OUTRIPPLE =
t H_ON x ( VIN − VOUT )
L OUT
where:
tH_ON = High-side switch on-time (based on nominal
VOUT) (see Equation 1)
LOUT = Output inductance
VDDH = Input voltage
VOUT = Output voltage.
From Equation 10, for the same switching frequency,
ripple current increases as L decreases. This increased
ripple current results in increased AC losses, larger peak
current, and for the same output capacitance, results in
increased output voltage ripple.
Maxim Integrated │ 24
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
IOUTRIPPLE should be set to 25% to 50% of the IC’s
rated output current. A suitable inductor value can then
be found by solving Equation 10 for inductance as in
Equation 11 and Equation 12.
Equation 11:
LOUT =
VOUT × ( VDDH − VOUT )
VDDH ×IOUTRIPPLE × fSW
And assuming IOUTRIPPLE = 0.25 x IOUT for a typical
inductor value (Equation 12).
Equation 12:
L OUT =
VOUT x (VDDH − VOUT )
VDDH x (0.25 x I OUT ) x f SW
So, for a 35A regulator running at 400kHz with VDDH =
12V and VOUT = 1V, Equation 13 shows the target value
for the inductor.
Equation 13:
1 x (12 − 1)
12 x 0.25 x 35 x 400000
= 262nH
L OUT =
The saturation current rating of the inductor is another
important consideration. At current limit, the peak inductor
current is given Equation 14
Equation 14:
=
IPK I OCP + I OUTRIPPLE
where:
IOCP = Overcurrent-protection trip point (see the Electrical
Characteristics table and the Current-Limiting and ShortCircuit Protection section).
Also, note that during a hard VOUT short circuit,
IOUTRIPPLE increases due to VOUT going to zero in
Equation 10.
Finally, the power dissipation of the inductor influences
the regulation efficiency. Losses in the inductor include
core loss, DC resistance loss, and AC resistance loss.
For the best efficiency, use inductors with core material
exhibiting low loss in the range of 0.5MHz to 2MHz and
low-winding resistance.
Table 9 provides a summary of recommended inductor
suppliers and part numbers.
Output Capacitor Selection
The minimum recommended output capacitance forstability
is described in the Control-Loop Stability section and is
normally implemented using several 100μF 1206 (or similar)
MLCCs. For low slew-rate transient loads, RGAIN_EFF
determines the VOUT_ERROR for a given load step per
the small-signal model, as discussed above. In this case,
COUT has no effect on the VOUT_ERROR.
However, in the event that the slew rate of the load transient
greatly exceeds the slew rate of the inductor current, the
transient VOUT_ERROR can be larger than predicted by
the small-signal model. In this case, the VOUT loading
and unloading transients can be approximated by taking
the larger result between Equation 7 and Equation 16.
Equation 16:
I
L OUT × I STEP + OUTRIPPLE
2
VSAG =
2× C OUT × (VDDH - VOUT )
2
2
I
L OUT × I STEP + OUTRIPPLE
t H_ON
IOUTRIPPLE = Peak-to-peak inductor current ripple,
2
+I
=
VSOAR
STEP ×
defined above
2× C OUT × VOUT
C OUT
For proper OCP operation of the regulator, it is important
that IPK never exceeds the saturation current rating of
where:
the inductor (ISAT). It is recommended that a margin of at
least 20% is included between IPK and ISAT, as shown in
VSAG = Loading transient
Equation 15.
V
= Unloading transient.
Equation 15:
SOAR
I SAT > 1.2 x IPK
www.maximintegrated.com
In order to meet an aggressive transient specification,
COUT may have to be increased and/or LOUT decreased.
However, note that decreasing LOUT results in larger
inductor ripple current; thus, decreased efficiency and
increased output voltage ripple.
Maxim Integrated │ 25
MAX20743
Output voltage ripple is another important consideration
in the selection of output capacitors. For a buck regulator
operating in CCM, the total voltage ripple across the
output capacitor bank can be approximated as the sum
of three voltage waveforms: 1) the triangle wave that
results from multiplying the AC ripple current by the ESR,
2) the square wave that results from multiplying the ripple
current slew rate by the ESL, and 3) the piecewise
quadratic waveform that results from charging and
discharging the output capacitor. In a typical MAX20743
application with a bank of 0805 X5R, 6.3V, 22µF output
capacitors, these three voltage waveform components
are roughly equal. Although the phasing of these three
components impacts the total output voltage ripple, a
common approximation is to ignore the phasing and to find
the upper bound of the peak-to-peak ripple by summing all
three components, as shown in Equation 17.
Equation 17:
V
VPP ESR (I OUTRIPPLE ) + ESL DDH
=
L
OUT
I OUTRIPPLE
+
8 x f SW x C OUT
where:
ESR = Equivalent series resistance at the output
IOUTRIPPLE = Peak-to-peak inductor current ripple
ESL = High-frequency equivalent series inductance at
output
VDDH = Input voltage
LOUT = Output inductance
fSW = Switching frequency
COUT = Output capacitance.
The ESL effect of an output capacitor on output voltage ripple
cannot be easily estimated from the resonant frequency;
the high-frequency (10MHz or above) impedance of that
capacitor should be used instead. PCB traces and vias in the
VOUT/GND loop contribute additional parasitic inductance.
The final considerations in the selection of output capacitors
are ripple-current rating and power dissipation. Using
a conservative design approach, the output capacitors
should be designed to handle the maximum peak-topeak AC ripple current experienced in the worst-case
scenario. Because the recommended output capacitors
have extremely low ESR values, they are typically rated
well above the current and power stresses seen here.
www.maximintegrated.com
Integrated, Step-Down Switching
Regulator with PMBus
For the triangular AC ripple current at the output, the total
RMS current and power is given by Equation 18 and
Equation 19.
Equation 18:
I
IRMS _ COUT = OUTRIPPLE
12
where:
IOUTRIPPLE = Peak-to peak ripple current value.
Equation 19:
=
PCOUT IRMS _ COUT 2 × ESR
where:
ESR = Equivalent series resistance of the entire output
capacitor bank.
Input Capacitor Selection
The selection and placement of input capacitors are
important considerations. High-frequency input capacitors
serve to control switching noise. Bulk input capacitors are
designed to filter the pulsed DC current that is drawn by
the regulator. For the best performance, lowest cost and
smallest size of the MAX20743 systems, MLCC capacitors
with 1210 or smaller case sizes, capacitance values of
47µF or smaller, 16V or 25V voltage ratings, and X5R or
better temperature characteristics are recommended as
bulk. The minimum recommended value of capacitance
is 2 x 47µF (bulk) and 1.0µF + 0.1µF (high frequency).
Smaller values of bulk capacitance can be used in direct
proportion to the maximum load current.
It is recommended to choose the main MLCC input
capacitance to control the peak-to-peak input voltage
ripple to 2% to 3% of its DC value in accordance with
Equation 20.
Equation 20:
C IN =
IMAX x VOUT x (VDDH − VOUT )
( f SW x VDDH 2 x VINPP )
where:
CIN = Input capacitance (MLCC)
IMAX = Maximum load current
VDDH = DC input voltage
VOUT = DC output voltage
fSW = Switching frequency (CCM)
VDDHPP = Target peak-to-peak input-voltage ripple.
Maxim Integrated │ 26
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Because the bulk input capacitors must source the pulsed
DC input current of the regulator, the power dissipation,
and ripple-current rating for these capacitors are far more
important than that for the output capacitors. The RMS
current that the input capacitor must withstand can be
approximated using Equation 21.
accuracy of the set output voltage. Due to the form of
Equation 4, the effect is higher at higher output voltages.
Figure 5 shows the effect of 0.1% tolerance
resistors over a range of output voltages. For different
tolerance resistors, multiply the output voltage error by the
resistors’ tolerances divided by 0.1%. For example, for
0.5% tolerance resistors, multiply the output error shown
by 5. To obtain accuracy over temperature, for a worst-case
scenario, the temperature coefficients multiplied by the
temperature range should be added to the tolerance (i.e.,
for 25ppm/°C resistors over a 50°C excursion, add 0.125%
to the 25°C tolerance).
Equation 21:
IRMS_CIN =
ILOAD
VOUT x (VDDH − VOUT )
VDDH
where:
The error due to the voltage-feedback resistors’ tolerance
(RFB1 and RFB2) should be added to the output voltage
tolerance due to the IC’s feedback-voltage accuracy
shown in the Electrical Characteristics table.
ILOAD = Output DC load current.
With an equivalent series resistance of the bulk input
capacitor bank (ESRCIN), the total power dissipation in
the input capacitors is given by Equation 22.
Voltage Margining
Equation 22:
Voltage margining can be achieved by changing the
VOUT setting through PMBus. VOUT changes occur with
a default linear slew rate of 1V/ms. The slew rate can be
set to 1, 2, or 4mV/μs using the VRATE bits. See AN6042:
MAX20743 PMBus Application Note for details. If a
voltage-divider is present in the feedback loop, the VOUT
slew rate is scaled accordingly.
=
PCIN IRMS _ CIN2 × ESRCIN
Resistor Selection and its Effect on DC
Output-Voltage Accuracy
RFB1 and RFB2 set the output voltage, as described in
Equation 4. The tolerance of these resistors affects the
0.18%
0.16%
ERROR (%)
0.14%
0.12%
0.10%
0.08%
εVOUT = 2εR (VOUT - VREP) / VOUT
0.06%
0.04%
0.02%
0.00%
0
1.5
2
2.5
3
3.5
4
4.5
5
VOUT/VREF RATIO
Figure 5. DC Accuracy Impact Showing Effect of 0.1% Tolerance for RFB1 and RFB2
www.maximintegrated.com
Maxim Integrated │ 27
MAX20743
PCB Layout
PCB layout can dramatically affect the performance of the
regulator. A poorly designed board can degrade efficiency,
noise performance, and even control-loop stability. At higher
switching frequencies, layout issues are especially critical.
As a general guideline, the input capacitors and the
output inductor should be placed in close proximity to
the regulator IC, while the output capacitors should
be lumped together as close as possible to the load.
Traces to these components should be kept as short and
wide as possible to minimize parasitic inductance and
resistance. Traces connecting the input capacitors and
VDDH (power input node) on the IC require particular
attention since they carry currents with the largest
RMS values and fastest slew rates. According to best
practice, the input capacitors should be placed as close as
possible to the input supply pins, with the smallest
package high-frequency capacitor being the closest to the
IC and no more than 60 mils from the IC pins. Preferably,
there should be an uninterrupted ground plane located
immediately underneath these high-frequency current
paths, with the ground plane located no more than 8
mils below the top layer. By keeping the flow of this highfrequency AC current localized to a tight loop at the
regulator, electromagnetic interference (EMI) can be
minimized.
Voltage-sense lines should be routed differentially directly
from the load points. The ground plane can be used as a
shield for these or other sensitive signals to protect them from
capacitive or magnetic coupling of high-frequency noise.
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Integrated, Step-Down Switching
Regulator with PMBus
For remote-sense applications where the load and
regulator IC are separated by a significant distance
or impedance, it is important to place the majority of
the output capacitors directly at the load. Ideally, for
system stability, all of the output capacitors should be
placed as close as possible to the load. In remote-sense
applications, common-mode filtering is necessary to filter
high-frequency noise in the sense lines.
The following layout recommendations should be used for
optimal performance:
●● It is essential to have a low-impedance and
uninterrupted ground plane under the IC and extended
out underneath the inductor and output capacitor bank.
●● Multiple vias are recommended for all paths that carry
high currents (i.e., GND, VDDH, VX). Vias should be
placed close to the chip to create the shortest possible
current loops. Via placement must not obstruct the
flow of currents or mirror currents in the ground plane.
●● A single via in close proximity to the chip should be
used to tie the top layer AGND trace to the second
layer ground plane, it must not be connected to the top
power ground area.
●● The feedback-divider and compensation network
should be close to the IC to minimize the noise on the
IC side of the divider.
Gerber files with layout information and complete
reference designs can be obtained by contacting a Maxim
account representative.
Maxim Integrated │ 28
C4
DNS
0402
Vboot = 0.6484V
PMBus Addr = 1010 000b
Soft Start Time = 3ms
R1
1.78K
0402
SMALERT
DATA
CLK
OE
STAT
20K
R2
162K
0402
C23
DNS
0402
PGMB
PGMA
Fsw = 400kHz
OCP = 35A Valley
Rgain = 0.9 m-ohms
C32
1000pF
0402
DNS = Do Not Stuff
PGMB
PGMA
VX
BST
U1
VSENSE-
VSENSE+
MAX20743
SMALERT
DATA
CLK
OE
STAT
AGND
R8 0402
C36
10uF
X5R
0402
VCC
VCC
VDDH
VDDH
20K
C51
10uF
X5R
0402
GND
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R5 0402
C9
10uF
X5R
0402
C7
1uF
X7R
0603
C8
0.22uF
X7R
0402
SENSE-
SENSE+
VX
BST
C3
0.1uF
X7R
0402
Diff Pair
C5
47uF
X5R
1206
170nH
L1
C6
47uF
X5R
1206
VDDH
C11
47uF
X5R
1206
R9
3.48K
0402
R6
1.87K
0402
SENSE_VOUT
C10
47uF
X5R
1206
Diff Pair
INPUT SUPPLY
0 0402
R11
0
R4 0402
C24
0.01uF
0402
C12-17
6x100uf
1206
+
C28-29
2x470uF
5 m-ohms
VOUT = 1V
VOUT
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Figure 6. MAX20743 Reference Schematic (VOUT = 1V, VDDH = 4.5V to 16V)
Maxim Integrated │ 29
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX20743EPL+
-40°C to +125°C
15 FCQFN
MAX20743EPL+T
-40°C to +125°C
15 FCQFN
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
www.maximintegrated.com
Maxim Integrated │ 30
MAX20743
Integrated, Step-Down Switching
Regulator with PMBus
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
0
6/16
Initial release
1
10/16
Updated the Typical Operating Characteristics, and Absolute Maximum Ratings
sections; Added the Input Current Limit section and updated numbering for Equations
3-22.
DESCRIPTION
—
1–7,
9–10, 18–19,
22–27
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2016 Maxim Integrated Products, Inc. │ 31
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