MAX3876EHJ

19-1631; Rev 0a; 8/01 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Features ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications This device operates from a +3.3V or +5.0V single supply over a -40°C to +85°C temperature range. Power consumption is typically only 445mW with a +3.3V supply. The MAX3876 is available in a 32-pin TQFP package as well as in die form. ♦ Differential CML Data and Clock Outputs ♦ 440mW Power Dissipation (at +3.3V) ♦ Clock Jitter Generation: 3.7mUIRMS ♦ +3.3V or +5V Single Power Supply ♦ Fully Integrated Clock Recovery and Data Retiming ♦ Additional High-Speed Input Facilitates System Loopback Diagnostic Testing ♦ Tolerates >2500 Consecutive Identical Digits ♦ Loss-of-Lock Indicator Ordering Information Applications SDH/SONET Receivers and Regenerators TEMP. RANGE PIN-PACKAGE Add/Drop Multiplexers MAX3876EHJ PART -40°C to +85°C 32 TQFP Digital Cross-Connects MAX3876E/D -40°C to +85°C Dice* *Dice are designed to operate over this range, but are tested and guaranteed at TA = +25°C only. Contact factory for availability. Pin Configuration appears at end of data sheet. 2.488Gbps ATM Receiver Digital Video Transmission SDH/SONET Test Equipment Intrarack/Subrack Interconnects Typical Application Circuit +3.3V +3.3V TTL 0.01µF +3.3V VCC FILT PHOTODIODE LOL VCC OUT+ SDI+ OUT- SDI- SDO+ SDO- MAX3866 0.01µF IN PREAMPLIFIER MAX3831 MAX3876 4:1/1:4 TRANSCEIVER SLBI+ SCLKO+ SCLKO- SLBISIS SYSTEM LOOPBACK TTL FIL+ FIL- 1µF ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3876 General Description The MAX3876 is a compact, low-power clock recovery and data retiming IC for 2.488Gbps SDH/SONET applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input. The data is retimed by the recovered clock. Differential CML outputs are provided for both clock and data signals, and an additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor. The MAX3876 is designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Its jitter performance exceeds all of the SONET/SDH specifications. MAX3876 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +7.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 0.5V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±11mA CML Output Current Levels (SDO+, SDO-, SCLKO+, SCLKO-) ................................±22mA Voltage at LOL, SIS, FIL+, FIL-...................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) 32-Pin TQFP (derate 16.1mW/°C above +85°C).............1.0W Operating Temperature Range MAX3876EHJ..................................................-40°C to +85°C Operating Junction Temperature Range (die) ..-55°C to +150°C Storage Temperature Range .............................-60°C to +160°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Supply Current ICC Excluding CML output termination Input Common-Mode Voltage VCM DC-coupled Differential Input Voltage (SDI±, SLBI±) VID Single-Ended Input Voltage (SDI±, SLBI±) VIS Input Termination to VCC (SDI±, SLBI±) RIN CML Differential Output Voltage Swing VIH VIL VOH TTL Output Low Voltage (LOL) VOL mA V 50 1000 50 1600 VCC - 0.4 VCC + 0.4 TA = 0°C to +85°C 640 800 1000 TA = -40°C 580 800 1000 85 100 115 VCC - 0.2 VCC - 0.4V (a) AC-COUPLED SINGLE-ENDED INPUT (CML OR PECL) V -10 +10 µA 2.4 VCC V 0.4 V SCLKO+ VCC tCK-Q 500mV VCC - 0.25V SDO VCC - 0.5V (b) DC-COUPLED SINGLE-ENDED CML INPUT Figure 1. Input Amplitude 2 Ω V tCK 25mV mVp-p 0.8 25mV VCC V V 2.0 VCC + 0.4V 800mV mVp-p Ω 48 TTL Input Current (SIS) TTL Output High Voltage (LOL) UNITS 167 Figure 1, AC-coupled RL = 50Ω to VCC TTL Input Low Voltage (SIS) MAX 135 VCC - 0.25 Differential Output Impedance TTL Input High Voltage (SIS) TYP Figure 1, DC-coupled RL = 50Ω to VCC CML Output Common-Mode Voltage MIN Figure 2. Output Clock-to-Q Delay _______________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC MAX3876 AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP Serial Output Clock Rate MAX UNITS 2.488 Clock-to-Q Delay Figure 2 Jitter Peaking f ≤ 2MHz JP Jitter Transfer Bandwidth 110 JBW Jitter Tolerance Jitter Generation JGEN ps 0.03 0.1 dB 1.4 2.0 MHz f = 70kHz (Note 3) 2.1 4.4 f = 100kHz 1.76 3.32 f = 1MHz 0.41 0.74 f = 10MHz 0.32 0.51 Jitter BW = 12kHz to 20MHz GHz 290 UIp-p 3.7 6.2 mUIRMS 19.2 61.0 mUIp-p Clock Output Edge Speed 20% to 80% 75 ps Data Output Edge Speed 20% to 80% 95 ps 2500 Bits Tolerated Consecutive Identical Digits Input Return Loss (SDI±, SLBI±) 100kHz to 2.5GHz 17 2.5GHz to 4.0GHz 15 dB Note 1: Dice are tested at TA = +25°C only. Note 2: AC characteristics are guaranteed by design and characterization. Note 3: At jitter frequencies < 70kHz, the jitter tolerance characteristics exceed the ITU/Bellcore specifications. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT) DATA JITTER TOLERANCE MAX3876 toc2 10 50mV/div CLOCK MAX3876 toc03 TA = +25°C PRBS = 223-1 VIN = 50mVp-p WIDEBAND JITTER = 3.94psRMS INPUT JITTER (UIp-p) 200mV/div MAX3876 toc1 223-1 PATTERN VIN = 50mVp-p RECOVERED CLOCK JITTER 1 BELLCORE MASK PRBS = 223 - 1 50mVp-p INPUT 0.1 100ps/div 10ps/div 10k 100k 1M 10M JITTER FREQUENCY (kHz) _______________________________________________________________________________________ 3 Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) JITTER TOLERANCE vs. INPUT AMPLITUDE 0 JITTER TRANSFER (dB) 0.7 0.6 JITTER FREQUENCY = 5MHz 0.4 0.3 -0.5 BELLCORE MASK -1.0 10-6 BIT ERROR RATE 0.8 10-5 -1.5 MAX3876 toc06 0.5 MAX3876 toc05 JITTER FREQUENCY = 1MHz 0.5 BIT ERROR RATE vs. INPUT AMPLITUDE JITTER TRANSFER MAX3876 toc04 0.9 JITTER TOLERANCE (UIp-p) 10-7 10-8 -2.0 0.2 10-9 -2.5 TA = +85°C PRBS = 223 - 1 0.1 PRBS = 223 - 1 10-10 8.8 8.9 9.0 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 INPUT SIGNAL AMPLITUDE (mVp-p) PRBS = 223 - 1 -3.0 0 10 100 1k 1000 10k 100k 1M 10M JITTER FREQUENCY (Hz) INPUT SIGNAL AMPLITUDE (mVp-p) SUPPLY CURRENT vs. TEMPERATURE JITTER TOLERANCE vs. PULSE-WIDTH DISTORTION 160 155 SUPPLY CURRENT (mA) 1MHz 1.0 MAX3876 toc08 PRBS = 223 - 1 100mVp-p INPUT 100kHz MAX3876 toc07 10 JITTER TOLERANCE (UI) MAX3876 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC 150 VCC = 5.0V 145 140 135 VCC = 3.0V 130 10MHz 125 120 0.1 0 0.05 0.10 0.15 0.20 0.25 -50 -25 0 25 50 75 100 AMBIENT TEMPERATURE (°C) PULSE-WIDTH DISTORTION (UI) Pin Description PIN NAME 1, 2, 8, 9, 10, 16, 26, 29, 32 GND Supply Ground 3, 6, 11, 14, 15, 17, 20, 21, 24, 27, 28 VCC Positive Supply Voltage 4 SDI+ Positive Data Input. 2.488Gbps serial-data stream. 5 SDI- Negative Data Input. 2.488Gbps serial-data stream. 7 SIS Signal Input Selection, TTL. Low for normal data input. High for system loopback input. 12 SLBI+ Positive System Loopback Input. 2.488Gbps serial-data stream. 13 SLBI- Negative System Loopback Input. 2.488Gbps serial-data stream. 18 SCLKO- 4 FUNCTION Negative Serial Clock Output, CML, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-. _______________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC PIN NAME 19 SCLKO+ FUNCTION Positive Serial Clock Output, CML, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+. 22 SDO- Negative Data Output, CML, 2.488Gbps 23 SDO+ Positive Data Output, CML, 2.488Gbps 25 LOL Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor) 30 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 31 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. SIS FIL+ FIL- SDO+ D SDI+ Q CML CK AMP SDO- SDIMUX PHASE AND FREQUENCY DETECTOR SLBI+ LOOP FILTER I VCO SCLKO+ Q CML SCLKO- AMP SLBILOL MAX3876 TTL Figure 3. Functional Diagram Detailed Description The MAX3876 consists of a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, and CML output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. Input Amplifier Input amplifiers are implemented for both the main data and system loopback inputs. These amplifiers accept DC-coupled differential input amplitudes from 50mVp-p up to 1000mVp-p. With AC-coupling, differential input signal amplitudes can be increased to a maximum of 1600mVp-p. The bit error rate is better than 1 · 10-10 for input signals as small as 10mVp-p, though the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. Phase Detector The phase detector incorporated in the MAX3876 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. _______________________________________________________________________________________ 5 MAX3876 Pin Description (continued) Frequency Detector HO(j2πf) (dB) OPEN-LOOP GAIN The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on the rising edge of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector. CF = 1.0µF fZ = 2.6kHz CF = 0.1µF fZ = 26kHz Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. See Design Procedure for guidelines on selecting this capacitor. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low-phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 1.5psRMS within a jitter bandwidth of 12kHz to 20MHz. Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is incorporated in the MAX3876 frequency detector. A loss-of-lock condition is signaled immediately with a TTL low. When the PLL is frequency locked, LOL switches to TTL high in approximately 800ns. Note: The LOL monitor is valid only when a data stream is present on the inputs to the MAX3876. As a result, LOL does not detect a loss-of-power condition due to loss of the incoming signal. f (kHz) 1 100 10 1000 Figure 4. Open-Loop Transfer Function H(j2πf) (dB) CF = 0.1µF 0 CLOSED-LOOP GAIN MAX3876 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC -3 CF = 1.0µF f (kHz) 1 10 100 1000 Figure 5. Closed-Loop Transfer Function Design Procedure Setting the Loop Filter The MAX3876 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 1.5MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 4 and 5 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: fz = 6 1 2π 60 CF For an overdamped system (fZ/fL) < 0.25, the jitter peaking (MP) of a second-order system can be approximated by:  f  MP = 20log 1+ Z   fL  For example, using CF = 0.1µF results in a jitter peaking of 0.2dB. Reducing CF below 0.01µF may result in PLL instability. The recommended value for CF is 1.0µF to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low TC, high-quality capacitor of type X7R or better. ( ) _______________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC PECL Input Levels When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50Ω termination (Figure 7). AC-coupling is also required to maintain the input common-mode level. Jitter Tolerance and Input Sensitivity Trade-Offs When the received data amplitude is higher than 50mVp-p, the MAX3876 provides a typical jitter tolerance of 0.51UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.36UI for receiver preamplifier and postamplifier design. The BER is better than 1 · 10-10 for input signals greater than 10mVp-p. At this input level, jitter tolerance will be degraded but will still be above the SDH/SONET requirement. The user can make a trade-off between jitter tolerance and input sensitivity according to the specific application. See the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Amplitude graphs. Jitter Tolerance vs. Pulse-Width Distortion The MAX3876 can typically tolerate up to 0.20UI of pulse-width distortion (PWD) and still exceed ITU and Bellcore specifications for sinusoidal jitter tolerance. Refer to the Typical Operating Characteristics for Jitter Tolerance and PWD vs. Jitter Frequency graphs. Layout The MAX3876’s performance can be significantly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough. VCC 50Ω 50Ω SDO+ SDO- MAX3876 Figure 6. CML Outputs Applications Information Consecutive Identical Digits (CIDs) The MAX3876 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 · 10-10. The CID tolerance is tested using a 213 - 1 PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2500 bits is typical. System Loopback The MAX3876 is designed to allow system loopback testing. The user can connect a serializer output in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3876 for system diagnostics. To select the SLBI± inputs, apply a TTL logic high to the SIS pin. _______________________________________________________________________________________ 7 MAX3876 Input and Output Terminations The MAX3876’s digital outputs (SDO+, SDO-, SCLKO+, SCLKO-) are internally terminated with 50Ω to V CC (Figure 6). See the DC Electrical Characteristics for signal swing and common-mode voltage levels. To ensure best performance, the differential outputs must have balanced loads. The input termination can be driven differentially or can be driven single-ended by externally biasing SDI- or SLBI- to the center of the voltage swing. MAX3876 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC VCC VCC = 3.3V VCC = 3.3V 3.3V 0.1µF 25Ω PECL LEVELS SDI+ 226Ω 243Ω ZIN = 50Ω SDI+ RT* 100Ω 0.1µF RT* 25Ω SDI- ZIN = 50Ω PECL OUTPUT ZIN = 50Ω 3.3V 82Ω 226Ω 243Ω SDIZIN = 50Ω 82Ω MAX3876 MAX3876 *SELECT RT SUCH THAT THE CORRECT PECL COMMON-MODE LEVEL IS ACHIEVED (TYPICAL PECL OUTPUT CURRENT = 14mA). Figure 7. PECL-to-CML Interface 8 Figure 8. Direct Coupling of a PECL Output into the MAX3876 _______________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Pin Configuration FIL+ GND FIL+ FIL- GND VCC VCC GND LOL TOP VIEW 32 31 30 29 28 27 26 25 GND GND FIL- VCC VCC LOL GND VCC GND 1 24 VCC GND 2 23 SDO+ GND SDO+ GND SDO- VCC VCC VCC 3 22 SDO- SDI+ 4 21 VCC SDI- SDI- 5 20 VCC VCC VCC 6 19 SCLKO+ SIS VCC SIS 7 18 SCLKO- GND GND GND 8 17 VCC 14 15 16 GND VCC 13 VCC GND 12 VCC 11 SLBI- 10 SLBI+ 9 GND MAX3876 MAX3876 Chip Topography 0.072" VCC (1.828mm) SCLKO+ SDI+ SCLKO- GND SLBI+ VCC VCC VCC SLBI- N.C. N.C. 0.071" (1.803mm) TQFP TRANSISTOR COUNT: 1334 SUBSTRATE CONNECTED TO GROUND _______________________________________________________________________________________ 9 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC 32L,TQFP.EPS MAX3876 Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.