19-1456; Rev 0; 8/99
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
Features
♦ Quad, 8-Channel Sample/Hold
♦ 0.01% Accuracy of Acquired Signal
♦ 0.01% Linearity Error
♦ Fast Acquisition Time: 2.5µs
♦ Low Droop Rate: 1mV/sec
♦ Low Hold Step: 0.25mV
♦ Wide Output Voltage Range: +7V to -4V
Ordering Information
Applications
Automatic Test Systems (ATE)
Industrial Process Controls
Arbitrary Function Generators
Avionics Equipment
PART
TEMP. RANGE
MAX5166LCCM
0°C to +70°C
PINPACKAGE
ROUT
(Ω)
48 TQFP
50
MAX5166MCCM 0°C to +70°C
MAX5166NCCM 0°C to +70°C
MAX5166LECM -40°C to +85°C
48 TQFP
48 TQFP
48 TQFP
500
1k
50
MAX5166MECM -40°C to +85°C
MAX5166NECM -40°C to +85°C
48 TQFP
48 TQFP
500
1k
OUT23
OUT22
38
37
OUT25
OUT24
39
40
41
OUT28
OUT27
OUT26
42
43
44
45
46
A1
A0
OUT31
OUT30
OUT29
47
TOP VIEW
48
Pin Configuration
A2
M0
M1
M2
M3
VL
1
36
2
35
3
34
4
33
5
32
DGND
VSS
AGND
IN3
IN2
IN1
7
6
31
MAX5166
30
24
23
OUT9
OUT10
22
21
20
OUT6
OUT7
OUT8
19
OUT4
OUT5
IN0
OUT0
OUT1
OUT2
OUT3
18
25
17
26
12
16
27
11
15
28
10
14
29
9
13
8
OUT21
OUT20
OUT19
OUT18
OUT17
OUT16
VDD
OUT15
OUT14
OUT13
OUT12
OUT11
TQFP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX5166
General Description
The MAX5166 contains four 1-to-8 multiplexers and 32
sample/hold amplifiers. The sample/hold amplifiers are
organized into four octal sample/holds with separate
inputs and independent TTL/CMOS-compatible hold
enables for each octal set. Additional 3-bit TTL/CMOScompatible address logic selects the 1-to-8 multiplexer
channel. The MAX5166 is available with an output impedance of 50Ω, 500Ω, or 1kΩ, allowing output filtering.
The MAX5166 operates with +10V and -5V supplies,
and a separate +5V digital logic supply. Manufactured
with a proprietary BiCMOS process, it provides high
accuracy, fast acquisition time, low droop rate, and a
low hold step. The device acquires 8V step input signals to 0.01% accuracy in 2.5µs. Transitions from sample mode to hold mode result in only 0.5mV of error.
While in hold mode, the output voltage slowly droops at
a rate of 1mV/sec. The MAX5166 is available in a 48-pin
TQFP package.
MAX5166
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
ABSOLUTE MAXIMUM RATINGS
VDD to AGND.......................................................-0.3V to +11.0V
VSS to AGND .........................................................-6.0V to +0.3V
VDD to VSS ......................................................................+15.75V
VL to DGND ...........................................................-0.3V to +6.0V
VL to AGND ...........................................................-0.3V to +6.0V
DGND to AGND.....................................................-0.3V to +2.0V
IN_ to AGND ...............................................................VSS to VDD
A_, M_ to DGND ....................................................-0.3V to +6.0V
Maximum Current into Output Pin ....................................±10mA
Maximum Current into A_, M_ ..........................................±20mA
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 12.5mW/°C above +70°C)..................1W
Operating Temperature Ranges
MAX5166_CCM ...................................................0°C to +70°C
MAX5166_ECM.................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +10V, VSS = -5V, VL = +5V ±5%, AGND = DGND, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-4V < VIN < +7V, RL = ∞
0.01
0.08
%
IN_ = AGND
0.25
1.00
mV
1
40
mV/sec
-5
+30
mV
40
µV/°C
VDD 2.4
V
ANALOG SECTION
Linearity Error
Hold Step
Droop Rate
Offset Voltage
Output Voltage Range
VHS
∆VOUT
VOS
VOUT_
IN_ = AGND, TA = +25°C
CIN_
-30
+15°C ≤ TA ≤ +65°C (Note 1)
20
VSS +
0.75
RL = ∞
8V step with
500ns rising edge
(Note 1)
Analog Crosstalk
Input Capacitance
IN_ = AGND, TA = +25°C
MAX5165L, CL = 250pF
-72
-76
5
20
MAX5166L
35
50
65
MAX5166M
350
500
650
MAX5166N
700
1000
1300
MAX5165M, CL = 10nF
(Note 1)
RL = ∞,
CL = 250pF
dB
MAX5165N, CL = 10nF
pF
Ω
DC Output Impedance
ROUT_
Output Source Current
ISOURCE
2
mA
ISINK
2
mA
Output Sink Current
TIMING PERFORMANCE
Acquisition Time
tAQ
8V step to 0.08%, RL = ∞, Figure 2 (Note 2)
2.5
TA = +25°C, 100mV step to ±1mV, RL = ∞,
Figure 2 (Note 2)
1
1
4
µs
Hold-Mode Settling Time
tH
To ±1mV of final value, Figure 2 (Note 1)
Aperture Delay
tAP
Figure 2 (Note 1)
Inhibit Pulse Width
tPW
Figure 2 (Note 1)
200
ns
Data Hold Time
tDH
Figure 2 (Note 1)
150
ns
Data Setup Time
tDS
Figure 2 (Note 1)
50
ns
2
_______________________________________________________________________________________
2
µs
200
ns
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
(VDD = +10V, VSS = -5V, VL = +5V ±5%, AGND = DGND, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical
values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
Input Voltage High
VIH
Input Voltage Low
VIL
Input Current
II
2.0
A_ = DGND or VL; M_ = DGND or VL
V
-1
0.8
V
+1
µA
POWER SUPPLIES
Positive Analog Supply Voltage
VDD
(Note 3)
9.5
10.0
10.5
V
Negative Analog Supply Voltage
VSS
(Note 3)
-4.75
-5.0
-5.45
V
Digital Logic Supply Voltage
VL
4.75
5.0
5.25
V
Positive Analog Supply Current
IDD
RL = ∞
36
mA
Negative Analog Supply Current
ISS
RL = ∞
36
mA
A_ = DGND or VL;
M_ = DGND or VL
0.5
mA
Digital Logic Supply Current
Power-Supply Rejection Ratio
IL
PSRR
mA
VA0–VA3 = 0.8V or 2V;
VM0, VM1, VM2 = 0.8V or 2V
For both VDD and VSS in
sample mode, VIN = 0
5
-60
-75
dB
Note 1: Guaranteed by design.
Note 2: Only one M_ input may be asserted low at a time, so only one channel is selected (see Single vs. Simultaneous Sampling).
Note 3: Do not exceed the absolute maximum rating for VDD to VSS of +15.75V (see Absolute Maximum Ratings).
_______________________________________________________________________________________
3
MAX5166
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDD = +10V, VSS = -5V, VL = +5V, IN_ = +5V, RL = ∞, CL = 0, AGND = DGND, TA = +25°C, unless otherwise noted.)
12
10
8
-70
1.35
1.30
1.25
1.20
-50
-40
-30
4
1.10
-20
2
1.05
-10
0
1.00
-20
0
20
40
60
80
0
-5.0 -3.5 -2.0 -0.5 1.0 2.5 4.0 5.5 7.0 8.5 10.0
100
1
10
100
INPUT VOLTAGE (V)
TEMPERATURE (°C)
POWER-SUPPLY REJECTION RATIO
(SAMPLE MODE)
HOLD STEP vs. TEMPERATURE
-100
MAX5166-04
-80
-90
-80
-70
-50
-SUPPLY
-40
-30
50
HOLD STEP (µV)
HOLD STEP (µV)
+SUPPLY
-60
25
-70
-60
-50
-40
-30
-20
-20
-10
-10
0
0
10
100
1000
0
-40
10,000
-20
0
20
40
60
80
-5.0
-3.0
-1.0
TEMPERATURE (°C)
FREQUENCY (kHz)
3.0
OFFSET VOLTAGE vs. INPUT VOLTAGE
-3.5
MAX5166-05
-2.5
1.0
-3.6
OFFSET VOLTAGE (mV)
-3.7
-3.0
-3.5
-4.0
-3.8
-3.9
-4.0
-4.1
-4.2
-4.3
-4.5
-4.4
-5.0
-4.5
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
5.0
INPUT VOLTAGE (V)
OFFSET VOLTAGE vs. TEMPERATURE
-2.0
OFFSET VOLTAGE (mV)
100
MAX5166-08
1
4
10,000
HOLD STEP vs. INPUT VOLTAGE
75
MAX5166-03
-90
1000
FREQUENCY (kHz)
MAX5166-07
-40
+SUPPLY
-SUPPLY
-60
1.15
6
MAX5166-02
-80
1.40
DROOP RATE (mV/sec)
14
1.45
PSRR (dB)
16
-90
MAX5166-06
1.50
MAX5166-01
18
DROOP RATE (mV/sec)
POWER-SUPPLY REJECTION RATIO
(HOLD MODE)
DROOP RATE vs. INPUT VOLTAGE
DROOP RATE vs. TEMPERATURE
PSRR (dB)
MAX5166
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
-5.0
-3.0
-1.0
1.0
3.0
5.0
7.0
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9.0
7.0
9.0
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
MAX5166
M3 M2 M1 M0
A2 A1 A0
MAX5166
3-TO-8
DECODER
8
1-TO-8 MULTIPLEXER
8
AND0
AND7
EN
OUT0
IN0
IN
OUT7
SAMPLE-AND-HOLD
1-TO-8 MULTIPLEXER
8
OUT8
EN
IN1
IN
OUT15
SAMPLE-AND-HOLD
1-TO-8 MULTIPLEXER
8
OUT16
EN
IN2
IN
OUT23
SAMPLE-AND-HOLD
1-TO-8 MULTIPLEXER
8
OUT24
EN
IN3
IN
OUT31
SAMPLE-AND-HOLD
VSS
VDD
AGND
VL
DGND
Figure 1. Functional Diagram
_______________________________________________________________________________________
_______________________________________________________________________________________
5
MAX5166
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
Pin Description
PIN
NAME
1, 47, 48
A2, A0, A1
2–5
M0–M3
6
VL
7
DGND
8
VSS
9
AGND
10–13
IN3–IN0
14–29
OUT0–OUT15
30
VDD
31–46
OUT16–OUT31
FUNCTION
Address Inputs. The input of a 3-to-8 decoder that controls channel selection for all four 1-to-8
multiplexers. Selects which output channels are connected to the input during sample mode
(Tables 1, 2).
Mode-Selection/Multiplexer-Enable Inputs 0 to 3. All four 1-to-8 multiplexers are independently
controlled. A logic low enables sample mode by connecting the selected channel to IN_. A logic
high enables hold mode (Tables 1, 2).
Positive Digital Logic Power-Supply Input
Digital Ground
Negative Analog Power-Supply Input
Analog Ground
Analog Inputs 0 to 3
Outputs 0 to 15
Positive Analog Power-Supply Input
Outputs 16 to 31
_______________Detailed Description
The MAX5166 connects four separate analog inputs to
four internal 1-to-8 analog multiplexers. Each multiplexer channel connects to a buffered sample/hold circuit
and a series output resistor, creating a four-input
device with 32 sample/hold output channels. Three
multiplexer channel-address inputs and four modeselect inputs (one for each multiplexer) control channel
selection and sample/hold functions (Figure 1 and
Tables 1 and 2).
Digital Interface
Three address pins and 3-to-8 address decoder logic
select the channel for all four internal analog multiplexers. The mode-select inputs (M3–M0) independently
control the sample/hold functions for each multiplexer
(Tables 1 and 2).
Sample/Hold
The MAX5166 contains 32 buffered sample/hold circuits with internal hold capacitors. Internal hold capacitors minimize leakage current, dielectric absorption,
feedthrough, and required board space. The value of
the hold capacitor affects acquisition time, hold step,
and droop rate. Lower capacitance allows faster acqui-
sition times but increases the droop rate. Higher values
increase hold time and acquisition time. The hold
capacitor used in the MAX5166 provides fast 2.5µs
(typ) acquisition time while maintaining a low 1mV/sec
(typ) droop rate, making the sample/hold ideal for highspeed sampling.
Sample Mode
Driving M3–M0 low (one at a time) selects sample
mode (Tables 1 and 2). During sample mode, the
selected multiplexer channel connects to IN_ allowing
the hold capacitor to acquire the input signal. To guarantee an accurate sample, maintain sample mode for
at least 4µs. Sampling for longer than 4µs results in
tracking. Only the addressed channel on the selected
multiplexer samples the input; all other channels remain
in hold mode.
Hold Mode
Driving M3–M0 high selects hold mode. Hold mode disables the multiplexer, which disconnects all eight channels on the 1-to-8 multiplexer from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/sec
droop rate (towards VDD).
6 _________________________________________________________________________________________
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
MAX5166
Table 1. Output Selection
ADDRESS
OUTPUT SELECTED
A2
A1
A0
MUX0
MUX1
MUX2
MUX3
0
0
0
OUT0
OUT8
OUT16
OUT24
0
0
1
OUT1
OUT9
OUT17
OUT25
0
1
0
OUT2
OUT10
OUT18
OUT26
0
1
1
OUT3
OUT11
OUT19
OUT27
1
0
0
OUT4
OUT12
OUT20
OUT28
1
0
1
OUT5
OUT13
OUT21
OUT29
1
1
0
OUT6
OUT14
OUT22
OUT30
1
1
1
OUT7
OUT15
OUT23
OUT31
0 = Logic Low, 1 = Logic High
Table 2. Mode Selection
MODE-SELECT
INPUTS* (M3–M0)
ACTION
0
Sample mode enabled on selected
analog multiplexer and channel
(Table 1).
1
Hold mode enabled on selected
analog multiplexer and channel
(Table 1).
0 = Logic Low, 1 = Logic High
* Only one M_ input asserted low; all others must be logic high
to meet the timing specification (see Single vs. Simultaneous
Sampling).
Hold Step
When switching between sample mode and hold
mode, the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capacitor. The MAX5166 limits the hold step to 0.25mV (typ).
An output capacitor to ground can be used to filter out
this small hold-step error.
Output
The MAX5166 contains an output buffer for each multiplexer channel (32 total), so the hold capacitor sees a
high-impedance input, reducing the droop rate. While
in hold mode, the hold capacitor discharges at a rate of
1mV/sec (typ). The buffer also provides a low output
impedance; however, the device contains output resistors in series with the buffer output (Figure 1) for selected output filtering. To provide greater design flexibility,
the MAX5166 is available with an RO of 50Ω, 500Ω, or
1kΩ.
Note: Output loads increase the analog supply current (IDD and ISS). Excessive loading of the output(s)
damages the device by consuming more power than
the device will dissipate (see Absolute Maximum
Ratings). The resistor-divider formed by the output
resistor (ROUT_) and load impedance (RL) scales the
sampled voltage (VSAMP). Determine the output voltage (VOUT_) as follows:
Voltage Gain = AV = RL/(RL + ROUT)
VOUT_ = VSAMP · AV
The maximum output voltage range depends on the
analog supply voltages available and the scaling factor
used:
(VSS + 0.75V) · AV ≤ VOUT_ ≤ (VDD - 2.4V) · AV
when RL = ∞, then AV = 1, and this equation becomes
(VSS + 0.75V) ≤ VOUT ≤ (VDD - 2.4V).
Timing Definitions
Acquisition time (t AQ ) is the amount of time the
MAX5166 must remain in sample mode for the hold
capacitor to acquire an accurate sample. The holdmode settling time (tH) is the amount of time necessary
for the output voltage to settle to its final value.
Aperture delay (tAP) is the time interval required to disconnect the input from the hold capacitor. The inhibit
pulse width (tPW) is the amount of time the MAX5166
must remain in hold mode while the address is
changed. The data setup time (tDS) is the amount of
time an address must be maintained before the
address becomes valid. The data hold time (tDH) is the
amount of time an address must be maintained after
mode select has gone from low to high (Figure 2).
_______________________________________________________________________________________
7
MAX5166
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
tPW
MODE
SELECT
tDS
ADDRESS
(A0–A2)
tDH
OUTPUT
HOLD STEP
tH
INPUT
tAQ
tAP
Figure 2. Timing Performance
__________Applications Information
Combining Inputs
The MAX5166 contains a separate input for each 1-to-8
multiplexer. Externally connect the input pins to form
larger multiplexers. When all four inputs are connected
to the same source, the MAX5166 is functionally equivalent to the MAX5165, except the MAX5166 does not
contain output clamping diodes.
Control-Line Reduction
The MAX5166 contains four separate 1-to-8 multiplexers
and individual mode selectors for each multiplexer. When
sampling one channel at a time, use an external 2-to-4
decoder (with active-low outputs) to reduce the number
of digital control lines from seven to five (Figure 3).
Single vs. Simultaneous Sampling
Individually control the four mode/multiplexer-select
pins to simultaneously sample on four channels, the
same channel for each multiplexer (Figure 4). Each
mode-select pin controls sampling on one of the 1-to-8
multiplexers, while the 3-bit address selects one of the
eight channels on all the multiplexers (Tables 1 and 2).
Setting any combination of the mode-select pin low
enables sampling on the addressed channels for the
selected multiplexers.
8
Simultaneously sampling two or more channels reduces
offset voltage but increases acquisition time. Multiply
the single-channel acquisition time by the number of
channels sampling.
Multiplexed DAC
Figure 5 shows a typical demultiplexer application.
Different digital codes are converted by the digital-toanalog converter (DAC) and then stored on eight different channels, or as many as 32 different channels
when all four inputs are active. The 100mV/sec (max)
droop rate requires refreshing the hold capacitors
every 100ms before the voltage drops by 1/2LSB for an
8-bit DAC with a 5V full-scale voltage.
Powering the MAX5166
The MAX5166 does not require a special power-up
sequence to avoid latchup. The device requires three
separate supply voltages for operation; however, when
one or two of the voltages are not available, DC-DC
charge-pump (switched-capacitor) converters provide
a simple, efficient solution. The MAX860 provides voltage doubling or inversion, ideal for conversions from
+5V to +10V or from +5V to -5V. The MAX860 also
functions as a voltage divider to provide conversion
from +10V to +5V.
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
1/16 MAX5166
3
5
MAX5166
CHANNEL
ADDRESS
A0–A2
3
ADDRESS
DECODER
2
M0
M1
M2
M3
MODE SELECTOR
DECODER
OUT0
IN0
IN1
INPUT
SIGNAL
IN2
AGND
OUT24
IN3
AGND
Figure 3. Control-Line Reduction
CHANNEL
ADDRESS
1/16 MAX5166
3
A0–A2
3
ADDRESS
DECODER
MODE/MULTIPLEXER
SELECTION
M0
M1
M2
M3
OUT0
IN0
INPUT
SIGNAL
IN1
IN2
AGND
OUT24
IN3
AGND
Figure 4. Simultaneous Sampling
_______________________________________________________________________________________
9
MAX5166
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
CHANNEL
ADDRESS
3
A0–A2
3
ADDRESS
DECODER
MODE/MULTIPLEXER
SELECTION
1/16 MAX5166
M0
M1
M2
M3
OUT0
AGND
DIGITAL
INPUTS
DAC
OUT7
IN
IN1
IN2
IN3
AGND
Figure 5. Multiplexing a DAC
Chip Information
TRANSISTOR COUNT: 5077
10
______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
TQFPPO.EPS
______________________________________________________________________________________
11
MAX5166
Package Information
MAX5166
32-Channel Sample/Hold Amplifier
with Four Multiplexed Inputs
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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