EVALUATION KIT AVAILABLE
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
General Description
The MAX5215/MAX5217 are pin-compatible 14-bit
and 16-bit digital-to-analog converters (DACs). The
MAX5215/MAX5217 are single-channel, low-powered,
buffered voltage-output DACs. The devices use a precision external reference applied through the high resistance input for rail-to-rail operation and low system power
consumption. The MAX5215/MAX5217 accept a wide
2.7V to 5.5V supply voltage range. Power consumption
is extremely low to accommodate most low-power and
low-voltage applications.
The MAX5215/MAX5217 have an I2C-compatible, 2-wire
serial interface that operates at clock rates up to 400kHz.
On power-up, the MAX5215/MAX5217 reset the DAC output to zero, providing additional safety for applications
that drive valves or other transducers that need to be off
on power-up. The DAC output is buffered resulting in a
low supply current of 80µA (max) and a low offset error
of ±0.25mV. An asynchronous active-low input, AUX,
is provided. This input can be programmed to support
clear or load DAC operations, independent of the serial
interface. The MAX5215/MAX5217 are available in an
ultra-small (3mm x 5mm), 8-pin µMAXM package and are
specified over the -40°C to +105°C extended industrial
temperature range.
Applications
Remote Sensing
Portable Instrumentation
Communication Systems
Automatic Tuning
Gain and Offset
Adjustment
Power Amplifier Control
Automatic Test Equipment
Process Control and
Servo Loops
Data Acquisition
Programmable Voltage
and Current Sources
Features
S Low-Power Consumption (80µA, max)
S 18µs Settling Time
S 16-/14-Bit Resolution in a 3mm x 5mm, 8-Pin
µMAX Package
S Relative Accuracy
±0.4 LSB INL (MAX5215, 14 Bit) typ, 1 LSB (max)
±1.2 LSB INL (MAX5217, 16 Bit) typ, 4 LSB (max)
S Guaranteed Monotonic Over All Operating Range
S Low Gain and Offset Error
S Wide 2.7V to 5.5V Supply Range
S Rail-to-Rail Buffered Output Operation
S Safe Power-Up-Reset to Zero DAC Output
S I2C-Compatible 400kHz Serial Interface
S User-Programmable AUX Input Functions
CLR, Clear to 0, Midscale, or Full Scale
LDAC, Asynchronous Load DAC
S 256kI Reference Input Resistance for Low-Power
Operation
S Buffered Voltage Output Directly Drives 10kI
Loads
S Output Power-Down Terminated with 1kI or
100kI to Ground or Left High Impedance
Ordering Information appears at end of data sheet.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Functional Block Diagram
VDD
REF
POR
ADDR
I2C SERIAL
INTERFACE
SCL
SDA
CODE
REGISTER
DAC
REGISTER
14-/16-BIT
DAC
OUT
BUFFER
MAX5215
MAX5217
100kI
1kI
GND
(
) FOR AUX CONFIGURED AS CLR
AUX = CLR /LDAC
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5215.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6469; Rev 0; 11/12
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND..............................................................-0.3V to +6V
ADDR, REF, OUT,
AUX to GND........-0.3V to the lower of (VDD + 0.3V) and +6V
SCL, SDA, to GND...................................................-0.3V to +6V
Continuous Power Dissipation (TA = +70NC)
FMAX (derate at 4.8mW/NC above 70NC).....................387mW
Maximum Current into Any Input or Output..................... Q50mA
Operating Temperature Range......................... -40NC to +105NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
FMAX
Junction-to-Ambient Thermal Resistance (BJA).........206NC/W
Junction-to-Case Thermal Resistance (BJC)................42NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to 105NC, unless otherwise noted. Typical values are
at TA = +25NC.)(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (Note 3)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
N
INL
DNL
OE
MAX5215
14
MAX5217/MAX5217B
16
MAX5215 (14 bit) (Note 4)
-1
Q0.4
+1
MAX5217 (16 bit) (Note 4)
-4
Q1.2
+4
+8
MAX5217B (16 bit) (Note 4)
-8
Q3
MAX5215 (14 bit) (Note 4)
-1
Q0.1
+1
MAX5217/5217B (16 bit) (Note 4)
-1
Q0.25
+1
-1.25
Q0.25
+1.25
-3
Q0.5
-3
MAX5215/5217 (Note 5)
-0.06
-0.04
0
MAX5217B (Note 5)
-0.10
-0.04
0
MAX5215/5217 (Note 5)
MAX5217B (Note 5)
Offset-Error Drift
Gain Error
Bits
Q1.6
GE
Gain Temperature Coefficient
LSB
LSB
mV
FV/NC
%FS
ppm FS/
NC
Q2
REFERENCE INPUT
Reference-Input Voltage Range
VREF
2
Reference-Input Impedance
RREF
200
VDD
256
V
kI
DAC OUTPUT
Output Voltage Range (Note 6)
DC Output Impedance
Maxim Integrated
No load
0
10kI load to GND
0
10kI load to VDD
0.2
VDD
VDD - 0.2
V
VDD
0.1
I
2
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to 105NC, unless otherwise noted. Typical values are
at TA = +25NC.)(Note 2)
PARAMETER
SYMBOL
Maximum Capacitive Load (No
Sustained Oscillations)
CL
Resistive Load (Note 7)
RL
CONDITIONS
MIN
Series resistance = 0I
TYP
MAX
0.1
Series resistance = 1kI
UNITS
nF
15
FF
5
kI
Short-Circuit Current
VDD = 5.5V
Power-Up Time
From power-down mode
25
Fs
Positive and negative
0.5
V/Fs
¼ scale to ¾ scale, to Q0.5 LSB, 14 bit.
18
Fs
Hex code = 2000 (MAX5215),
Hex code = 8000 (MAX5217)
100
kHz
Digital Feedthrough
Code = 0, all digital inputs from 0V to
VDD, SCL < 400kHz
1.0
nV·s
DAC Glitch Impulse
Major code transition
5
nV·s
1kHz
73
10kHz
70
0.1Hz to 10Hz
3.5
-25
Q6
+25
mA
DYNAMIC PERFORMANCE (Note 7)
Voltage-Output Slew Rate
SR
Voltage-Output Settling Time
Reference –3dB Bandwidth
BW
Output Noise
Integrated Output Noise
nV/√Hz
FVP-P
POWER REQUIREMENTS
Supply Voltage
VDD
Supply Current
IDD
Power-Down Supply Current
PDIDD
2.7
5.5
V
No load; all digital inputs at 0V or VDD,
supply current only; excludes reference
input current.
70
80
FA
No load, all digital inputs at 0V or VDD
0.4
2
FA
DIGITAL INPUTS (SCL, SDA, AUX, ADDR )
Input High Voltage
VIH
Input Low Voltage
VIL
Hysteresis Voltage
VHYS
Input Leakage Current
IIN
Input Capacitance (Note 7)
CIN
ADDR Pullup/Pulldown Strength
0.7 x VDD
V
0.3 x VDD
0.15
VIN = 0V or VDD
(Note 8)
Q0.1
30
50
V
V
Q1
FA
10
pF
90
kI
0.2
V
DIGITAL OUTPUT (SDA)
Output Low Voltage
Maxim Integrated
VOL
ISINK = 3mA
3
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VREF = 2.5V to VDD, CL = 60pF, RL = 10kI, TA = -40NC to 105NC, unless otherwise noted. Typical values are
at TA = +25NC.)(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
TIMING CHARACTERISTICS
SCL Clock Frequency
fSCL
sBus Free Time Between a STOP
and a START Condition
tBUF
1.3
Fs
Hold Time for a Repeated START
Condition
tHD;STA
0.6
Fs
SCL Pulse Width Low
tLOW
1.3
Fs
SCL Pulse Width High
tHIGH
0.6
Fs
Setup Time for Repeated START
Condition
tSU;STA
0.6
Fs
Data Hold Time
tHD;DAT
0
Data Setup Time
tSU;DAT
100
900
ns
ns
SDA and SCL Receiving Rise Time
tr
20 + CB/10
300
ns
SDA and SCL Receiving Fall Time
tf
20 + CB/10
300
ns
tf
20 + CB/10
250
SDA Transmitting Fall Time
Setup Time for STOP Condition
tSU;STO
Bus Capacitance Allowed
CB
Pulse Width of Suppressed Spike
tSP
CLR Removal Time Prior to a
Recognized START
0.6
VDD = 2.7V to 5.5V
ns
Fs
10
400
50
pF
ns
tCLRSTA
100
ns
CLR Pulse Width Low
tCLPW
20
ns
LDAC Pulse Width Low
tLDPW
20
ns
400
ns
SCLK Rise to LDAC Fall Hold
tLDH
Applies to execution edge
Note 2: Electrical specifications are production tested at TA = +25°C and TA = +105°C. Specifications over the entire operating
temperature range are guaranteed by design and characterization. Typical specifications are at TA = +25°C and are not
guaranteed.
Note 3: Static accuracy tested without load.
Note 4: Linearity is tested within 20mV of GND and VDD.
Note 5: Gain and offset is tested within 20mV of GND and VDD.
Note 6: Subject to offset and gain error limits and VREF settings.
Note 7: Specification is guaranteed by design and characterization.
Note 8: Unconnected conditions on the ADDR_ inputs are sensed through a resistive pullup and pulldown operation; for proper
operation, the ADDR_ inputs must be connected to VDD, GND, or left unconnected with minimal capacitance.
Maxim Integrated
4
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
SDA
tLOW
tf
tSU;DAT
tr
tHD;STA
tf
tSP
tBUF
tr
SCL
tHD;STA
tCLPW
S
tHIGH
tSU;STA
tHD;DAT
tSU;STO
Sr
P
CLR
tLDPW
tLDH
tCLRSTA
S
LDAC
Figure 1. I2C Serial Interface Timing Diagram
Typical Operating Characteristics
(VDD = 5V, TA = +25°C, unless otherwise noted.)
0.4
0.2
0.2
0
-0.2
0
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
4096
8192
12288
DIGITAL INPUT CODE (LSB)
Maxim Integrated
16384
0
-1
-2
-1.0
0
MAX5217
VREF = 5V
2
1
-0.2
-0.4
3
MAX5215 toc02a
0.6
0.4
INL (LSB)
INL (LSB)
0.6
MAX5215
VREF = 2.5V
0.8
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
INL (LSB)
MAX5215
VREF = 5V
0.8
1.0
MAX5215 toc01a
1.0
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5215 toc01b
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
-3
0
4096
8192
12288
DIGITAL INPUT CODE (LSB)
16384
0
16384
32768
49152
65536
DIGITAL INPUT CODE (LSB)
5
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Characteristics (continued)
(VDD = 5V, TA = +25°C, unless otherwise noted.)
1.5
0
-1
MAX5217
0
-0.5
-1.0
0
MIN
-0.50
-0.75
-1.00
2.7
DEVICE NUMBER
3.5 3.9 4.3 4.7
SUPPLY VOLTAGE (V)
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
65536
MAX5217
2
1.00
MIN
7
9
11
13
15
17
19
MAX5215
0.50
INL (LSB)
0
5
0.75
MAX
1
3
3
0
MIN
-0.25
-1
5.1
5.5
MAX5217
MAX
1
MAX
0.25
3.1
2
INL (LSB)
3
1
MAX5215 toc05a
49152
MAX5215 toc04b
32768
MAX5215 toc05b
DIGITAL INPUT CODE (LSB)
16384
0
INL (LSB)
MAX
0.25
-0.25
-2.0
-2.5
-3.0
-3
MAX5215
0.75
0.50
1.0
0.5
-1.5
-2
1.00
INL (LSB)
INL MIN/MAX (LSB)
INL (LSB)
1
VREF = 5.0V
VREF = 2.5V
VREF = 5.0V
VREF = 2.5V
2.5
2.0
MAX5215 toc03
MAX5217
VREF = 2.5V
2
3.0
MAX5215 toc02b
3
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INL MIN/MAX
(VREF = 5.0V/2.5V)
MAX5215 toc04a
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
0
MIN
-1
-0.50
-2
-0.75
-1.00
-3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
-3
-40
5.5
SUPPLY VOLTAGE (V)
-20
0
20 40 60
TEMPERATURE (°C)
80
-40°C
+25°C
+105°C
COUNT (units)
60
50
40
30
80
100
MAX5217
-40°C
+25°C
+105°C
60
50
40
30
10
10
Maxim Integrated
20
40
60
TEMPERATURE (°C)
20
20
0
0
70
COUNT (units)
70
-20
80
MAX5215 toc06a
MAX5215
-40
MAX(ABS(INL)) DISTRIBUTION
vs. TEMPERATURE
MAX(ABS(INL)) DISTRIBUTION
vs. TEMPERATURE
80
100
MAX5215 toc06b
-2
0
0
0.10 0.20 0.30 0.40 0.50 0.60 0.70
LSB
0
0.4
0.8
1.2 1.6
LSB
2.0
2.4
2.8
6
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Characteristics (continued)
(VDD = 5V, TA = +25°C, unless otherwise noted.)
MAX5215
VREF = 5V
0.3
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5215
VREF = 2.5V
0.5
0.3
MAX5215 toc07c
0.5
MAX5215 toc07a
0.5
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5215 toc07b
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
MAX5217
VREF = 5V
0.4
0.3
-0.1
0.1
DNL (LSB)
DNL (LSB)
DNL (LSB)
0.2
0.1
-0.1
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.5
-0.5
-0.3
-0.4
12288
16384
16384
16384
32768
65536
49152
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
DNL MIN/MAX
(VREF = 5.0V/2.5V)
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
VREF = 5.0V
VREF = 2.5V
VREF = 5.0V
VREF = 2.5V
0.8
0.6
MAX5217
0.5
MAX5215 toc08
1.0
0.3
0.2
0.1
-0.1
DNL (LSB)
0.2
0.1
DNL (LSB)
0.4
0
0
-0.2
-0.2
-0.3
-0.6
-0.3
-0.4
-0.8
-0.4
-0.5
-1.0
32768
49152
65536
MIN
-0.1
-0.4
16384
MAX
0
-0.2
0
MAX5215
0.4
0.2
-0.5
3
1
5
7
9
11
13
15
17
19
3.1
2.7
3.5
3.9
4.3
4.7
5.1
DEVICE NUMBER
SUPPLY VOLTAGE (V)
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0.2
0.4
0.3
MAX
DNL (LSB)
0.1
0
-0.1
-0.2
MAX5215
0.4
0.2
0.1
0.1
MAX
0
-0.1
MIN
0
-0.3
-0.4
-0.4
-0.4
-0.5
-0.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
Maxim Integrated
5.1
5.5
MIN
-0.2
-0.3
3.5
MAX
-0.1
-0.3
3.1
MAX5217
0.3
0.2
-0.2
MIN
0.5
DNL (LSB)
0.3
0.5
MAX5215 toc10a
MAX5217
0.4
5.5
MAX5215 toc10b
DIGITAL INPUT CODE (LSB)
0.5
2.7
0
DIGITAL INPUT CODE (LSB)
MAX5215 toc09b
DNL (LSB)
12288
DIGITAL INPUT CODE (LSB)
0.3
DNL (LSB)
8192
DIGITAL INPUT CODE (LSB)
MAX5217
VREF = 2.5V
0.4
-0.5
4096
0
MAX5215 toc07d
0.5
8192
MAX5215 toc09a
4096
0
-0.5
-40
-20
0
20
40
60
TEMPERATURE (°C)
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
7
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Characteristics (continued)
(VDD = 5V, TA = +25°C, unless otherwise noted.)
0.75
0.50
MAX5215
0
2
0
0
3.5
3.9
4.3
4.7
5.1
5.5
-40
-20
0
GAIN ERROR vs. SUPPLY
-0.02
-0.03
MAX5215
-0.04
DRIFT (µV/°C)
GAIN ERROR vs. TEMPERATURE
VREF = 2.5V
14
10
-0.02
-0.03
MAX5215
-0.04
3.5
3.9
4.7
5.1
-0.06
5.5
-40
-20
0
0
20
40
60
80
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
FULL-SCALE OUTPUT
vs. SUPPLY VOLTAGE
FULL-SCALE OUTPUT
vs. TEMPERATURE
2.498
MAX5215
2.496
2.494
2.492
MAX5217
MAX5215
2.496
2.494
2.492
VREF = 2.5V
2.490
2.7
3.1
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
Maxim Integrated
5.1
5.5
-20
0
20
40
60
TEMPERATURE (°C)
0.50
78
76
80
100
VDD = 5V
VDD = 5.25V
74
72
70
68
66
62
60
-40
0.20
0.30
0.40
DRIFT (ppmFS/°C)
80
64
VREF = 2.5V
2.490
0.10
0
SUPPLY CURRENT vs. TEMPERATURE
2.498
OUTPUT VOLTAGE (V)
MAX5217
100
2.500
MAX5215 toc17
2.500
6
2
MAX5217
4.3
8
4
SUPPLY CURRENT (µA)
3.1
-40°C TO +105°C
BOX METHOD
12
MAX5215 toc18
2.7
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2
GAIN ERROR DRIFT
vs. TEMPERATURE DISTRIBUTION
MAX5217
OUTPUT VOLTAGE (V)
0
100
-0.05
-0.05
-0.06
80
-0.01
GAIN ERROR (%FS)
GAIN ERROR (%FS)
-0.01
60
0
MAX5215 toc14
VREF = 2.5V
40
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0
20
COUNT (UNITS)
3.1
MAX5215 toc15
2.7
6
4
MAX5217
0.25
8
MAX5215 toc16
0.2
10
MAX5215 toc19a
MAX5215
-40°C TO +105°C
BOX METHOD
12
COUNT (UNITS)
0.6
MAX5217
1.00
OFFSET ERROR (mV)
OFFSET ERROR (mV)
0.8
14
MAX5215 toc12
VREF = 2.5V
0.4
1.25
MAX5215 toc11
1.0
OFFSET ERROR DRIFT
vs. TEMPERATURE DISTRIBUTION
OFFSET ERROR vs. TEMPERATURE
MAX5215 toc13
OFFSET ERROR vs. SUPPLY VOLTAGE
VDD = 2.7V
MAX5215/MAX5217
NO LOAD
VDD = VREF
VOUT = MIDSCALE
-40
-20
0
20
40
VDD = 4V
60
80
100
TEMPERATURE (°C)
8
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Characteristics (continued)
(VDD = 5V, TA = +25°C, unless otherwise noted.)
55
MAX5215/MAX5217
NO LOAD
VDD = VREF
VOUT = ZEROSCALE
40
-40
-20
0
20
40
60
80
68
MAX5215
66
64
2.7
TEMPERATURE (°C)
SUPPLY CURRENT (µA)
3.1
3.5
3.9
4.3
0.3
0.2
0.1
NO LOAD
VDD = VREF
75
SUPPLY CURRENT (µA)
-40°C
0°C
+25°C
+85°C
+105°C
4.7
5.1
MAX5215
70
65
VREF = 5.0V
VREF = 2.5V
60
55
3.5
3.9
4.3
3.1
4.7
5.1
5.5
MAX5215 toc20b
3.5 3.9 4.3 4.7
SUPPLY VOLTAGE (V)
5.1
5.5
SUPPLY CURRENT vs. DAC CODE
80
MAX5217
NO LOAD
VDD = VREF
75
70
65
VREF = 5.0V
VREF = 2.5V
60
55
50
45
0
3.1
MAX5217
2.7
5.5
50
2.7
50
SUPPLY CURRENT vs. DAC CODE
80
MAX5215 toc21
0.6
0.4
55
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(POWER-DOWN MODE)
0.5
MAX5215
60
40
60
100
65
45
62
SUPPLY CURRENT (µA)
VDD = 2.7V
45
70
MAX5215 toc22a
50
MAX5217
72
70
MAX5215 toc22b
60
74
NO LOAD
VDD = VREF
VOUT = ZERO SCALE
75
SUPPLY CURRENT (µA)
VDD = 4V
65
76
SUPPLY CURRENT (µA)
VDD = 5.25V
VDD = 5V
NO LOAD
VDD = VREF
VOUT = MIDSCALE
78
80
MAX5215 toc20a
75
SUPPLY CURRENT (µA)
80
MAX5215 toc19b
80
70
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
0
2500
5000 7500 10,000 12,500 15,000
45
0
10,000 20,000 30,000 40,000 50,000 60,000
CODE
SUPPLY VOLTAGE (V)
VOUT vs. TIME
(EXITING POWER-DOWN MODE)
CODE
MAJOR CODE TRANSITION
(0x7FFF TO 0x8000)
MAX5215 toc24a
MAX5215 toc23
MAX5215/MAX5217
RL = 10kI
VREF = 5V
OUT = MIDSCALE
AC-COUPLED
1mV/div
OUT = MIDSCALE
1V/div
0V
MAX5217
VREF = 5V
NO LOAD
10µs/div
Maxim Integrated
4µs/div
9
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Characteristics (continued)
(VDD = 5V, TA = +25°C, unless otherwise noted.)
MAJOR CODE TRANSITION
(0x8000 TO 0x7FFF)
MAJOR CODE TRANSITION
(0x1FFF TO 0x2000)
MAX5215 toc24b
MAX5215 toc24c
MAX5215
VREF = 5V
NO LOAD
MAX5217
VREF = 5V
NO LOAD
OUT = MIDSCALE
AC-COUPLED
1mV/div
OUT = MIDSCALE
AC-COUPLED
1mV/div
4µs/div
4µs/div
MAJOR CODE TRANSITION
(0x2000 TO 0x1FFF)
SETTLING TO ±0.5 LSB 14 BIT
(VDD = VREF = 5V, CL = 100pF)
MAX5215 toc24d
MAX5215 toc25a
MAX5215
VREF = 5V
NO LOAD
18µs
OUT = MIDSCALE
AC-COUPLED
1mV/div
MAX5215/MAX5217
1/4 SCALE TO 3/4 SCALE
4µs/div
4µs/div
SETTLING TO ±0.5 LSB 14 BIT
(VDD = VREF = 5V, CL = 100pF)
DIGITAL FEEDTHROUGH
MAX5215 toc26
MAX5215 toc25b
MAX5215/MAX5217
3/4 SCALE TO 1/4 SCALE
VOUT
AC-COUPLED
50mV/div
SCL
5V/div
17µs
4µs/div
Maxim Integrated
400ns/div
10
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Characteristics (continued)
(VDD = 5V, TA = +25°C, unless otherwise noted.)
OUTPUT VOLTAGE
vs. OUTPUT CURRENT
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
2.40
2.35
2.30
VDD = 5V
VREF = 5V
2000
VDDI = 2.7V
LOW T0 HIGH
1500
VDD = 2.7V
HIGH T0 LOW
1000
0
0
1
2
3
4
5
6
0
-5
-10
-15
500
2.25
MAX5215 toc29
MAX5215 toc28
VDD = 5V
LOW T0 HIGH
VDD = 5V
HIGH T0 LOW
2500
0
1
2
3
4
5
-20
10
1
DIGITAL INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
100
1000
INPUT FREQUENCY (kHz)
DAC OUPUT NOISE DENSITY
vs. FREQUENCY
INTEGRATED OUTPUT NOISE
(0.1Hz TO 10Hz)
MAX5215 toc30
200
MAX5215/MAX5217
OUT
1µV/div
NOISE (nVRMS /√Hz)
175
MAX5215 toc31
2.45
3000
5
ATTENUATION (dB)
OUTPUT VOLTAGE (V)
2.50
3500
DIGITAL SUPPLY CURRENT (µA)
MAX5215 toc27
2.55
REFERENCE INPUT BANDWIDTH
vs. FREQUENCY
FULL-SCALE (CODE 0XFF00)
150
ZERO-SCALE (CODE 0x00FF)
125
MIDSCALE (CODE 0x8000)
100
75
50
1s/div
10
100
1k
10k
100k
FREQUENCY (Hz)
Maxim Integrated
11
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Pin Configuration
TOP VIEW
REF
1
ADDR
2
SCL
3
SDA
4
+
MAX5215
MAX5217
8
GND
7
VDD
6
OUT
5
AUX
µMAX
Pin Description
PIN
NAME
1
REF
FUNCTION
2
ADDR
3
SCL
I2C Serial Clock Input
4
SDA
I2C Serial Data Input
5
AUX
User-Configurable Active-Low Asynchronous Input.
When configured as CLR mode: drive AUX low to clear the contents of the input CODE and the DAC
registers and return the DAC to a user-selectable return state (default).
When configured as LDAC mode: drive AUX low to load the pending CODE register content to the
active DAC register.
6
OUT
Buffered DAC Voltage Output
7
VDD
Supply Voltage. Bypass VDD with a 0.1FF capacitor to GND.
8
GND
Ground
Reference Voltage Input. Bypass REF with a 0.1FF capacitor to GND.
I2C Device Address Input. Pull high, low, or do not connect to set the two LSBs of the device address.
Detailed Description
The MAX5215/MAX5217 are 14-bit and 16-bit singlechannel, low-power, high reference input resistance,
buffered voltage-output DACs. These devices feature a
fast 400kHz I2C serial interface. The MAX5215/MAX5217
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) circuit
to initialize the DAC output to code zero, and an output
buffer to allow rail-to-rail operation. The 2.7V to 5.5V
wide supply voltage range and low-power consumption
accommodate most low-power and low-voltage applications. On power-up, the MAX5215/MAX5217 reset the
DAC output to zero, providing additional safety for applications that drive valves or other transducers that need
to be off during power-up.
The MAX5215/MAX5217 feature a configurable asynchronous active-low input (AUX) that can be programmed
Maxim Integrated
by the user to act as either an asynchronous clear input
(CLR) or a load DAC input (LDAC). By default, the devices operate in CLR mode on power-up.
DAC Output (OUT)
The MAX5215/MAX5217 include an internal buffer on the
DAC output. The internal buffer provides improved load
regulation and transition glitch suppression for the DAC
output. The output buffer slews at 0.5V/Fs and drives
up to 10kI in parallel with 100pF. The analog supply
voltage (VDD) determines the maximum output voltage
range of the device as VDD powers the output buffer.
Under no-load conditions, the output buffer drives from
GND to VDD, subject to offset and gain errors. With a
10kI load to GND, the output buffer drives from GND to
within 200mV of VDD. With a 10kI load to VDD, the output
buffer drive from VDD to within 200mV of GND.
12
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
The DAC ideal output voltage is defined by:
VOUT = VREF x D/2N
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution
DAC Reference (REF)
The external reference input features a typical input
impedance of 256kI (independent of the DAC code) and
accepts an input voltage from +2V to VDD. Connect an
external voltage supply between REF and GND to apply
an external reference. Visit www.maximintegrated.com/
products/references for a list of available voltagereference devices.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to the control register or DAC, as determined by
the user command.
Within the device, there is a CODE register followed
by a DAC Latch register (see the Functional Diagram).
The contents of the CODE register hold pending DAC
output settings which can later be loaded into the DAC
register. The CODE register can be updated using both
CODE and CODE_LOAD user commands. The contents
of the DAC register hold the current DAC output settings. The DAC register can be updated directly from the
serial interface using the CODE_LOAD commands or can
upload the current contents of the CODE register using
LOAD commands or the LDAC logic input.
The contents of both CODE and DAC registers are
maintained during power-down states, so that when the
DAC is powered on, the previously stored output setting
is restored. Any CODE or LOAD commands issued during power-down states continue to update the register
contents.
AUX Configured as Clear Input, CLR
When configured in CLR mode, the AUX input performs
an asynchronous level sensitive CLEAR operation. If CLR
is pulled low, the CODE and DAC data registers are reset
to their clear values as defined by the user configuration
settings (see Table 9). User configuration settings are not
affected.
If CLR is asserted at any point during an I2C write
sequence, from that point on, and until CLR is deasserted, all I2C commands attempting to modify CODE or
DAC register contents are ignored. The CLR activity is
Maxim Integrated
given precedence and the commands are gated. In all
cases, the I2C interface continues to function according
to protocol, however slave ACK pulses beyond the command byte acknowledge will not be sent for gated command sequences (notifying the FP that the gated instructions are being ignored). This gating condition remains
in effect until the CLR condition is removed and a subsequent I2C START condition is recognized (beginning a
new I2C write sequence), meeting tCLRSTA requirements
(Figure 1). If CLR is driven low during an I2C command
read sequence, the exchange continues as normal,
however the data being read back may be stale, having
since been cleared. The user may determine the state of
the CLR pin by issuing a Part ID read command.
An equivalent software clear operation is provided
through the SW_CLEAR command.
AUX Configured as
Load DAC Input, LDAC
When configured in LDAC mode, the AUX input performs an asynchronous level sensitive LOAD operation
when it is pulled low. Internally, a dual register system
is provided, with pending DAC output settings stored in
a CODE register, while the current output settings are
stored in the DAC latches. When LDAC is pulled low,
the DAC latches are held in a transparent state, and
the CODE register contents are loaded and stored. This
allows several DACs to be updated simultaneously using
a common LDAC line, or allows the DAC to be quickly
updated to a pending setting via a single pin operation.
Users wishing to load new DAC data in direct response
to I2C activity can enable and connect LDAC permanently low. Users wishing to control the DAC update instance
independently of the I2C instruction should hold LDAC
high during programming cycles. Once the programming
is complete, LDAC may be strobed and the new DAC
codes will be loaded (this method allows simultaneous
updates of several devices). Be sure to observe the tLDH
timing requirements (Figure 1).
A software load operation is provided through the LOAD
or CODE_LOAD command. With the software load operation, the content of the CODE register will be latched into
the DAC register regardless of the status and configuration of the LDAC pin. Multiple MAX5215/MAX5217 can
be loaded synchronously using software load commands
in conjunction with the Broadcast ID.
13
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
I2C Serial Interface
is required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
The MAX5215/MAX5217 feature an I2C/SMBusKcompatible 2-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA and
SCL enable communication between the part and the
master at clock rates up to 400kHz. Figure 1 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX5215/MAX5217 by transmitting the proper slave address followed by the register
address and then the data word. Each transmit sequence
is framed by a START (S) or Repeated START (Sr) condition and a STOP (P) condition. Each word transmitted to
the part is 8 bits long and is followed by an acknowledge
clock pulse.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5215/
MAX5217 from high voltage spikes on the bus lines, and
minimize crosstalk and undershoot of the bus signals.
The MAX5215/MAX5217 can accommodate bus voltages higher than VDD up to a limit of 5.5V; bus voltages
lower than VDD are not recommended and may result in
significantly increased interface currents.
A master reading data from the MAX5215/MAX5217 must
transmit the proper slave address followed by a series
of nine SCL pulses for each byte of data requested. The
MAX5215/MAX5217 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition.
I2C START and STOP Conditions
SDA operates as both an input and an open-drain output.
A pullup resistor, typically 4.7kI, is required on SDA. SCL
operates only as an input. A pullup resistor, typically 4.7kI,
I2C Bit Transfer
One data bit is transferred during each SCL cycle. The data
on SDA must remain stable during the high period of the
SCL pulse. Changes in SDA while SCL is high are control
signals (see the I2C START and STOP Conditions section).
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
to the MAX5215/MAX5217. The master terminates transmission, and frees the bus, by issuing a STOP condition.
The bus remains active if a Repeated START condition is
generated instead of a STOP condition.
I2C Early STOP and
Repeated START Conditions
SMBus is a trademark of Intel Corp.
S
Sr
P
SCL
SDA
VALID START, REPEATED START, AND STOP PULSES
P
S
S
P
P
S
P
The MAX5215/MAX5217 recognize a STOP condition at
any point during data transmission except if the STOP
condition occurs in the same high pulse as a START
condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Transmissions ending in an early STOP condition
will not impact the internal device settings. If the STOP
occurs during a readback byte, the transmission is terminated and a later read mode request will begin transfer of
the requested register data from the beginning.
Table 1. Two LSBs of the Slave Address
Determined by the ADDR Input
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
Maxim Integrated
ADDR
A1
A0
GND
0
0
N.C.
0
1
VDD
1
1
14
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
I2C Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the R/W bit (Figure 1). The 5
MSBs (A[6:2]) are 00111 with the two LSBs (A[1:0]) determined by the input ADDR as shown in Table 1. Setting the
R/W bit to 1 configures the MAX5215/MAX5217 for read
mode. Setting the R//W bit to 0 configures the MAX5215/
MAX5217 for write mode. The slave address is the first
byte of information sent to the MAX5215/MAX5217 after
the START condition.
The MAX5215/MAX5217 have the ability to detect an
unconnected state on the ADDR input for additional
address flexibility; if leaving the ADDR input unconnected, be certain to minimize all loading on the pin (i.e. provide a landing for the pin, but do not any board traces.
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5215/MAX5217 devices
on a given I2C bus. All MAX5215/MAX5217 acknowledge
and respond to the broadcast device address 01010100
regardless of the state of the address input pin. The
broadcast is intended for use in write mode only (as indicated by R/W = 0 in the address given)
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked
9th bit that the MAX5215/MAX5217 use to handshake
receipt of each byte of data when in write mode as shown
in Figure 3. The MAX5215/MAX5217 pull down SDA
during the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master will retry
communication.
I2C Write Operation
(Standard Protocol)
A master device communicates with the MAX5215/
MAX5217 by transmitting the proper slave address
followed by command and data words. Each transmit
sequence is framed by a START or Repeated START
condition and a STOP condition as described above.
Each word is 8 bits long and is always followed by an
acknowledge clock (ACK) pulse as shown in Figure
4and Figure 5. The first byte contains the address of the
MAX5215/MAX5217 with R/W = 0 to indicate a write. The
second byte contains the register (or command) to be
written and the third and fourth bytes contain the data to
be written. By repeating register address plus data pairs
(Byte #2 through Byte #4 in Figure 4 and Figure 5), the
user can perform multiple register writes using a single
I2C command sequence; there is no limit as to how many
registers the user can write with a single command. The
MAX5215/MAX5217 support this capability for all useraccessible write mode commands.
I2C Write Operation
(Multibyte Protocol)
The MAX5215/MAX5217 support a multibyte transfer
protocol for some commands. In multibyte mode, once
a command is issued, that command is continuously
executed based on two byte data blocks for the duration
I2C operation. Essentially, bytes 1 to 4 are processed
normally, but for every two bytes of data provided after
CLOCK PULSE
FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
In read mode, the master pulls down SDA during the 9th
clock cycle to acknowledge receipt of data when the
MAX5215/MAX5217 are in read mode. An acknowledge
is sent by the master after each read byte to allow data
transfer to continue. A not-acknowledge is sent when the
master reads the final byte of data from the MAX5215/
MAX5217, followed by a STOP condition.
1
2
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 3. I2C Acknowledge
Maxim Integrated
15
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
START
SDA
WRITE BYTE #1:
DEVICE ADDRESS
WRITE BYTE #2:
USER COMMAND
WRITE BYTE #3:
DATA BYTE #1
WRITE BYTE #4:
DATA BYTE #2
0 0 1 1 1 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A 15 14 13 12 11 10 9
SCL
8 A 7 6 5 4 3
2
A ACK. GENERATED BY MAX5215/MAX5217
STOP
1
0
A
COMMAND EXECUTED
Figure 4. I2C Single Register Write Sequence
START
SDA
SCL
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS
0
0 1 1
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
1 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A 15 14 13 12 11 10 9
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
8 A 7 6 5
4 3
2 1
0 A
COMMAND1
EXECUTED
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
R7 R6 R5 R4 R3 R2 R1 R0 A 15 14 13 12 11 10 9
A ACK. GENERATED BY MAX5215/MAX5217
BYTE #7: DATAn LOW BYTE
(B[7:0])
8 A 7 6 5
4 3
2 1
STOP
0 A
COMMANDn
EXECUTED
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
byte 4, the originally requested command is executed
again with the latest byte pair provided as input data
(Figure 6). Multibyte protocol is enforced until a STOP
condition (or Repeated START) is encountered and this
provides a higher speed transfer mode that is useful in
servo DAC applications.
I2C Readback Operation
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse (Figure 7). The first byte contains the address
of the MAX5215/MAX5217 with R/W = 0 to indicate a write.
The second byte contains the register that is to be read
back. There is a Repeated START condition, followed by
the device address with R/W = 1 to indicate a read and
an acknowledge clock. The final two bytes in the frame
contain the register data readback followed by a STOP
Maxim Integrated
condition. The master has control of the SCL line but the
MAX5215/MAX5217 take over the SDA line. Following
each byte of data read back from the MAX5215/MAX5217
the master must acknowledge the transfer by pulling SDA
low. If additional bytes beyond those required to read back
the requested data are provided, the MAX5215/5217 will
continue to read back ones.
A user can read back the device’s configuration, Part
ID, CODE register, or DAC register contents using the
readback programming sequence as shown in Figure 7.
I2C Compatibility
The MAX5215/MAX5217 are fully compatible with existing I2C systems. SCL and SDA are high-impedance
inputs; SDA has an open drain which pulls the data line
low during the 9th clock pulse or as required for data
readback. Figure 8 shows a typical I2C application.
16
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
WRITE ADDRESS
BYTE #1: DEVICE ADDRESS
START
SDA
0
SCL
0 1 1
WRITE REGISTER NO.
BYTE #2: FIRST REG# = N
WRITE DATA
BYTE #3: REG(N)[15:8] DATA
1 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A 15 14 13 12 11 10 9
WRITE DATA
BYTE #4: REG(N)[7:0] DATA
8 A 7 6 5
4 3
2 1
0 A
REG N
UPDATED
ADDITIONAL DATA BYTE PAIRS
(2 BYTE BLOCKS)
WRITE DATA
BYTE #X-1: REG(N)[15:8] DATA
15 14 13 12 11 10 9
WRITE DATA
BYTE #X: REG(N)[7:0] DATA
8 A 7 6 5
4 3
2 1
STOP
0 A
REG N
UPDATED
A ACK. GENERATED BY MAX5215/MAX5217
Figure 6. Multiple Register Write Sequence (Multibyte Protocol)
START
SDA
SCL
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
READ ADDRESS
REPEATED BYTE #3: I2C SLAVE
START
ADDRESS
0 0 1 1 1 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A
READ DATA
BYTE #4: DATA1 HIGH
BYTE (B[15:8])
0 0 1 1 1 A1 A0 R A 15 14 13 12 11 10 9
A ACK. GENERATED BY MAX5215/MAX5217
READ DATA
BYTE #5: DATA1 LOW
BYTE (B[7:0])
STOP
8 A 7 6 5 4 3 2 1 0 -A
A ACK. GENERATED BY I2C MASTER
Figure 7. Standard I2C Read Sequence
µC
SDA
SCL
SCL
SDA
ADDR
MAX5215
MAX5217
+5V
SCL
SDA
ADDR
MAX5215
MAX5217
Figure 8. Typical I2C Application Circuit
Maxim Integrated
17
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
I2C User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5215/MAX5217. Table 2 provides
detailed information about the Command Registers.
No_Op Command (0x00)
The No_Op command (Table 3) has no external effect on
the device for I2C write. The asynchronous CLR input has
no effect on the No_Op command.
Table 2. I2C User Write Commands
WRITE
COMMAND
COMMAND BYTE
DATA BYTES
R7
R6
R5
R4
R3
R2
R1
R0
No-Op
(0x00)
0
0
0
0
0
0
0
0
Don’t Care
CODE_LOAD
(0x01)
0
0
0
0
0
0
0
1
CODE
(0x02)
0
0
0
0
0
0
1
LOAD
(0x03)
0
0
0
0
0
0
1
CODE_LOAD_m
(0x05)
0
0
0
0
0
1
0
CLR
GATED*
DESCRIPTION
No operation: DAC settings
and modes unaffected
N
14-/16-bit code
Write and load data to the
CODE and DAC registers
Y
0
14-/16-bit code
Write data to the CODE
register
Y
1
Don’t Care
Load current CODE register
content to the DAC register
Y
Multiple sets of
14-/16-bit codes
Similar to CODE_LOAD
command, but accepts
multiple sets of dual-byte
data following the initial
command byte (see the I2C
Write Operation (Multibyte
Protocol) section)
Y
Y
1
CODE_m
(0x06)
0
0
0
0
0
1
1
0
Multiple sets of
14-/16-bit codes
Similar to CODE command,
but accepts multiple sets
of dual-byte data following
the initial command byte
(see the I2C Write Operation
(Multibyte Protocol) section)
USER_CONFIG
(0x08)
0
0
0
0
1
0
0
0
16-bit
configuration data
User configuration command
N
SW_RESET
(0x09)
0
0
0
0
1
0
0
1
Don’t Care
Software Reset
N
SW_CLEAR
(0x0A)
0
0
0
0
1
0
1
0
Don’t Care
Software Clear
N
Reserved
Any commands not specifically listed above are reserved for Maxim internal use only.
*Note: If a user write command is gated by CLR, and CLR has been asserted during the I2C write sequence, the command is
ignored and the associated data bytes will not be acknowledged. If a user write command is not gated by CLR, the command is
executed as normal, regardless of the activity of the CLR pin.
Table 3. No_Op Command (0x00)
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
0000_0000
No_Op Command
Don’t Care
Don’t Care
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Maxim Integrated
B1
B0
18
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
CODE_LOAD Command (0x01)
LOAD Command (0x03)
The CODE_LOAD command (Table 4) is the combination of the CODE command and LOAD command. The
CODE_LOAD command is executed on the SCL rising
edge following the 2nd data byte. Upon its execution, the
CODE_LOAD command updates the CODE register and
the DAC latch with the user data content provided.
The LOAD command (Table 6) is executed on the SCL
rising edge following the 2nd data byte. The LOAD command loads the DAC latches with the current contents of
the CODE register. Alternatively, a load operation can be
achieved by driving the AUX input low (when configured
as LDAC).
The asynchronous CLR input gates this command if it is
asserted during the I2C write sequence.
The asynchronous CLR input gates this command if it is
asserted during the I2C write sequence.
CODE Command (0x02)
The CODE command (Table 5) is executed on the SCL
rising edge following the 2nd data byte. The CODE
command updates the CODE register with the user data
content provided.
The asynchronous CLR input gates this command if it is
asserted during the I2C write sequence.
CODE_LOAD_m Command (0x05)
The CODE_LOAD_m command (Table 7) is the multibyte
version of the CODE_LOAD command. The CODE_
LOAD_m command is initially executed on the SCL rising
edge following the 2nd data byte. The command is subsequently executed after each pair of data bytes which follow,
for the duration of the operation (see the I2C Write Operation
(Multibyte Protocol) section).
The asynchronous CLR input gates this command if it is
asserted during the I2C write sequence.
Table 4. CODE_LOAD Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
0000_0001
16-bit CODE_LOAD Command
CODE and DAC Registers Data
CODE and DAC Registers Data
0000_0001
14-bit CODE_LOAD Command
CODE and DAC Registers Data
CODE and
DAC Registers Data
COMMAND BYTE
DATA HIGH BYTE
B0
Don’t
Care
DATA LOW BYTE
Table 5. CODE Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
0000_0010
16-bit CODE Command
CODE Register Data
0000_0010
14-bit CODE Command
CODE Register Data
COMMAND BYTE
DATA HIGH BYTE
B8
B7
B6
B5
B4
B3
B2
B1
B0
CODE Register Data
Don’t
Care
CODE Register Data
DATA LOW BYTE
Table 6. Load Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
0000_0011
LOAD Command
Don’t Care
Don’t Care
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Maxim Integrated
B1
B0
19
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
CODE_m Command (0x06)
USER_CONFIG Command (0x08)
The CODE_m command (Table 8) is the multibyte version of the CODE command. The CODE_m command
is initially executed on the SCL rising edge following
the 2nd data byte. The command is subsequently executed after each pair of data bytes which follow, for the
duration of the operation (see the I2C Write Operation
(Multibyte Protocol) section). This command is of practical use when the AUX pin is configured as LDAC and
continuously asserted low.
The USER_CONFIG command allows the user to select
the configuration of the device: setting the clear value
to which the DAC returns in response to a CLEAR
event, configuring the input mode for AUX, and setting
the power-down mode for the MAX5215/MAX5217.
The USER_CONFIG command is executed on the SCL
rising edge following the 2nd data byte. Table 9 and
Table 10 describe the command and the configuration
bits in detail.
The asynchronous CLR input gates this command if it is
asserted during the I2C write sequence.
The asynchronous CLR input has no effect on the USER_
CONFIG command.
Table 7. CODE_LOAD_m Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
0000_0101
16-bit CODE_LOAD_m Command
CODE and DAC Registers Data
CODE and DAC Registers Data
0000_0101
14-bit CODE_LOAD_m Command
CODE and DAC Registers Data
CODE and
DAC Registers Data
COMMAND BYTE
DATA HIGH BYTE
B0
Don’t
Care
DATA LOW BYTE
Table 8. CODE_m Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
B1
0000_0110
16-bit CODE_m Command
CODE and DAC Registers Data
CODE and DAC Registers Data
0000_0110
14-bit CODE_m Command
CODE and DAC Registers Data
CODE and
DAC Registers Data
COMMAND BYTE
DATA HIGH BYTE
B0
Don’t
Care
DATA LOW BYTE
Table 9. USER_CONFIG Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
0000_1000
USER_CONFIG Command
DATA DEFAULT VALUEg
COMMAND BYTE
Maxim Integrated
B8
X
X
X
X
B6
Don’t
Care
Don’t Care
X
B7
X
DATA HIGH BYTE
X
X
X
X
B5
B4
Clear
Value
Mode:
00 =
Default
01 =
Zero
10 = Mid
11 = Full
0
0
B3
B2
AUX
Input
Mode:
00 =
Disable
01 =
LDAC
10 =
CLR
11 =
Disable
1
0
B1
B0
PowerDown
Mode:
00 =
DAC
01 =
High-Z
10 =
100kI
11 = 1kI
0
0
DATA LOW BYTE
20
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
SW_RESET Command (0x09)
The SW_RESET command (Table 11) resets the CODE
register, the DAC latch, and all the configurations programmed via the USER_CONFIG command to the POR
default values. The SW_RESET command is executed on
the SCL rising edge following the second data byte.
The asynchronous CLR input has no effect on the
SW_RESET command.
SW_CLEAR Command (0x0A)
The SW_CLEAR command (Table 12) will clear the CODE
register and the DAC latch to the clear value selected in
the USER_CONFIG register. The SW_CLEAR command
is executed on the SCL rising edge following the 2nd data
byte. Alternatively, a clear operation can be achieved by
driving the AUX input low (when configured as CLR).
The asynchronous CLR input has no effect on the
SW_CLEAR command.
Table 10. User_Configuration Bits (B[5:0])
CONFIGURATION
BITS
CLEAR VALUE
(B[5:4])
CONFIGURATION DETAIL
The DAC value to be cleared to in response to a CLEAR event:
00: POR default value (zero scale)
01: Zero scale (ground)
10: Midscale
11: Full scale (reference)
AUX MODE
(B[3:2])
The mode in which the AUX input will operate:
00: Pin disabled
01: Enable LDAC functionality
10: Enable CLR functionality. Default after POR.
11: Pin disabled
Power-Down
Mode (PD)
(B[1:0])
Power-down mode for the device:
00: Normal operation: The DAC will be powered up and returned to its previous setting. Default after POR.
01: Power-down: The DAC core will be powered down and VOUT is high-impedance.
10: Power-down: The DAC core will be powered down and VOUT is connected to ground via 100kI.
11: Power-down: The DAC core will be powered down and VOUT is connected to ground via 1kI.
Table 11. SW_RESET Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
0000_1001
SW_RESET Command
Don’t Care
Don’t Care
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
B1
B0
B1
B0
Table 12. SW_CLEAR Command
R7
R6
R5
R4
R3
R2
R1
R0 B15 B14 B13 B12 B11 B10 B9
B8
B7
B6
B5
B4
B3
B2
0000_1010
SW_CLEAR Command
Don’t Care
Don’t Care
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Maxim Integrated
21
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
User Read Command Descriptions
The MAX5215/MAX5217 allow the user to read back
the data for supported registers. Table 13 lists the User
Readback commands and the 2 data byte contents
being read back. For the MAX5215, CODE and DAC
read back, the data content is left justified and the 2
LSBs ([1:0]) of the input 2-byte data are not used and
read out as 0.
Applications Information
Power-On Reset (POR)
When power is applied to VDD, the input registers are set
to zero so the DAC output is set to code zero. Initially the
device powers up to an untrimmed zero code setting.
The device will operate in a fully trimmed mode following
the first I2C operation which modifies DAC latch content.
Power Supplies and
Bypassing Consideations
Bypass VDD with high-quality ceramic capacitors to
a low-impedance ground as close as possible to the
device. Minimize lead lengths to reduce lead inductance.
Connect the GND input to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5215/MAX5217 GND.
Carefully lay out the traces to reduce AC cross-coupling.
Do not use wire-wrapped boards and sockets. Use
shielding to improve noise immunity. Do not run analog
and digital signals parallel to one another, especially
clock signals. Avoid routing digital lines underneath the
MAX5215/MAX5217 package.
Table 13. User Readback Command and Content
R7
R6
R5
R4
R3
R2
R1
R0
READ COMMAND
READ DATA1
HIGH BYTE D[15:8]
READ DATA1
LOW BYTE D[7:0]
0
0
0
0
0
0
0
0
ID Readback
(0x00)
0011100, CLEAR
Status
(0x11)
0
0
0
0
0
0
0
1
CODE_LOAD Readback
(0x01)
DAC_latch[15:8]
DAC_latch[7:0]
0
0
0
0
0
0
1
0
CODE Readback
(0x02)
CODE_register[15:8]
CODE_register[7:0]
0
0
0
0
0
0
1
1
LOAD Readback
(0x03)
DAC_latch[15:8]
DAC_latch[7:0]
0
0
0
0
0
1
0
1
CODE_LOAD_m Readback
(0x05)
DAC_latch[15:8]
DAC_latch[7:0]
0
0
0
0
0
1
1
0
CODE_m Readback
(0x06)
CODE_register[15:8]
CODE_register[7:0]
0
0
0
0
1
0
0
0
CONFIG Readback
(0x08)
0000_0000
00, CLEAR_VALUE[1:0],
AUX_MODE[1:0], PD[1:0]
Maxim Integrated
22
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL is
greater than -1 LSB, the DAC guarantees no missing
codes and is monotonic.
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Maxim Integrated
Settling Time
The settling time is the amount of time required from
the start of a transition, until the DAC output settles to
the new output value within the measurment’s specified
accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
Digital-to-Analog
Power-Up Glitch Impulse
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
23
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Typical Operating Circuit
V+
VREF_IN
100nF
4.7µF
VREF_OUT
MAX6133
100nF
VDD
AUX
V+
OUT
DAC
VOUT = -VREF TO +VREF
VOUT
ADDR
µC
SCL
MAX5215
MAX5217
SDA
V+
REF
VR1
R2
R1 = R2
GND
V-
BIPOLAR OPERATION
V+
VREF_IN
100nF
4.7µF
MAX6133
VREF_OUT
100nF
VDD
AUX
OUT
DAC
VOUT = 0V TO VREF
VOUT
ADDR
µC
SCL
SDA
MAX5215
MAX5217
REF
GND
UNIPOLAR OPERATION
Maxim Integrated
24
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Ordering Information
PIN-PACKAGE
RESOLUTION (BITS)
INL MAX (LSB)
MAX5215GUA+
PART
8 FMAX
14
Q1
MAX5217GUA+
8 FMAX
16
Q4
MAX5217BGUA+
8 FMAX
16
Q8
Note: All devices are specified over the -40°C to +105°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
R = Tape and reel.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 FMAX
U8+3
21-0036
90-0092
25
MAX5215/MAX5217
14-/16-Bit, Low-Power, Buffered Output,
Rail-to-Rail DACs with I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012
Maxim Integrated
26
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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