MAX532BCWE

19-0046; Rev. 1; 3/94 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC ________________________Applications Automatic Test Equipment Arbitrary Waveform Generators ____________________________Features ♦ Two 12-Bit MDACs with Output Amplifiers ♦ Fast, 6MHz 3-Wire Interface ♦ SPI, QSPI, and Microwire Compatible ♦ ±12V Output Swing ♦ ±10mA Output Current ♦ 2.5µs Settling Time to ±1/2LSB ♦ Guaranteed Monotonic Over Temperature ♦ Low Integral Nonlinearity: ±1/2LSB Max ♦ Low Gain Tempco: 2ppm/°C ♦ Operates from ±12V to ±15V Supplies ♦ Power-On Reset ♦ Available in 16-Pin DIP and Wide SO Packages ______________Ordering Information PART TEMP. RANGE PIN-PACKAGE Programmable-Gain Amplifiers Motion Control Systems Servo Controls ________________Functional Diagram ERROR (LSBs) MAX532ACPE 0°C to +70°C 16 Plastic DIP ±1/2 MAX532BCPE MAX532ACWE MAX532BCWE MAX532BC/D 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* ±1 ±1/2 ±1 ±1 Ordering Information continued on last page. * Contact factory for dice specifications. VDD __________________Pin Configuration MAX532 DACA LATCH RFBA VREFA DACA DIN SCLK TOP VIEW VOUTA RFBA 1 16 V DD VREFA 2 15 LDAC DOUT VOUTA 3 RFBB AGNDA 4 AGNDB 5 12 DOUT VOUTB 6 11 SCLK VREFB 7 10 DGND AGNDA 24-BIT SHIFT REGISTER CS DACB LDAC DACB LATCH VREFB VOUTB AGNDB 14 CS MAX532 RFBB 8 VSS DGND 13 DIN 9 V SS DIP/Wide SO ™Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. 1 MAX532 _______________General Description The MAX532 is a complete, dual, serial-input, 12-bit multiplying digital-to-analog converter (MDAC) with output amplifiers. No external user trims are required to achieve full specified performance. The MAX532’s 3wire serial interface minimizes the number of package pins, so it uses less board space than parallel-interface parts. The interface is SPI™, QSPI™ and Microwire™ compatible. A serial output, DOUT, allows cascading of two or more MAX532s and read-back of the data written to the device. The device’s serial interface minimizes digital-noise feedthrough from its logic pins to its analog outputs. Serial interfacing also simplifies opto-coupler-isolated or transformer-isolated applications. The MAX532 is specified with ±12V to ±15V power supplies. All logic inputs are TTL and CMOS compatible. It comes in space-saving 16-pin DIP and wide SO packages. MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC ABSOLUTE MAXIMUM RATINGS Pin Voltages VDD to DGND, AGNDA, AGNDB........................-0.3V to +17V VSS to DGND, AGNDA, AGNDB (Note 1) ..........+0.3V to -17V VREFA, VREFB.............................(VSS - 0.3V) to (VDD + 0.3V) AGNDA, AGNDB .....................(DGND - 0.3V) to (VDD + 0.3V) VOUTA, VOUTB ...........................(VSS - 0.3V) to (VDD + 0.3V) RFBA, RFBB.................................(VSS - 0.3V) to (VDD + 0.3V) SCLK, DIN, DOUT, LDAC, CS ..(DGND - 0.3V) to (VDD + 0.3V) DOUT Sink Current .............................................................20mA Continuous Power Dissipation (TA = +70°C) Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW Wide SO (derate 9.52mW/°C above +70°C)................762mW CERDIP (derate 10.00mW/°C above +70°C) ...............800mW Operating Temperature Ranges: MAX532_C__ ......................................................0°C to +70°C MAX532_E__....................................................-40°C to +85°C MAX532_MJE ................................................-55°C to +125°C Junction Temperatures: MAX532_C__, E__........................................................+150°C MAX532_MJE...............................................................+175°C Storage Temperature Range ........................... -65°C to +160°C Lead Temperature (soldering, 10sec) ........................... +300°C Note 1: If VSS is open-circuited with VDD and either AGND applied, the VSS pin will float positive, exceeding the Absolute Maximum Ratings. A Schottky diode connected between VSS and GND ensures the maximum ratings will not be exceeded. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2kΩ, CL = 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (Note 1) Resolution Relative Accuracy Differential Nonlinearity Zero-Code Offset Error Zero-Code Offset Temperature Coefficient 12 INL Bits MAX532A ±1/2 MAX532B ±1 Guaranteed monotonic DAC latch loaded with all 0s ±1 TA = +25°C, MAX532_ ±2 TA = TMIN to TMAX, MAX532A ±3 TA = TMIN to TMAX, MAX532B ±4 DAC latch loaded with all 0s ±5 MAX532A ±2 MAX532B ±5 TA = TMIN to TMAX, DAC latch loaded with all 1s MAX532A ±4 MAX532B ±7 Gain-Error Temperature Coefficient LSB mV µV/°C TA = +25°C, DAC latch loaded with all 1s Gain Error LSB LSB ppm/°C of FSR ±2 REFERENCE INPUTS (VREFA, VREFB) VREFA, VREFB Input Resistance VREFA, VREFB Input Resistance Matching 2 8 10 13 kΩ ±0.5 ±3.0 % _______________________________________________________________________________________ Dual, Serial-Input, Voltage-Output, 12-Bit MDAC (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2kΩ, CL = 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS DIGITAL INPUTS (SCLK, DIN, LDAC, CS) VINH Input High Voltage MIN TYP 2.4 Digital inputs at 0V or VDD Input Current Input Capacitance (Note 2) DIGITAL OUTPUT (DOUT) (Note 3) Output Voltage Low VOL Output High Leakage ILKG Output High Capacitance (Note 2) COUT ISINK = 5mA 0.08 ISINK = 16mA 0.2 VDOUT = 0V to VDD ANALOG OUTPUTS (VOUTA, VOUTB) DC Output Impedance Short-Circuit Current VOUTA, VOUTB connected to AGNDA, AGNDB POWER REQUIREMENTS Positive Supply Voltage Negative Supply Voltage Power-Supply Rejection Positive Supply Current Negative Supply Current AC CHARACTERISTICS Voltage-Output Settling Time VDD VSS V ±1 µA 8 pF 0.4 µA 15 pF Ω mA V 16.5 -16.5 ∆Full scale/∆VDD, VDD = 11.4V to 16.5V, VREF = -8.9V, DAC latches loaded with all 1s ±0.035 ∆Full scale/∆VSS, VSS = -11.4V to -16.5V, VREF = 8.9V, DAC latches loaded with all 1s ±0.035 PSR IDD ISS V ±10 0.2 20 11.4 -11.4 V V LSB/% Output unloaded Output unloaded 5 4 Settling time to within 1/2 LSB of final DAC value; DAC latch alternately loaded with all 0s and all 1s Slew Rate Digital-to-Analog Glitch Impulse 0.8 (VDD - 2.5) to (VSS + 2.5) Output Voltage Swing UNITS V VINL Input Low Voltage MAX DAC latch alternately loaded with 011...11 and 100...00 VREFA to VOUTB Channel-to-Channel Isolation VREFB to VOUTA VREFA = 20Vp-p 10kHz sine wave; DAC latches loaded with all 0s VREFB = 20Vp-p 10kHz sine wave; DAC latches loaded with all 0s 10 6 mA mA 2.5 µs 8 V/µs 60 nV-s -100 dB -100 _______________________________________________________________________________________ 3 MAX532 ELECTRICAL CHARACTERISTICS (continued) MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC ELECTRICAL CHARACTERISTICS (continued) (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V, VREFA and VREFB = +10V, RL = 2kΩ, CL = 100pF, VOUT_ connected to RFB_, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Multiplying Feedthrough Error VREF = 20Vp-p 10kHz sine wave; DAC latch loaded with all 0s -77 dB Unity-Gain Small-Signal Bandwidth VREF = 100mVp-p sine wave; DAC latch loaded with all 1s 1.0 MHz Full-Power Bandwidth VREF = 20Vp-p sine wave; DAC latch loaded with all 1s 125 kHz VREF = 6VRMS, 1kHz sine wave; DAC latch loaded with all 1s -90 dB Digital Feedthrough CS = 1; transitions on SCLK, LDAC, DIN 1.1 nV-s Digital Crosstalk Output Noise Voltage DACA code all 1s, DACB code transition from all 0s to all 1s 0.1Hz to 10Hz 10 2 nV-s µVRMS Total Harmonic Distortion THD Note 1: Static performance tested at VDD = +15V, VSS = -15V. Performance over supplies guaranteed by PSR test. Note 2: Guaranteed by design. Not subject to production testing. Note 3: Open-drain output. TIMING CHARACTERISTICS (VDD = 11.4V to 16.5V, VSS = -11.4V to -16.5V, AGNDA = AGNDB = DGND = 0V) (Notes 4, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 6.25 MHz SCLK Clock Frequency fCLK SCLK Pulse Width High tCH 80 ns SCLK Pulse Width Low tCL 80 ns DIN to SCLK Rise Setup Time tDS 50 ns DIN to SCLK Rise Hold Time tDH 0 ns CS Fall to SCLK Rise Setup Time tCSS0 50 ns CS Rise to SCLK Rise Setup Time tCSS1 50 ns SCLK Fall to CS Fall Hold Time tCSH0 5 ns SCLK Rise to CS Rise Hold Time tCSH1 80 ns CS Pulse Width High tCSW 120 SCLK Fall to DOUT Valid (Note 6) tDO CL = 20pF, RPULL-UP = 1kΩ to 5V CS Fall to DOUT Enable (Note 7) tDV CS Rise to DOUT Disable (Note 7) tTR LDAC Pulse Width Low CS Rise to LDAC Fall Setup Time tLDAC tLDACS 0 ns 200 ns CL = 20pF, RPULL-UP = 1kΩ to 5V 100 ns CL = 20pF, RPULL-UP = 1kΩ to 5V 60 ns 60 100 ns ns Note 4: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0V to 5V. Note 5: See Figure 1. Note 6: Timing is for SCLK fall to DOUT fall to 0.8V, or for SCLK fall to DOUT rise to 2.4V. Additional time must be added for any larger passive RC pull-up delay. Note 7: DOUT enable: DOUT falls to 4.5V from 5.0V. DOUT disable: DOUT rises to 0.5V from 0V. 4 _______________________________________________________________________________________ Dual, Serial-Input, Voltage-Output, 12-Bit MDAC OUTPUT VOLTAGE SWING vs. RESISTIVE LOAD NOISE SPECTRAL DENSITY LARGE-SIGNAL FREQUENCY RESPONSE 25 5 VOUT (Vp-p) 15 10 5 VREF = 0V DAC CODE = 11...111 GAIN = -1 300 -10 200 10 1k 100 VREF = 20Vp-p DAC CODE = 11...111 GAIN = -1 -15 -20 -25 100 -30 -35 0 0 -40 10 10k 100 1k 100k 10k 100 1k 10k 100k 1M 10M LOAD RESISTANCE (Ω) FREQUENCY (Hz) FREQUENCY (Hz) SMALL-SIGNAL FREQUENCY RESPONSE MULTIPLYING FEEDTHROUGH ERROR TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH = 80kHz) 5 -94 -35 VREFA = 20Vp-p VREFB = AGNDB DAC CODE = 00...00 -40 0 VREF = 100mVp-p DAC CODE = 11...111 -10 -15 -50 -98 -55 -60 -65 -100 -102 -70 -75 -20 VREF = 6VRMS DAC CODE = 111...111 -96 THD (dB) ATTENUATION (dB) -45 -5 -104 -80 -25 -106 -85 100 1k 10k 100k 1M 10M 1k FREQUENCY (Hz) 10k 100k 100 1M 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) TOTAL HARMONIC DISTORTION + NOISE vs. FREQUENCY (BANDWIDTH > 500kHz) -60 VREF = 6VRMS DAC CODE = 111...111 -65 -70 THD (dB) GAIN (dB) 0 -5 GAIN (dB) NOISE SPECTRAL DENSITY (nV Hz) VREF = 20Vp-p at 1kHz 20 -75 -80 -85 -90 -95 -100 100 1k 10k 100k FREQUENCY (Hz) _________________________________________________________________________________________________ 5 MAX532 __________________________________________Typical Operating Characteristics (VDD = 15V, VSS = -15V, RL = 2kΩ, CL = 100pF, unless otherwise noted.) MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC ____________________________Typical Operating Characteristics (continued) (VDD = 15V, VSS = -15V, RL = 2kΩ, CL = 100pF, unless otherwise noted.) SMALL-SIGNAL PULSE RESPONSE AGNDA LARGE-SIGNAL PULSE RESPONSE A A = VOUTA, 50mV/div TIMEBASE = 2µs/div VREFA = ±100mV SQUARE WAVE AGNDA A A = VOUTA, 5V/div TIMEBASE = 2µs/div VREFA = ±10V SQUARE WAVE ______________________________________________________________Pin Description PIN 6 NAME FUNCTION 1 RFBA Feedback Resistor for DACA 2 VREFA Reference Input for DACA 3 VOUTA Voltage Output for DACA 4 AGNDA Analog Ground for DACA 5 AGNDB Analog Ground for DACB 6 VOUTB Voltage Output for DACB 7 VREFB Reference Input for DACB 8 RFBB Feedback Resistor for DACB 9 VSS 10 DGND 11 SCLK 12 DOUT 13 DIN 14 CS 15 LDAC 16 VDD Negative Supply Voltage Digital Ground Serial Clock Input Serial Data Output. Open-drain N-channel MOSFET output: requires external pull-up resistor. Data on DOUT changes on the falling edge of SCLK. Serial output data is delayed 24 clock cycles from DIN. Serial Data Input. CMOS- and TTL-compatible input. Data is clocked into DIN on the rising edge of SCLK. CS must be low for data to be clocked in. Chip-Select Input, active low. Data is shifted in and out when CS is low. DAC latches are updated when CS is high and LDAC is low. Asynchronous Load DAC Input, active low. DAC latches are updated when CS is high and LDAC is low. Positive Supply Voltage _______________________________________________________________________________________ Dual, Serial-Input, Voltage-Output, 12-Bit MDAC tCSW tCSH1 tLDACS CS tCSHO tCSSO tCH tCSS1 tCL SCLK tDS tDH D0 DIN tDV D1 D23 tD0 Q0 DOUT tTR Q1 Q23 D0 LDAC tLDAC DACS UPDATED Figure 1. Timing Diagram _______________________________________________________________________________________ 7 MAX532 ____________________________________________________________Timing Diagrams MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC _______________________________________________Timing Diagrams (continued) CS DACS UPDATED SCLK DIN D23............................................D16 MSB DACB D15 D14 D13 D12 D11.......... LSB DACB D1 D0 MSB DACA LSB DACA DOUT Q23 Q22..................................... Q16 MSB DACB FROM PREVIOUS WRITE Q15 Q14 Q13 Q12 Q11.......... MSB DACA FROM PREVIOUS WRITE Q1 Q0 D23 D23 Figure 2. 3-Wire Interface Timing Diagram (LDAC = DGND) CS SCLK DIN D23............................................D16 MSB DACB D15 D14 D13 D12 D11.......... LSB DACB MSB DACA D1 D0 LSB DACA DOUT Q23 Q22 ................................... Q16 MSB DACB FROM PREVIOUS WRITE Q15 Q14 Q13 Q12 Q11.......... MSB DACA FROM PREVIOUS WRITE Q1 Q0 D23 D23 LDAC DACS UPDATED Figure 3. 4-Wire Inferface Timing Diagam 8 _______________________________________________________________________________________ Dual, Serial-Input, Voltage-Output, 12-Bit MDAC 1k MAX532 MAX532 5V 5V 1k SCLK SK DOUT MISO DIN SO DIN MOSI DOUT SI MICROWIRE PORT MAX532 SCLK CS I/O CS LDAC I/O LDAC THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX532, BUT MAY BE USED FOR READ-BACK PURPOSES. SCK SS SPI PORT I/O I/O CPOL = 0, CPHA = 0 THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX532, BUT MAY BE USED FOR READ-BACK PURPOSES. Figure 4. Connections for Microwire Figure 5. Connections for SPI _______________Detailed Description the device’s 24-bit shift register. The data at DOUT is delayed 24 clock cycles from the data at DIN (see Figures 2 and 3, and the Functional Diagram). DOUT is an open-drain N-channel MOSFET that requires an external pull-up resistor (typically 1kΩ if pulled up to +5V, and 3kΩ if pulled up to +12V or +15V). Logic levels are guaranteed with sink currents up to 5mA (see Electrical Characteristics). Output data changes on the falling edge of SCLK when CS is low. If CS is high, DOUT is three-state (high-impedance). Digital Interface The MAX532 is Microwire and SPI compatible (Figures 4 and 5). Both DACs are programmed by writing three 8-bit words (see Figures 2 and 3, and the Functional Diagram). Serial data is clocked into the data registers MSB first, with DACB information preceding DACA information. Data is clocked in on the rising edge of SCLK while CS is low. With CS high, data can not be clocked into DIN, and DOUT is high impedance. SCLK can be driven at rates up to 6.25MHz. The MAX532 uses either a 3-wire or a 4-wire serial interface. Three wires may be used (CS, DIN, SCLK) by tying LDAC low. With LDAC low, the DACs are updated simultaneously when CS goes high (see Figure 2 and the Functional Diagram). The 3-wire interface may be used if the MAX532 is used alone, or if two or more MAX532s are cascaded (DOUT of one device tied to DIN of the other) (Figure 6). The 4-wire interface (LDAC, CS, DIN, SCLK) is required if several serial devices are tied to the same data line, and it is desirable to update them simultaneously (Figure 7). With the 4-wire interface, the DACs are updated when LDAC goes low (see Figure 3 and the Functional Diagram). A serial output, DOUT, allows cascading of two or more MAX532s and allows read-back of the data written to Daisy-Chaining Devices Any number of MAX532s can be daisy-chained by connecting the DOUT pin of one device (with a pull-up resistor) to the DIN pin of the following device in the chain (Figure 6). When daisy-chaining devices, tCSS0 (CS low to SCLK high), must be the greater of tDV + tDS or tDS + (tRC + tTR - tCS), where tCSW is the CS pulse width used in the system and the term (tRC + tTR - tCSW) accounts for the time spent charging the DOUT capacitance with the external pull-up resistor. So, for tRC < 250ns, tCSS0 is simply tDV + tDS. Calculate tRC using the following equation: tRC = RP x C x ln (VPULL-UP/(VPULL-UP - 2.4V)) where VPULL-UP is the voltage that the pull-up resistor is connected to, RP is the value of the pull-up resistor, and C is the capacitance at DOUT. Values of tRC are given in Table 1. _______________________________________________________________________________________ 9 MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC +5V +5V RP 1k RP 1k MAX532 SCLK SCLK DIN DIN CS CS RP 1k MAX532 SCLK DOUT +5V MAX532 SCLK DOUT DIN CS DOUT DIN CS LDAC LDAC LDAC TO OTHER SERIAL DEVICES MAX532 SCLK SCLK DIN DIN CS CS LDAC Figure 6. Daisy-chained or individual MAX532s are simultaneously updated by bringing CS high when using the 3-wire interface (LDAC = DGND). DIN SCLK LDAC CS1 CS2 CS3 TO OTHER SERIAL DEVICES CS CS CS LDAC LDAC LDAC SCLK DIN MAX532 MAX532 MAX532 SCLK SCLK DIN DIN Figure 7. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3, . . ., are driven separately, thus controlling which data are written to devices 1, 2, 3, . . . . 10 ______________________________________________________________________________________ Dual, Serial-Input, Voltage-Output, 12-Bit MDAC VPULL-UP (V) C (pF) RP (kΩ) tRC (ns) 4.5 20 1 15 4.5 35 1 27 4.5 50 1 38 4.5 100 1 76 4.5 150 1 114 11.4 20 3 14 11.4 35 3 25 11.4 50 3 35 11.4 100 3 71 11.4 150 3 106 13.5 20 3 12 13.5 35 3 21 13.5 50 3 29 13.5 100 3 59 13.5 150 3 88 Figure 8 shows a simplified circuit diagram for one of the DACs and the output amplifier. A segmented scheme is used to improve linearity, whereby the two MSBs of the 12-bit data word are decoded to drive the three switches, SA, SB, and SC. The remaining ten bits drive the switches S0 through S9 in a standard R-2R ladder configuration. Each of the switches, SA, SB, and SC, steers 1/4 of the total reference current with the remaining 1/4 passing through the R-2R section. The output amplifier and feedback resistor perform the current-to-voltage conversion, giving the following: VOUT_ = -D x VREF_, where _ denotes A or B, and D is the fractional representation of the digital word. (D can be set from 0 to 4095/4096.) +12V to +15V VDD With the values of tRC given in Table 1, tCSS0 is always given by tDV + tDS. For different values of R or C, tRC must be calculated to determine tCSS0. Additionally, the maximum clock frequency is limited to fCLK (max) = VIN VREFA 1 ————————————— . 2 x (tDO + tRC -15ns + tDS) VOUTA DACA DGND For example, with tRC = 15ns (5V ±10% supply with 1kΩ pull-up), the maximum clock frequency is 2MHz. RFBA VSS AGNDA VOUT MAX532 -12V to -15V Figure 9. Unipolar Binary Operation VREF_ R R 2R 2R 2R 2R SC SB SA S9 R 2R S8 2R 2R S0 R/2 RFB_ VOUT_ SHOWN FOR ALL 1s ON DAC AGND_ Figure 8. Simplified D/A Circuit Diagram ______________________________________________________________________________________ 11 MAX532 Digital-to-Analog Section Table 1. tRC Delay Times MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC Output Amplifiers The output amplifiers are stable with any combination of resistive loads ≥ 2kΩ and capacitive loads ≤ 100pF. They are internally compensated, and settle to ±0.01% FSR (1/2LSB) in 2.5µs. Unipolar Configuration Figure 9 shows DACA connected for unipolar binary operation. Similar connections apply for DACB. When VIN is an AC signal, the circuit performs two-quadrant multiplication. Table 2 shows the codes for this circuit. Bipolar Operation Figure 10 shows the MAX532 connected for bipolar operation. The coding is offset binary, as shown in Table 3. When VIN is an AC signal, the circuit performs four-quadrant multiplication. To maintain gain error specifications, resistors R1, R2, and R3 should be ratiomatched to 0.01%. Table 2. Unipolar Code Table DAC Latch Contents MSB Layout, Grounding, and Bypassing For best system performance, use printed circuit boards with separate analog and digital ground planes. Wirewrap boards are not recommended. The two ground planes should be tied together at the low-impedance power-supply source, as shown in Figure 11. The board layout should ensure that digital and analog signal lines are kept separate from each other as much as possible. Do not run analog and digital lines parallel to one another. The output amplifiers are sensitive to high-frequency noise in the VDD and V SS power supplies. Bypass these supplies to the analog ground plane with 0.1µF and 10µF bypass capacitors. Minimize capacitor lead lengths for best noise rejection. Table 3. Bipolar Code Table DAC Latch Contents Analog Output, VOUT LSB __________Applications Information MSB Analog Output, VOUT LSB 1111 1111 1111 -VIN x (4095/4096) 1111 1111 1111 +VIN x (2047/2048) 1000 0000 0000 -VIN x (2048/4096) = -1/2VIN 1000 0000 0001 +VIN x (1/2048) 0000 0000 0001 -VIN x (1/4096) 1000 0000 0000 0V 0000 0000 0000 0V 0111 1111 1111 -VIN x (1/2048) 0000 0000 0000 -VIN + (2048/2048) = -VIN 1LSB = VIN/4096 1LSB = VIN/2048 R2 20k R1 20k ANALOG SUPPLY DIGITAL SUPPLY VOUT +12V to +15V VDD VIN RFB_ VREF_ MAX532 VSS AGND_ -12V to -15V Figure 10. Bipolar Operation 12 -15V AGND VDD VSS AGNDA +5V DGND VOUT_ DAC_ DGND +15V R3 10k AGNDB DGND MAX532 Figure 11. Power-Supply Grounding ______________________________________________________________________________________ +5V DGND DIGITAL CIRCUITRY Dual, Serial-Input, Voltage-Output, 12-Bit MDAC MAX532 DACA R 2 VIN 1 RFBA VREFA 2 4096 CODE R/2 VOUTA 3 VOUT AGNDA 4 VOUT VIN = -4096 CODE R 4096 REQA = —— (————) , 2 CODE Figure 12. Programmable-Gain Amplifer where CODE is the DAC code in decimal. The transfer function is thus: VOUT ——— = VIN -4096 ——— CODE The code may be programmed between 1 and (212 -1). The zero code is not allowed, as it results in an openloop amplifier response. Power-On Reset On power-up, the internal DAC latches are set to 00 . . . . .00. ______________________________________________________________________________________ 13 MAX532 Programmable-Gain Amplifier (PGA) The DAC/amplifier combination, along with access to the feedback resistors, makes the MAX532 ideal as a programmable-gain amplifier. In this application, the DAC functions as a programmable resistor in the feedback loop. This type of configuration is shown in Figure 12, and is suitable for AC gain control. The DAC code controls the gain for the PGA. As the code decreases, the effective DAC resistance increases, and so the gain also increases. The transfer function is given by: VOUT/VIN = -REQA/RFBA, where RFBA is the value of the feedback resistor (R/2), and REQA is the effective DAC resistance controlled by the digital input code: MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC __Ordering Information (continued) PART TEMP. RANGE PIN-PACKAGE ERROR (LSBs) MAX532AEPE -40°C to +85°C 16 Plastic DIP ±1/2 MAX532BEPE MAX532AEWE MAX532BEWE -40°C to +85°C -40°C to +85°C -40°C to +85°C 16 Plastic DIP 16 Wide SO 16 Wide SO ±1 ±1/2 ±1 MAX532AMJE MAX532BMJE -55°C to +125°C -55°C to +125°C 16 CERDIP** 16 CERDIP** ±1/2 ±1 **Contact factory for availability and processing to MIL-STD-883B. ___________________Chip Topography VREFA RFBA V DD LDAC CS VOUTA DIN AGNDA 0.250" (6.35mm) AGNDB DOUT VOUTB SCLK VREFB RFBB V SS V SS DGND 0.140" (3.56mm) TRANSISTOR COUNT: 1324; SUBSTRATE CONNECTED TO VDD. 14 ______________________________________________________________________________________ Dual, Serial-Input, Voltage-Output, 12-Bit MDAC DIM D1 A A1 A2 A3 B B1 C D D1 E E1 e eA eB L α E E1 D A3 A A2 L A1 INCHES MAX MIN 0.200 – – 0.015 0.150 0.125 0.080 0.055 0.022 0.016 0.065 0.050 0.012 0.008 0.765 0.745 0.030 0.005 0.325 0.300 0.280 0.240 0.100 BSC 0.300 BSC 0.400 – 0.150 0.115 15˚ 0˚ MILLIMETERS MIN MAX – 5.08 0.38 – 3.18 3.81 1.40 2.03 0.41 0.56 1.27 1.65 0.20 0.30 18.92 19.43 0.13 0.76 7.62 8.26 6.10 7.11 2.54 BSC 7.62 BSC – 10.16 2.92 3.81 0˚ 15˚ 21-587A α 16-PIN PLASTIC DUAL-IN-LINE PACKAGE C e B1 eA B eB DIM E A A1 B C D E e H h L α H INCHES MAX MIN 0.104 0.093 0.012 0.004 0.019 0.014 0.013 0.009 0.413 0.398 0.299 0.291 0.050 BSC 0.419 0.394 0.030 0.010 0.050 0.016 8˚ 0˚ MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.35 0.49 0.23 0.32 10.10 10.50 7.40 7.60 1.27 BSC 10.00 10.65 0.25 0.75 0.40 1.27 0˚ 8˚ 21-589B h x 45˚ D α A 0.127mm 0.004in. e B A1 C L 16-PIN PLASTIC SMALL-OUTLINE (WIDE) PACKAGE ______________________________________________________________________________________ 15 MAX532 ________________________________________________________Package Information MAX532 Dual, Serial-Input, Voltage-Output, 12-Bit MDAC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 1994 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.