19-1846; Rev 3; 1/09
KIT
ATION
EVALU
E
L
B
A
IL
AVA
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
The MAX5441–MAX5444 are serial-input, voltage-output, 16-bit digital-to-analog converters (DACs) in tiny
µMAX® packages, 50% smaller than comparable DACs
in 8-pin SOs. They operate from low +3V (MAX5443/
MAX5444) or +5V (MAX5441/MAX5442) single supplies. They provide 16-bit performance (±2LSB INL and
±1LSB DNL) over temperature without any adjustments.
Unbuffered DAC outputs result in a low supply current
of 120µA and a low offset error of 2LSB.
The DAC output ranges from 0 to VREF. For bipolar
operation, matched scaling resistors are provided in
the MAX5442/MAX5444 for use with an external precision op amp (such as the MAX400), generating a
±VREF output swing.
A 16-bit serial word is used to load data into the DAC
latch. The 25MHz, 3-wire serial interface is compatible
with SPI/QSPI™/MICROWIRE, and can interface directly
with optocouplers for applications requiring isolation. A
power-on reset circuit clears the DAC output to code 0
(MAX5441/MAX5443) or code 32768 (MAX5442
/MAX5444) when power is initially applied.
A logic low on CLR asynchronously clears the DAC output to code 0 (MAX5441/MAX5443) or code 32768
(MAX5442/MAX5444) independent of the serial interface.
The MAX5441/MAX5443 are available in 8-pin µMAX
packages. The MAX5442/MAX5444 are available in 10pin µMAX packages.
Applications
High-Resolution Offset and Gain Adjustment
Features
o
o
o
o
o
o
o
o
o
o
o
Ultra-Small 3mm x 5mm 8-Pin µMAX Package
Low 120µA Supply Current
Fast 1µs Settling Time
25MHz SPI/QSPI/MICROWIRE-Compatible Serial
Interface
VREF Range Extends to VDD
+5V (MAX5441/MAX5442) or +3V
(MAX5443/MAX5444) Single-Supply Operation
Full 16-Bit Performance Without Adjustments
Unbuffered Voltage Output Directly Drives
60kΩ Loads
Power-On Reset Circuit Clears DAC Output to
Code 0 (MAX5441/MAX5443) or Code 32768
(MAX5442/MAX5444)
Schmitt-Trigger Inputs for Direct Optocoupler
Interface
Asynchronous CLR
Pin Configurations
TOP VIEW
+
8 GND
REF 1
CS
2
SCLK 3
DIN
MAX5441
MAX5443
4
7 VDD
REF 1
5 CLR
10 GND
CS 2
SCLK 3
6 OUT
+
9 VDD
MAX5442
MAX5444
8 RFB
DIN 4
7 INV
CLR 5
6 OUT
Industrial Process Control
µMAX-10
µMAX-8
Automated Test Equipment
Data-Acquisition Systems
Functional Diagrams appear at end of data sheet.
Ordering Information
INL (LSB)
SUPPLY (V)
MAX5441ACUA+
PART
TEMP RANGE
0°C to +70°C
8 µMAX
PIN-PACKAGE
±2
5
MAX5441AEUA+
-40°C to +85°C
8 µMAX
±2
5
MAX5441BCUA+
0°C to +70°C
8 µMAX
±4
5
MAX5441BEUA+
-40°C to +85°C
8 µMAX
±4
5
5
MAX5442ACUB+
0°C to +70°C
10 µMAX
±2
MAX5442AEUB+
-40°C to +85°C
10 µMAX
±2
5
MAX5442BCUB+
0°C to +70°C
10 µMAX
±4
5
MAX5442BEUB+
-40°C to +85°C
10 µMAX
±4
5
+Denotes a lead(Pb)-free/RoHS-compliant package.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
Note: For leaded version, contact factory.
MICROWIRE is a registered trademark of National Semiconductor Corp. Ordering Information continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX5441–MAX5444
General Description
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
CS, SCLK, DIN, CLR to GND ...................................-0.3V to +6V
REF to GND ................................................-0.3V to (VDD + 0.3V)
OUT, INV to GND .....................................................-0.3V to VDD
RFB to INV ...................................................................-6V to +6V
RFB to GND.................................................................-6V to +6V
Maximum Current Into Any Pin ...........................................50mA
Continuous Power Dissipation (TA = +70°C)
8-Pin µMAX (derate 4.5mW/°C above +70°C)...............362mW
10-Pin µMAX (derate 5.6mW/°C above +70°C) ..............444mW
Operating Temperature Ranges
MAX544 _ _CU_ ...................................................0°C to +70°C
MAX544 _ _EU_.................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Maximum Die Temperature..............................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), VREF = +2.5V, CL = 10pF, GND = 0, RL = ∞, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
Differential Nonlinearity
Integral Nonlinearity
DNL
INL
Zero-Code Offset Error
ZSE
Zero-Code Tempco
ZSTC
MIN
TYP
16
Guaranteed monotonic
±0.5
±1
MAX544_A
±0.5
±2
MAX544_B
±0.5
±4
±2
±0.05
ROUT
Bipolar Resistor Matching
ppm/°C
kΩ
RFB/RINV
1
±0.015
±20
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Resistance
(Note 4)
RREF
LSB
6.2
BZSTC
PSR
LSB
±0.1
Ratio error
Power-Supply Rejection
LSB
(Note 2)
Bipolar Zero Offset Error
Bipolar Zero Tempco
LSB
ppm/°C
±10
Gain-Error Tempco
UNITS
Bits
Gain Error (Note 1)
DAC Output Resistance
MAX
±0.5
±1
+4.5V ≤ VDD ≤ +5.5V (MAX5441/MAX5442)
±1
2.0
Unipolar mode
10
Bipolar mode
6
DYNAMIC PERFORMANCE—ANALOG SECTION
Voltage-Output Slew Rate
SR
(Note 5)
LSB
ppm/°C
+2.7V ≤ VDD ≤ +3.3V (MAX5443/MAX5444)
(Note 3)
%
VDD
LSB
V
kΩ
15
V/µs
To ± /2LSB of FS
1
µs
DAC Glitch Impulse
Major-carry transition
7
nV-s
Digital Feedthrough
Code = 0000 hex; CS = VDD;
SCLK, DIN = 0 to VDD levels
0.2
nV-s
Output Settling Time
2
1
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
(VDD = +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), VREF = +2.5V, CL = 10pF, GND = 0, RL = ∞, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth
BW
Reference Feedthrough
Signal-to-Noise Ratio
Reference Input Capacitance
Code = FFFF hex
Code = 0000 hex, VREF = 1VP-P at 100kHz
SNR
CINREF
1
MHz
1
mVP-P
92
dB
Code = 0000 hex
70
Code = FFFF hex
170
pF
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
VIH
2.4
Input Low Voltage
VIL
0.8
V
Input Current
IIN
±1
µA
Input Capacitance
CIN
10
pF
Hysteresis Voltage
VH
(Note 6)
V
3
0.15
V
POWER SUPPLY
Positive Supply Range (Note 7)
VDD
Positive Supply Current
IDD
Power Dissipation
PD
MAX5443/MAX5444
2.7
3.6
MAX5441/MAX5442
4.5
5.5
All digital inputs at VDD or GND
All digital inputs at
VDD or GND
0.12
MAX5443/MAX5444
0.36
MAX5441/MAX5442
0.60
V
0.20
mA
mW
TIMING CHARACTERISTICS
(VDD = +2.7V to +3.3V (MA5443/MAX5444) , VDD = +4.5V to +5.5V (MAX5441/MAX5442), VREF = +2.5V, GND = 0, CMOS inputs,
TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
25
MHz
SCLK Frequency
fCLK
SCLK Pulse Width High
tCH
20
ns
SCLK Pulse Width Low
tCL
20
ns
CS Low to SCLK High Setup
tCSS0
15
ns
CS High to SCLK High Setup
tCSS1
15
ns
SCLK High to CS Low Hold
tCSH0
35
ns
SCLK High to CS High Hold
tCSH1
20
ns
DIN to SCLK High Setup
tDS
15
ns
DIN to SCLK High Hold
tDH
0
ns
tCLW
20
ns
CLR Pulse Width Low
VDD High to CS Low
(power-up delay)
(Note 6)
20
µs
Note 1: Gain error tested at VREF = +2.0V, +2.5V, and +3.0V (MAX5443/MAX5444) or VREF = +2.0V, +2.5V, +3.0V, and +5.5V
(MAX5441/ MAX5442).
Note 2: ROUT tolerance is typically ±20%.
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code-dependent, minimum at 8555hex in unipolar mode, 4555hex in bipolar mode.
Note 5: Slew-rate value is measured from 10% to 90%.
Note 6: Guaranteed by design. Not production tested.
Note 7: Guaranteed by power-supply rejection test and Timing Characteristics.
_______________________________________________________________________________________
3
MAX5441–MAX5444
ELECTRICAL CHARACTERISTICS (continued)
__________________________________________Typical Operating Characteristics
(VDD = +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), VREF = +2.5V, GND = 0, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
VDD = +3V
0.075
0.050
0.10
0.09
0.08
0.07
0.025
MAX5441/44 toc03
0.11
0.12
0.11
SUPPLY CURRENT (mA)
0.100
MAX5441/44 toc02
VDD = +5V
0.12
SUPPLY CURRENT (mA)
SUUPLY CURRENT (mA)
0.125
MAX5441/44 toc01
0.150
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
0.10
0.09
0.08
0.07
0.06
0.06
VDD = +5V
10
35
60
0
85
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.6
+INL
0.1
0.2
-0.1
-DNL
-0.3
-0.2
-0.4
-0.4
-0.2
-15
10
35
60
-40
85
-15
35
60
GAIN ERROR
vs. TEMPERATURE
0.20
0.15
-0.15
-0.25
10
35
TEMPERATURE (°C)
60
85
85
0.075
0.050
0.05
0.025
0
0
-0.025
-0.10
-0.050
-0.15
-0.075
-0.20
-0.100
-0.125
-0.25
-0.30
60
0.100
0.10
-0.05
-0.20
35
DIFFERENTIAL NONLINEARITY
DNL (LSB)
INL (LSB)
-0.10
10
0.125
MAX5441/44 toc08
0.25
MAX5441/44 toc07
-0.05
-15
-15
TEMPERATURE (°C)
INTEGRAL NONLINEARITY vs. CODE
0
-40
-40
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
10
MAX5441/44 toc09
-40
3.0
+DNL
-INL
-0.1
2.5
-0.2
0
0
2.0
0
DNL (LSB)
INL (LSB)
0.1
1.5
0.2
0.4
0.2
1.0
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0.8
MAX5441/44 toc04
0.3
0.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
0.4
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C)
MAX5441/44 toc06
-15
MAX5441/44 toc05
-40
OFFSET ERROR (LSB)
VDD = +3V
0.05
0.05
0
GAIN ERROR (LSB)
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
0 5k
15k
25k
35k
45k
55k
66k
0 5k
15k
25k
CODE
_______________________________________________________________________________________
35k
CODE
45k
55k
66k
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
FULL-SCALE STEP RESPONSE
(FALLING)
REFERENCE CURRENT
vs. DIGITAL INPUT CODE
MAX5441/44 toc11
120
MAX5441/44 toc12
MAX5441/44 toc10
140
100
CS
2V/div
CS
2V/div
AOUT
1V/div
AOUT
1V/div
80
60
40
20
CL = 20pF
CL = 20pF
0
10000 20000 30000 40000 50000 60000 70000
400ns/div
CODE
MAJOR-CARRY GLITCH
(RISING)
MAX5441/44 toc14
MAX5441/44 toc13
MAJOR-CARRY GLITCH
(FALLING)
CS
1V/div
CS
1V/div
AOUT
20mV/div
AOUT
20mV/div
CL = 20pF
CL = 20pF
200ns/div
200ns/div
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
MAX5441/44 toc16
0.70
0.65
DIN
2V/div
UNIPOLAR POWER-ON GLITCH
(REF = VDD)
0.60
VDD
2V/div
0.55
0.50
AOUT
10mV/div
MAX5441/44 toc17
DIGITAL FEEDTHROUGH
INL (LSB)
0
400ns/div
MAX5441/44 toc15
REFERENCE CURRENT (µA)
FULL-SCALE STEP RESPONSE
(RISING)
VOUT
10mV/div
0.45
CL = 112pF
0.40
50ns/div
2.0
2.5
3.0
3.5
4.0
4.5
5.0
50ms/div
REFERENCE VOLTAGE (V)
_______________________________________________________________________________________
5
MAX5441–MAX5444
Typical Operating Characteristics (continued)
(VDD = +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), VREF = +2.5V, GND = 0, RL = ∞, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Pin Description
PIN
MAX5441
MAX5443
1
MAX5442
MAX5444
1
NAME
FUNCTION
REF
Voltage Reference Input
2
2
CS
Chip-Select Input
3
3
SCLK
4
4
DIN
Serial Data Input
5
5
CLR
Clear Input. Logic low asynchronously clears the DAC to code 0 (MAX5441/MAX5443)
or code 32768 (MAX5442/MAX5444).
6
6
OUT
DAC Output Voltage
—
7
INV
Junction of Internal Scaling Resistors. Connect to external op amp’s inverting input in
bipolar mode.
—
8
RFB
Feedback Resistor. Connect to external op amp’s output in bipolar mode.
Serial Clock Input. Duty cycle must be between 40% and 60%.
7
9
VDD
Supply Voltage. Use +3V for MAX5443/MAX5444 and +5V for MAX5441/MAX5442.
8
10
GND
Ground
tCSH1
CS
tCSHO
tCSSO
tCH
tCSS1
tCL
SCLK
tDH
tDS
DIN
D15
D14
D0
Figure 1. Timing Diagram
6
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
MAX5441–MAX5444
+2.5V
MAX6166
+3V/+5V
1µF
0.1µF
0.1µF
(GND)
REF
VDD
MC68XXXX
PCS0
CS
MOSI
DIN
SCLK
SCLK
IC1
CLR
UNIPOLAR
OUT
MAX495
MAX5441
MAX5442
MAX5443
MAX5444
OUT
EXTERNAL OP AMP
GND
Figure 2a. Typical Operating Circuit—Unipolar Output
MAX6166
+3V/+5V
+2.5V
1µF
0.1µF
0.1µF
+5V
MC68XXXX
RFB
VDD
PCS0
CS
MOSI
DIN
SCLK
SCLK
IC1
CLR
RINV
RFB
INV
MAX400
OUT
MAX5442
MAX5444
BIPOLAR
OUT
EXTERNAL OP AMP
-5V
(GND)
GND
Figure 2b. Typical Operating Circuit—Bipolar Output
Detailed Description
The MAX5441–MAX5444 voltage-output, 16-bit digitalto-analog converters (DACs) offer full 16-bit performance with less than 2LSB integral linearity error and
less than 1LSB differential linearity error, thus ensuring
monotonic performance. Serial data transfer minimizes
the number of package pins required.
The MAX5441–MAX5444 are composed of two
matched DAC sections, with a 12-bit inverted R-2R
DAC forming the 12 LSBs and the four MSBs derived
from 15 identically matched resistors. This architecture
allows the lowest glitch energy to be transferred to the
DAC output on major-carry transitions. It also lowers the
DAC output impedance by a factor of eight compared
_______________________________________________________________________________________
7
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
to a standard R-2R ladder, allowing unbuffered operation in medium-load applications.
The MAX5442/MAX5444 provide matched bipolar offset
resistors, which connect to an external op amp for bipolar output swings (Figure 2b).
Digital Interface
The MAX5441–MAX5444 digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 data bits have been loaded into the
serial input register, it transfers its contents to the DAC
latch on CS’s low-to-high transition (Figure 3). Note that
if CS is not kept low during the entire 16 SCLK cycles,
data will be corrupted. In this case, reload the DAC
latch with a new 16-bit word.
Clearing the DAC
A 20ns (min) logic-low pulse on CLR asynchronously
clears the DAC buffer to code 0 in the MAX5441/
MAX5443 and to code 32768 in the MAX5442/ MAX5444.
External Reference
The MAX5441–MAX5444 operate with external voltage
references from 2V to V DD . The reference voltage
determines the DAC’s full-scale output voltage.
Power-On Reset
The power-on reset circuit sets the output of the
MAX5441/MAX5443 to code 0 and the output of the
MAX5442/MAX5444 to code 32768 when VDD is first
applied. This ensures that unwanted DAC output voltages will not occur immediately following a system
power-up, such as after a loss of power.
Applications Information
Reference and Ground Inputs
The MAX5441–MAX5444 operate with external voltage
references from 2V to VDD, and maintain 16-bit performance if certain guidelines are followed when selecting
and applying the reference. Ideally, the reference’s
temperature coefficient should be less than
0.1ppm/°C to maintain 16-bit accuracy to within 1LSB
over the -40°C to +85°C extended temperature range.
Since this converter is designed as an inverted R-2R voltage-mode DAC, the input resistance seen by the voltage
reference is code-dependent. In unipolar mode, the
worst-case input-resistance variation is from 11.5kΩ (at
code 8555hex) to 200kΩ (at code 0000hex). The maximum change in load current for a 2.5V reference is 2.5V /
11.5k Ω = 217µA; therefore, the required load regulation
is 7ppm/mA for a maximum error of 0.1LSB. This implies
a reference output impedance of less than 18mΩ. In
addition, the impedance of the signal path from the voltage reference to the reference input must be kept low
because it contributes directly to the load-regulation
error.
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REF and GND provides high-frequency
bypassing. A surface-mount ceramic chip capacitor is
preferred because it has the lowest inductance. An
; ; ;;
CS
DAC
UPDATED
SCLK
SUB-BITS
DIN
D15 D14 D13 D12 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Figure 3. MAX5441–MAX5444 3-Wire Interface Timing Diagram
8
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, allowing 16-bit performance from +VREF to GND
without degradation at zero-scale. The DAC’s output
impedance is also low enough to drive medium loads
(RL > 60kΩ) without degradation of INL or DNL; only
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
The requirements on the external output buffer amplifier
change whether the DAC is used in the unipolar or bipolar mode of operation. In unipolar mode, the output
amplifier is used in a voltage-follower connection. In
bipolar mode (MAX5442/MAX5444 only), the amplifier
operates with the internal scaling resistors (Figure 2b). In
each mode, the DAC’s output resistance is constant and
is independent of input code; however, the output amplifier’s input impedance should still be as high as possible
to minimize gain errors. The DAC’s output capacitance is
also independent of input code, thus simplifying stability
requirements on the external amplifier.
In bipolar mode, a precision amplifier operating with
dual power supplies (such as the MAX400) provides
the ±VREF output range. In single-supply applications,
precision amplifiers with input common-mode ranges
including GND are available; however, their output
swings do not normally include the negative rail (GND)
without significant degradation of performance. A single-supply op amp, such as the MAX495, is suitable if
the application does not use codes near zero.
Since the LSBs for a 16-bit DAC are extremely small
(38.15µV for VREF = 2.5V), pay close attention to the
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resistance (typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into consideration. Over the -40°C to +85°C extended temperature range, the offset voltage temperature coefficient
(referenced to +25°C) must be less than 0.24µV/°C to
add less than 1/2LSB of zero-scale error. The external
amplifier’s input resistance forms a resistive divider with
the DAC output resistance, which results in a gain error.
To contribute less than 1/2LSB of gain error, the input
resistance typically must be greater than:
6.25kΩ × 217 = 819MΩ
The settling time is affected by the buffer input capacitance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be significantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to within
1/2LSB of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance will
increase the settling time.
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approximately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time constant of the combined system is:
⎡ 83ns 2 + 159ns 2 ⎤ = 180ns
( ) (
) ⎦⎥
⎣⎢
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 12 180ns = 2.15µs.
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a
3-wire standard that is compatible with SPI, QSPI, and
MICROWIRE interfaces. The three digital inputs (CS,
DIN, and SCLK) load the digital input data serially into
the DAC.
A 20ns (min) logic-low pulse on CLR clears the data in
the DAC buffer.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that optocouplers can interface directly to the MAX5441–
MAX5444 without additional external logic. The digital
inputs are compatible with TTL/CMOS-logic levels.
_______________________________________________________________________________________
9
MAX5441–MAX5444
additional 1µF between REF and GND provides low-frequency bypassing. A low-ESR tantalum, film, or organic
semiconductor capacitor works well. Leaded capacitors are acceptable because impedance is not as critical at lower frequencies. The circuit can benefit from
even larger bypassing capacitors, depending on the
stability of the external reference with capacitive loading.
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Unipolar Configuration
Figure 2a shows the MAX5441–MAX5444 configured for
unipolar operation with an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit. The bipolar MAX5442/MAX5444 can also be
used in unipolar configuration by connecting RFB and
INV to REF. This allows the DAC to power-up to midscale.
Bipolar Configuration
Figure 2b shows the MAX5442/MAX5444 configured for
bipolar operation with an external op amp. The op amp
is set for unity gain with an offset of -1/2VREF. Table 2
lists the offset binary codes for this circuit.
Power-Supply Bypassing and
Ground Management
Bypass VDD with a 0.1µF ceramic capacitor connected
between VDD and GND. Mount the capacitor with short
leads close to the device (less than 0.25 inches).
10
Table 1. Unipolar Code Table
DAC LATCH CONTENTS
MSB
ANALOG OUTPUT, VOUT
LSB
1111 1111 1111 1111
VREF (65,535 / 65,536)
1000 0000 0000 0000
VREF (32,768 / 65,536) = 1/2VREF
0000 0000 0000 0001
VREF (1 / 65,536)
0000 0000 0000 0000
0
Table 2. Bipolar Code Table
DAC LATCH CONTENTS
MSB
ANALOG OUTPUT, VOUT
LSB
1111 1111 1111 1111
+VREF (32,767 / 32,768)
1000 0000 0000 0001
+VREF (1 / 32,768)
1000 0000 0000 0000
0
0111 1111 1111 1111
-VREF (1 / 32,768)
0000 0000 0000 0000
-VREF (32,768 / 32,768) = -VREF
______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
VDD
VDD
MAX5441
MAX5443
REF
REF
OUT
16-BIT DAC
CS
SCLK
DIN
RFB
INV
MAX5442
MAX5444
CS
16-BIT DATA LATCH
SCLK
CONTROL
LOGIC
DIN
SERIAL INPUT REGISTER
CLR
OUT
16-BIT DAC
16-BIT DATA LATCH
CONTROL
LOGIC
SERIAL INPUT REGISTER
CLR
GND
GND
Ordering Information (continued)
INL (LSB)
SUPPLY (V)
MAX5443ACUA+
PART
TEMP RANGE
0°C to +70°C
8 µMAX
PIN-PACKAGE
±2
3
MAX5443AEUA+
-40°C to +85°C
8 µMAX
±2
3
MAX5443BCUA+
0°C to +70°C
8 µMAX
±4
3
MAX5443BEUA+
-40°C to +85°C
8 µMAX
±4
3
3
MAX5444ACUB+
0°C to +70°C
10 µMAX
±2
MAX5444AEUB+
-40°C to +85°C
10 µMAX
±2
3
MAX5444BCUB+
0°C to +70°C
10 µMAX
±4
3
MAX5444BEUB+
-40°C to +85°C
10 µMAX
±4
3
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: For leaded version, contact factory.
Package Information
_____________________Chip Information
PROCESS: BiCMOS
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
8 µMAX
U8+1
21-0036
90-0092
10 µMAX
U10+2
21-0061
90-0330
______________________________________________________________________________________
11
MAX5441–MAX5444
Functional Diagrams
MAX5441–MAX5444
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/00
Initial release
—
2
10/07
Changed timing diagram
6
3
1/09
Added lead-free notation in Ordering Information.
DESCRIPTION
PAGES
CHANGED
1, 11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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