MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
General Description
The MAX5703/MAX5704/MAX5705 single-channel, lowpower, 8-/10-/12-bit, voltage-output digital-to-analog
converters (DACs) include output buffers and an internal
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5703/MAX5704/MAX5705 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (< 1mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
The MAX5703/MAX5704/MAX5705 have a 50MHz,
3-wire SPI/QSPI™/MICROWIRE®/DSP-compatible serial
interface. The DAC output is buffered and has a low
supply current of 155FA (typical at 3V) and a low offset
error of Q0.5mV (typical). On power-up, the MAX5703/
MAX5704/MAX5705 reset the DAC outputs to zero,
providing additional safety for applications that drive
valves or other transducers which need to be off on
power-up. The internal reference is initially powered
down to allow use of an external reference.
The MAX5703/MAX5704/MAX5705 include a userconfigurable active-low asynchronous input, AUX for
additional flexibility. This input can be programmed to
asynchronously clear (CLR) or temporarily gate (GATE) the
DAC output to a user-programmable value. A dedicated
active-low asynchronous LDAC input is also included. This
allows simultaneous output updates of multiple devices.
Benefits and Features
S Single High-Accuracy DAC Channel
12-Bit Accuracy Without Adjustments
±1 LSB INL Buffered Voltage Output
Monotonic Over All Operating Conditions
S Three Precision Selectable Internal References
2.048V, 2.500V, or 4.096V
S Internal Output Buffer
Rail-to-Rail Operation with External Reference
6.3µs Settling Time
Output Directly Drives 2kI Loads
S Small, 10-Pin, 2mm x 3mm TDFN and 3mm x 5mm
µMAX Packages
S Wide 2.7V to 5.5V Supply Range
S Flexible 1.8V to 5.5V VDDIO
S 50MHz, 3-Wire, SPI/QSPI/MICROWIRE/DSPCompatible Serial Interface
S Power-On-Reset to Zero-Scale DAC Output
S User-Configurable Asynchronous I/O Functions:
CLR, LDAC, GATE
S Three Software-Selectable Power-Down Output
Impedances: 1kI, 100kI, or High Impedance
S Low 155µA DAC Supply Current at 3V
Functional Diagram
The MAX5703/MAX5704/MAX5705 are available in 10-pin
TDFN/µMAXM packages and are specified over the -40NC
to +125NC temperature range.
Applications
Programmable Voltage and Current Sources
VDDIO
Automatic Tuning and Optical Control
AUX
CODE
REGISTER
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
8-/10-/
12-BIT
DAC
DAC
LATCH
SPI
SERIAL
INTERFACE
CODE
LDAC
Process Control and Servo Loops
Data Acquisition
MAX5703
MAX5704
MAX5705
CS
SCLK
DIN
Portable Instrumentation
REF
INTERNAL REFERENCE /
EXTERNAL BUFFER
Gain and Offset Adjustment
Power Amplifier Control and Biasing
VDD
BUFFER
OUT
CLEAR /
CLEAR /
LOAD GATE
RESET
RESET
DAC CONTROL LOGIC
POR
POWER
DOWN
100kI 1kI
GND
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to: www.maximintegated.com/MAX5703.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6463; Rev 3; 11/14
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND..............................................................-0.3V to +6V
VDDIO to GND..........................................................-0.3V to +6V
OUT, REF to GND.........-0.3V to lower of (VDD + 0.3V) and +6V
CS, SCLK, DIN, AUX, LDAC to GND.......................-0.3V to +6V
Continuous Power Dissipation (TA = +70NC)
TDFN (derate 14.9mW/NC above +70NC)................1188.7mW
µMAX (derate 8.8mW/NC above +70NC)...................707.3mW
Maximum Continuous Current into Any Pin..................... ±50mA
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θJA)........67.3NC/W
µMAX
Junction-to-Ambient Thermal Resistance (θJA)......113.1NC/W
Junction-to-Ambient Thermal Resistance (θJC)............36NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC PERFORMANCE (Note 3)
Resolution and Monotonicity
Integral Nonlinearity (Note 4)
Differential Nonlinearity (Note 4)
Offset Error (Note 5)
N
INL
DNL
MAX5703
8
MAX5704
10
MAX5705
12
MAX5703, 8 bits
-0.25
±0.05
+0.25
MAX5704, 10 bits
-0.5
±0.2
+0.5
MAX5705, 12 bits
-1
±0. 5
+1
MAX5703, 8 bits
-0.25
±0.05
+0.25
MAX5704, 10 bits
-0.5
±0.1
+0.5
MAX5705, 12 bits
-1
±0.2
+1
-5
±0.5
+5
OE
Offset Error Drift
Gain Error (Note 5)
Gain Temperature Coefficient
±10
GE
-1.0
With respect to VREF
Zero-Scale Error
Full-Scale Error
Maxim Integrated
Bits
With respect to VREF
±0.1
LSB
LSB
mV
FV/NC
+1.0
%FS
ppm of
FS/NC
±2.5
0
+10
mV
-0.5
+0.5
%FS
2
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
Output Voltage Range (Note 6)
Load Regulation
No load
0
VDD
2kI load to GND
0
VDD 0.2
2kI load to VDD
0.2
VDD
VOUT = VFS/2
DC Output Impedance
VOUT = VFS/2
Capacitive Load Handling
CL
Resistive Load Handling
RL
Short-Circuit Output Current
VDD = 3V Q10%,
|IOUT| P 5mA
300
VDD = 5V Q10%,
|IOUT| P 10mA
300
VDD = 3V Q10%,
|IOUT| P 5mA
0.3
VDD = 5V Q10%,
|IOUT| P 10mA
0.3
FV/mA
I
500
2
VDD = 5.5V
V
pF
kI
Sourcing (output
short to GND)
30
Sinking (output
shorted to VDD)
40
mA
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Positive and negative
2.0
¼ scale to ¾ scale, to P 1 LSB, MAX5703
2.8
¼ scale to ¾ scale, to P 1 LSB, MAX5704
5.2
¼ scale to ¾ scale, to P 1 LSB, MAX5705
6.3
DAC Glitch Impulse
Major code transition
5.0
nV·s
Digital Feedthrough
Code = 0, all digital inputs from 0V to
VDDIO
0.5
nV·s
Startup calibration time (Note 7)
200
Fs
From power-down mode
60
Fs
VDD = 3V Q10% or 5V Q10%
100
FV/V
Voltage-Output Settling Time
Power-Up Time
DC Power-Supply Rejection
Maxim Integrated
SR
V/Fs
Fs
3
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
Output Voltage-Noise Density
(DAC Output at Midscale)
SYMBOL
CONDITIONS
f = 1kHz
External reference
f = 10kHz
f = 10kHz
98
2.5V internal
reference
f = 1kHz
117
f = 10kHz
110
4.096V internal
reference
f = 1kHz
152
f = 10kHz
145
f = 0.1Hz to 10Hz
10
2.048V internal
reference
2.5V internal
reference
Integrated Output Noise
(DAC Output at Full Scale)
72
f = 0.1Hz to 300kHz
298
f = 0.1Hz to 10Hz
11
f = 0.1Hz to 10kHz
89
f = 0.1Hz to 300kHz
370
f = 0.1Hz to 10Hz
12
99
355
f = 0.1Hz to 10Hz
13
f = 0.1Hz to 10kHz
128
f = 0.1Hz to 300kHz
400
f = 1kHz
113
f = 10kHz
100
2.048V internal
reference
f = 1kHz
172
f = 10kHz
157
2.5V internal
reference
f = 1kHz
195
f = 10kHz
180
4.096V internal
reference
f = 1kHz
279
f = 10kHz
258
f = 0.1Hz to 10Hz
12
f = 0.1Hz to 10kHz
88
f = 0.1Hz to 300kHz
280
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
Maxim Integrated
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
External reference
UNITS
108
f = 0.1Hz to 10kHz
External reference
MAX
79
f = 1kHz
4.096V internal
reference
Output Voltage-Noise Density
(DAC Output at Full Scale)
TYP
88
2.048V internal
reference
External reference
Integrated Output Noise
(DAC Output at Midscale)
MIN
f = 0.1Hz to 10Hz
14
f = 0.1Hz to 10kHz
135
f = 0.1Hz to 300kHz
530
f = 0.1Hz to 10Hz
15
f = 0.1Hz to 10kHz
160
f = 0.1Hz to 300kHz
550
f = 0.1Hz to 10Hz
23
f = 0.1Hz to 10kHz
220
f = 0.1Hz to 300kHz
610
nV/√Hz
FVP-P
nV/√Hz
FVP-P
4
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Current
IREF
Reference Input Impedance
RREF
1.24
VREF = VDD = 5.5V
55
VDD
V
75
FA
75
100
VREF = 2.048V, TA = +25NC
2.043
2.048
2.053
VREF = 2.5V, TA = +25NC
2.494
2.500
2.506
VREF = 4.096V, TA = +25NC
4.086
4.096
4.106
kI
REFERENCE OUPUT
Reference Output Voltage
VREF
VREF = 2.048V
Reference Output Noise Density
VREF = 2.500V
VREF = 4.096V
VREF = 2.048V
Integrated Reference Output
Noise
VREF = 2.500V
VREF = 4.096V
f = 1kHz
129
f = 10kHz
122
f = 1kHz
158
f = 10kHz
151
f = 1kHz
254
f = 10kHz
237
f = 0.1Hz to 10Hz
12
f = 0.1Hz to 10kHz
110
f = 0.1Hz to 300kHz
390
f = 0.1Hz to 10Hz
15
f = 0.1Hz to 10kHz
129
f = 0.1Hz to 300kHz
430
f = 0.1Hz to 10Hz
20
f = 0.1Hz to 10kHz
205
f = 0.1Hz to 300kHz
525
nV/√Hz
FVP-P
Reference Temperature
Coefficient (Note 8)
MAX5705A
±4
±12
MAX5703/MAX5704/MAX5705B
±10
±25
Reference Drive Capacity
External load
Reference Capacitive Load
Handling
Reference Load Regulation
Reference Line Regulation
Maxim Integrated
ISOURCE = 0 to 500FA
V
ppm/NC
25
kI
200
pF
1.0
mV/mA
0.1
mV/V
5
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Supply Voltage
I/O Supply Voltage
VDD
VREF = 4.096V
4.5
5.5
All other options
2.7
5.5
1.8
5.5
VDDIO
External reference
Supply Current (DAC Output at
Midscale) (Note 9)
IDD
Internal reference,
reference pin
undriven
Internal reference,
reference pin driven
External reference
Supply Current (DAC Output at
Full Scale) (Note 9)
IDD
Internal reference,
reference pin
undriven
Internal reference,
reference pin driven
Power-Down Mode Supply
Current (DAC Powered Down,
Reference Remains Active)
(Note 9)
Power-Down Mode Supply
Current (Note 9)
Digital Supply Current (Note 9)
IDD
IPD
Internal reference,
reference pin driven
V
V
VREF = 3V
135
190
VREF = 5V
165
225
VREF = 2.048V
190
265
VREF = 2.5V
205
280
VREF = 4.096V
250
340
VREF = 2.048V
215
300
VREF = 2.5V
225
315
VREF = 4.096V
275
375
VREF = 3V
155
210
VREF = 5V
200
265
VREF = 2.048V
205
280
VREF = 2.5V
220
300
VREF = 4.096V
275
375
VREF = 2.048V
225
310
VREF = 2.5V
240
330
VREF = 4.096V
300
410
VREF = 2.048V
90
135
VREF = 2.5V
93
135
VREF = 4.096V
100
150
0.4
2
FA
1.0
FA
External reference, VDD = VREF
IDDIO
FA
FA
FA
DIGITAL INPUT CHARACTERISTICS (CS, SCLK, DIN, LDAC, AUX)
Input High Voltage
Input Low Voltage
Maxim Integrated
2.2V < VDDIO < 5.5V
0.7 x
VDDIO
1.8V < VDDIO < 2.2V
0.8 x
VDDIO
VIH
V
2.2V < VDDIO < 5.5V
0.3 x
VDDIO
1.8V < VDDIO < 2.2V
0.2 x
VDDIO
VIL
V
6
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Hysteresis Voltage
VH
0.15
Input Leakage Current (Note 9)
IIN
±0.1
Input Capacitance
CIN
3
MAX
UNITS
±1
FA
V
pF
SPI TIMING CHARACTERISTICS (CS, SCLK, DIN, LDAC, AUX) (Note 10)
SCLK Frequency
SCLK Period
tSCLK
2.7V ≤ VDDIO ≤ 5.5V
1.8V ≤ VDDIO < 2.7V
0
50
0
33
2.7V ≤ VDDIO ≤ 5.5V
1.8V ≤ VDDIO < 2.7V
20
30
MHz
ns
SCLK Pulse Width High
tCH
8
ns
SCLK Pulse Width Low
tCL
8
ns
2.7V ≤ VDDIO ≤ 5.5V
8
1.8V ≤ VDDIO < 2.7V
12
CS Fall to SCLK Fall Setup Time
tCSS0
To first SCLK
falling edge
CS Fall to SCLK Fall Hold Time
tCSH0
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
0
ns
CS Rise to SCLK Fall Hold Time
tCSH1
Applies to the 24th SCLK falling edge
0
ns
CS Rise to SCLK Fall
tCSA
Applies to the 24th SCLK falling edge,
aborted sequence
12
ns
SCLK Fall to CS Fall
tCSF
Applies to 24th SCLK falling edge
100
ns
CS Pulse Width High
tCSPW
20
ns
ns
DIN to SCLK Fall Setup Time
tDS
5
ns
DIN to SCLK Fall Hold Time
tDH
4.5
ns
20
ns
20
ns
20
ns
20
ns
CLR Pulse Width Low
tCLPW
CLR Rise to CS Fall
tCSC
LDAC Pulse Width Low
LDAC Fall to SCLK Fall Hold
Maxim Integrated
Required for command to be executed
tLDPW
tLDH
Applies to 24th SCLK falling edge
7
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI , TA = -40NC to +125NC, unless otherwise noted.)
(Note 2)
Note 2: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 3: DC Performance is tested without load.
Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 5: Gain and offset calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5705, code 8 and
1016 for MAX5704, and code 2 and 254 for MAX5703.
Note 6: Subject to zero and full-scale error limits and VREF settings.
Note 7: On power-up, the device initiates an internal 200Fs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 8: Specification is guaranteed by design and characterization.
Note 9: Static logic inputs with VIL = VGND and VIH = VDDIO.
Note 10: All timing is tested with VIL = VGND and VIH = VDDIO.
DIN23
DIN
DIN22
DIN21
DIN20
1
tCSH0
2
tCSS0
3
4
tCH
DIN18
DIN17
DIN16
DIN15
DIN14
7
8
9
10
DIN1
DIN0
DIN23’
tSCLK
tDH
tDS
SCLK
DIN19
5
6
tCL
23
24
tCSA
1
tCSH1
CS
tCSPW
CLR
tCLPW
tCSF
tCSC
tLDH
tLDPW
LDAC
Figure 1. SPI Serial Interface Timing Diagram
Maxim Integrated
8
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics
(MAX5705, 12-bit performance, TA = +25NC, unless otherwise noted.)
INL vs. CODE
VDD = VREF = 5V
NO LOAD
0.8
0.6
0.1
0
-0.2
0
-0.1
-0.4
-0.4
-0.2
-0.6
-0.6
-0.3
-0.8
-0.8
-0.4
-1.0
-1.0
512 1024 1536 2048 2560 3072 3584 4096
-0.5
0
512 1024 1536 2048 2560 3072 3584 4096
DNL vs. CODE
VDD = VREF
0.8
0.6
MAX INL
0
-0.1
0
-0.2
0
-0.2
-0.4
-0.3
-0.6
-0.4
-0.6
-0.4
-0.8
-0.8
MIN INL
-1.0
3.1
3.5
3.9
4.3
4.7
5.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
0.6
0.4
0.25
ERROR (mV)
OFFSET ERROR
0.20
0.15
ZERO-SCALE ERROR
VREF = 2.5V (EXTERNAL)
NO LOAD
0
OFFSET ERROR (VDD = 3V)
OFFSET ERROR (VDD = 5V)
-0.4
0.10
-1.0
3.1
3.5
3.9
4.3
4.7
SUPPLY VOLTAGE (V)
Maxim Integrated
5.1
5.5
FULL-SCALE ERROR
-0.05
-0.06
GAIN ERROR
-0.07
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.09
-0.8
0
-0.04
-0.08
-0.6
0.05
-0.03
ZERO-SCALE ERROR
0.2
-0.2
-0.02
MAX5703 toc09
0.8
ERROR (%fs)
1.0
0.30
2.7
MIN INL
CODE (LSB)
VREF = 2.5V (EXTERNAL)
NO LOAD
0.35
MIN DNL
-1.0
2.7
MAX5703 toc08
0.40
512 1024 1536 2048 2560 3072 3584 4096
MAX5703 toc07
0
MAX DNL
0.2
-0.2
-0.5
MAX INL
0.4
0.2
MIN DNL
VDD = VREF = 3V
0.6
ERROR (LSB)
0.1
0.8
MAX DNL
0.4
ERROR (LSB)
0.2
INL AND DNL vs. TEMPERATURE
1.0
MAX5703 toc05
1.0
MAX5703 toc04
VDD = VREF = 5V
NO LOAD
0.3
CODE (LSB)
INL AND DNL vs. SUPPLY VOLTAGE
0.5
0.4
512 1024 1536 2048 2560 3072 3584 4096
0
CODE (LSB)
MAX5703 toc06
0
DNL (LSB)
0.2
INL (LSB)
0.2
0.2
CODE (LSB)
DNL (LSB)
0.3
0.4
-0.2
VDD = VREF = 3V
NO LOAD
0.4
0.4
0
ERROR (mV)
0.5
MAX5703 toc02
0.6
INL (LSB)
MAX5703 toc01
VDD = VREF = 3V
NO LOAD
0.8
DNL vs. CODE
1.0
MAX5703 toc03
INL vs. CODE
1.0
-0.10
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY VOLTAGE (V)
9
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, TA = +25NC, unless otherwise noted.)
0.06
GAIN ERROR (VDD = 3V)
0.04
260
VREF = 2.048V,
VDD = 3V
VREF = 2.5V, VDD = 3V
180
140
0
100
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(2.048V INTERNAL REFERENCE)
DAC ON
REFERENCE PAD DRIVEN
250
220
0.02
VREF = VDD = 5V
200
DAC OFF
REFERENCE
OUTPUT ONLY
150
100
VDD = VDDIO
VDAC = FULL SCALE
NO LOAD
50
VREF = VDD = 3V
DAC ON
REFERENCE PAD
UNDRIVEN
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(2.500V INTERNAL REFERENCE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(4.096V INTERNAL REFERENCE)
POWER-DOWN MODE CURRENT
vs. SUPPLY VOLTAGE
DAC ON
REFERENCE PAD UNDRIVEN
150
DAC ON EXT REFERENCE = 2.5V
100
VDD = VDDIO
VDAC = FULL SCALE
NO LOAD
50
DAC OFF
REFERENCE
OUTPUT ONLY
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
300
250
DAC OFF
REFERENCE
OUTPUT ONLY
200
150
100
VDD = VDDIO
VDAC = FULL SCALE
NO LOAD
50
0
5.5
DAC ON
REFERENCE PAD
UNDRIVEN
4.00
4.25
4.50
4.75
5.25
SUPPLY CURRENT (µA)
0.4
TA = +125°C
0.3
0.2
TA = +25°C
0.1
2.7
5.50
TA = -40°C
3.5
3.9
4.3
4.7
5.1
5.5
IREF (EXTERNAL) vs. CODE
250
200
150
VDD = VREF(EXT) = 5V
100
3.1
60
VDD = VREF(EXT) = 3V
VDD = VREF
NO LOAD
55
SUPPLY CURRENT (µA)
VDD = 5V,
VDD = 5V,
VDD = 5V,
VREF(INT) = 2.5V
VREF(INT) = 4.096V VREF(INT) = 2.048V
50
45
VREF = 5V
40
35
VREF = 3V
30
25
NO LOAD, TA = +25°C
0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
Maxim Integrated
TA = +85°C
0.5
SUPPLY VOLTAGE (V)
MAX5703 toc16
350
50
0.6
0
5.00
SUPPLY CURRENT vs. CODE
(FOR INTERNAL REF, PIN IS UNDRIVEN)
300
VDD = VREF
(EXTERNAL, ACTIVE)
0.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MAX5703 toc15
350
0.8
5.5
MAX5703 toc17
200
DAC ON
REFERENCE PAD DRIVEN
POWER-DOWN SUPPLY CURRENT (µA)
250
400
MAX5703 toc14
DAC ON REFERENCE PAD DRIVEN
SUPPLY CURRENT (µA)
300
SUPPLY CURRENT (µA)
300
300
SUPPLY CURRENT (µA)
FULL-SCALE ERROR
0.08
VREF = 4.096V,
VDD = 5V
MAX5703 toc11
GAIN ERROR (VDD = 5V)
VDD = VDDIO
VDAC_ = FULL SCALE
DAC ENABLED
NO LOAD
340
MAX5703 toc13
ERROR (%fsr)
0.10
380
SUPPLY CURRENT (µA)
VREF = 2.5V (EXTERNAL)
NO LOAD
MAX5703 toc10
0.12
SUPPLY CURRENT vs. TEMPERATURE
(PIN UNDRIVEN FOR INTERNAL REF MODES)
MAX5703 toc12
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
20
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
10
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, TA = +25NC, unless otherwise noted.)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5703 toc18
5.9µs
MAX5703 toc19
ZOOMED
VOUT
1 LSB/div
VOUT
2V/div
ZOOMED
VOUT
1 LSB/div
VOUT
2V/div
3/4 SCALE TO 1/4 SCALE
1/4 SCALE TO 3/4
SCALE
TRIGGER
PULSE
10V/div
6.3µs
TRIGGER
PULSE
10V/div
2µs/div
2µs/div
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAJOR CODE TRANSITION GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5703 toc20
MAX5703 toc21
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GILTCH IMPULSE = 5nV*S
ZOOMED
VOUT
1.25mV/div
ZOOMED
VOUT
1.25mV/div
TRIGGER
PULSE
5V/div
TRIGGER
PULSE
5V/div
2µs/div
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GILTCH IMPULSE = 5nV*S
2µs/div
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
POWER-ON RESET TO 0V
MAX5703 toc22
MAX5703 toc23
VCLK
5V/div
0V
VDD = VREF = 5V
10kI LOAD TO VDD
24TH EDGE
VDD
2V/div
0V
VOUT
1V/div
VDD = 5V, VREF = 2.5V
EXTERNAL
20µs/div
Maxim Integrated
VOUT
2V/div
0V
0V
40µs/div
11
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, TA = +25NC, unless otherwise noted.)
3
VDD = VREF
MIDSCALE
MAX5703 toc24
VDD = VREF = 5V
DAC AT MIDSCALE
2
1
∆VOUT (mV)
VOUT
125µV/div
MAX5703 toc25
OUTPUT LOAD REGULATION
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
VDD = 3V
0
VDD = 5V
-1
DIGITAL FEEDTHROUGH = 0.1nV·s
-2
-3
-30
-20
-10
0
HEADROOM AT RAILS
vs. OUTPUT CURRENT (VDD = VREF)
3.5
100
3.0
0
VDD = 3V
-200
2.5
VDD = 3V, SOURCING
FULL SCALE
2.0
1.5
-300
1.0
-400
0.5
-500
VDD = 3V AND 5V SINKING
ZERO SCALE
0
-40 -30 -20 -10
0
10
20
30
40
50
0
IOUT (mA)
1
2
3
4
5
6
7
8
9
VDD = 5V, VREF = 2.5V
(INTERNAL)
250
200
VDD = 5V, VREF = 2.048V
(INTERNAL)
150
100
50
VDD = 5V, VREF = 5V
(EXTERNAL)
0
100
1k
10k
100k
FREQUENCY (Hz)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
MAX5703 toc29
MAX5703 toc30
MIDSCALE UNLOADED
VP-P = 10µV
MIDSCALE UNLOADED
VP-P = 11µV
VOUT
5µV/div
4s/div
Maxim Integrated
10
VDD = 5V, VREF = 4.096V
(INTERNAL)
300
IOUT (mA)
VOUT
5µV/div
40
MAX5703 toc28
VDD = 5V, SOURCING
FULL SCALE
4.0
200
-100
30
350
NOISE-VOLTAGE DENSITY (nV/√(Hz))
VDD = 5V
4.5
VOUT (V)
∆VOUT (mV)
300
5.0
MAX5703 toc26
400
VDD = VREF
MIDSCALE
20
NOISE-VOLTAGE DENSITY
vs. FREQUENCY (DAC AT MIDSCALE)
MAX5703 toc27
OUTPUT CURRENT LIMITING
500
10
IOUT (mA)
1µs/div
4s/div
12
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, TA = +25NC, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.500V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5703 toc31
MAX5703 toc32
MIDSCALE UNLOADED
VP-P = 12µV
MIDSCALE UNLOADED
VP-P = 13µV
VOUT
5µV/div
VOUT
5µV/div
4s/div
4s/div
VREF DRIFT vs. TEMPERATURE
35
-0.05
30
∆VREF (mV)
-0.10
25
20
-0.15
-0.20
15
10
-0.30
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
300
400
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2000
MAX5703 toc35
VREF = 2.5V
250
200
150
100
VDD = 5V
1800
ALL I/O PINS SWEPT
1600
SUPPLY CURRENT (µA)
350
1400
VREF = 2.048V
VDDIO = 5V
1000
800
VDDIO = 3V
600
VDDIO = 1.8V
200
0
500
1200
400
50
200
INTERNAL REFERENCE NOISE
DENSITY vs. FREQUENCY
VREF = 4.096V
300
100
REFERENCE OUTPUT CURRENT (µA)
450
400
0
TEMPERATURE COEFFICIENT (ppm/°C)
MAX5703 toc36
0
NOISE-VOLTAGE DENSITY (nV/√(Hz))
VREF = 2.048V, 2.5V, 4.096V
-0.25
5
0
100
1k
10k
FREQUENCY (Hz)
Maxim Integrated
VDD = 5V
INTERNAL REFERENCE
MAX5703 toc34
VDD = 2.7V
VREF = 2.5V
BOX METHOD
40
DEVICE COUNT
REFERENCE LOAD REGULATION
0
MAX5703 toc33
45
100k
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
13
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Pin Configurations
TOP VIEW
1
LDAC
2
CS
3
SCLK
4
DIN
5
10 REF
+
AUX
MAX5703
MAX5704
MAX5705
*EP
AUX
1
2
+
10
REF
9
OUT
8
GND
9
OUT
LDAC
8
GND
CS
3
7
VDD
SCLK
4
7
VDD
6
VDDIO
DIN
5
6
VDDIO
TDFN
MAX5703
MAX5704
MAX5705
µMAX
*CONNECTED TO GND
Pin Description
PIN
NAME
FUNCTION
1
AUX
2
LDAC
3
CS
4
SCLK
SPI Interface Clock Input
5
DIN
SPI Interface Data Input
6
VDDIO
Active-Low Auxilliary Asynchronous Input. User configurable, see Table 7. If not using the AUX
functions, connect this input to VDDIO.
Dedicated Active-Low Asynchronous Load DAC
SPI Chip-Select Input
Digital Interface Power-Supply Input
7
VDD
Supply Voltage Input. Bypass VDD with a 0.1FF capacitor to GND.
8
GND
Ground
9
OUT
Buffered DAC Output
10
REF
Reference Voltage Input/Output
—
EP
Maxim Integrated
Exposed Pad (TDFN Only). Connect to ground.
14
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Detailed Description
The MAX5703/MAX5704/MAX5705 are single-channel,
low-power, 8-/10-/12-bit voltage-output digital-to-analog
converters (DACs) with an internal output buffer. The
wide supply voltage range of 2.7V to 5.5V and low power
consumption accommodate low-power and low-voltage
applications. The devices present a 100kI (typ) load to
the external reference. The internal output buffer allows
rail-to-rail operation. An internal voltage reference is
available with software selectable options of 2.048V,
2.500V, or 4.096V. The devices feature a 50MHz, 3-wire
SPI/QSPI/MICROWIRE/DSP-compatible serial interface
to save board space and reduce complexity in isolated
applications. The MAX5703/MAX5704/MAX5705 include
a serial-in/parallel-out shift register, internal CODE and
DAC registers, a power-on-reset (POR) circuit to initialize
the DAC output to code zero, and control logic. A userconfigurable AUX pin is available to asynchronously
clear or gate the device output independent of the serial
interface.
DAC Output (OUT)
The MAX5703/MAX5704/MAX5705 include an internal
buffer on the DAC output. The internal output buffer
provides improved load regulation for the DAC output.
The output buffer slews at 1V/Fs (typ) and drives up to
2kI in parallel with 500pF. The analog supply voltage
(VDD) determines the maximum output voltage range
of the devices as VDD powers the output buffer. Under
no-load conditions, the output buffer drives from GND to
VDD, subject to offset and gain errors. With a 2kI load
to GND, the output buffer drives from GND to within and
200mV of VDD. With a 2kI load to VDD, the output buffer
drives from VDD to within 200mV of GND.
The DAC ideal output voltage is defined by:
D
V=
OUT V REF × N
2
Where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can
be routed to control registers or the DAC itself, as
determined by the user command.
Maxim Integrated
Within the device there is a CODE register followed by
a DAC Latch register (see the Functional Diagram).
The contents of the CODE register hold pending DAC
output settings which can later be loaded into the DAC
registers. The CODE register can be updated using both
CODE and CODE_LOAD user commands. The contents
of the DAC register hold the current DAC output settings.
The DAC register can be updated directly from the serial
interface using the CODE_LOAD commands or can
upload the current contents of the CODE register using
LOAD commands or the LDAC input.
The contents of both CODE and DAC registers are
maintained during all software power-down states, so that
when the DAC is returned to a normal operating mode, it
returns to its previously stored output settings. Any CODE
or LOAD commands issued during software power-down
states continue to update the register contents. The
SW_CLEAR command clears the contents of the CODE
and DAC registers to the user-programmable default
values. The SW_RESET command resets all configuration
registers to their power-on default states, while resetting
the CODE and DAC registers to zero scale.
Internal Reference
The MAX5703/MAX5704/MAX5705 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF pin
for other external circuitry (see the Typical Operating
Circuits) and can drive a 25kI load.
External Reference
The external reference input features a typical input
impedance of 100kI and accepts an input voltage
from +1.24V to VDD. Connect an external voltage
supply between REF and GND to apply an external
reference. The MAX5703/4/5 power up and reset to
external reference mode. Visit www.maximintegated.
com/products/references for a list of available external
voltage-reference devices.
AUX Input
The MAX5703/MAX5704/MAX5705 provide an asynchronous AUX (active-low) input. Use the CONFIG command
to program the device to use the input in one of the following modes: CLR (default), GATE, or disabled. If not
using the AUX functions, connect this input to VDDIO.
15
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
CLR Mode
In CLR mode, the AUX input performs an asynchronous
level sensitive CLEAR operation when pulled low. If
CLR is configured and asserted, all CODE and DAC
data registers are cleared to their default/return values
as defined by the configuration settings. Other userconfiguration settings are not affected.
Some SPI interface commands are gated by CLR activity
during the transfer sequence. If CLR is issued during a
command write sequence, any gated commands within
the sequence are ignored. Any non-gated commands
appearing in the transfer sequence are executed. For
the gating condition to be removed, drive CLR high,
satisfying the tCSC requirements.
GATE Mode
Use of the GATE mode provides a means of momentarily
holding the DAC in a user-selectable default/return state,
returning the DAC to the last programmed state upon
removal. The MAX5703/MAX5704/MAX5705 also feature
a software-accessible GATE command. While asserted
in GATE mode, the AUX pin does not interfere with
RETURN, CODE, or DAC register updates and related
load activity.
LDAC Input
The MAX5703/MAX5704/MAX5705 provide a dedicated
asynchronous LDAC (active-low) input. The LDAC input
performs an asynchronous level sensitive LOAD operation
when pulled low. Use of the LDAC input mode provides
a means of updating multiple devices together as a
group. Users wishing to control the DAC update instance
independently of the I/O instruction should hold LDAC
high during programming cycles. Once programming
is complete, LDAC may be strobed and the new CODE
register content is loaded into the DAC latch output.
Users wishing to load new DAC data in direct response
to I/O CODE register activity should connect LDAC
permanently low; in this configuration, the MAX5703/
MAX5704/MAX5705 DAC output updates in response to
each completed I/O CODE instruction update edge. A
software LOAD command is also provided.
VDDIO Input
The MAX5703/MAX5704/MAX5705 feature a separate
supply pin (VDDIO) for the digital interface (1.8V to 5.5V).
Connect VDDIO to the I/O supply of the host processor.
SPI Serial Interface
The MAX5703/MAX5704/MAX5705 3-wire serial interface
is compatible with MICROWIRE/SPI/QSPI and DSPs. The
interface provides three inputs: SCLK, CS, and DIN. The
chip-select input (CS, active-low) frames the data loaded
through the serial data input (DIN). Following a CS input
high-to-low transition, the data is shifted in synchronously
and latched into the input register on each falling edge of
the serial clock input (SCLK). Each serial operation word
is 24-bits long. The DAC data is left justified as shown in
Table 1. The serial input register transfers its contents to
the destination registers after loading 24 bits of data on
the 24th SCLK falling edge. To initiate a new SPI operation, drive CS high and then low to begin the next operation sequence, being sure to meet all relevant timing
requirements. During CS high periods, SCLK is ignored,
allowing communication to other devices on the same
bus. SPI operations consisting of more than 24 SCLK
cycles are executed on the 24th SCLK falling edge, using
the first three bytes of data available. SPI operations consisting of less than 24 SCLK cycles will not be executed.
The content of the SPI operation consists of a command
byte followed by a two byte data word.
Figure 1 shows the timing diagram for the complete
3-wire serial interface transmission. The DAC code
settings (D) for the MAX5703/MAX5704/MAX5705 are
accepted in an offset binary format (see Table 1).
Otherwise, the expected data format for each command
is listed in Table 2.
SPI User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5703/MAX5704/MAX5705.
Table 2 provides detailed information about the SPI
Command Registers.
The LDAC operation does not interact with the user
interface directly. However, in order to achieve the best
possible glitch performance, timing with respect to the
interface update edge should follow tLDH specifications
when issuing CODE commands.
Maxim Integrated
16
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
CODE Command
The CODE command (B[23:20] = 1000) updates the
CODE register content for the DAC. Changes to the
CODE register content based on this command will not
affect the DAC output directly unless the LDAC input
is in a low state. Otherwise, a subsequent hardware
or software LOAD operation will be required to move
this content to the active DAC latch. This command is
gated when CLR is asserted, updates to this register are
ignored while the register is being cleared. See Table
1 and Table 2.
µC
CSB1
CS
SCLK
SCLK
MOSI
DIN
CSB2
CS
MAX5703
MAX5704
MAX5705
*
SCLK
LOAD Command
DIN
The LOAD command (B[23:20] = 1001) updates the DAC
latch register content by uploading the current contents
of the CODE register. This command is gated when CLR
is asserted, updates to this register are ignored while the
register is being cleared. See Table 2.
MISO
DOUT
CSB3
CS
*
SCLK
CODE_LOAD Command
DIN
The CODE_LOAD command (B[23:20] = 1010 and 1011)
updates the CODE register contents as well as the DAC
register content of the DAC. This command is gated
when CLR is asserted, updates to these registers are
ignored while the register is being cleared. See Table 1
and Table 2.
*ADDITIONAL SPI DEVICE
Figure 2. Typical SPI Application Circuit
Table 1. DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MAX5703
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
MAX5704
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
MAX5705
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Maxim Integrated
17
B23
1
1
1
1
0
CODE
LOAD
CODE_LOAD
CODE_LOAD
RETURN
DAC COMMANDS
COMMAND
Maxim Integrated
1
0
0
0
0
B22
1
1
1
0
0
B21
1
1
0
1
0
B20
X
X
X
X
X
B19
X
X
X
X
X
B18
X
X
X
X
X
B17
X
X
X
X
X
B16
X
B15
Table 2. SPI Commands Summary
X
X
X
B8
X
B7
B6
B5
REGISTER DATA[3:0]
DATA[11:4]
DATA[3:0]
RETURN REGISTER
CODE AND DAC
X
CODE AND DAC REGISTER
X
REGISTER DATA[3:0]
X
DATA[11:4]
X
B4
CODE AND DAC
X
DATA[3:0]
X
B9
CODE AND DAC REGISTER
X
B10
CODE REGISTER
B11
DATA[11:4]
B12
CODE REGISTER
B13
RETURN REGISTER DATA[11:4]
B14
X
X
X
X
X
B3
X
X
X
X
X
B2
X
X
X
X
X
B1
X
X
X
X
X
B0
contents for the DAC
RETURN register
Updates the
register
while updating DAC
CODE register
writes data to the
Simultaneously
register
while updating DAC
CODE register
writes data to the
Simultaneously
to the DAC register
the CODE registers
Transfers data from
CODE register
Writes data to the
DESCRIPTION
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
18
COMMAND
B23
B22
Maxim Integrated
0
0
0
0
SOFTWARE
POWER
CONFIG
DEFAULT
1
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
B21
1
0
0
1
0
1
0
B20
X
X
X
X
X
X
B16
Type:
11 = 4.1V
10 = 2.0V
01 = 2.5V
00 = EXT
Ref Mode
B17
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other = No Effect
101 = RST
100 = CLR
001 = GATE
000 = END
B18
B19
0 = No Drive
1 = Drive Pin
X
X
X
X
X
X
X
B15
X
X
X
X
X
X
X
B14
X
X
X
X
X
X
X
B13
X
X
X
X
X
X
X
B12
X
X
X
X
X
X
X
B11
X
X
X
X
X
X
X
B10
Reserved Commands: Any commands not specifically listed above are reserved for Maxim internal use only.
No Operation
NO OPERATION COMMANDS
0
REF
CONFIGURATION COMMANDS
0 = Default
1 = Always ON
Table 2. SPI Commands Summary (continued)
X
X
X
X
X
X
X
B9
X
X
X
X
X
X
X
B8
X
X
B6
X
000 = POR
X
X
X
X
X
X
Other = No Effect
100 = RETURN
011 = FULL
010 = MID
001 = ZERO
111 = NONE
110 = CLEAR
011 = GATE
X
X
X
B3
AUX Mode:
X
X
X
B4
X
X
X
X
X
X
Other = No Effect
X
X
X
B5
Default Values:
X
11 = HiZ
10 = 100kI
01 = 1kI
00 = DAC
Mode:
Power
X
X
B7
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
B0
the part.
will have no effect on
These commands
value for the DAC
Sets the default
of the AUX input
Updates the function
mode
Sets the Power
chosen
operation of the type
Executes a software
operating mode.
Sets the reference
DESCRIPTION
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
19
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
REF Command
SOFTWARE Commands
The SOFTWARE (B[23:20] = 0011) commands provide
a means of issuing several flexible software actions. See
Table 4.
The REF (B[23:20] = 0010) command updates the global
reference setting used for the DAC. Set B[17:16] = 00 to
use an external reference for the DAC or set B[17:16] to
01, 10, or 11 to select either the 2.5V, 2.048V, or 4.096V
internal reference, respectively.
The SOFTWARE Command Action Mode is selected by
B[18:16]:
END (000): Used to end any active gate operation,
returning to normal operation (default).
GATE (001):
DAC contents will be gated to their
DEFAULT selected values until the gate
condition is removed.
CLEAR (100):
All CODE and DAC contents will be
cleared to their DEFAULT selected
values.
RESET (101):
All CODE, DAC, RETURN, and
configuration registers reset to their
power-up defaults (including REF,
POWER, and CONFIG settings),
simulating a power cycle reset.
OTHER:
No effect.
If RF3 (B19) is set to zero (default) in the REF command,
the REF I/O will not be driven by the internal reference
circuit, saving current. If RF3 is set to one, the REF I/O
will be driven by the internal reference circuit, consuming
an additional 25FA (typ) of current when the reference is
powered; when the reference is powered down, the REF
I/O will be high-impedance.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time the DAC
is powered down (in STANDBY mode). If RF2 (B18) is
set to one, the reference will remain powered even if the
DAC is powered down, allowing continued operation of
external circuitry. In this mode, the 1FA shutdown state is
not available. See Table 3.
Table 3. REF (0010) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10
1
0
RF3 RF2 RF1 RF0
REF COMMAND
0 = Off in Standby
1 = On in Standby
0
0 = REF Not driven
1 = REF Driven
0
DEFAULT VALUES
0
0
X
X
X
Ref Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
0
0
X
X
X
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
Don’t Care
X
X
COMMAND BYTE
X
X
X
Don’t Care
X
X
X
X
X
DATA HIGH BYTE
X
X
X
DATA LOW BYTE
Table 4. SOFTWARE (0011) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
X
SOFTWARE
COMMANDS
Don’t Care
0
DEFAULT VALUES
X
SW2 SW1 SW0 X
X
Mode:
000: END
001: GATE
100: CLR
101: RST
Other: No
Effect
0
COMMAND BYTE
Maxim Integrated
X
0
0
X
X
X
X
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
Don’t Care
X
X
X
X
X
Don’t Care
X
DATA HIGH BYTE
X
X
X
X
X
X
X
DATA LOW BYTE
20
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
POWER Command
mode, the DAC register retains its value so that the
output is restored when the device powers up. The serial
interface remains active in power-down mode with all
registers accessible.
The MAX5703/MAX5704/MAX5705 feature a softwarecontrolled POWER mode command (B[23:20] = 0100).
In power-down, the DAC output is disconnected from
the buffer and is grounded with either one of the two
selectable internal resistors or set to high impedance.
See Table 5 and Table 6 for the selectable internal
resistor values in power-down mode. In power-down
In power-down mode, the internal reference can be
powered down or it can be set to remain powered-on for
external use. Also, in power-down mode, parts using the
external reference do not load the REF pin. See Table 5.
Table 5. POWER (0100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
0
X
POWER
COMMAND
DEFAULT VALUES
X
X
X
X
X
X
Don’t Care
X
X
X
COMMAND BYTE
X
X
X
X
B8
X
X
X
X
X
X
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
Power
Mode:
00 =
Normal
01 = 1kI
10 =
100kI
11 = Hi-Z
Don’t Care
X
B7
PD1 PD0
X
X
X
0
0
DATA HIGH BYTE
Don’t Care
X
X
X
X
DATA LOW BYTE
Table 6. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B7)
PD0 (B6)
0
0
Normal operation
0
1
Power-down with internal 1kI pulldown resistor to GND.
1
0
Power-down with internal 100kI pulldown resistor to GND.
1
1
Power-down with high-impedance output.
Maxim Integrated
OPERATING MODE
21
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
CONFIG Command
The CONFIG command (B[23:20] = 0101) updates the
function of the AUX input enabling its gate, load, or clear
(default) operation mode. See Table 7.
AUX Config settings are written by B[5:3]:
GATE (011): AUX functions as a GATE. DAC code is
gated to DEFAULT value input when pin
is low.
CLEAR (110): AUX functions as a CLR input (default).
CODE and DAC content is cleared to
DEFAULT value if pin is low.
NONE (111):
AUX functions are disabled.
OTHER:
AUX function is not altered.
Note: CONFIG should not be programmed with the AUX
pin asserted (low) or unexpected behavior could result.
DEFAULT Command
DEFAULT (0110): The DEFAULT command selects the
default value for the DAC. These default values are used
for all future clear and gate operations. The new default
setting is determined by bits DF[2:0]. See Table 8.
Available default values are:
POR (000): DAC defaults to power-on reset value
(default).
ZERO (001): DAC defaults to zero scale.
MID (010):
DAC defaults to midscale.
FULL (011):
DAC defaults to full scale.
RETURN (100): DAC defaults to value specified by the
RETURN register
OTHER:
No effect, the default setting remains
unchanged.
Note: The selected default values do not apply to resets
initiated by SW_RESET commands or supply cycling,
both of which return the DACs to the power-on reset state
(zero scale).
Table 7. CONFIG (0101) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
0
1
X
CONFIG COMMAND
DEFAULT VALUES
X
X
X
X
X
X
Don’t Care
X
X
X
X
X
X
X
B8
B7
B6
X
X
X
Don’t
Care
Don’t Care
X
X
X
COMMAND BYTE
X
X
X
X
X
X
X
X
DATA HIGH BYTE
B5
B4
B3
AB2 AB1 AB0
AUXB Mode:
011 = GATE
110 = CLEAR
111 = NONE
Other = No
Effect
1
1
0
B2
B1
B0
X
X
X
Don’t Care
X
X
X
DATA LOW BYTE
Table 8. DEFAULT (0110) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
0
1
1
0
X
DEFAULT
COMMAND
DEFAULT VALUES
X
X
X
X
X
Don’t Care
X
X
COMMAND BYTE
Maxim Integrated
X
X
X
X
X
X
B8
X
X
X
X
X
X
B6
B5
DF2 DF1 DF0
B4
B3
B2
B1
B0
X
X
X
X
X
Default Values:
000: POR
001: ZERO
010: MID
011: FULL
100: RETURN
Other: No
Effect
Don’t Care
X
B7
X
DATA HIGH BYTE
X
X
0
0
0
Don’t Care
X
X
X
X
X
DATA LOW BYTE
22
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
RETURN Command
The RETURN command (B[23:20] = 0111) updates the
RETURN register content for the DAC. If the DEFAULT
configuration register is set to RETURN mode, the DAC
will be cleared or gated to the RETURN register value in
the event of a SW or HW CLEAR or GATE condition. It is
not necessary to program this register if the DEFAULT =
RETURN mode will not be used. The data format for the
RETURN register is identical to that used for CODE and
LOAD operations. See Table 1 and Table 2.
Applications Information
Power-On Reset (POR)
When power is applied to VDD, the DAC output is
set to zero scale. To optimize DAC linearity, wait until
the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Power Supplies and Bypassing
Considerations
Bypass VDD with high-quality ceramic capacitors to
a low-impedance ground as close as possible to the
device. Minimize lead lengths to reduce lead inductance.
Connect GND to the analog ground plane.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with
a low-inductance ground plane, or star connect all
ground return paths back to the MAX5703/MAX5704/
MAX5705 GND. Carefully layout the traces between
channels to reduce AC cross-coupling. Do not use wirewrapped boards and sockets. Use shielding to maximize
noise immunity. Do not run analog and digital signals
parallel to one another, especially clock signals. Avoid
routing digital lines underneath the MAX5703/MAX5704/
MAX5705 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Maxim Integrated
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level
nonidealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
23
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Circuits
100nF
100nF
VDDIO
4.7µF
VDD
OUT
DAC
VOUT = -VREF to +VREF
CS
MICRO CONTROLLER
SCLK
DIN
LDAC
MAX5703
MAX5704
MAX5705
REF
R1
AUX
R2
R1 = R2
GND
NOTE: BIPOLAR OPERATION SHOWN
100nF
100nF
VDDIO
CS
MICRO CONTROLLER
4.7µF
VDD
OUT
DAC
VOUT = 0V to VREF
SCLK
DIN
LDAC
MAX5703
MAX5704
MAX5705
REF
AUX
GND
NOTE: UNIPOLAR OPERATION SHOWN
Maxim Integrated
24
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Ordering Information
PIN-PACKAGE
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
MAX5703ATB+T
PART
10 TDFN-EP*
8
10 (typ), 25 (max)
MAX5703AUB+
10 FMAX
8
10 (typ), 25 (max)
MAX5704ATB+T
10 TDFN-EP*
10
10 (typ), 25 (max)
MAX5704AUB+
10 FMAX
10
10 (typ), 25 (max)
MAX5705AAUB+
10 FMAX
12
4 (typ), 12 (max)
MAX5705BATB+T
10 TDFN-EP*
12
10 (typ), 25 (max)
MAX5705BAUB+
10 FMAX
12
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
10 (typ), 25 (max)
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
T1032N+1
21-0429
90-0082
10 FMAX
U10+2
21-0061
90-0330
25
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/12
Initial release
1
2/13
Released MAX5703/MAX5704. Updated the Electrical Characteristics.
2
6/13
Released the MAX5703/MAX5704/MAX5705 TDFN packages.
3
11/14
Added details to AUX input description
DESCRIPTION
PAGES
CHANGED
—
2–8, 25
25
14, 15, 22
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2014 Maxim Integrated Products, Inc.
26
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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