EVALUATION KIT AVAILABLE
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
General Description
The MAX5813/MAX5814/MAX5815 4-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal reference
that is selectable to be 2.048V, 2.500V, or 4.096V. The
MAX5813/MAX5814/MAX5815 accept a wide supply
voltage range of 2.7V to 5.5V with extremely low power
(3mW) consumption to accommodate most low-voltage
applications. A precision external reference input allows
rail-to-rail operation and presents a 100kI (typ) load to
an external reference.
The MAX5813/MAX5814/MAX5815 have an I2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low supply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5813/
MAX5814/MAX5815 reset the DAC outputs to zero, providing additional safety for applications that drive valves
or other transducers which need to be off on power-up.
The internal reference is initially powered down to allow
use of an external reference. The MAX5813/MAX5814/
MAX5815 allow simultaneous output updates using software LOAD commands or the hardware load DAC logic
input (LDAC).
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
sets the DAC outputs to zero. The MAX5813/MAX5814/
MAX5815 are available in a 14-pin TSSOP and an ultrasmall, 12-bump WLP package and are specified over the
-40NC to +125NC temperature range.
Benefits and Features
S Four High-Accuracy DAC Channels
12-Bit Accuracy Without Adjustment
±1 LSB INL Buffered Voltage Output
Guaranteed Monotonic Over All Operating
Conditions
Independent Mode Settings for Each DAC
S Three Precision Selectable Internal References
2.048V, 2.500V, or 4.096V
S Internal Output Buffer
Rail-to-Rail Operation with External Reference
4.5µs Settling Time
Outputs Directly Drive 2kI Loads
S Small 5mm x 4.4mm 14-Pin TSSOP or Ultra-Small
1.6mm x 2.2mm 12-Bump WLP Package
S Wide 2.7V to 5.5V Supply Range
S Separate 1.8V to 5.5V VDDIO Power-Supply Input
S Fast 400kHz I2C-Compatible, 2-Wire Serial
Interface
S Power-On-Reset to Zero-Scale DAC Output
S LDAC and CLR For Asynchronous Control
S Three Software-Selectable Power-Down Output
Impedances
1kI, 100kI, or High Impedance
Functional Diagram
Applications
VDDIO
VDD
REF
Programmable Voltage and Current Sources
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
Data Acquisition
MAX5813
MAX5814
MAX5815
INTERNAL REFERENCE/
EXTERNAL BUFFER
Gain and Offset Adjustment
SCL
1 OF 4 DAC CHANNELS
SDA
CODE
REGISTER
ADDR0
(ADDR1)
DAC
LATCH
8 -/10-/12-BIT
DAC
OUTA
BUFFER
I2C SERIAL
INTERFACE
OUTB
CLR
CODE
CLEAR/
RESET
LOAD
(LDAC)
DAC CONTROL LOGIC
OUTC
CLEAR/
RESET
100kI
1kI
OUTD
POWER-DOWN
POR
Ordering Information appears at end of data sheet.
GND
( ) TSSOP PACKAGE ONLY
For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/MAX5813.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6167; Rev 4; 6/13
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ABSOLUTE MAXIMUM RATINGS
VDD, VDDIO to GND................................................. -0.3V to +6V
OUT_, REF to GND.....0.3V to the lower of (VDD + 0.3V) and +6V
SCL, SDA, LDAC, CLR to GND............................... -0.3V to +6V
ADDR_ to GND.............................................-0.3V to the lower of
(VDDIO + 0.3V) and +6V
Continuous Power Dissipation (TA = +70NC)
TSSOP (derate at 10mW/NC above 70NC)....................797mW
WLP (derate at 16.1mW/NC above 70NC)...................1288mW
Maximum Continuous Current into Any Pin..................... Q50mA
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (TSSOP only)(soldering, 10s)............+300NC
Soldering Temperature (reflow)..................................... +260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA) ........100NC/W
Junction-to-Case Thermal Resistance (θJC) ...............30NC/W
WLP
Junction-to-Ambient Thermal Resistance (θJA)
(Note 2).........................................................................62NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Note 2: Visit www.maximintegrated.com/app-notes/index.mvp/id/1891 for information about the thermal performance of WLP packaging.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC PERFORMANCE (Note 4)
Resolution and Monotonicity
Integral Nonlinearity (Note 5)
Differential Nonlinearity (Note 5)
Offset Error (Note 6)
N
INL
DNL
MAX5813
8
MAX5814
10
MAX5815
12
MAX5813
-0.25
Q0.05
+0.25
MAX5814
-0.5
Q0.25
+0.5
MAX5815
-1
Q0.5
+1
MAX5813
-0.25
Q0.05
+0.25
MAX5814
-0.5
Q0.1
+0.5
MAX5815
-1
Q0.2
+1
-5
Q0.5
+5
OE
Offset Error Drift
Gain Error (Note 6)
Gain Temperature Coefficient
Q10
GE
-1.0
With respect to VREF
Zero-Scale Error
Full-Scale Error
Maxim Integrated
Bits
With respect to VREF
Q0.1
LSB
LSB
mV
FV/NC
+1.0
%FS
ppm of
FS/NC
Q3.0
0
10
mV
-0.5
+0.5
%FS
2
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
Output Voltage Range (Note 7)
Load Regulation
No load
0
VDD
2kI load to GND
0
VDD 0.2
2kI load to VDD
0.2
VDD
VOUT = VFS/2
DC Output Impedance
VOUT = VFS/2
Maximum Capacitive Load
Handling
CL
Resistive Load Handling
RL
Short-Circuit Output Current
300
VDD = 5V Q10%,
|IOUT| P 10mA
300
VDD = 3V Q10%,
|IOUT| P 5mA
0.3
VDD = 5V Q10%,
|IOUT| P 10mA
0.3
FV/mA
I
500
2
VDD = 5.5V
DC Power-Supply Rejection
VDD = 3V Q10%,
|IOUT| P 5mA
V
pF
kI
Sourcing (output
shorted to GND)
30
Sinking (output
shorted to VDD)
50
mA
VDD = 3V Q10% or 5V Q10%
100
FV/V
Positive and negative
1.0
V/Fs
¼ scale to ¾ scale, to P 1 LSB, MAX5813
2.2
¼ scale to ¾ scale, to P 1 LSB, MAX5814
2.6
¼ scale to ¾ scale, to P 1 LSB, MAX5815
4.5
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
SR
DAC Glitch Impulse
Major code transition
Channel-to-Channel
Feedthrough (Note 8)
External reference
3.5
Internal reference
3.3
Code = 0, all digital inputs from 0V to
VDDIO
0.2
nV*s
Startup calibration time (Note 9)
200
Fs
From power-down
50
Fs
Digital Feedthrough
Power-Up Time
Maxim Integrated
7
Fs
nV*s
nV*s
3
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
External reference
Output Voltage-Noise Density
(DAC Output at Midscale)
82
f = 1kHz
112
f = 10kHz
102
2.5V internal
reference
f = 1kHz
125
f = 10kHz
110
4.096V internal
reference
f = 1kHz
160
f = 10kHz
145
f = 0.1Hz to 10Hz
12
2.048V internal
reference
2.5V internal
reference
External reference
Integrated Output Noise
(DAC Output at Full Scale)
76
f = 0.1Hz to 300kHz
385
f = 0.1Hz to 10Hz
14
f = 0.1Hz to 10kHz
91
f = 0.1Hz to 300kHz
450
f = 0.1Hz to 10Hz
15
f = 0.1Hz to 10kHz
99
f = 0.1Hz to 300kHz
470
f = 0.1Hz to 10Hz
16
f = 0.1Hz to 10kHz
124
f = 0.1Hz to 300kHz
490
f = 1kHz
114
99
2.048V internal
reference
f = 1kHz
175
f = 10kHz
153
2.5V internal
reference
f = 1kHz
200
f = 10kHz
174
4.096V internal
reference
f = 1kHz
295
f = 10kHz
255
f = 0.1Hz to 10Hz
13
2.048V internal
reference
2.5V internal
reference
4.096V internal
reference
Maxim Integrated
f = 0.1Hz to 10kHz
f = 10kHz
External reference
MAX
UNITS
90
2.048V internal
reference
4.096V internal
reference
Output Voltage-Noise Density
(DAC Output at Full Scale)
TYP
f = 10kHz
External reference
Integrated Output Noise
(DAC Output at Midscale)
f = 1kHz
MIN
f = 0.1Hz to 10kHz
94
f = 0.1Hz to 300kHz
540
f = 0.1Hz to 10Hz
19
f = 0.1Hz to 10kHz
143
f = 0.1Hz to 300kHz
685
f = 0.1Hz to 10Hz
21
f = 0.1Hz to 10kHz
159
f = 0.1Hz to 300kHz
705
f = 0.1Hz to 10Hz
26
f = 0.1Hz to 10kHz
213
f = 0.1Hz to 300kHz
750
nV/√Hz
FVP-P
nV/√Hz
FVP-P
4
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
V
74
FA
REFERENCE INPUT
Reference Input Range
VREF
Reference Input Current
IREF
Reference Input Impedance
RREF
1.24
VREF = VDD = 5.5V
55
75
100
kI
VREF = 2.048V, TA = +25NC
2.043
2.048
2.053
VREF = 2.5V, TA = +25NC
VREF = 4.096V, TA = +25NC
2.494
2.500
2.506
4.086
REFERENCE OUPUT
Reference Output Voltage
VREF
4.096
4.106
Reference Temperature
Coefficient (Note 10)
MAX5815A
Q3.7
Q10
MAX5813/MAX5814/MAX5815B
Q10
Q25
Reference Drive Capacity
External load
25
Reference Capacitive Load
Reference Load Regulation
ISOURCE = 0 to 500FA
Reference Line Regulation
V
ppm/NC
kI
200
pF
2
mV/mA
0.05
mV/V
POWER REQUIREMENTS
Supply Voltage
I/O Supply Voltage
VDD
VREF = 4.096V
4.5
5.5
All other options
2.7
5.5
1.8
5.5
VDDIO
Internal reference
Supply Current (Note 11)
IDD
External reference
Interface Supply Current
(Note 11)
Power-Down Mode Supply
Current
VREF = 2.048V
0.93
1.25
VREF = 2.5V
0.98
1.30
VREF = 4.096V
1.16
1.50
VREF = 3V
0.85
1.15
VREF = 5V
1.10
1.40
IDDIO
IPD
1
All DACs off, internal reference ON
140
All DACs off, internal reference OFF,
TA = -40NC to +85NC
0.5
1
All DACs off, internal reference OFF,
TA = +125NC
1.2
2.5
V
V
mA
FA
FA
DIGITAL INPUT CHARACTERISTICS (SCL, SDA, ADDR0, ADDR1, LDAC, CLR)
Input High Voltage (Note 11)
Maxim Integrated
2.2V < VDDIO < 5.5V
0.7 x
VDDIO
V
1.8V < VDDIO < 2.2V
0.8 x
VDDIO
V
VIH
5
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
PARAMETER
Input Low Voltage (Note 11)
SYMBOL
VH
Input Leakage Current
IIN
ADDR_ Pullup/Pulldown Strength
MIN
TYP
0.3 x
VDDIO
1.8V < VDDIO < 2.2V
0.2 x
VDDIO
0.15
VIN = 0V or VDDIO (Note 11)
Q0.1
CIN
RPU, RPD
MAX
2.2V < VDDIO < 5.5V
VIL
Hysteresis Voltage
Input Capacitance (Note 10)
CONDITIONS
30
50
V
V
Q1
FA
90
kI
0.2
V
400
kHz
3
(Note 12)
UNITS
pF
DIGITAL OUTPUT (SDA)
Output Low Voltage
VOL
ISINK = 3mA
I2C TIMING CHARACTERISTICS (SCL, SDA, LDAC, CLR)
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
Fs
tHD;STA
0.6
Fs
SCL Pulse Width Low
tLOW
1.3
Fs
SCL Pulse Width High
Hold Time Repeated for a
START Condition
tHIGH
0.6
Fs
Setup Time for Repeated START
Condition
tSU;STA
0.6
Fs
Data Hold Time
tHD;DAT
0
Data Setup Time
tSU;DAT
100
SDA and SCL Receiving
Rise Time
tr
20 +
CB/10
300
ns
SDA and SCL Receiving
Fall Time
tf
20 +
CB/10
300
ns
SDA Transmitting Fall Time
tf
20 +
CB/10
250
ns
400
pF
Setup Time for STOP Condition
tSU;STO
Bus Capacitance Allowed
CB
Pulse Width of Suppressed Spike
tsp
CLR Removal Time Prior to a
Recognized START
900
ns
0.6
VDD = 2.7V to 5.5V
ns
Fs
10
50
ns
tCLRSTA
100
ns
CLR Pulse Width Low
tCLPW
20
ns
LDAC Pulse Width Low
tLDPW
20
ns
400
ns
SCLK Rise to LDAC Fall to Hold
Maxim Integrated
tLDH
Applies to execution edge
6
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VDDIO = 1.8V to 5.5V, VGND = 0V, CL = 200pF, RL = 2kI, TA = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 3)
Note 3: Electrical specifications are production tested at TA = +25°C. Specifications over the entire operating temperature range
are guaranteed by design and characterization. Typical specifications are at TA = +25°C.
Note 4: DC Performance is tested without load.
Note 5: Linearity is tested with unloaded outputs to within 20mV of GND and VDD.
Note 6: Offset and gain errors are calculated from measurements made with VREF = VDD at code 30 and 4065 for MAX5815,
code 8 and 1016 for MAX5814, and code 2 and 254 for MAX5813.
Note 7: Subject to zero and full-scale error limits and VREF settings.
Note 8: Measured with all other DAC outputs at midscale with one channel transitioning 0 to full scale.
Note 9: On power-up, the device initiates an internal 200µs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 10: Guaranteed by design.
Note 11: All channels active at VFS, unloaded. Static logic inputs with VIL = VGND and VIH = VDDIO.
Note 12: An unconnected condition on the ADDR_ pins is sensed via a resistive pullup and pulldown operation; for proper
operation, ADDR_ pins should be tied to VDDIO, GND, or left unconnected with minimal capacitance.
SDA
tLOW
tf
tSU;DAT
tr
tHD;STA
tf
tSP
tBUF
tr
SCL
tHD;STA
tCLPW
S
tHIGH
tHD;DAT
tSU;STA
tSU;STO
Sr
P
CLR
tLDPW
tLDH
tCLRSTA
S
LDAC
Figure 1. I2C Serial Interface Timing Diagram
Typical Operating Characteristics
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
VDD = VREF = 5V
NO LOAD
0.8
0.6
DNL vs. CODE
1.0
MAX5813 toc02
0.6
0.6
0.4
0.2
0.2
0.2
-0.2
DNL (LSB)
0.4
0
0
-0.2
0
-0.2
-0.4
-0.4
-0.4
-0.6
-0.6
-0.6
-0.8
-0.8
-0.8
-1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
Maxim Integrated
VDD = VREF = 3V
NO LOAD
0.8
0.4
INL (LSB)
INL (LSB)
MAX5813 toc01
VDD = VREF = 3V
NO LOAD
0.8
INL vs. CODE
1.0
MAX5813 toc03
INL vs. CODE
1.0
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
7
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
INL AND DNL vs. SUPPLY VOLTAGE
0.6
0
-0.4
-0.6
-0.8
-0.8
-1.0
-1.0
-0.8
-1.0
3.1
3.5
3.9
4.3
4.7
5.1
5.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
ZERO-SCALE ERROR
0.8
0.6
VREF = 2.5V (EXTERNAL)
NO LOAD
ZERO-SCALE ERROR
0.020
0.016
0.012
0
-0.2
OFFSET ERROR
-0.4
0.2
OFFSET ERROR (VDD = 5V)
0
-0.2
-0.4
OFFSET ERROR (VDD = 3V)
0.004
0
-0.004
-0.6
-0.012
-0.8
-0.8
-0.016
-1.0
3.9
4.3
4.7
5.1
5.5
-40 -25 -10 5 20 35 50 65 80 95 110 125
SUPPLY VOLTAGE (V)
MAX5813 toc10
GAIN ERROR (VDD = 5V)
0
FULL-SCALE ERROR
GAIN ERROR (VDD = 3V)
-0.05
1.2
OUT_ = FULL SCALE
NO LOAD
V
REF (INTERNAL) = 4.096V,
VDD = 5V
VREF (INTERNAL) = 2.5V, VDD = 5V
1.0
VREF (INTERNAL) = 2.048V, VDD = 5V
0.8
VREF (EXTERNAL) = VDD = 5V
0.4
-0.10
3.5
3.9
4.3
4.7
5.1
5.5
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.6
VREF (EXTERNAL) = VDD = 3V
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
3.1
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
1.4
SUPPLY CURRENT (mA)
0.05
2.7
TEMPERATURE (°C)
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
VREF = 2.5V (EXTERNAL)
NO LOAD
VREF = 2.5V (EXTERNAL)
NO LOAD
-0.020
1.2
1.1
1.0
SUPPLY CURRENT (mA)
3.5
MAX5813 toc11
3.1
FULL-SCALE ERROR
-0.008
-0.6
-1.0
GAIN ERROR
0.008
ERROR (%fs)
ERROR (mV)
0.4
0.2
MAX5813 toc09
1.0
0.4
0.10
MIN INL
SUPPLY VOLTAGE (V)
0.6
2.7
MIN DNL
-0.6
CODE (LSB)
VREF = 2.5V (EXTERNAL)
NO LOAD
0.8
0
-0.2
VREF (INTERNAL) = 4.096V
VREF (INTERNAL) = 2.5V
MAX5813 toc12
1.0
MAX DNL
0.2
-0.4
MIN DNL
MIN INL
2.7
512 1024 1536 2048 2560 3072 3584 4096
MAX INL
0.4
-0.2
-0.6
0.6
MAX DNL
0.2
-0.4
VDD = VREF = 3V
0.8
ERROR (LSB)
ERROR (LSB)
0
-0.2
MAX5813 toc07
DNL (LSB)
0.2
0
ERROR (mV)
MAX INL
0.4
0.4
ERROR (%fsr)
VREF = 2.7V
0.8
MAX5813 toc08
0.6
INL AND DNL vs. TEMPERATURE
1.0
MAX5813 toc06
MAX5813 toc04
VDD = VREF = 5V
NO LOAD
0.8
1.0
MAX5813 toc05
DNL vs. CODE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VREF (EXTERNAL) = 2.5V
VREF (INTERNAL) = 2.048V
NO LOAD
TA = +25°C
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VDD (V)
8
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
POWER-DOWN MODE SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT (mA)
1.2
TA = +125°C
0.8
TA = +25°C
TA = +85°C
0.4
TA = -40°C
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
0.8
0.7
0.6
0.5
0.4
REFERENCE CURRENT (µA)
40
VDD = 3V, VREF
(EXTERNAL) = 3V
VDD = 5V, VREF
(INTERNAL) = 2.5V
0
5.5
NO LOAD
TA = +25°C
500 1000 1500 2000 2500 3000 3500 4000 4500
CODE (LSB)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5813 toc15
50
VDD = 5V, VREF
(INTERNAL) = 2.048V
0.3
0.2
0.1
0
IREF (EXTERNAL) vs. CODE
VDD = VREF
NO LOAD
VDD = 5V, VREF
(EXTERNAL) = 5V
0.9
SUPPLY VOLTAGE (V)
60
VDD = 5V, VREF
(INTERNAL) = 4.096V
1.1
1.0
MAX5813 toc16
POWER-DOWN MODE
ALL DACs
MAX5813 toc14
SUPPLY CURRENT vs. CODE
1.2
MAX5813 toc13
POWER-DOWN SUPPLY CURRENT (µA)
1.6
VOUT
0.5V/div
1/4 SCALE TO 3/4 SCALE
VREF = 5V
30
ZOOMED VOUT
1 LSB/div
VREF = 3V
20
3.75µs
TRIGGER PULSE
5V/div
10
0
0
512 1024 1536 2048 2560 3072 3584 4096
4µs/div
CODE (LSB)
MAX5813 toc17
3/4 SCALE TO 1/4 SCALE
MAX5813 toc18
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
SETTLING TO ±1 LSB
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
ZOOMED VOUT
3.3mV/div
4.3µs
ZOOMED VOUT
1 LSB/div
VOUT
0.5V/div
TRIGGER PULSE
5V/div
TRIGGER PULSE
5V/div
4µs/div
Maxim Integrated
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GLITCH ENERGY = 6.7nV•s
2µs/div
9
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
MAJOR CODE TRANSITION
GLITCH ENERGY
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5813 toc20
MAX5813 toc19
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GLITCH ENERGY = 6nV•s
VOUT vs. TIME TRANSIENT
EXITING POWER-DOWN
VSCL
5V/div
0V
36TH EDGE
DAC OUTPUT
500mV/div
ZOOMED VOUT
3.3mV/div
0V
VDD = 5V, VREF = 2.5V
EXTERNAL
TRIGGER PULSE
5V/div
2µs/div
10µs/div
POWER-ON RESET TO 0V
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC,
RL = 2kI, CL = 200pF)
MAX5813 toc22
MAX5813 toc21
VDD = VREF = 5V
10kI LOAD TO VDD
VDD
2V/div
0V
RL = 2kI
TRANSITIONING
DAC
1V/div
NO LOAD
STATIC DAC
1.25mV/div
VOUT
2V/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.5nV*s
0V
20µs/div
4µs/div
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = VREF = 5V, TA = +25NC, NO LOAD)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, RL = 2kI, CL = 200pF)
MAX5813 toc24
MAX5813 toc23
NO LOAD
NO LOAD
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.8nV*s
5µs/div
Maxim Integrated
TRIGGER PULSE
10V/div
TRANSITIONING
DAC
1V/div
RL = 2kI
TRANSITIONING
DAC
1V/div
STATIC DAC
1.25mV/div
NO LOAD
STATIC DAC
1.25mV/div
TRIGGER PULSE
10V/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 3.3nV*s
TRIGGER PULSE
10V/div
5µs/div
10
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL FEEDTHROUGH
(VDD = 5V, VREF = 4.096V (INTERNAL),
TA = +25NC, NO LOAD) MAX5813 toc25
DIGITAL FEEDTHROUGH
(VDD = VREF = 5V, RL = 2kI, CL = 200pF)
MAX5813 toc26
VDD = 5V
VREF = 5V (EXTERNAL)
DACS AT MIDSCALE
NO LOAD
TRANSITIONING DAC
1V/div
NO LOAD
STATIC DAC
1.25mV/div
TRANSITIONING DAC: 0 TO FULL SCALE
STATIC DAC: MIDSCALE
ANALOG CROSSTALK = 1.1nV*S
VOUT
1.65mV/div
TRIGGER PULSE
10V/div
DIGITAL FEEDTHROUGH = 0.1nV·s·
4µs/div
40ns/div
OUTPUT CURRENT LIMITING
OUTPUT LOAD REGULATION
6
DVOUT (mV)
VDD = 3V
-2
-200
-6
-300
-8
-400
VDD = 3V
-500
-10
-30 -20 -10
0
10
20
30
40
50
HEADROOM AT RAILS
vs. OUTPUT CURRENT (VDD = VREF)
NOISE-VOLTAGE DENSITY
VS. FREQUENCY (DAC AT MIDSCALE)
3.50
3.00
2.50
VDD = 3V, SOURCING
1.50
VDD = 3V AND 5V
SINKING
1.00
DAC = ZERO SCALE
0
0
1
2
3
4
VDD = 5V, VREF = 4.096V
(INTERNAL)
300
VDD = 5V, VREF = 2.5V
(INTERNAL)
250
VDD = 5V, VREF = 2.048V
(INTERNAL)
200
150
100
50
VDD = 5V, VREF = 4.5V
(EXTERNAL)
0
5
6
IOUT (mA)
Maxim Integrated
350
NOISE-VOLTAGE DENSITY (nV/√Hz)
MAX5813 toc29
VDD = 5V, SOURCING
4.00
0.50
10 20 30 40 50 60 70
IOUT (mA)
DAC = FULL SCALE
2.00
-30 -20 -10 0
60
IOUT (mA)
5.00
VOUT (V)
0
-100
-4
4.50
VDD = 5V
100
MAX5813 toc30
DVOUT (mV)
300
200
2
0
VDD = VREF
400
VDD = 5V
4
MAX5813 toc28
VDD = VREF
8
500
MAX5813 toc27
10
7
8
9
10
100
1k
10k
100k
FREQUENCY (Hz)
11
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Typical Operating Characteristics (continued)
(MAX5815, 12-bit performance, TA = +25°C, unless otherwise noted.)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.048V)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
REFERENCE (VDD = 5V, VREF = 4.5V)
MAX5813 toc32
MAX5813 toc31
MIDSCALE UNLOADED
VP-P = 13µV
MIDSCALE UNLOADED
VP-P = 12µV
2µV/div
2µV/div
4s/div
4s/div
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 2.5V)
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (VDD = 5V, VREF = 4.096V)
MAX5813 toc33
MAX5813 toc34
MIDSCALE UNLOADED
VP-P = 16µV
MIDSCALE UNLOADED
VP-P = 15µV
2µV/div
2µV/div
4s/div
4s/div
10
SUPPLY CURRENT vs. INPUT LOGIC VOLTAGE
MAX5813 toc36
-0.4
-0.6
VREF = 2.048V, 2.5V, AND 4.096V
5
-0.8
0
-1.0
2000
1800
1600
SUPPLY CURRENT (µA)
15
VDD = 5V
INTERNAL REFERENCE
-0.2
DVREF (mV)
20
MAX5813 toc35
PERCENT OF POPULATION (%)
VDD = 2.7V,
INTERNAL VREF = 2.5V
BOX METHOD
REFERENCE LOAD REGULATION
0
MAX5813 toc37
VREF DRIFT vs. TEMPERATURE
25
1400
1200
VDDIO = 5V
1000
800
600
VDDIO = 3V
400
200
2.8 2.9 3.0 3.2 3.3 3.4 3.6 3.7 3.9 4.0 4.1 4.3 4.4
TEMPERATURE DRIFT (ppm/°C)
Maxim Integrated
VDDIO = 1.8V
0
0
50 100 150 200 250 300 350 400 450 500
REFERENCE OUTPUT CURRENT (µA)
0
1
2
3
4
5
INPUT LOGIC VOLTAGE (V)
12
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Pin/Bump Configurations
TOP VIEW
TOP VIEW
REF
1
+
14
OUTA
2
13
VDDIO
OUTB
3
12
CLR
GND
4
11
SDA
OUTC
5
OUTD
6
VDD
MAX5813
MAX5814
MAX5815
7
10
SCL
9
ADDR0
8
MAX5815
LDAC
ADDR1
1
2
3
4
OUTB
OUTC
OUTD
REF
GND
VDDIO
VDD
CLR
SDA
SCL
ADDR0
+ OUTA
A
B
C
TSSOP
WLP
Pin/Bump Description
PIN
BUMP
TSSOP
WLP
1
B1
REF
Reference Voltage Input/Output
2
A1
OUTA
Buffered Channel A DAC Output
3
A2
OUTB
Buffered Channel B DAC Output
4
B2
GND
Ground
5
A3
OUTC
Buffered Channel C DAC Output
6
A4
OUTD
Buffered Channel D DAC Output
7
B4
VDD
8
—
ADDR1
Supply Voltage Input. Bypass VDD with a 0.1FF capacitor to GND.
I2C Interface Address Selection Bit 1
9
C4
ADDR0
I2C Interface Address Selection Bit 0
10
C3
SCL
I2C Interface Clock Input
11
C2
SDA
I2C Bidirectional Serial Data
12
C1
CLR
Active-Low Clear Input
13
B3
VDDIO
Digital Interface Power-Supply Input
14
—
LDAC
Load DAC. Active-low hardware load DAC input.
Maxim Integrated
NAME
FUNCTION
13
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Detailed Description
The MAX5813/MAX5814/MAX5815 are 4-channel, lowpower, 8-/10-/12-bit buffered voltage-output DACs. The
2.7V to 5.5V wide supply voltage range and low-power
consumption accommodates most low-power and lowvoltage applications. The devices present a 100kI load
to the external reference. The internal output buffers
allow rail-to-rail operation. An internal voltage reference
is available with software selectable options of 2.048V,
2.5V, or 4.096V. The devices feature a fast 400kHz I2Ccompatible interface. The MAX5813/MAX5814/MAX5815
include a serial-in/parallel-out shift register, internal
CODE and DAC registers, a power-on-reset (POR) circuit to initialize the DAC outputs to code zero, and control logic. CLR is available to asynchronously clear the
device independent of the serial interface.
DAC Outputs (OUT_)
The MAX5813/MAX5814/MAX5815 include internal buffers on all DAC outputs. The internal output buffers
provide improved load regulation for the DAC outputs.
The output buffers slew at 1V/Fs (typ) and drive up to
2kI in parallel with 500pF. The analog supply voltage
(VDD) determines the maximum output voltage range
of the devices as VDD powers the output buffer. Under
no-load conditions, the output buffers drive from GND to
VDD, subject to offset and gain errors. With a 2kω load to
GND, the output buffers drive from GND to within 200mV
of VDD. With a 2kω load to VDD, the output buffers drive
from VDD to within 200mV of GND.
The DAC ideal output voltage is defined by:
D
V=
OUT VREF × N
2
where D = code loaded into the DAC register, VREF =
reference voltage, N = resolution.
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can be
routed to control registers, individual, or multiple DACs
as determined by the user command.
Within each DAC channel there is a CODE register
followed by a DAC latch register (see the Detailed
Functional Diagram). The contents of the CODE register
hold pending DAC output settings which can later be
Maxim Integrated
loaded into the DAC registers. The CODE register can be
updated using both CODE and CODE_LOAD user commands. The contents of the DAC register hold the current
DAC output settings. The DAC register can be updated
directly from the serial interface using the CODE_LOAD
commands or can upload the current contents of the
CODE register using LOAD commands or the LDAC
hardware pin.
The contents of both CODE and DAC registers are maintained during power-down states, so that when the DACs
are powered on, they return to their previously stored
output settings. Any CODE or LOAD commands issued
during power-down states continue to update the register
contents. SW_CLEAR and SW_RESET commands reset
the contents of all CODE and DAC registers to their zeroscale defaults.
Internal Reference
The MAX5813/MAX5814/MAX5815 include an internal
precision voltage reference that is software selectable
to be 2.048V, 2.500V, or 4.096V. When an internal reference is selected, that voltage is available on the REF pin
for other external circuitry (see Figure 9) and can drive
a 25kI load.
External Reference
The external reference input has a typical input
impedance of 100kI and accepts an input voltage
from +1.24V to VDD. Connect an external voltage
supply between REF and GND to apply an external reference. The MAX5813/MAX5814/MAX5815
power up and reset to external reference mode. Visit
www.maximintegrated.com/products/references for a
list of available external voltage-reference devices.
Load DAC (LDAC) Input
The MAX5813/MAX5814/MAX5815 feature an activelow LDAC logic input that allows the outputs to update
asynchronously. Connect LDAC to VDDIO or keep LDAC
high during normal operation when the device is controlled only through the serial interface. Drive LDAC low
to simultaneously update the DAC outputs with data
from the CODE registers. Holding LDAC low causes the
DAC registers to become transparent and CODE data is
passed through to the DAC registers immediately updating the DAC outputs. A software CONFIG command can
be used to configure the LDAC operation of each DAC
independently.
14
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Clear Input (CLR)
The MAX5813/MAX5814/MAX5815 feature an asynchronous active-low CLR logic input that simultaneously sets
all four DAC outputs to zero. Driving CLR low clears the
contents of both the CODE and DAC registers and also
aborts the on-going I2C command. To allow a new I2C
command, drive CLR high, satisfying the tCLRSTA timing
requirement.
Figure 2
S
Sr
P
SCL
SDA
Interface Power Supply (VDDIO)
The MAX5813/MAX5814/MAX5815 feature a separate
supply pin (VDDIO) for the digital interface (1.8V to 5.5V).
Connect VDDIO to the I/O supply of the host processor.
VALID START, REPEATED START, AND STOP PULSES
I2C Serial Interface
The MAX5813/MAX5814/MAX5815 feature an I2C-/
SMBusK-compatible, 2-wire serial interface consisting of
a serial data line (SDA) and a serial clock line (SCL). SDA
and SCL enable communication between the MAX5813/
MAX5814/MAX5815 and the master at clock rates up
to 400kHz. Figure 1 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
MAX5813/MAX5814/MAX5815 by transmitting the proper
slave address followed by the command byte and then
the data word. Each transmit sequence is framed by a
START (S) or Repeated START (Sr) condition and a STOP
(P) condition. Each word transmitted to the MAX5813/
MAX5814/MAX5815 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX5813/MAX5814/MAX5815 must transmit the
proper slave address followed by a series of nine SCL
pulses for each byte of data requested. The MAX5813/
MAX5814/MAX5815 transmit data on SDA in sync with
the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence
is framed by a START or Repeated START condition, a
not acknowledge, and a STOP condition. SDA operates
as both an input and an open-drain output. A pullup
resistor, typically 4.7kI is required on SDA. SCL operates only as an input. A pullup resistor, typically 4.7kI, is
required on SCL if there are multiple masters on the bus,
or if the single master has an open-drain SCL output.
Series resistors in line with SDA and SCL are optional.
Series resistors protect the digital inputs of the MAX5813/
MAX5814/MAX5815 from high voltage spikes on the bus
lines and minimize crosstalk and undershoot of the bus
P
S
S
P
P
S
P
INVALID START/STOP PULSE PAIRINGS -ALL WILL BE RECOGNIZED AS STARTS
Figure 2. I2C START, Repeated START, and STOP Conditions
signals. The MAX5813/MAX5814/MAX5815 can accommodate bus voltages higher than VDDIO up to a limit of
5.5V; bus voltages lower than VDDIO are not recommended and may result in significantly increased interface currents. The MAX5813/MAX5814/MAX5815 digital inputs
are double buffered. Depending on the command issued
through the serial interface, the CODE register(s) can
be loaded without affecting the DAC register(s) using
the write command. To update the DAC registers, either
drive the LDAC input low to asynchronously update all
DAC outputs, or use the software LOAD command.
I2C START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition.
A START condition is a high-to-low transition on SDA with
SCL high. A STOP condition is a low-to-high transition
on SDA while SCL is high (Figure 2). A START condition
from the master signals the beginning of a transmission
SMBus is a trademark of Intel Corp.
Maxim Integrated
15
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
to the MAX5813/MAX5814/MAX5815. The master terminates transmission and frees the bus, by issuing a STOP
condition. The bus remains active if a Repeated START
condition is generated instead of a STOP condition.
I2C Early STOP and
Repeated START Conditions
The MAX5813/MAX5814/MAX5815 recognize a STOP
condition at any point during data transmission except
if the STOP condition occurs in the same high pulse as
a START condition. Transmissions ending in an early
STOP condition will not impact the internal device settings. If the STOP occurs during a readback byte, the
transmission is terminated and a later read mode request
will begin transfer of the requested register data from
the beginning (this applies to combined format I2C read
mode transfers only, interface verification mode transfers
will be corrupted). See Figure 2.
I2C Slave Address
The slave address is defined as the seven most significant bits (MSBs) followed by the R/W bit. See
Figure 4. For the TSSOP packages, the three most significant bits are 001 with the 4 LSBs determined by ADDR1
and ADDR0 as shown in Table 1. For the WLP package,
the five most significant bits are 00011 with the 2 LSBs
determined by ADDR0 as shown in Table 2. Setting
the R/W bit to 1 configures the MAX5813/MAX5814/
MAX5815 for read mode. Setting the R/W bit to 0 configures the MAX5813/MAX5814/MAX5815 for write mode.
The slave address is the first byte of information sent
to the MAX5813/MAX5814/MAX5815 after the START
condition.
The MAX5813/MAX5814/MAX5815 have the ability to
detect an unconnected state on the ADDR input for
additional address flexibility; if leaving the ADDR input
unconnected, be certain to minimize all loading on the
pin (i.e. provide a landing for the pin, but do not allow
any board traces).
I2C Broadcast Address
A broadcast address is provided for the purpose of
updating or configuring all MAX5813/MAX5814/MAX5815
devices on a given I2C bus. All MAX5813/MAX5814/
MAX5815 devices acknowledge and respond to the
broadcast device address 00010000. The devices will
respond to the broadcast address, regardless of the
state of the address pins. The broadcast mode is intended for use in write mode only (as indicated by R/W = 0 in
the address given).
Maxim Integrated
CLOCK PULSE
FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 3. I2C Acknowledge
Table 1. I2C Slave Address LSBs for
TSSOP Package
TSSOP PACKAGE (A[6:4] = 001)
ADDR1
ADDR0
A3
A2
A1
A0
VDDIO
VDDIO
0
0
0
0
VDDIO
N.C.
0
0
1
0
VDDIO
GND
0
0
1
1
N.C.
VDDIO
1
0
0
0
N.C.
N.C.
1
0
1
0
N.C.
GND
1
0
1
1
GND
VDDIO
1
1
0
0
GND
N.C.
1
1
1
0
GND
GND
1
1
1
1
Table 2. I2C Slave Address LSBs for WLP
Package
WLP PACKAGE (A[6:2] = 00011)
ADDR0
A1
A0
VDDIO
0
0
N.C.
1
0
GND
1
1
16
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
I2C Acknowledge
In write mode, the acknowledge bit (ACK) is a clocked 9th
bit that the MAX5813/MAX5814/MAX5815 use to handshake receipt of each byte of data as shown in Figure 3.
The MAX5813/MAX5814/MAX5815 pull down SDA during
the entire master-generated 9th clock pulse if the previous
byte is successfully received. Monitoring ACK allows for
detection of unsuccessful data transfers. An unsuccessful
data transfer occurs if a receiving device is busy or if a
system fault has occurred. In the event of an unsuccessful data transfer, the bus master will retry communication.
In read mode, the master pulls down SDA during the
9th clock cycle to acknowledge receipt of data from the
MAX5813/MAX5814/MAX5815. An acknowledge is sent
by the master after each read byte to allow data transfer
to continue. A not-acknowledge is sent when the master
reads the final byte of data from the MAX5813/MAX5814/
MAX5815, followed by a STOP condition.
I2C Command Byte and Data Bytes
A command byte follows the slave address. A command
byte is typically followed by two data bytes unless it is
the last byte in the transmission. If data bytes follow the
command byte, the command byte indicates the address
of the register that is to receive the following two data
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
bytes. The data bytes are stored in a temporary register
and then transferred to the appropriate register during
the ACK periods between bytes. This avoids any glitching or digital feedthrough to the DACs while the interface
is active.
I2C Write Operations
A master device communicates with the MAX5813/
MAX5814/MAX5815 by transmitting the proper slave
address followed by command and data words. Each
transmit sequence is framed by a START or Repeated
START condition and a STOP condition as described
above. Each word is 8 bits long and is always followed
by an acknowledge clock (ACK) pulse as shown in the
Figure 4 and Figure 5. The first byte contains the address
of the MAX5813/MAX5814/MAX5815 with R/W = 0 to
indicate a write. The second byte contains the register
(or command) to be written and the third and fourth bytes
contain the data to be written. By repeating the register
address plus data pairs (Byte #2 through Byte #4 in
Figure 4 and Figure 5), the user can perform multiple
register writes using a single I2C command sequence.
There is no limit as to how many registers the user can
write with a single command. The MAX5813/MAX5814/
MAX5815 support this capability for all user-accessible
write mode commands.
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
START
STOP
0
SDA
SCL
0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
COMMAND EXECUTED
A ACK. GENERATED BY MAX5813/MAX5814/MAX5815
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 4. I2C Single Register Write Sequence
Maxim Integrated
17
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
START
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
WRITE COMMAND1
BYTE #2: COMMAND1 BYTE
(B[23:16])
WRITE DATA1
BYTE #3: DATA1 HIGH BYTE
(B[15:8])
WRITE DATA1
BYTE #4: DATA1 LOW BYTE
(B[7:0])
0 0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4 3 2 1 0 A
SDA
SCL
COMMAND1
EXECUTED
ADDITIONAL COMMAND AND
DATA PAIRS (3 BYTE BLOCKS)
BYTE #5: COMMANDn BYTE
(B[23:16])
BYTE #6: DATAn HIGH BYTE
(B[15:8])
BYTE #7: DATAn LOW BYTE
(B[7:0])
23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 4
STOP
3 2 1 0 A
COMMANDn
EXECUTED
A ACK. GENERATED BY MAX5813/MAX5814/MAX5815
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 5. Multiple Register Write Sequence (Standard I2C Protocol)
WRITE ADDRESS
BYTE #1: I2C SLAVE
ADDRESS*
START
SDA
SCL
0
0
WRITE COMMAND 1
BYTE #2: COMMAND 1
BYTE
1 A3 A2 A1 A0 W A 0 0 N N N N N N A
A
READ ADDRESS
BYTE #3: I2C SLAVE
ADDRESS*
REPEATED
START
0
0
READ DATA
BYTE #4: DATA 1 HIGH
BYTE (B[15:8])
READ DATA
BYTE #5: DATA 1 LOW
BYTE (B[7:0])
STOP
1 A3 A2 A1 A0 R A D D D D D D D D A D D D D D D D D ~A
ACK. GENERATED BY MAX5813/MAX5814/ MAX5815
A ACK. GENERATED BY I2C MASTER
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 6. Standard I2C Register Read Sequence
Combined Format I2C Readback Operations
Each readback sequence is framed by a START or
Repeated START condition and a STOP condition. Each
word is 8 bits long and is followed by an acknowledge
clock pulse as shown in Figure 6. The first byte contains
the address of the MAX5813/MAX5814/MAX5815 with
R/W = 0 to indicate a write. The second byte contains
the register that is to be read back. There is a Repeated
START condition, followed by the device address with
R/W = 1 to indicate a read and an acknowledge clock.
The master has control of the SCL line but the MAX5813/
MAX5814/MAX5815 take over the SDA line. The final two
bytes in the frame contain the register data readback
followed by a STOP condition. If additional bytes beyond
those required to readback the requested data are provided, the MAX5813/MAX5814/MAX5815 will continue to
readback ones.
Maxim Integrated
Readback of individual CODE registers is supported for
the CODE command (B[23:20] = 0000). For this command, which supports a DAC address, the requested
channel CODE register content will be returned; if all
DACs are selected, CODEA content will be returned.
Readback of individual DAC registers is supported for
all LOAD commands (B[23:20] = 0001, 0010, or 0011).
For these commands, which support a DAC address, the
requested DAC register content will be returned. If all
DACs are selected, DACA content will be returned.
Modified readback of the POWER register is supported
for the POWER command (B[23:20] = 0100). The power
status of each DAC is reported in locations B[3:0], with a
1 indicating the DAC is powered down and a 0 indicating
the DAC is operational (see Table 3).
18
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Readback of all other registers is not directly supported.
All requests to read unsupported registers reads back
the device’s reference status and the device ID and revision information in the format as shown in Table 3.
Interface Verification I2C
Readback Operations
While the MAX5813/MAX5814/MAX5815 support standard I2C readback of selected registers, it is also
capable of functioning in an interface verification mode.
This mode is accessed any time a readback operation
follows an executed write mode command. In this mode,
the last executed three-byte command is read back in its
entirety. This behavior allows verification of the interface.
Sample command sequences are shown in Figure 7.
The first command transfer is given in write mode with
R/W = 0 and must be run to completion to qualify for
interface verification readback. There is now a STOP/
START pair or Repeated START condition required, followed by the readback transfer with R/W = 1 to indicate
a read and an acknowledge clock from the MAX5813/
MAX5814/MAX5815. The master still has control of the
SCL line but the MAX5813/MAX5814/MAX5815 take over
the SDA line. The final three bytes in the frame contain
the command and register data written in the first transfer
presented for readback, followed by a STOP condition. If
additional bytes beyond those required to read back the
requested data are provided, the MAX5813/MAX5814/
MAX5815 will continue to read back ones.
It is not necessary for the write and read mode transfers
to occur immediately in sequence. I2C transfers involving other devices do not impact the MAX5813/MAX5814/
MAX5815 readback mode. Toggling between readback
modes is based on the length of the preceding write
mode transfer. Combined format I2C readback operation
is resumed if a write command greater than two bytes
but less than four bytes is supplied. For commands written using multiple register write sequences, only the last
command executed is read back. For each command
written, the readback sequence can only be completed
one time; partial and/or multiple attempts to readback
executed in succession will not yield usable data.
Table 3. Standard I2C User Readback Data
COMMAND BYTE (REQUEST)
READBACK DATA HIGH BYTE
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
READBACK DATA LOW BYTE
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
DAC selection
CODEn[11:4]
CODEn[3:0]
0
0
0
0
0
0
0
1
DAC selection
DACn[11:4]
DACn[3:0]
0
0
0
0
0
0
1
0
DAC selection
DACn[11:4]
DACn[3:0]
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
X
X
1
0
0
0
0
0
0
0
CODEA[11:4]
CODEA[3:0]
0
0
0
0
1
0
0
0
0
0
0
1
DACA[11:4]
DACA[3:0]
0
0
0
0
1
0
1
0
0
0
1
0
DACA[11:4]
DACA[3:0]
0
0
0
0
1
0
1
1
0
0
1
1
DACA[11:4]
DACA[3:0]
0
0
0
0
DAC selection
DACn[11:4]
0
0
0
0
0
DACn[3:0]
0
0
0
0
0
0
Any other command (TSSOP)
1111 1000
000
Any other command (WLP)
1001 1000
000
0
PWD PWC PWB PWA
REV_ID[2:0]
(010)
REF MODE
RF[1:0]
Table 4. Format DAC Data Bit Positions
PART
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MAX5813
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
x
x
MAX5814
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
x
MAX5815
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
Maxim Integrated
19
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
START
0
SDA
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0 A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
START
0
0
SDA
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
START
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
WRITE COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
WRITE DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 W A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
6
5
4
3
2
1
STOP
0 ~A
WRITE DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
REPEATED
START
0
A
SCL
POINTER UPDATED
(QUALIFIES FOR COMBINED READ BACK)
WRITE ADDRESS
BYTE #1: I2C SLAVE ADDRESS*
0
READ COMMAND
BYTE #2: COMMAND BYTE
(B[23:16])
READ DATA
BYTE #3: DATA HIGH BYTE
(B[15:8])
0 1 A3 A2 A1 A0 R A 23 22 21 20 19 18 17 16 A 15 14 13 12 11 10 9
A ACK. GENERATED BY MAX5813/MAX5814/MAX5815
COMMAND EXECUTED
(QUALIFIES FOR INTERFACE READ BACK)
READ DATA
BYTE #4: DATA LOW BYTE
(B[7:0])
8 A 7
6
5
4
3
2
1
STOP
0 ~A
A ACK. GENERATED BY I2C MASTER
*I2C SLAVE ADDRESS FOR THE TSSOP PACKAGE IS USED
Figure 7. Interface Verification I2C Register Read Sequences
Maxim Integrated
20
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
LOADn Command
µC
SDA
SCL
MAX5813
MAX5814
MAX5815
SCL
SDA
ADDR0
(ADDR1)
MAX5813
MAX5814
MAX5815
+5V
SCL
SDA
ADDR0
(ADDR1)
( ) TSSOP PACKAGE ONLY
Figure 8. Typical I2C Application Circuit
I2C Compatibility
The MAX5813/MAX5814/MAX5815 are fully compatible
with existing I2C systems. SCL and SDA are high-impedance inputs; SDA has an open drain which pulls the data
line low to transmit data or ACK pulses. Figure 8 shows a
typical I2C application.
I2C User-Command Register Map
This section lists the user accessible commands and
registers for the MAX5813/MAX5814/MAX5815.
Table 5 provides detailed information about the Command
Registers.
CODEn Command
The CODEn command (B[23:20] = 0000) updates the
CODE register contents for the selected DAC(s). Changes
to the CODE register content based on this command will
not affect DAC outputs directly unless the LDAC is in a
low state or the DAC latch has been configured to be
transparent. Issuing the CODEn command with DAC
SELECTION = ALL DACs is equivalent to CODE_ALL
(B[23:16] = 10000000). See Table 5 and Table 6.
Maxim Integrated
The LOADn command (B[23:20] = 0001) updates the
DAC register content for the selected DAC(s) by uploading the current contents of the CODE register. The
LOADn command can be used with DAC SELECTION =
ALL DACs to issue a software load for all DACs, which
is equivalent to the LOAD_ALL (B[23:16] = 10000001)
command. See Table 5 and Table 6.
CODEn_LOAD_ALL Command
The CODEn_LOAD_ALL command (B[23:20] = 0010)
updates the CODE register contents for the selected
DAC(s) as well as the DAC register content of all DACs.
Channels for which the CODE register content has not
been modified since the last load to DAC register or LDAC
operation will not be updated to reduce digital crosstalk.
Issuing this command with DAC_ADDRESS = ALL is
equivalent to the CODE_ALL_LOAD_ALL command. The
CODEn_LOAD_ALL command by definition will modify at
least one CODE register. To avoid this, use the LOADn
command with DAC SELECTION = ALL DACs or use the
LOAD_ALL command. See Table 5 and Table 6.
CODEn_LOADn Command
The CODEn_LOADn command (B[23:20] = 0011) updates
the CODE register contents for the selected DAC(s) as
well as the DAC register content of the selected DAC(s).
Channels for which the CODE register content has not
been modified since the last load to DAC register or
LDAC operation will not be updated to reduce digital
crosstalk. Issuing this command with DAC SELECTION
= ALL DACs is equivalent to the CODE_ALL_LOAD_ALL
command. See Table 5 and Table 6.
CODE_ALL Command
The CODE_ALL command (B[23:16] = 10000000)
updates the CODE register contents for all DACs. See
Table 5.
LOAD_ALL Command
The LOAD_ALL command (B[23:16] = 10000001) updates
the DAC register content for all DACs by uploading the
current contents of the CODE registers. See Table 5.
CODE_ALL_LOAD_ALL Command
The CODE_ALL_LOAD_ALL command (B[23:16] =
1000001x) updates the CODE register contents for all
DACs as well as the DAC register content of all DACs.
See Table 5.
21
Maxim Integrated
0
0
0
LOADn
CODEn_
LOAD_ALL
CODEn_
LOADn
0
0
0
0
1
1
0
0
1
0
1
0
1
1
SW_CLEAR 0
SW_RESET
0
1
0
POWER
0
0
0
1
1
0
CONFIGURATION COMMANDS
0
CODEn
DAC COMMANDS
0
0
0
0
0
0
0
0
1
0
Power
Mode
00 =
Normal
01 = PD
1kI
10 = PD
100kI
11 = PD
Hi-Z
DAC SELECTION
DAC SELECTION
DAC SELECTION
DAC SELECTION
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B8
X
X
X
X
X
X
X
X
DAC DAC DAC DAC
D
C
B
A
CODE REGISTER
DATA [11:4]
CODE REGISTER
DATA [11:4]
X
CODE REGISTER
DATA [11:4]
COMMAND B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
Table 5. I2C Commands Summary
B6
B5
B4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CODE REGISTER
DATA [3:0]
CODE REGISTER
DATA [3:0]
X
CODE REGISTER
DATA [3:0]
B7
X
X
X
X
X
X
X
B3
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
B0
Executes a software reset
(all CODE, DAC, and
control registers returned
to their default values)
Executes a software clear (all
CODE and DAC registers
cleared to their default values)
Sets the power mode of
the selected DACs (DACs
selected with a 1 in the
corresponding DACn bit
are updated, DACs with
a 0 in the corresponding
DACn bit are not
impacted)
Simultaneously writes data
to the selected CODE
register(s) while updating
selected DAC register(s)
Simultaneously writes data
to the selected CODE
register(s) while updating
all DAC registers
Transfers data from the
selected CODE register(s)
to the selected DAC
register(s)
Writes data to the selected
CODE register(s)
DESCRIPTION
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
22
1
1
1
1
1
LOAD_ALL
CODE_
ALL_
LOAD_ALL
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
X
1
0
1
X
X
All DACs
X
X
X
0
0
0
0
X
X
X
0
0
0
REF
Power
0=
DAC
1=
ON
0
LD_EN
X
X
X
1
0
0
X
X
X
X
1
0
REF
Mode
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.1V
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CODE REGISTER
DATA [11:4]
X
CODE REGISTER
DATA [11:4]
X
X
DAC D
X
X
X
X
X
X
X
X
X
X
X
X
X
B5
X
X
B4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CODE REGISTER
DATA [3:0]
X
CODE REGISTER
DATA [3:0]
X
X
B6
Reserved Commands: Any commands not specifically listed above are reserved for Maxim internal use only.
No
Operation
NO OPERATION COMMANDS
1
CODE_ALL
ALL DAC COMMANDS
0
REF
1
X
0
COMMAND B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9
DAC B
DAC C
Maxim Integrated
CONFIG
B7
B8
DAC A
Table 5. I2C Commands Summary (continued)
X
X
X
X
X
X
X
X
B3
X
X
X
X
X
X
X
X
B2
X
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
X
B0
These commands will have
no effect on the device
Simultaneously writes data
to all CODE registers while
updating all DAC registers
Updates all DAC latches
with current CODE register
data
Writes data to all CODE
registers
Sets the reference
operating mode.
REF Power (B18):
0 = Internal reference is
only powered if at least
one DAC is powered
1 = Internal reference is
always powered
Sets the DAC Latch Mode
of the selected DACs.
Only DACS with a 1 in the
selection bit are updated
by the command.
LD_EN = 0: DAC latch is
operational (LOAD and
LDAC controlled)
LD_EN = 1: DAC latch is
transparent
DESCRIPTION
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
23
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Table 6. DAC Selection
B19
B18
B17
B16
0
0
0
0
DAC A
0
0
0
1
DAC B
0
0
1
0
DAC C
0
0
1
1
DAC D
X
1
X
X
ALL DACs
1
X
X
X
ALL DACs
POWER Command
DAC SELECTED
ers up. The serial interface remains active in power-down
mode.
The MAX5813/MAX5814/MAX5815 feature a softwarecontrolled power-mode (POWER) command (B[23:20] =
0100). The POWER command updates the power-mode
settings of the selected DACs while the power settings of
the rest of the DACs remain unchanged. The new power
setting is determined by bits B[17:16] while the affected
DAC(s) are selected by bits B[11:8]. If all DACs are powered down, the device enters a STANDBY mode.
In STANDBY mode, the internal reference can be powered down or it can be set to remain powered-on for
external use. Also, in STANDBY mode, devices using the
external reference do not load the REF pin. See Table 7.
SW_RESET and SW_CLEAR Command
The SW_RESET (B[23:16] = 01010001) and SW_CLEAR
(B[23:16] = 01010000) commands provide a means of
issuing a software reset or software clear operation. Use
SW_CLEAR to issue a software clear operation to return
all CODE and DAC registers to the zero-scale value. Use
SW_RESET to reset all CODE, DAC, and configuration
registers to their default values.
In power-down, the DAC output is disconnected from the
buffer and is grounded with either one of the two selectable internal resistors or set to high impedance. See Table
8 for the selectable internal resistor values in power-down
mode. In power-down mode, the DAC register retains its
value so that the output is restored when the device pow-
Table 7. POWER (100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16
0
1
0
0
0
0
POWER Command
Default Values (all DACs) →
PD1 PD0
B15
X
Power
Mode:
00 =
Normal
01 = 1kI
10 =
100kI
11 = Hi-Z
0
0
B14 B13 B12 B11 B10
X
X
X
X
X
C
B8
B7
B6
B5
B4
B3
B2
B1
B0
B
A
X
X
X
X
X
X
X
X
X
X
X
DAC Select:
1 = DAC Selected
0 = DAC Not
Selected
Don’t Care
X
D
B9
X
1
1
1
1
Don’t Care
X
X
X
X
X
Table 8. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B17)
PD0 (B16)
0
0
Normal operation
0
1
Power-down with internal 1kI pulldown resistor to GND.
1
0
Power-down with internal 100kI pulldown resistor to GND.
1
1
Power-down with high-impedance output.
Maxim Integrated
OPERATING MODE
24
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
CONFIG Command
or 11 to select either the 2.5V, 2.048V, or 4.096V internal
reference, respectively.
The CONFIG command (B[23:20] = 0110) updates the
LDAC and LOAD functions of selected DACs. Issue the
command with B16 = 0 to allow the DAC latches to operate normally or with B16 = 1 to disable the DAC latches,
making them perpetually transparent. Mode settings of
the selected DACs are updated while the mode settings
of the rest of the DACs remain unchanged; DAC(s) are
selected by bits B[11:8]. See Table 9.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time all DAC
channels are powered down (in STANDBY mode). If RF2
(B18 = 1) is set to one, the reference will remain powered
even if all DAC channels are powered down, allowing
continued operation of external circuitry. In this mode,
the 1FA shutdown state is not available. See Table 10.
REF Command
The REF command updates the global reference setting
used for all DAC channels. Set B[17:16] = 00 to use an
external reference for the DACs or set B[17:16] to 01, 10,
Table 9. CONFIG Command Format
B23 B22 B21 B20 B19 B18 B17 B16
0
CONFIG Command
All
0
0
CONFIG
Command
Default Values (All DACs) →
LDB
X
0 = Normal
1 = Transparent
1
1 = Select All DACs
1
0 = Select Individual DACs
0
B15 B14 B13 B12 B11 B10 B9
0
X
X
X
X
X
C
B
B7
B6
B5
B4
B3
B2
B1
B0
A
X
X
X
X
X
X
X
X
DAC Select:
1 = DAC Selected
0 = DAC Not
Selected
Don’t Care
X
D
B8
X
1
1
Don’t Care
1
1
X
X
X
X
X
X
X
X
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
X
X
X
X
X
X
X
X
X
X
X
X
X
Table 10. REF Command Format
B23 B22 B21 B20 B19 B18 B17 B16
1
1
1
0
RF2 RF1 RF0
REF Command
0 = Off in Standby
1 = On in Standby
0
Default Values →
0
Maxim Integrated
B15 B14 B13 B12 B11 B10
X
X
X
REF Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
0
0
X
X
X
Don’t Care
X
X
X
X
X
Don’t Care
X
X
X
X
X
X
X
X
25
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Applications Information
Power-On Reset (POR)
Power Supplies and
Bypassing Considerations
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Layout Considerations
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
When power is applied to VDD and VDDIO, the DAC output is set to zero scale. To optimize DAC linearity, wait
until the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Bypass VDD and VDDIO with high-quality ceramic capacitors to a low-impedance ground as close as possible to
the device. Minimize lead lengths to reduce lead inductance. Connect the GND to the analog ground plane.
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with a
low-inductance ground plane, or star connect all ground
return paths back to the MAX5813/MAX5814/MAX5815
GND. Carefully layout the traces between channels to
reduce AC cross-coupling. Do not use wire-wrapped
boards and sockets. Use shielding to minimize noise immunity. Do not run analog and digital signals parallel to one
another, especially clock signals. Avoid routing digital lines
underneath the MAX5813/MAX5814/MAX5815 package.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R 1 LSB, the DAC
output may still be monotonic.
Maxim Integrated
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Gain Error
Zero-Scale Error
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level nonidealities.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
26
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Detailed Functional Diagram
VDD
REF
100kI RIN
MAX5813
MAX5814
MAX5815
INTERNAL / EXTERNAL REFERENCE (USER OPTION)
CODE
REGISTER
A
CODE
CLEAR /
RESET
DAC
LATCH
A
8-/10-/12-BIT
DAC A
CLEAR /
RESET
LOAD
OUTA
BUFFER A
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
VDDIO
CODE
REGISTER
B
DAC
LATCH
B
8-/10-/12-BIT
DAC B
OUTB
BUFFER B
SCL
SDA
CODE
CLEAR /
RESET
CLEAR /
RESET
LOAD
ADDR0
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
I2C SERIAL
INTERFACE
(ADDR1)
CODE
REGISTER
C
DAC
LATCH
C
8-/10-/12-BIT
DAC C
OUTC
BUFFER C
CLR
(LDAC)
CODE
CLEAR /
RESET
CLEAR /
RESET
LOAD
100kI
1kI
POWER-DOWN
DAC CONTROL LOGIC
POR
CODE
REGISTER
D
CODE
CLEAR /
RESET
DAC
LATCH
D
LOAD
DAC CONTROL LOGIC
() TSSOP PACKAGE ONLY
Maxim Integrated
8-/10-/12-BIT
DAC D
OUTD
BUFFER D
CLEAR /
RESET
100kI
1kI
POWER-DOWN
GND
27
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
VDDIO
100nF
RPU =
5kI
VDD
100µF
4.7µF
RPU =
5kI
VDDIO
(LDAC)
VDD
OUT
DAC
SDA
MICROCONTROLLER
SCL
ADDR0
(ADDR1)
MAX5813
MAX5814
MAX5815
REF
R1
CLR
R2
R1 = R2
GND
( ) TSSOP PACKAGE ONLY
NOTE: ONE CHANNEL SHOWN
Figure 9. Bipolar Operating Circuit
Typical Operating Circuit
VDDIO
100nF
RPU =
5kI
VDD
4.7µF
RPU =
5kI
VDDIO
(LDAC)
100µF
VDD
OUT_
DAC
SDA
MICROCONTROLLER
SCL
ADDR0
(ADDR1)
MAX5813
MAX5814
MAX5815
REF
CLR
GND
( ) TSSOP PACKAGE ONLY
NOTE: UNIPOLAR OPERATION (ONE CHANNEL SHOWN)
Maxim Integrated
28
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Ordering Information
PART
PIN-PACKAGE
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
MAX5813AUD+T
14 TSSOP
8
10 (typ)
MAX5814AUD+T
14 TSSOP
10
10 (typ)
MAX5815AAUD+T
14 TSSOP
12
3 (typ),10 (max)
MAX5815BAUD+T
14 TSSOP
12
10 (typ)
MAX5815AWC+T
12 WLP
12
3 (typ),10 (max)
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Chip Information
PROCESS: BiCMOS
Maxim Integrated
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
14 TSSOP
U14+1
21-0066
90-0113
12 WLP
W121B2+1
21-0009
Refer to
Application Note 1891
29
MAX5813/MAX5814/MAX5815
Ultra-Small, Quad-Channel, 8-/10-/12-Bit Buffered
Output DACs with Internal Reference and I2C Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
2/12
Initial release
1
6/12
Revised the Electrical Characteristics and Typical Operating Characteristics.
2
11/12
Revised the Electrical Characteristics, Typical Operating Characteristics, Ordering
Information, Figure 9, and Typical Operating Circuit.
3
1/13
Updated the Electrical Characteristics and the Ordering Information.
4
6/13
Updated the Electrical Characteristics, Pin/Bump Configurations, and the Ordering
Information.
DESCRIPTION
PAGES
CHANGED
—
3, 5, 9, 12
7, 8, 9, 11, 12,
25, 26, 28, 29
7, 29
6, 7, 14, 26
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc.
30
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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