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MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
General Description
Features
The MAX5982A/MAX5982B/MAX5982C provide a complete interface for a powered device (PD) to comply with
the IEEE® 802.3af/at standard in a power-over-Ethernet
(PoE) system. The MAX5982A/MAX5982B/MAX5982C
provide the PD with a detection signature, classification signature, and an integrated isolation power switch
with inrush current control. During the inrush period, the
MAX5982A/MAX5982B/MAX5982C limit the current to
less than 182mA before switching to the higher current
limit (1700mA to 2100mA) when the isolation power
MOSFET is fully enhanced. The devices feature an input
UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure
glitch-free transition during power-on/-off conditions. The
MAX5982A/MAX5982B/MAX5982C can withstand up to
100V at the input.
● Sleep Mode and Ultra-Low-Power Sleep
(MAX5982A/MAX5982B)
The MAX5982A/MAX5982B/MAX5982C support a
2-Event classification method as specified in the IEEE
802.3at standard and provide a signal to indicate when
probed by a Type 2 power sourcing equipment (PSE).
The devices detect the presence of a wall adapter power
source connection and allow a smooth switchover from
the PoE power source to the wall power adapter.
● LED Driver with Programmable LED Current
(MAX5982A/MAX5982B)
The MAX5982A/MAX5982B/MAX5982C also provide a
power-good (PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit. A sleep
mode feature in the MAX5982A/MAX5982B provides low
power consumption while supporting Maintain Power
Signature (MPS). An ultra-low-power sleep mode feature
in the MAX5982A/MAX5982B further reduces power
consumption while still supporting MPS. The MAX5982A/
MAX5982B also feature an LED driver that is automatically activated during sleep mode.
● IEEE 802.3af/at Compliant
● 2-Event Classification or an External Wall Adapter
Indicator Output
● Simplified Wall Adapter Interface
● PoE Classification 0–5
● 100V Input Absolute Maximum Rating
● Inrush Current Limit of 182mA Maximum
● Current Limit During Normal Operation Between
1700mA and 2100mA
● Current Limit and Foldback
● Legacy UVLO at 36V
● Overtemperature Protection
● Thermally Enhanced, 5mm x 5mm, 16-Pin TQFN
Applications
● IEEE 802.3af/at Powered Devices
● IP Phones, Wireless Access Nodes, IP Security
Cameras
● WiMAX™ Base Stations
Ordering Information appears at end of data sheet.
The MAX5982A/MAX5982B/MAX5982C are available
in a 16-pin, 5mm x 5mm, TQFN power package. These
devices are rated over the -40°C to +85°C and -40°C to
+125°C extended temperature ranges.
WiMAX is a trademark of WiMAX Forum.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
19-5960; Rev 4; 11/21
© 2021 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A.
|
Tel: 781.329.4700
|
© 2021 Analog Devices, Inc. All rights reserved.
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Absolute Maximum Ratings
Operating Temperature Range.......................... -40°C to +125°C
Maximum Junction Temperature......................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)........................................ +260°C
VDD to VSS...........................................................-0.3V to +100V
DET, RTN, WAD, PG, 2EC to VSS.......................-0.3V to +100V
CLS, SL, WK, ULP, LED to VSS..............................-0.3V to +6V
Maximum Current on CLS (100ms maximum)..................100mA
Continuous Power Dissipation (TA = +70°C) (Note 1)
TQFN (derate 28.6mW/°C above +70°C)
Multilayer Board.......................................................2285.7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
Package Thermal Characteristics (Note 2)
TQFN
Junction-to-Ambient Thermal Resistance (θJA)...........35°C/W
Junction-to-Case Thermal Resistance (θJC)...............2.7°C/W
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(VIN = (VDD - VSS) = 48V, RDET = 24.9kΩ, RCLS = 615Ω, and RSL = 60.4kΩ. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40°C to +85°C (MAX5982AETE/BETE/CETE), TA = TJ = -40°C to
+125°C (MAX5982AATE/BATE/CATE), unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
µA
DETECTION MODE
Input Offset Current
Effective Differential Input
Resistance
IOFFSET
dR
VIN = 1.4V to 10.1V (Note 4)
VIN = 1.4V up to 10.1V with 1V step,
VDD = RTN = WAD = PG = 2EC (Note 5)
23.95
25.00
25.50
kΩ
VIN rising (Note 6)
22.0
22.8
23.6
V
CLASSIFICATION MODE
Classification Disable Threshold
VTH,CLS
Classification Stability Time
0.2
Class 0, RCLS = 615Ω
Classification Current
ICLASS
VIN = 12.5V to
20.5V, VDD =
RTN = WAD =
PG = 2EC
TYPE 2 (802.3at) CLASSIFICATION MODE
Mark Event Threshold
VTHM
3.96
Class 1, RCLS = 117Ω
9.12
11.88
Class 2, RCLS = 66.5Ω
17.2
19.8
Class 3, RCLS = 43.7Ω
26.3
29.7
Class 4, RCLS = 30.9Ω
36.4
43.6
Class 5, RCLS = 21.3Ω
52.7
63.3
VIN falling
10.1
Hysteresis on Mark Event
Threshold
10.7
11.6
0.82
Mark Event Current
IMARK
VIN falling to enter mark event, 5.2V ≤
VIN ≤ 10.1V
Reset Event Threshold
VTHR
VIN falling
www.analog.com
ms
0
0.25
mA
V
V
0.85
-40°C to +125°C
2.7
3.8
5.2
-40°C to +85°C
2.8
3.8
5.2
mA
V
Analog Devices │ 2
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Electrical Characteristics (continued)
(VIN = (VDD - VSS) = 48V, RDET = 24.9kΩ, RCLS = 615Ω, and RSL = 60.4kΩ. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40°C to +85°C (MAX5982AETE/BETE/CETE), TA = TJ = -40°C to
+125°C (MAX5982AATE/BATE/CATE), unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
60
V
0.25
0.55
mA
35.4
36.6
V
POWER MODE
VIN Supply Voltage Range
VIN Supply Current
VIN Turn-On Voltage
VIN Turn-Off Voltage
VIN Turn-On/-Off Hysteresis
VIN Deglitch Time
Inrush to Operating Mode
Delay
IQ
VON
VOFF
VHYST_UVLO
tOFF_DLY
tDELAY
Current through internal MOSFET = 0
VIN rising
34.3
(Note 7)
4.2
VIN falling from 40V to 20V (Note 8)
30
120
90
96
VIN falling
30
tDELAY = minimum PG current pulse
width after entering into power mode
TJ = +25°C
Isolation Power MOSFET
On-Resistance
RON_ISO
IRTN = 950mA
RTN Leakage Current
IRTN_LKG
VRTN = 12.5V to 30V
CURRENT LIMIT
Inrush Current Limit
Current Limit During Normal
Operation
Current Limit in Foldback
Condition
IINRUSH
ILIM
ILIM-FLDBK
Foldback Threshold
VWAD-REF
WAD Detection Threshold
Hysteresis
WAD Input Current
TJ = +125°C
During initial turn-on period, VRTN = 1.5V
After inrush
completed,
VRTN = 1V (Note 9)
2EC Sink Current
µA
mA
1900
2100
-40°C to +125°C
1650
1900
2150
Both during inrush and after inrush
completed VRTN = 7.5V
53
VTH
VWK falling and VULP rising and falling
Falling
RSL = 0Ω
SL Current
ILED
RSL = 60.4kΩ, VLED = 3.5V
RSL = 30.2kΩ, VLED = 3.75V
RSL = 30.2kΩ, VLED = 4V
mA
mA
6.5
7.0
7.5
V
8
9
10
V
0.35
VWAD = 10V (referenced to RTN)
V2EC = 3.5V (referenced to RTN),
VSS disconnected
VPG = 60V
www.analog.com
10
1700
PG Off-Leakage Current
SLEEP MODE (MAX5982A/MAX5982B)
LED Current Amplitude
Ω
-40°C to +85°C
PG Sink Current
SL Logic Threshold
0.2
0.25
182
VRTN = 1.5V, VPG = 0.8V, during inrush
period
WK and ULP Logic Threshold
0.1
135
VWAD rising, VIN = 14V to 48V
(referenced to RTN)
ms
0.15
1
1.5
V2EC = 48V
2EC Off-Leakage Current
102
0.2
VWAD falling, VRTN = 0V, VSS
unconnected
IWAD-LKG
V
µs
90
VRTN (Note 10)
LOGIC
WAD Detection Threshold
TJ = +85°C
V
125
230
1.5
0.75
0.8
V
3.5
µA
2.25
mA
1
µA
375
µA
1
µA
3
V
0.85
140
V
µA
10
10.5
11.5
19.5
20.9
22.5
mA
19
Analog Devices │ 3
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Electrical Characteristics (continued)
(VIN = (VDD - VSS) = 48V, RDET = 24.9kΩ, RCLS = 615Ω, and RSL = 60.4kΩ. RTN, WAD, PG, 2EC, WK, and ULP unconnected, all
voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40°C to +85°C (MAX5982AETE/BETE/CETE), TA = TJ = -40°C to
+125°C (MAX5982AATE/BATE/CATE), unless otherwise noted. Typical values are at TA = +25°C.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
LED Current Programmable
Range
10
LED Current with Grounded SL
LED Current Frequency
LED Current Duty Cycle
VDD Current Amplitude
VSL = 0V
20.5
UNITS
20
mA
28.5
mA
250
Hz
DILED
Normal and ultra-low-power sleep modes
25
%
DIVDD
Normal and ultra-low-power sleep modes
Normal sleep mode, VLED = 3.5V
Internal Current Enable Time
tMPS
Ultra-low-power
sleep mode
Internal Current Disable Time
tMPDO
Ultra-low-power
sleep mode
SL Delay Time
24.5
MAX
Normal and ultra-low-power sleep modes
fILED
IVDD
Internal Current Duty Cycle
TYP
10
11
12.2
75
%
-40°C to +85°C
80
84
88
-40°C to +125°C
80
84
90
-40°C to +125°C
217
228
240
-40°C to +85°C
220
228
236
5.4
6.0
6.6
tSL
Time VSL must remain below the SL
logic threshold to enter sleep and ultralow-power modes (MAX5982A)
TSD
TJ rising
mA
ms
ms
s
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
Note
Note
Note
Note
Note
Note
TJ falling
3:
4:
5:
6:
7:
8:
+150
°C
30
°C
All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
The input offset current is illustrated in Figure 1.
Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1.
Classification current is turned off whenever the device is in power mode.
UVLO hysteresis is guaranteed by design, not production tested.
A 20V glitch on input voltage, which takes VDD below VON shorter than or equal to tOFF_DLY does not cause the
MAX5982A/MAX5982B/MAX5982C to exit power-on mode.
Note 9: Maximum current limit during normal operation is guaranteed by design; not production tested.
Note 10: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload
condition across VDD and RTN.
IIN
dRi =
1V
(VINi + 1 - VINi)
=
(IINi + 1 - IINi) (IINi + 1 - IINi)
IOFFSET = IINi -
VINi
dRi
IINi + 1
dRi
IINi
IOFFSET
VINi
1V
VINi + 1
VIN
Figure 1. Effective Differential Input Resistance/Offset Current
www.analog.com
Analog Devices │ 4
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Typical Operating Characteristics
(VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected; all
voltages are referenced to VSS.)
0.2
4
25.0
TA = +25°C
TA = +85°C
MAX5982A toc03
5
TA = -40°C
24.5
0.1
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
3
2
TA = +85°C
1
0
-1
-2
TA = +25°C
-3
TA = -40°C
-4
70
2
4
6
8
24.0
10
0
2
4
6
8
VIN (V)
VIN (V)
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
CLASSIFICATION SETTLING TIME
CLASS 5
60
MAX5982A toc05
2.0
IIN (mA)
CLASS 3
4
VIN
5V/div
1.6
IIN
100mA/div
1.2
VCLS
2V/div
CLASS 1
10
STEP INPUT APPLIED TO
VIN FROM 10V TO 12V
CLASS 0
0
5
10
15
20
25
30
10
TA = +25°C
TA = +85°C
0.8
0.4
0
100µs/div
0
10
20
150
100
0.14
0.12
0.10
0.08
0.06
0.04
10
20
30
VPG (V)
www.analog.com
60
40
50
60
0
NORMAL OPERATION CURRENT LIMIT
vs. RTN VOLTAGE
1.5
1.0
0.5
0.02
0
50
2.0
CURRENT LIMIT (A)
TA = +25°C
2.5
MAX5982A toc08
MAX5982A toc07
250
TA = +85°C
40
MAX5982A toc09
INRUSH CURRENT LIMIT
vs. RTN VOLTAGE
0.16
INRUSH CURRENT LIMIT (A)
TA = -40°C
200
30
V2EC (V)
PG SINK CURRENT vs. PG VOLTAGE
300
IPG (µA)
8
2EC SINK CURRENT vs. 2EC VOLTAGE
VIN (V)
50
6
CLASS 2
20
0
2
TA = -40°C
CLASS 4
30
0
VIN (V)
50
40
-5
10
I2EC (mA)
0
MAX5982A toc04
0
MAX5982A toc06
25.5
RSIGNATURE (kΩ)
IIN (mA)
0.3
IIN = IVDD + IDET
RDET = 25.4kΩ
RTN = 2EC = PG = WAD = VDD
INPUT OFFSET CURRENT (µA)
IIN = IVDD + IDET
RDET = 25.4kΩ
RTN = 2EC = PG = WAD = VDD
0.4
26.0
MAX5982A toc01
0.5
SIGNATURE RESISTANCE
vs. INPUT VOLTAGE
MAX5982A toc02
DETECTION CURRENT
vs. INPUT VOLTAGE
0
10
20
30
VRTN (V)
40
50
60
0
0
10
20
30
40
50
60
VRTN (V)
Analog Devices │ 5
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Typical Operating Characteristics (continued)
(VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, and RSL = 60.4kω. RTN, WAD, PG, 2EC, WK, and ULP unconnected; all
voltages are referenced to VSS.)
INRUSH CONTROL WAVEFORM
WITH TYPE 2 CLASSIFICATION
INRUSH CONTROL WAVEFORM
WITH TYPE 2 CLASSIFICATION
MAX5982A toc11
MAX5982A toc10
VIN
50V/div
VIN
50V/div
V2EC
50V/div
VPG
50V/div
VRTN
50V/div
V2EC
50V/div
VRTN
50V/div
IRTN
100mA/div
IRTN
100mA/div
20ms/div
400µs/div
MAX5982A toc12
25
LED CURRENT vs. LED VOLTAGE
25
MAX5982A toc13
LED CURRENT vs. RSL
RSL = 30.2kΩ
20
ILED (mA)
ILED (mA)
22
19
16
RSL = 60.4kΩ
10
5
13
10
15
0
0 5 10 15 20 25 30 35 40 45 50 55 60 65
0
1
2
3
5
4
RSL (kΩ)
VLED (V)
DRIVING LED WITH ULP IN
POWER MODE
SLEEP/ULTRA-LOW-POWER MODE
DELAY (MAX5982A)
MAX5982A toc14
MAX5982A toc15
VULP
2V/div
VSL
1V/div
ILED
5mA/div
ILED
5mA/div
10µs/div
www.analog.com
1s/div
Analog Devices │ 6
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
1
11
2EC
VDD
2
10
PG
9
WAD
DET
3
I.C.
4
N.C.
N.C.
LED
N.C.
SL
N.C.
WK
*EP
N.C.
13
+
MAX5982C
*EP
5
6
7
8
5
6
7
8
RTN
4
CLS
14
RTN
I.C.
MAX5982A
MAX5982B
12
15
VSS
3
+
16
VSS
DET
13
RTN
2
14
RTN
VDD
15
VSS
1
16
TOP VIEW
VSS
N.C.
ULP
Pin Configurations
TQFN
12
CLS
11
2EC
10
PG
9
WAD
TQFN
*CONNECT EP TO VSS.
Pin Description
PIN
MAX5982A/
MAX5982B
MAX5982C
1
1, 13–16
NAME
FUNCTION
N.C.
No Connection. Not internally connected.
2
2
3
3
DET
VDD
Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS.
4
4
I.C.
Internally Connected. Leave unconnected.
5, 6
5, 6
VSS
Negative Supply Input. VSS connects to the source of the integrated isolation n-channel
power MOSFET.
7, 8
7, 8
RTN
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel
power MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in
the Typical Application Circuit.
WAD
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment
VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from
WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation
n-channel power MOSFET turns off and 2EC current sink turns on. Connect WAD directly
to RTN when the wall power adapter or other auxiliary power source is not used.
9
10
www.analog.com
9
10
PG
Detection Resistor Input. Connect a signature resistor (RDET = 24.9kΩ) from DET to VDD.
Open-Drain, Power-Good Indicator Output. PG sinks 230µA to disable the downstream
DC-DC converter while turning on the hot-swap MOSFET switch. PG current sink is
disabled during detection, classification, and in the steady-state power mode. The PG
current sink is turned on to disable the downstream DC-DC converter when the device is in
sleep mode.
Analog Devices │ 7
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Pin Description (continued)
PIN
MAX5982A/
MAX5982B
MAX5982C
NAME
FUNCTION
11
11
2EC
2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is
enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a
Type 2 PSE, the 2EC current sink is enabled after the isolation MOSFET is fully on until
VIN drops below the UVLO threshold. 2EC is latched when powered by a Type 2 PSE
until VIN drops below the reset threshold. 2EC also asserts when a wall adapter supply,
typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if asserted
by WAD. The 2EC current sink is turned off when the device is in sleep mode.
12
12
CLS
Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the
desired classification current. See the classification current specifications in the Electrical
Characteristics table to find the resistor value for a particular PD classification.
13
––
LED
LED Driver Output. During sleep mode, LED sources a periodic current (ILED) at 250Hz
with 25% duty cycle. The amplitude of ILED is set by RSL according to the formula ILED
(in A) = 645.75/(RSL + 1200).
14
––
SL
Sleep Mode Enable Input. In the MAX5982B, a falling edge on SL brings the device into
sleep mode (VSL must drop below 0.75V). In the MAX5982A, VSL must remain below the
threshold (0.75V) for a period of at least 6s after falling edge to bring the device into sleep
mode. An external resistor (RSL) connected between SL and VSS sets the LED current
(ILED).
15
––
WK
Wake Mode Enable Input. WK has an internal 2.5kΩ pullup resistor to the internal 5V
bias rail. A falling edge on WK brings the device out of sleep mode and into the normal
operating mode (wake mode).
16
––
ULP
Ultra-Low-Power Sleep Enable Input (in Sleep Mode). ULP has an internal 50kΩ pullup
resistor to the internal 5V bias rail. A falling edge on SL in the MAX5982B (and a 6s period
below the SL threshold in the MAX5982A) while ULP is asserted low enables ultra-lowpower sleep mode. When ultra-low-power sleep mode is enabled, the power consumption
of the device is reduced even lower than normal sleep mode to comply with ultra-lowpower sleep power requirements while still supporting MPS.
––
––
EP
Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected
to VSS through a resistive path and must be connected to VSS externally. To optimize
power dissipation, solder the exposed pad to a large copper power plane.
www.analog.com
Analog Devices │ 8
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
MAX5982A/MAX5982B Simplified Block Diagram
VDD
VDD
EN
CLS
CLASSIFICATION
VDD
2EC
5V REGULATOR
D SET Q
D SET Q
CLR Q
CLR Q
1.5mA
VDD
5V
PG
46µA
DET
VON/VOFF
VDD
230µA
VDD
THERMAL
SHUTDOWN
WAD
R
S
Q
9V
tDELAY
ISWITCH
VSS
RTN
ISOLATION
SWITCH
K x ISWITCH
S
1/K
MUX
I0
I1
MAX5982A
MAX5982B
SL
5V
2.5kΩ
WK
LOGIC
LED
5V
50kΩ
ULP
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Analog Devices │ 9
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
MAX5982C Simplified Block Diagram
VDD
VDD
EN
CLS
CLASSIFICATION
VDD
2EC
5V REGULATOR
D SET Q
D SET Q
CLR Q
CLR Q
1.5mA
VDD
5V
PG
46µA
DET
VON/VOFF
VDD
230µA
VDD
THERMAL
SHUTDOWN
tDELAY
R
S
WAD
Q
9V
VSS
ISWITCH
RTN
ISOLATION
SWITCH
K x ISWITCH
S
1/K
MUX
www.analog.com
I0
MAX5982C
I1
Analog Devices │ 10
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Typical Operating Circuit
2-EVENT
CLASSIFICATION
DETECTION
GND
2EC
VDD
RJ-45
AND
BRIDGE
RECTIFIER
PG
RDET
24.9kΩ
68nF
DET
MAX5982A
MAX5982B
1.5mA
MAX5982C
VSS
WK
DC-DC
CONVERTER
WAD
24V/48V
BATTERY
RCLS
-54V
GND
ENABLE
2EC/WAD
CLS
SMAJ58A
IN+
IN-
RTN
MAX5982A/MAX5982B ONLY
1kΩ
SL
ISOLATED SLEEP
MODE INPUT
ULP
-54V
LED
ISOLATED
ULTRA-LOW-POWER
SLEEP
-54V
www.analog.com
-54V
Analog Devices │ 11
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Detailed Description
Operating Modes
Depending on the input voltage (VIN = VDD - VSS), the
MAX5982A/MAX5982B/MAX5982C operate in four different modes: PD detection, PD classification, mark event,
and PD power. The devices enter PD detection mode
when the input voltage is between 1.4V and 10.1V. The
device enters PD classification mode when the input voltage is between 12.6V and 20V. The devices enter PD
power mode once the input voltage exceeds VON.
Detection Mode (1.4V ≤ VIN ≤ 10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on VIN in the 1.4V to 10.1V range
(1V step minimum) and then records the current measurements at the two points. The PSE then computes ΔV/ΔI
to ensure the presence of the 24.9kΩ signature resistor.
Connect the signature resistor (RDET) from VDD to DET for
proper signature detection. The MAX5982A/MAX5982B/
MAX5982C pull DET low in detection mode. DET goes
high impedance when the input voltage exceeds 12.5V.
In detection mode, most of the MAX5982A/MAX5982B/
MAX5982C internal circuitry is off and the offset current
is less than 10μA.
If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal damage to the MAX5982A/MAX5982B/MAX5982C (see the
Typical Application Circuit). Since the PSE uses a slope
technique (ΔV/ΔI) to calculate the signature resistance,
the DC offset due to the protection diodes is subtracted
and does not affect the detection process.
Classification Mode (12.6V ≤ VIN ≤ 20V)
In the classification mode, the PSE classifies the PD based
on the power consumption required by the PD. This allows
the PSE to efficiently manage power distribution. Class 0–5
is defined as shown in Table 1. (The IEEE 802.3af/at standard defines only Class 0–4 and Class 5 for any special
requirement.) An external resistor (RCLS) connected from
CLS to VSS sets the classification current.
The PSE determines the class of a PD by applying a voltage
at the PD input and measuring the current sourced out of
the PSE. When the PSE applies a voltage between 12.6V
and 20V, the MAX5982A/MAX5982B/MAX5982C exhibit
a current characteristic with a value shown in Table 1.
The PSE uses the classification current information to
classify the power requirement of the PD. The classification current includes the current drawn by RCLS and the
supply current of the MAX5982A/MAX5982B/MAX5982C
so the total current drawn by the PD is within the IEEE
802.3af/at standard figures. The classification current is
turned off whenever the device is in power mode.
2-Event Classification and Detection
During 2-Event classification, a Type 2 PSE probes PD
for classification twice. In the first classification event, the
PSE presents an input voltage between 12.6V and 20.5V
and the MAX5982A/MAX5982B/MAX5982C present the
programmed load ICLASS. The PSE then drops the probing voltage below the mark event threshold of 10.1V and
the MAX5982A/MAX5982B/MAX5982C present the mark
current (IMARK). This sequence is repeated one more time.
When the MAX5982A/MAX5982B/MAX5982C are powered by a Type 2 PSE, the 2-Event identification output
2EC asserts low after the internal isolation n-channel
MOSFET is fully turned on. 2EC current sink is turned
off when VDD goes below the UVLO threshold (VOFF)
and turns on when VDD goes above the UVLO threshold
(VON), unless VDD goes below VTHR to reset the latched
output of the Type 2 PSE detection flag.
Table 1. Setting Classification Current
CLASS
MAXIMUM
POWER USED
BY PD
(W)
RCLS
(Ω)
VIN*
(V)
0
0.44 to 12.95
615
12.6 to 20
CLASS CURRENT SEEN AT VIN
(mA)
IEEE 802.3at PD
CLASSIFICATION CURRENT
SPECIFICATION (mA)
MIN
MAX
MIN
MAX
0
4
0
5
1
0.44 to 3.94
117
12.6 to 20
9
12
8
13
2
3.84 to 6.49
66.5
12.6 to 20
17
20
16
21
3
6.49 to 12.95
43.7
12.6 to 20
26
30
25
31
4
12.95 to 25.5
30.9
12.6 to 20
36
44
35
45
5
> 25.5w
21.3
12.6 to 20
54
64
51
68
*VIN is measured across the MAX5982A/MAX5982B/MAX5982C input VDD to VSS.
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Analog Devices │ 12
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Alternatively, the 2EC output also serves as a wall adapter detection output when the MAX5982A/MAX5982B/
MAX5982C are powered by an external wall power adapter. See the Wall Power Adapter Detection and Operation
section for more information.
edge to SL (MAX5982B) or hold SL low for a minimum of
6s (MAX5982A). Apply a falling edge on the wake-mode
enable input (WK) to disable sleep or ultra-low-power
sleep mode and resume normal operation.
Power Mode (Wake Mode)
The MAX5982A/MAX5982B drive an LED connected from
the output LED to VSS. During sleep mode/ultra-low-power sleep mode, the LED is driven by current pulses with
the amplitude set by the resistor connected from SL to
VSS. The LED driver current amplitude is programmable
from 10mA to 20mA using RSL according to the following
formula:
The MAX5982A/MAX5982B/MAX5982C enter power
mode when VIN rises above the undervoltage-lockout threshold (VON). When VIN rises above VON, the
MAX5982A/MAX5982B/MAX5982C turn on the internal
n-channel isolation MOSFET to connect VSS to RTN with
inrush current limit internally set to 53mA when VRTN VSS > 7V and 135mA when VRTN - VSS < 7V. The isolation MOSFET is fully turned on when the voltage at RTN
is near VSS and the inrush current is reduced below the
inrush limit. Once the isolation MOSFET is fully turned
on, the MAX5982A/MAX5982B/MAX5982C change the
current limit to 1900mA (typ). The open-drain power-good
output (PG) remains low for a minimum of tDELAY until
the power MOSFET fully turns on to keep the downstream
DC-DC converter disabled during inrush.
Undervoltage Lockout
The MAX5982A/MAX5982B/MAX5982C operate up to a
60V supply voltage with a turn-on UVLO threshold (VON)
at 35.4V and a turn-off UVLO threshold (VOFF) at 31V.
When the input voltage is above VON, the MAX5982A/
MAX5982B/MAX5982C enter power mode and the internal
MOSFET is turned on. When the input voltage goes below
VOFF for more than tOFF_DLY, the MOSFET turns off.
Sleep and Ultra-Low-Power
Sleep Modes (MAX5982A/MAX5982B)
The MAX5982A/MAX5982B feature a sleep mode, which
pulls PG low while keeping the internal n-channel isolation MOSFET turned on. The PG output is used to disable
downstream DC-DC converters reducing the power consumption of the overall PD system in sleep mode. In sleep
mode, the LED driver output (LED) sources periodic current pulses. The LED current (ILED) is set by an external
resistor (RSL); see the Applications Information section for
more information. To enable sleep mode, apply a falling
edge to SL (MAX5982B) or hold SL low for a minimum of
6 seconds after a falling edge.
An ultra-low-power sleep mode allows the MAX5982A/
MAX5982B to further reduce power consumption while
maintaining the power signature of the standard. The
ultra-low-power sleep enable input ULP is internally held
high with a 50kΩ pullup resistor to the internal 5V bias of
the MAX5982A/MAX5982B. To enable ultra-low-power
sleep sleep mode, set ULP to logic-low and apply a falling
www.analog.com
LED Driver (MAX5982A/MAX5982B)
ILED =
645.75
(in amperes)
RSL + 1200
Power-Good Output
An open-drain output (PG) is used to allow disabling
downstream DC-DC converter until the n-channel isolation MOSFET is fully turned on. PG is pulled low to VSS
for a period of tDELAY and until the internal isolation
MOSFET is fully turned on. The PG is also pulled low
during sleep mode and coming out of thermal shutdown.
Thermal-Shutdown Protection
The MAX5982A/MAX5982B/MAX5982C include thermal
protection from excessive heating. If the junction temperature exceeds the thermal-shutdown threshold of +150°C,
the MAX5982A/MAX5982B/MAX5982C turn off the internal
power MOSFET, LED driver, and 2EC current sink. When
the junction temperature falls below +120°C, the devices
enter inrush mode and then return to power mode. Inrush
mode ensures the downstream DC-DC converter is turned
off as the internal power MOSFET is turned on.
Wall Power Adapter Detection and Operation
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD, the
MAX5982A/MAX5982B/MAX5982C feature wall power
adapter detection. The MAX5982A/MAX5982B/MAX5982C
give highest priority to the WAD and smoothly switch the
power supply to WAD when it is detected. Once the input
voltage (VDD - VSS) exceeds the mark event threshold, the
MAX5982A/MAX5982B/MAX5982C enable wall adapter
detection. The wall power adapter is connected from WAD
to RTN. The MAX5982A/MAX5982B/MAX5982C detect
the wall power adapter when the voltage from WAD to RTN
is greater than 9V. When a wall power adapter is detected,
the internal n-channel isolation MOSFET turns off, 2EC
current sink turns on, and classification current is disabled
if VIN is in the classification range.
Analog Devices │ 13
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Applications Information
2) Use large SMT component pads for power dissipating devices such as the MAX5982A/MAX5982B/
MAX5982C and the external diodes.
Operation with 12V Adapter
Layout Procedure
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimum
performance:
1) Place the input capacitor, classification resistor, and
transient voltage suppressor as close as possible to
the MAX5982A/MAX5982B/MAX5982C.
3) Use short and wide traces for high-power paths.
4) Place enough vias in the pad for the EP of the
MAX5982A/MAX5982B/MAX5982C so that heat
generated inside can be effectively dissipated by the
PCB copper. The recommended spacing for the vias
is 1mm to 1.2mm pitch. The thermal vias should be
plated (1oz copper) and have a small barrel diameter
(0.3mm to 0.33mm).
2-EVENT
CLASSIFICATION
(ASSERTED ON)
GND
VDD
RJ-45
AND
BRIDGE
RECTIFIER
DET
MAX5982A
MAX5982B
MAX5982C
I.5mA
DC-DC
CONVERTER
WAD
IN-
VSS
RTN
THIS CIRCUIT ACHIEVES
PROPER 2EC LOGIC WHEN
BATTERY IS < 12.5V
WALK MODE
INPUT
WK
GND
12V
BATTERY
RCLS
-54V
ENABLE
2EC/WAD
CLS
SMAJ58A
IN+
PG
RDET
24.9kΩ
68nF
2EC
MAX5982A/MAX5982B ONLY
SL
ISOLATED SLEEP
MODE INPUT
60.4kΩ
ULP
1kΩ
-54V
LED
ULTRA-LOW-POWER
SLEEP
-54V
-54V
Figure 2. Typical Configuration When Using a 12V Wall Power Adapter
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Analog Devices │ 14
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Typical Application Circuit
ISOLATED 2-EVENT
CLASSIFICATION
OUTPUT
GND
GND
2EC
VDD
24.9kΩ
VAC
DET
68nF
CLS
SMAJ58A
VAC
2EC/WAD
MAX5982A
MAX5982B
MAX5982C
WAD
1.4mA
24/48V
BATTERY
43.7Ω
VSS
-54V
GND
NT
RIN
RTN
D2
CIN
L2
RTN
RTN
D3
RDCLMP1
PG
RTN
RTN
D1
L1
CBULK
PG
PG
NP
IN
T1
NS
RGATE2
N
EN
N2
5i412DP
RFB2
D4
RDCLMP2
N
DCLMP
CSS
SS
RDT
MAX5974C
MAX5974D
DITHER/
SYNC
IN
N3
NDRV
CCLAMP
RGATE3
N
RGATE4
RRT
RTN
N1
DT
CDITHER
AUXDRV
RT
ROPTO3
ROPTO1
CCOMP1
RCOMP2
U1
P
CCOMP2
N4
CAUX
RBIAS
18V
RFFB
RF
FFB
RTN
CF
RG2
COMP
RTN
CINT
CS
FB
RG1
GND
CSSC
PGND
RCOMP2
RTN
D5
RTN
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RTN
RAUX
RCSSC
RTN
ROPTO2
RFB1
COUT1 COUT2 COUT3 COUT4 COUT5
RGATE1
RTN
RTN
U2
RCS
RTN
Analog Devices │ 15
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Ordering Information
SLEEP/ULTRA-LOWPOWER MODE
6s FILTER DELAY ON SL
16 TQFN-EP*
Yes
Yes
-40°C to +85°C
16 TQFN-EP*
Yes
No
MAX5982CETE+
-40°C to +85°C
16 TQFN-EP*
No
––
MAX5982AATE+
-40°C to +125°C
16 TQFN-EP*
Yes
Yes
PART
TEMP RANGE
PIN-PACKAGE
MAX5982AETE+
-40°C to +85°C
MAX5982BETE+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
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Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
16 TQFN-EP
T1655+4
21-0140
90-0121
Analog Devices │ 16
MAX5982A/MAX5982B/
MAX5982C
IEEE 802.3af/at-Compliant,
Powered Device Interface Controllers with
Integrated 70W High-Power MOSFET
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/11
DESCRIPTION
Initial release
PAGES
CHANGED
—
1
3/19
Updated Electrical Characteristics and Ordering Information table
1–4, 16
2
6/19
Updated Electrical Characteristics and Ordering Information table
1–4, 16
3
7/19
Updated Electrical Characteristics and Ordering Information table
1–4, 16
4
11/21
Updated Ordering Information table
16
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use.Specifications subject to change without notice. No license is granted by implicationor
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property of their respective owners.
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