MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
General Description
The MAX7300 compact, serial-interfaced, I/O expansion
peripheral provides microprocessors with up to 28 ports.
Each port is individually user configurable to either a logic
input or logic output.
Each port can be configured as either a push-pull logic
output capable of sinking 10mA and sourcing 4.5mA, or
a Schmitt logic input with optional internal pullup. Seven
ports feature configurable transition detection logic, which
generates an interrupt upon change of port logic level. The
MAX7300 is controlled through an I2C-compatible 2-wire
serial interface, and uses four-level logic to allow 16 I2C
addresses from only two select pins.
The MAX7300AAX and MAX7300ATL have 28 ports and
are available in 36-pin SSOP and 40-pin TQFN packages,
respectively. The MAX7300AAI and MAX7300ATI have 20
ports and are available in 28-pin SSOP and TQFN packages. For an SPI-interfaced version, refer to the MAX7301
data sheet. For a pin-compatible port expander with additional 24mA constant-current LED drive capability, refer to
the MAX6956 data sheet.
Application
●● White Goods
●● Industrial Controllers
●● System Monitoring
Pin Configurations
●● 400kbps I2C-Compatible Serial Interface
●● 2.5V to 5.5V Operation
●● -40°C to +125°C Temperature Range
●● 20 or 28 I/O Ports, Each Configurable as
Push-Pull Logic Output
Schmitt Logic Input
Schmitt Logic Input with Internal Pullup
●● 11µA (max) Shutdown Current
●● Logic Transition Detection for Seven I/O Ports
Ordering Information
PART
TEMP RANGE
-40°C to +125°C
28 SSOP
MAX7300ATI
-40°C to +125°C
28 TQFN-EP*
MAX7300AAX
-40°C to +125°C
36 SSOP
MAX7300ATL
-40°C to +125°C
40 TQFN-EP*
*EP = Exposed pad.
Devices are also available in a lead(Pb)-free/RoHS-compliant
package. Specify lead-free by adding “+” to the part number
when ordering. Devices are also available in tape-and-reel
packaging. Specify tape and reel by adding “T” to the part
number when ordering.
Typical Operating Circuit
47nF
ISET 1
28 V+
GND 2
27 AD1
GND 3
26 SCL
AD0 4
25 SDA
P12 5
MAX7300
24 P31
P13 6
23 P30
P14 7
22 P29
P15 8
21 P28
P16 9
20 P27
P17 10
19 P26
P18 11
18 P25
P19 12
17 P24
P20 13
16 P23
P21 14
15 P22
28 SSOP
Pin Configurations continued at end of data sheet.
PIN-PACKAGE
MAX7300AAI
P4 32
P5 30
P6 28
P7 26
3V
TOP VIEW
19-2413; Rev 8; 5/14
Features
39kΩ
36 V+
3 GND
2 GND
1
ISET
P8
P9
P10
35
DATA
CLOCK
AD1
4 AD0
33 SDA
34 SCL
31 P31
29 P30
27 P29
25 P28
24 P27
23 P26
22 P25
21 P24
MAX7300AAX
5
7
9
11
P11
P12 6
P13 8
P14 10
P15 12
P16 13
P17 14
P18 15
P19 16
P20 17
P21 18
P22 19
P23 20
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Absolute Maximum Ratings
Voltage (with respect to GND)
V+.............................................................................-0.3V to +6V
SCL, SDA, AD0, AD1...............................................-0.3V to +6V
All Other Pins...............................................-0.3V to (V+ + 0.3V)
P4–P31 Current ...............................................................±30mA
GND Current.....................................................................800mA
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derate 9.1mW/°C above +70°C)...........727mW
28-Pin TQFN (derate 21.3mW/°C above +70°C).......1702mW
36-Pin SSOP (derate 11.8mW/°C above +70°C).........941mW
40-Pin TQFN (derate 26.3mW/°C above TA = +70°C).....2105mW
Operating Temperature Range
TMIN to TMAX)................................................ -40°C to +125°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -65°C to +150°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)
Lead (Pb)-free packages..............................................+260°C
Packages containing lead (Pb).....................................+240°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(Typical Operating Circuit, VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
Operating Supply Voltage
Shutdown Supply Current
Operating Supply Current
Operating Supply Current
Operating Supply Current
SYMBOL
CONDITIONS
V+
ISHDN
IGPOH
IGPOL
IGPI
MIN
TYP
2.5
All digital inputs at
V+ or GND
TA = +25°C
5.5
MAX
UNITS
5.5
V
8
TA = -40°C to +85°C
10
TMIN to TMAX
11
All ports programmed TA = +25°C
as outputs high, no
TA = -40°C to +85°C
load, all other inputs
at V+ or GND
TMIN to TMAX
180
All ports programmed TA = +25°C
as outputs low, no
TA = -40°C to +85°C
load, all other inputs
at V+ or GND
TMIN to TMAX
170
µA
240
260
µA
280
210
230
µA
240
All ports programmed
TA = +25°C
as inputs without
pullup, ports, and all TA = -40°C to +85°C
other inputs at V+ or
TMIN to TMAX
GND
110
135
140
µA
145
INPUTS AND OUTPUTS
Logic High Input Voltage
Port Inputs
VIH
Logic Low Input Voltage
Port Inputs
VIL
Input Leakage Current
IIH, IIL
GPIO Input Internal Pullup to V+
IPU
Hysteresis Voltage GPIO Inputs
DVI
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0.7 x
V+
GPIO inputs without pullup,
VPORT = V+ to GND
V
0.3 x
V+
V
nA
-100
±1
+100
VV+ = 2.5V
12
19
30
VV+ = 5.5V
80
120
180
0.3
µA
V
Maxim Integrated │ 2
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Electrical Characteristics (continued)
(Typical Operating Circuit, VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
Output High Voltage
Port Sink Current
Output Short-Circuit Current
SYMBOL
VOH
IOL
IOLSC
Input High-Voltage SDA, SCL,
AD0, AD1
VIH
Input Low-Voltage SDA, SCL,
AD0, AD1
VIL
Input Leakage Current SDA, SCL
VOL
MIN
GPIO outputs, ISOURCE = 2mA,
TA = -40°C to +85°C
V+ 0.7
GPIO outputs, ISOURCE = 1mA,
TA = TMIN to TMAX (Note 2)
V+ 0.7
VPORT = 0.6V
Port configured output low, shorted to V+
TYP
MAX
UNITS
V
2
10
18
mA
2.75
11
20
mA
0.7 x
V+
IIH, IIL
Input Capacitance
Output Low-Voltage SDA
CONDITIONS
V
-50
0.3 x
V+
V
+50
nA
(Note 2)
10
pF
ISINK = 6mA
0.4
V
MAX
UNITS
400
kHz
Timing Characteristics (Figure 2)
(VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Serial Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD, STA
0.6
µs
Repeated START Condition
Setup Time
tSU, STA
0.6
µs
STOP Condition Setup Time
tSU, STO
0.6
µs
Data Hold Time
tHD, DAT
Data Setup Time
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
µs
SCL Clock High Period
tHIGH
0.7
µs
(Note 3)
15
900
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 2, 4)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 2, 4)
20 +
0.1Cb
300
ns
tF,TX
(Notes 2, 5)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Notes 2, 6)
50
ns
Capacitive Load for Each Bus
Line
Cb
(Note 2)
400
pF
Fall Time of SDA Transmitting
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0
Maxim Integrated │ 3
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Timing Characteristics (Figure 2) (continued)
(VV+ = 2.5V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 5: ISINK ≤ 6mA. Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Typical Operating Characteristics
(RISET = 39kΩ, TA = +25°C, unless otherwise noted.)
ALL PORTS
OUTPUT (0)
ALL PORTS
OUTPUT (1)
0.24
0.20
0.16
0.12
0.08
VV+ = 3.3V
6
5
VV+ = 2.5V
MAX7300 toc03
ALL PORTS OUTPUT (1)
ALL PORTS OUTPUT (0)
4
ALL PORTS INPUT
(PULLUPS DISABLED)
ALL PORTS INPUT HIGH
0.04
0
VV+ = 5.5V
7
1
OPERATING SUPPLY CURRENT vs. V+
(OUTPUTS UNLOADED)
SUPPLY CURRENT ( mA)
0.32
0.28
8
MAX7300 toc02
VV+ = 2.5V TO 5.5V
NO LOAD
SUPPLY CURRENT (A)
SUPPLY CURRENT (mA)
0.36
MAX7300 toc01
0.40
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
OPERATING SUPPLY CURRENT
vs. TEMPERATURE
-40.0
-12.5
15.0
42.5
70.0
TEMPERATURE (°C)
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97.5
125.0
3
-40.0
-12.5
15.0
42.5
70.0
TEMPERATURE (°C)
97.5
125.0
0.1
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V+ (V)
Maxim Integrated │ 4
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Typical Operating Characteristics (continued)
(RISET = 39kΩ, TA = +25°C, unless otherwise noted.)
12
10
8
6
4
-40.0
PULLUP CURRENT (A)
15.0
42.5
70.0
97.5
4
3
-40.0
-12.5
15.0
42.5
70.0
97.5
GPI PULLUP CURRENT
vs. TEMPERATURE
GPO SHORT-CIRCUIT CURRENT
vs. TEMPERATURE
100
VV+ = 3.3V
-12.5
15.0
42.5
70.0
TEMPERATURE (°C)
125.0
GPO = 0, PORT
SHORTED TO V+
10
VV+ = 2.5V
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VV+ = 2.5V
5
TEMPERATURE (°C)
100
-40.0
VV+ = 3.3V
6
TEMPERATURE (°C)
VV+ = 5.5V
10
VV+ = 5.5V
7
2
125.0
MAX7300 toc06
1000
-12.5
PORT CURRENT (mA)
2
MAX7300 toc05
14
VPORT = 1.4V
8
MAX7300 toc07
PORT SINK CURRENT (mA)
16
9
PORT SOURCE CURRENT (mA)
VV+ = 2.5V TO 5.5V, VPORT = 0.6V
MAX7300 toc04
18
GPO SOURCE CURRENT vs. TEMPERATURE
(OUTPUT = 1)
GPO SINK CURRENT vs. TEMPERATURE
(OUTPUT = 0)
GPO = 1, PORT
SHORTED TO GND
97.5
125.0
1
-40.0
-12.5
15.0
42.5
70.0
97.5
125.0
TEMPERATURE (°C)
Maxim Integrated │ 5
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Pin Description
PIN
NAME
28 SSOP
28 TQFN-EP
36 SSOP
40 TQFN-EP
1
26
1
36
ISET
2, 3
27, 28
2, 3
37, 38, 39
GND
4
1
4
5–24
2–21
—
—
—
5–32
—
—
—
25
22
26
FUNCTION
Bias Current Setting. Connect ISET to GND through a resistor
(RISET) value of 39kW to 120kW.
Ground
Address Input 0. Sets device slave address. Connect to either
GND, V+, SCL, SDA to give four logic combinations. See Table 3.
I/O Ports. P12 to P31 can be configured as push-pull outputs,
—
P12–P31
CMOS-logic inputs, or CMOS-logic inputs with weak pullup resistor.
1–10, 12–19,
I/O Ports. P4 to P31 can be configured as push-pull outputs,
P4–P31
CMOS-logic inputs, or CMOS-logic inputs with weak pullup resistor.
21–30
11, 20, 31
N.C.
No Connection. Not internally connected.
40
AD0
33
32
SDA
I2C-Compatible Serial-Data I/O
23
34
33
SCL
I2C-Compatible Serial-Clock Input
27
24
35
34
AD1
28
25
36
35
V+
—
—
—
—
EP
Detailed Description
The MAX7300 general-purpose input/output (GPIO)
peripheral provides up to 28 I/O ports, P4 to P31, controlled through an I2C-compatible serial interface. The
ports can be configured to any combination of logic inputs
and logic outputs, and default to logic inputs on power-up.
Figure 1 is the MAX7300 functional diagram. Any I/O port
can be configured as a push-pull output (sinking 10mA,
sourcing 4.5mA), or a Schmitt-trigger logic input. Each
input has an individually selectable internal pullup resistor. Additionally, transition detection allows seven ports
(P24 to P30) to be monitored in any maskable combination for changes in their logic status. A detected transition is flagged through a status register bit, as well as an
interrupt pin (port P31), if desired.
The port configuration registers individually set the 28
ports, P4 to P31, as GPIO. A pair of bits in registers
0x09 through 0x0F sets each port’s configuration
(Tables 1 and 2).
The 36-pin MAX7300AAX and 40-pin MAX7300ATL have
28 ports, P4 to P31. The 28-pin MAX7300ANI,
MAX7300AAI, and MAX7300ATI have only 20 ports available, P12 to P31. The eight unused ports should be
configured as outputs on power-up by writing 0x55 to
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Address Input 1. Sets device slave address. Connect to either
GND, V+, SCL, SDA to give four logic combinations. See Table 3.
Positive Supply Voltage. Bypass V+ to GND with minimum
0.047µF capacitor.
Exposed Pad (TQFN Only). EP is internally connected to GND.
Connect to a large ground plane to maximize thermal
performance. Not intended as an electrical connection point.
registers 0x09 and 0x0A. If this is not done, the eight
unused ports remain as unconnected inputs and quiescent supply current rises, although there is no damage
to the part.
Register Control of I/O Ports
Across Multiple Drivers
The MAX7300 offers 20 or 28 I/O ports, depending on
package choice. Two addressing methods are available. Any single port (bit) can be written (set/cleared)
at once; or, any sequence of eight ports can be written
(set/cleared) in any combination at once. There are no
boundaries; it is equally acceptable to write P0 to P7, P1
to P8, or P31 to P38 (P32 to P38 are nonexistent, so the
instructions to these bits are ignored).
Shutdown
When the MAX7300 is in shutdown mode, all ports are
forced to inputs, and the pullup current sources are
turned off. Data in the port and control registers remain
unaltered, so port configuration and output levels are
restored when the MAX7300 is taken out of shutdown.
The MAX7300 can still be programmed while in shutdown
mode. For minimum supply current in shutdown mode,
logic inputs should be at GND or V+ potential. Shutdown
mode is exited by setting the S bit in the configuration
register (Table 8).
Maxim Integrated │ 6
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Table 1. Port Configuration Map
ADDRESS
CODE (HEX)
REGISTER
REGISTER DATA
D7
D6
D5
D4
D3
D2
P5
D1
D0
Port Configuration for P7, P6, P5, P4
0x09
P7
P6
P4
Port Configuration for P11, P10, P9, P8
0x0A
P11
P10
P9
P8
Port Configuration for P15, P14, P13, P12
0x0B
P15
P14
P13
P12
Port Configuration for P19, P18, P17, P16
0x0C
P19
P18
P17
P16
Port Configuration for P23, P22, P21, P20
0x0D
P23
P22
P21
P20
Port Configuration for P27, P26, P25, P24
0x0E
P27
P26
P25
P24
Port Configuration for P31, P30, P29, P28
0x0F
P31
P30
P29
P28
Table 2. Port Configuration Matrix
MODE
PORT
REGISTER
(0x20–0x5F)
FUNCTION
PIN BEHAVIOR
DO NOT USE THIS SETTING
Output
GPIO Output
Input
GPIO Input
without Pullup
Input
GPIO Input with Pullup
PORT
CONFIGURATION
BIT PAIR
UPPER
LOWER
0x09 to 0x0F
0
0
0x09 to 0x0F
0
1
Register bit = 0
Active-low logic output
Register bit = 1
Active-high logic output
Register bit =
input logic level
Schmitt logic input
0x09 to 0x0F
1
0
Schmitt logic input with pullup
0x09 to 0x0F
1
1
Serial Interface
Serial Addressing
The MAX7300 operates as a slave that sends and
receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and
from the MAX7300, and generates the SCL clock that
synchronizes the data transfer (Figure 2).
The MAX7300 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on SDA. The MAX7300 SCL line operates
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7300
7-bit slave address plus R/W bit (Figure 6), a register
address byte, one or more data bytes, and finally a
STOP condition (Figure 3).
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ADDRESS
CODE (HEX)
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
Acknowledge
The acknowledge bit is a clocked 9th bit, which the
recipient uses to handshake receipt of each byte of
data (Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is
sta-ble low during the high period of the clock pulse.
When the master is transmitting to the MAX7300, the
MAX7300 generates the acknowledge bit since the
Maxim Integrated │ 7
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
PORT REGISTERS
CONFIGURATION
MASK REGISTER
GPIO
P4 TO P31
CONFIGURATION
REGISTERS
PORT CHANGE
DETECTOR
DATA
R/W
CE
8
GPIO DATA
R/W
8
AD0
COMMAND
REGISTER DECODE
ADDRESS
MATCHER
AD1
7
8
8
DATA BYTE
D0
D1
D2
D3
D4
COMMAND BYTE
D5
D6
7
7-BIT DEVICE ADDRESS
SDA
SCL
D7
D8
D9
D10
TO/FROM DATA REGISTERS
D11
D12
D13
D14
D15
TO COMMAND REGISTERS
R/W
SLAVE ADDRESS BYTE
DATA BYTE
COMMAND BYTE
Figure 1. MAX7300 Functional Diagram
MAX7300 is the recipient. When the MAX7300 is
transmitting to the master, the master generates the
acknowledge bit since the master is the recipient.
Slave Address
The MAX7300 has a 7-bit-long slave address (Figure
6). The eighth bit following the 7-bit slave address is
the RW bit. It is low for a write command and high for a
read command.
The first 3 bits (MSBs) of the MAX7300 slave address
are always 100. Slave address bits A3, A2, A1, and A0
are selected by the address inputs, AD1 and AD0.
These two input pins can be connected to GND, V+,
SDA, or SCL. The MAX7300 has 16 possible slave
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addresses (Table 3), and therefore a maximum of 16
MAX7300 devices can share the same interface.
Message Format for Writing
the MAX7300
A write to the MAX7300 comprises the transmission
of the MAX7300’s slave address with the R/W bit set
to zero, followed by at least 1 byte of information. The
first byte of information is the command byte. The command byte determines which register of the MAX7300
is to be written by the next byte, if received. If a STOP
condition is detected after the command byte is
received, then the MAX7300 takes no further action
(Figure 7) beyond storing the command byte.
Maxim Integrated │ 8
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
SDA
tSU, STA
tSU, DAT
tLOW
tHD, DAT
SCL
tBUF
tHD, STA
tSU, STO
tHIGH
tHD, STA
tR
tF
REPEATED START CONDITION
START CONDITION
STOP CONDITION START CONDITION
Figure 2. 2-Wire Serial Interface Timing Details
SDA
S
P
START
CONDITION
STOP
CONDITION
SCL
Figure 3. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED
Figure 4. Bit Transfer
Any bytes received after the command byte are considered data bytes. The first data byte goes into the internal
register of the MAX7300 selected by the command byte
(Figure 8). If multiple data bytes are transmitted before
a STOP condition is detected, these bytes are generally stored in subsequent MAX7300 internal registers
because the command byte address generally autoincrements (Table 4).
Message Format for Reading
The MAX7300 is read using the MAX7300’s internally
stored command byte as address pointer, the same way
the stored command byte is used as address pointer for
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a write. The pointer generally autoincrements after each
data byte is read using the same rules as for a write
(Table 4). Thus, a read is initiated by first configuring the
MAX7300’s command byte by performing a write (Figure
7). The master can now read ‘n’ consecutive bytes from
the MAX7300, with the first data byte being read from
the register addressed by the initialized command byte
(Figure 9). When performing read-after-write verification,
remember to reset the command byte’s address because
the stored control byte address generally has been autoincremented after the write (Table 4). Table 5 is the register address map.
Maxim Integrated │ 9
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
CLOCK PULSE FOR ACKNOWLEDGMENT
START CONDITION
SCL
1
2
8
9
SDA
BY TRANSMITTER
S
SDA
BY RECEIVER
Figure 5. Acknowledge
SDA
1
0
0
A3
MSB
A2
A1
A0
R/W
ACK
LSB
SCL
Figure 6. Slave Address
Operation with Multiple Masters
If the MAX7300 is operated on a 2-wire interface with
multiple masters, a master reading the MAX7300 should
use a repeated start between the write, which sets the
MAX7300’s address pointer, and the read(s) that takes
the data from the location(s). This is because it is possible for master 2 to take over the bus after master 1
has set up the MAX7300?s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes, the MAX7300’s address pointer, then master 1’s
delayed read can be from an unexpected location.
Command Address Autoincrementing
Address autoincrementing allows the MAX7300 to be
configured with the shortest number of transmissions by
minimizing the number of times the command address
needs to be sent. The command address stored in the
MAX7300 generally increments after each data byte is
written or read (Table 4).
www.maximintegrated.com
Initial Power-Up
On initial power-up, all control registers are reset and the
MAX7300 enters shutdown mode (Table 6).
Transition (Port Data Change) Detection
Port transition detection allows any combination of the
seven ports P24–P30 to be continuously monitored for
changes in their logic status (Figure 10). A detected
change is flagged on the transition detection mask register INT status bit, D7 (Table 10). If port P31 is configured as an output (Tables 1 and 2), then P31 also
automatically becomes an active-high interrupt output
(INT), which follows the condition of the INT status bit.
Port P31 is set as output by writing bit D7 = 0 and bit
D6 = 1 to the port configuration register (Table 1). Note
that the MAX7300 does not identify which specific
port(s) caused the interrupt, but provides an alert that
one or more port levels have changed.
The mask register contains 7 mask bits that select
which of the seven ports P24–P30 are to be monitored
(Table 10). Set the appropriate mask bit to enable that
port for transition detect. Clear the mask bit if transi-
Maxim Integrated │ 10
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
D15 D14 D13 D12 D11 D10 D9
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
ACKNOWLEDGE FROM MAX7300
S
SLAVE ADDRESS
0
R/W
A
D8
A
COMMAND BYTE
P
ACKNOWLEDGE FROM MAX7300
Figure 7. Command Byte Received
ACKNOWLEDGE FROM MAX7300
D15 D14 D13 D12 D11 D10
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
ACKNOWLEDGE FROM MAX7300
S
SLAVE ADDRESS
0
A
COMMAND BYTE
D9
ACKNOWLEDGE FROM MAX7300
D8
D7
A
D6
D5
D4
D3
D2
D1
D0
DATA BYTE
A
P
1 BYTE
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 8. Command and Single Data Byte Received
tions on that port are to be ignored. Transition detection
works regardless of whether the port being monitored is
set to input or output, but generally, it is not particularly
useful to enable transition detection for outputs.
To use transition detection, first set up the mask register
and configure port P31 as an output, as described above.
Then enable transition detection by setting the M bit in
the configuration register (Table 9). Whenever the configuration register is written with the M bit set, the MAX7300
updates an internal 7-bit snapshot register, which holds
the comparison copy of the logic states of ports P24
through P30. The update action occurs regardless of the
previous state of the M bit, so that it is not necessary to
clear the M bit and then set it again to update the snapshot register.
When the configuration register is written with the M bit
set, transition detection is enabled and remains enabled
until either the configuration register is written with the
M bit clear, or a transition is detected. The INT status bit
(transition detection mask register bit D7) goes low. Port
P31 (if enabled as INT output) also goes low, if it was not
already low.
Once transition detection is enabled, the MAX7300
continuously compares the snapshot register against
the changing states of P24 through P31. If a change on
any of the monitored ports is detected, even for a short
time (like a pulse), the INT status bit (transition detection mask register bit D7) is set. Port P31 (if enabled
as INT output) also goes high. The INT output and INT
status bit are not cleared if more changes occur or if the
data pattern returns to its original snapshot condition.
www.maximintegrated.com
The only way to clear INT is to access (read or write) the
transition detection mask register (Table 10). So if the
transition detection mask register is read twice in succession after a transition event, the first time reads with bit
D7 set (identifying the event), and the second time reads
with bit D7 clear.
Transition detection is a one-shot event. When INT has
been cleared after responding to a transition event, transition detection is automatically disabled, even though
the M bit in the configuration register remains set (unless
cleared by the user). Reenable transition detection by
writing the configuration register with the M bit set to take
a new snapshot of the seven ports P24 to P30.
External Component RISET
The MAX7300 uses an external resistor, RISET, to set
internal biasing. Use a resistor value of 39kΩ.
Applications Information
Low-Voltage Operation
The MAX7300 operates down to 2V supply voltage
(although the sourcing and sinking currents are not guaranteed), providing that the MAX7300 is powered up initially to at least 2.5V to trigger the device’s internal reset.
Serial Interface Latency
When a MAX7300 register is written through the I2C
interface, the register is updated on the rising edge of
SCL during the data byte’s acknowledge bit (Figure 5).
The delay from the rising edge of SCL to the internal
register being updated can range from 50ns to 350ns.
Maxim Integrated │ 11
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
ACKNOWLEDGE FROM MAX7300
ACKNOWLEDGE FROM MAX7300
HOW COMMAND BYTE AND DATA BYTE MAP INTO MAX7300’s REGISTER
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX7300
S
SLAVE ADDRESS
0
COMMAND BYTE
A
DATA BYTE
A
A
P
‘n’ BYTES
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 9. ‘n’ Data Bytes Received
Table 3. MAX7300 Address Map
PIN
CONNECTION
DEVICE ADDRESS
AD1
AD0
A6
A5
A4
A3
A2
A1
A0
GND
GND
1
0
0
0
0
0
0
GND
V+
1
0
0
0
0
0
1
GND
SDA
1
0
0
0
0
1
0
GND
SCL
1
0
0
0
0
1
1
V+
GND
1
0
0
0
1
0
0
V+
V+
1
0
0
0
1
0
1
V+
SDA
1
0
0
0
1
1
0
V+
SCL
1
0
0
0
1
1
1
SDA
GND
1
0
0
1
0
0
0
SDA
V+
1
0
0
1
0
0
1
SDA
SDA
1
0
0
1
0
1
0
SDA
SCL
1
0
0
1
0
1
1
SCL
GND
1
0
0
1
1
0
0
SCL
V+
1
0
0
1
1
0
1
SCL
SDA
1
0
0
1
1
1
0
SCL
SCL
1
0
0
1
1
1
1
Table 4. Autoincrement Rules
COMMAND BYTE ADDRESS RANGE
x0000000 to x1111110
x1111111
PC Board Layout Considerations
AUTOINCREMENT BEHAVIOR
Command address autoincrements after byte read or written
Command address remains at x1111111 after byte written or read
Ensure that all the MAX7300 GND connections are used.
For TQFN versions, connect the underside exposed pad
to GND. A ground plane is not necessary, but may be
useful to reduce supply impedance if the MAX7300 outputs are to be heavily loaded. Keep the track length from
the ISET pin to the RISET resistor as short as possible,
and take the GND end of the register either to the ground
plane or directly to the GND pins.
www.maximintegrated.com
Power-Supply Considerations
The MAX7300 operates with power-supply voltages of
2.5V to 5.5V. Bypass the power supply to GND with a
0.047µF capacitor as close to the device as possible.
Add a 1µF capacitor if the MAX7300 is far away from the
board’s input bulk decoupling capacitor.
Maxim Integrated │ 12
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Table 5. Register Address Map
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
No-Op
X
0
0
0
0
0
0
0
0x00
Configuration
X
0
0
0
0
1
0
0
0x04
Transition Detect Mask
X
0
0
0
0
1
1
0
0x06
Factory Reserved; do not write to this port
X
0
0
0
0
1
1
1
0x07
Port Configuration P7, P6, P5, P4
X
0
0
0
1
0
0
1
0x09
Port Configuration P11, P10, P9, P8
X
0
0
0
1
0
1
0
0x0A
Port Configuration P15, P14, P13, P12
X
0
0
0
1
0
1
1
0x0B
Port Configuration P19, P18, P17, P16
X
0
0
0
1
1
0
0
0x0C
Port Configuration P23, P22, P21, P20
X
0
0
0
1
1
0
1
0x0D
Port Configuration P27, P26, P25, P24
X
0
0
0
1
1
1
0
0x0E
Port Configuration P31, P30, P29, P28
X
0
0
0
1
1
1
1
0x0F
Port 0 only (virtual port, no action)
X
0
1
0
0
0
0
0
0x20
Port 1 only (virtual port, no action)
X
0
1
0
0
0
0
1
0x21
Port 2 only (virtual port, no action)
X
0
1
0
0
0
1
0
0x22
Port 3 only (virtual port, no action)
X
0
1
0
0
0
1
1
0x23
Port 4 only (data bit D0. D7-D1 read as 0)
X
0
1
0
0
1
0
0
0x24
Port 5 only (data bit D0. D7-D1 read as 0)
X
0
1
0
0
1
0
1
0x25
Port 6 only (data bit D0. D7-D1 read as 0)
X
0
1
0
0
1
1
0
0x26
Port 7 only (data bit D0. D7-D1 read as 0)
X
0
1
0
0
1
1
1
0x27
Port 8 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0
0
0
0x28
Port 9 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0
0
1
0x29
Port 10 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0
1
0
0x2A
Port 11 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
0
1
1
0x2B
Port 12 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
1
0
0
0x2C
Port 13 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
1
0
1
0x2D
Port 14 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
1
1
0
0x2E
Port 15 only (data bit D0. D7-D1 read as 0)
X
0
1
0
1
1
1
1
0x2F
Port 16 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
0
0
0
0x30
Port 17 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
0
0
1
0x31
Port 18 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
0
1
0
0x32
Port 19 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
0
1
1
0x33
Port 20 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
1
0
0
0x34
Port 21 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
1
0
1
0x35
Port 22 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
1
1
0
0x36
Port 23 only (data bit D0. D7-D1 read as 0)
X
0
1
1
0
1
1
1
0x37
Port 24 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
0
0
0
0x38
Port 25 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
0
0
1
0x39
REGISTER
www.maximintegrated.com
Maxim Integrated │ 13
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Table 5. Register Address Map (continued)
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Port 26 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
0
1
0
0x3A
Port 27 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
0
1
1
0x3B
Port 28 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
1
0
0
0x3C
Port 29 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
1
0
1
0x3D
Port 30 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
1
1
0
0x3E
Port 31 only (data bit D0. D7-D1 read as 0)
X
0
1
1
1
1
1
1
0x3F
4 ports 4–7 (data bits D0–D3. D4–D7 read as 0)
X
1
0
0
0
0
0
0
0x40
5 ports 4–8 (data bits D0–D4. D5–D7 read as 0)
X
1
0
0
0
0
0
1
0x41
6 ports 4–9 (data bits D0–D5. D6–D7 read as 0)
X
1
0
0
0
0
1
0
0x42
7 ports 4–10 (data bits D0–D6. D7 reads as 0)
X
1
0
0
0
0
1
1
0x43
8 ports 4–11 (data bits D0–D7)
X
1
0
0
0
1
0
0
0x44
8 ports 5–12 (data bits D0–D7)
X
1
0
0
0
1
0
1
0x45
8 ports 6–13 (data bits D0–D7)
X
1
0
0
0
1
1
0
0x46
8 ports 7–14 (data bits D0–D7)
X
1
0
0
0
1
1
1
0x47
8 ports 8–15 (data bits D0–D7)
X
1
0
0
1
0
0
0
0x48
8 ports 9–16 (data bits D0–D7)
X
1
0
0
1
0
0
1
0x49
8 ports 10–17 (data bits D0–D7)
X
1
0
0
1
0
1
0
0x4A
8 ports 11–18 (data bits D0–D7)
X
1
0
0
1
0
1
1
0x4B
8 ports 12–19 (data bits D0–D7)
X
1
0
0
1
1
0
0
0x4C
8 ports 13–20 (data bits D0–D7)
X
1
0
0
1
1
0
1
0x4D
8 ports 14–21 (data bits D0–D7)
X
1
0
0
1
1
1
0
0x4E
8 ports 15–22 (data bits D0–D7)
X
1
0
0
1
1
1
1
0x4F
8 ports 16–23 (data bits D0–D7)
X
1
0
1
0
0
0
0
0x50
8 ports 17–24 (data bits D0–D7)
X
1
0
1
0
0
0
1
0x51
8 ports 18–25 (data bits D0–D7)
X
1
0
1
0
0
1
0
0x52
8 ports 19–26 (data bits D0–D7)
X
1
0
1
0
0
1
1
0x53
8 ports 20–27 (data bits D0–D7)
X
1
0
1
0
1
0
0
0x54
8 ports 21–28 (data bits D0–D7)
X
1
0
1
0
1
0
1
0x55
8 ports 22–29 (data bits D0–D7)
X
1
0
1
0
1
1
0
0x56
8 ports 23–30 (data bits D0–D7)
X
1
0
1
0
1
1
1
0x57
8 ports 24–31 (data bits D0–D7)
X
1
0
1
1
0
0
0
0x58
7 ports 25–31 (data bits D0–D6. D7 reads as 0)
X
1
0
1
1
0
0
1
0x59
6 ports 26–31 (data bits D0–D5. D6–D7 read as 0)
X
1
0
1
1
0
1
0
0x5A
5 ports 27–31 (data bits D0–D4. D5–D7 read as 0)
X
1
0
1
1
0
1
1
0x5B
4 ports 28–31 (data bits D0–D3. D4–D7 read as 0)
X
1
0
1
1
1
0
0
0x5C
3 ports 29–31 (data bits D0–D2. D3–D7 read as 0)
X
1
0
1
1
1
0
1
0x5D
2 ports 30–31 (data bits D0–D1. D2–D7 read as 0)
X
1
0
1
1
1
1
0
0x5E
1 port 31 only (data bits D0. D1–D7 read as 0)
X
1
0
1
1
1
1
1
0x5F
REGISTER
Note: Unused bits read as zero.
www.maximintegrated.com
Maxim Integrated │ 14
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Table 6. Power-Up Configuration
REGISTER
FUNCTION
POWER-UP CONDITION
Port Register
Bits 4 to 31
GPIO Output Low
Configuration
Register
ADDRESS
CODE
(HEX)
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
0x24 to
0x3F
X
X
X
X
X
X
X
0
Shutdown Enabled
Transition Detection Disabled
0x04
0
0
X
X
X
X
X
0
All Clear (Masked Off)
0x06
X
0
0
0
0
0
0
0
Port
Configuration
P7, P6, P5, P4: GPIO Inputs without Pullup
0x09
1
0
1
0
1
0
1
0
Port
Configuration
P11, P10, P9, P8: GPIO Inputs without Pullup
0x0A
1
0
1
0
1
0
1
0
Port
Configuration
P15, P14, P13, P12: GPIO Inputs without Pullup
0x0B
1
0
1
0
1
0
1
0
Port
Configuration
P19, P18, P17, P16: GPIO Inputs without Pullup
0x0C
1
0
1
0
1
0
1
0
Port
Configuration
P23, P22, P21, P20: GPIO Inputs without Pullup
0x0D
1
0
1
0
1
0
1
0
Port
Configuration
P27, P26, P25, P24: GPIO Inputs without Pullup
0x0E
1
0
1
0
1
0
1
0
Port
Configuration
P31, P30, P29, P28: GPIO Inputs without Pullup
0x0F
1
0
1
0
1
0
1
0
Input Mask
Register
X = unused bits; if read, zero results.
www.maximintegrated.com
Maxim Integrated │ 15
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Table 7. Configuration Register Format
REGISTER DATA
FUNCTION
ADDRESS CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Configuration Register
0x04
M
0
X
X
X
X
X
S
Table 8. Shutdown Control (S Data Bit D0) Format
REGISTER DATA
FUNCTION
ADDRESS CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Shutdown
0x04
M
0
X
X
X
X
X
0
Normal Operation
0x04
M
0
X
X
X
X
X
1
Table 9. Transition Detection Control (M Data Bit D7) Format
REGISTER DATA
FUNCTION
ADDRESS CODE
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
Disabled
0x04
0
0
X
X
X
X
X
S
Enabled
0x04
1
0
X
X
X
X
X
S
Table 10. Transition Detection Mask Register
FUNCTION
REGISTER
ADDRESS
(HEX)
Mask
Register
0x06
REGISTER DATA
READ/
WRITE
D7
D6
D5
D4
D3
D2
D1
D0
Read
INT Status*
Write
Unchanged
Port
30
mask
Port
29
mask
Port
28
mask
Port
27
mask
Port
26
mask
Port
25
mask
Port
24
mask
*INT is automatically cleared after it is read.
www.maximintegrated.com
Maxim Integrated │ 16
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
GPIO INPUT
CONDITIONING
GPIO IN
GPIO/PORT
OUTPUT LATCH
GPIO/PORT OUT
INT STATUS STORED AS MSB OF MASK REGISTER
P31
INT
OUTPUT LATCH
CLOCK PULSE AFTER EACH READ ACCESS TO MASK REGISTER
R
S
CONFIGURATION REGISTER M BIT = 1
GPIO INPUT
CONDITIONING
P30
GPIO IN
D
Q
GPIO/PORT OUT
MASK REGISTER BIT 6
GPIO/PORT OUTPUT LATCH
P29
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P28
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P27
GPIO/PORT OUTPUT LATCH
GPIO INPUT
CONDITIONING
P26
GPIO/PORT OUTPUT LATCH
P25
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
P24
GPIO INPUT
CONDITIONING
GPIO/PORT OUTPUT LATCH
GPIO IN
D
Q
GPIO/PORT OUT
GPIO IN
MASK REGISTER BIT 5
D
Q
GPIO/PORT OUT
GPIO IN
MASK REGISTER BIT 4
D
Q
GPIO IN
D
Q
GPIO/PORT OUT
GPIO IN
MASK REGISTER BIT 2
D
Q
GPIO/PORT OUT
GPIO IN
GPIO/PORT OUT
OR
MASK REGISTER BIT 3
GPIO/PORT OUT
MASK REGISTER BIT 1
D
Q
MASK REGISTER LSB
CLOCK PULSE WHEN WRITING CONFIGURATION REGISTER WITH M BIT SET
Figure 10. Maskable GPIO Ports P24 to P31
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Maxim Integrated │ 17
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Pin Configurations (continued)
36 SSOP
P27
P26
22
21
23
24
25
26
27
28
P4
P31
P5
P30
P6
P29
P7
P28
9
10
P17
8
7
P11
P15
P16
P25
15
SDA
22
14
SCL
23
13
P23
AD1
24
12
P22
V+
25
11
P21
MAX7300
P24
ISET 26
10
P20
GND
27
9
P19
GND
28
8
P18
7
19 P22
P17
20 P23
P21 18
P26
21 P24
P20 17
16
P19 16
N.C.
TOP VIEW
6
22 P25
P16
23 P26
P27
P17 14
P18 15
P23
P22
P21
P20
P19
P18
40 TQFN-EP
17
24 P27
5
25 P28
P16 13
P15
26 P7
P15 12
6
P11 11
P28
27 P29
P24
12
11
18
P14 10
AD0
4
28 P6
P14
9
5
P10
GND
GND
4
29 P30
3
8
P29
P13
P30
30 P5
19
7
20
6
P9
3
31 P31
P12
MAX7300
2
MAX7300
33
34
35
36
37
38
39
40
P13
32 P4
N.C.
P25
20
19
18
17
16
15
14
13
P12
33 SDA
5
2
4
P8
31
32
1
AD0
N.C.
SDA
SCL
AD1
V+
ISET
GND
P8
P12
P9
P13
P10
P14
34 SCL
P31
3
21
35 AD1
GND
1
2
29
36 V+
GND
ADO
ISET 1
30
TOP VIEW
28 TQFN-EP
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Maxim Integrated │ 18
MAX7300
Chip Information
PROCESS: CMOS
www.maximintegrated.com
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 SSOP
A28+1
21-0056
90-0095
28 TQFN-EP
T2855+6
21-0140
90-0026
36 SSOP
A36+4
21-0040
90-0098
40 TQFN-EP
T4066+5
21-0141
90-0055
Maxim Integrated │ 19
MAX7300
2-Wire-Interfaced, 2.5V to 5.5V,
20-Port or 28-Port I/O Expander
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
7
9/11
Updated Ordering Information, Absolute Maximum Ratings, Pin Description, Table 1,
and Package Information sections
1, 2, 6, 7, 19
8
5/14
No /V OPNs; removed automotive reference from Applications section
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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