19-0147; Rev. 4; 11/05
Microprocessor and Nonvolatile
Memory Supervisory Circuits
Features
The MAX792/MAX820 microprocessor (µP) supervisory
circuits provide the most functions for power-supply
and watchdog monitoring in systems without battery
backup. Built-in features include the following:
• µP reset: Assertion of RESET and RESET outputs during
power-up, power-down, and brownout conditions.
RESET is guaranteed valid for VCC down to 1V.
• Manual-reset input.
• Two-stage power-fail warning: A separate low-line
comparator compares V CC to a preset threshold
120mV above the reset threshold; the low-line and
reset thresholds can be programmed externally.
• Watchdog fault output: Assertion of WDO if the watchdog
input is not toggled within a preset timeout
period.
• Pulsed watchdog output: Advance warning of
impending WDO assertion from watchdog timeout that
causes hardware shutdown.
• Write protection of CMOS RAM, EEPROM, or other
memory devices.
The MAX792 and MAX820 are identical, except the
MAX820 guarantees higher low-line and reset threshold
accuracy (±2%).
♦ Manual-Reset Input
♦ 200ms Power-OK / Reset Time Delay
♦ Independent Watchdog Timer—Preset or Adjustable
♦
♦
♦
♦
♦
On-Board Gating of Chip-Enable Signals
Memory Write-Cycle Completion
10ns (max) Chip-Enable Gate Propagation Delay
Voltage Monitor for Overvoltage Warning
±2% Reset and Low-Line Threshold Accuracy
(MAX820, external programming mode)
Ordering Information
PART**
TEMP. RANGE
PIN-PACKAGE
MAX792_CPE
0°C to +70°C
16 Plastic DIP
MAX792_CSE
MAX792_C/D
0°C to +70°C
0°C to +70°C
16 Narrow SO
Dice*
Ordering Information continued at end of data sheet.
* Dice are tested at TA = +25°C, DC parameters only.
**These parts offer a choice of five different reset threshold voltages.
Select the letter corresponding to the desired nominal reset threshold
voltage and insert it into the blank to complete the part number.
Devices in PDIP, SO and µMAX packages are available in both leaded and lead-free packaging. Specify lead free by adding the + symbol at the end of the part number when ordering. Lead free not available for CERDIP package.
Applications
Computers
Controllers
Intelligent Instruments
Critical µP Power Monitoring
SUFFIX
RESET THRESHOLD (V)
L
M
T
S
R
4.62
4.37
3.06
2.91
2.61
Typical Operating Circuit
VCC
0.1µF
3
VCC
4
CE OUT
VCC
13
RESET IN/INT
µP
MAX792
5
RAM
CE IN
LLIN/
REFOUT
OVO
LOW LINE
7
8
RESET
OVI
MR
SWT
GND
14
ADDRESS
DECODER
A0-A15
6
10
1
NMI
RESET
9
GND
12
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
MAX792/MAX820
General Description
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
Input Voltage (with respect to GND)
VCC .......................................................................-0.3V to +6V
All Other Inputs.......................................-0.3V to (VCC + 0.3V)
Input Current
GND ................................................................................25mA
All Other Outputs ............................................................25mA
Continuous Power Dissipation (TA = +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Narrow SO (derate 9.52mW/°C above +70°C) ............762mW
CERDIP (derate 10.00mW/°C above +70°C) ...............800mW
Operating Temperature Ranges:
MAX792_C_ _/MAX820_C_ _ ...............................0°C to +70°C
MAX792_E_ _/MAX820_E_ _.............................-40°C to +85°C
MAX792_MJE_ _/MAX820_MJE_ _ .................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.75V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
Operating Voltage Range
(Note 1)
MIN
TYP
MAX
2.75
UNITS
V
Supply Current
70
150
µA
RESET COMPARATOR
Reset Threshold Voltage—
Internal Threshold Mode
(VTH)
Reset Threshold Voltage
External Threshold Mode (VTH)
RESET IN/INT Mode Threshold
(Note 2)
MAX792L, MAX820L
4.50
4.62
4.75
MAX792M, MAX820M
4.25
4.37
4.50
MAX792R, MAX820R
2.55
2.61
2.70
MAX792S, MAX820S
2.85
2.91
3.00
MAX792T, MAX820T
3.00
3.06
3.15
MAX820L, TA = +25°C, VCC falling
4.55
4.70
MAX820M, TA = +25°C, VCC falling
MAX820R, TA = +25°C, VCC falling
MAX820S, TA = +25°C, VCC falling
MAX820T, TA = +25°C, VCC falling
MAX792, VCC = 5V or VCC = 3V
MAX820, VCC = 5V or VCC = 3V
4.30
2.55
2.85
3.00
1.25
1.274
4.45
2.66
2.96
3.11
1.35
1.326
1.30
1.30
Internal threshold mode
mV
±25
nA
0.016 x VTH
70
200
280
0.01
0.3
0.1
0.4
V
µs
ms
±0.01
RESET Output Voltage
RESET Output Voltage
2
VCC falling
VCC rising
ISINK = 50µA, VCC = 1V, VCC falling
ISINK = 1.6mA
ISOURCE = 1mA
ISOURCE = 100µA
ISINK = 1.6mA
ISOURCE = 1mA
ISOURCE = 100µA
140
V
60
RESET IN/INT Leakage Current
Reset Threshold Hysteresis
Reset Comparator Delay
Reset Active Timeout Period
V
VCC - 1
VCC - 0.5
0.1
V
0.4
VCC - 1
VCC - 0.5
_______________________________________________________________________________________
V
Microprocessor and Nonvolatile
Memory Supervisory Circuits
MAX792/MAX820
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.75V to 5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOW-LINE COMPARATOR
Low-Line Threshold Voltage
(Internal Threshold Mode)—VTH
MAX792/MAX820L/M
50
120
210
MAX792/MAX820R/S/T
40
100
210
Low-Line Threshold Voltage
(External Programming Mode)
MAX792, VCC = 5V OR VCC = 3V
1.25
1.30
1.35
MAX820, VCC = 5V OR VCC = 3V
1.274
1.30
1.326
Low-Line Hysteresis
(Internal Threshold Mode)
20
LLIN/REFOUT Leakage Current
External Programming Mode
Low-Line Comparator Delay
±0.01
VCC falling
LOWLINE Voltage
ISOURCE = 1µA
LOWLINE Short-Circuit Current
±25
nA
µs
0.4
VCC - 1
Output source current, VCC = 5.5V
V
mV
450
ISINK = 3.2mA
mV
V
10
50
µA
1.60
1.60
2.25
2.25
sec
WATCHDOG FUNCTION
SWT connected to VCC, VCC = 5V
SWT connected to VCC, VCC = 3V
Watchdog Timeout Period
Watchdog Input Pulse Width
WDO Output Voltage
1.00
1.00
4.7nF capacitor connected from SWT to GND,
VCC = 3V
70
4.7nF capacitor connected from SWT to GND,
VCC = 5V
100
VCC = 5V
VCC = 3V
ISINK = 50µA, VCC = 1V, VCC falling
ISINK = 1.6mA
ISOURCE = 1mA
ISOURCE = 100µA
VIL = 0V, VIH = VCC
ms
100
300
0.01
0.1
70
WDPO Duration
0.5
WDI Threshold Voltage
WDI Input Current
0.30
0.4
VCC - 1
VCC - 0.5
WDPO to WDO Delay
WDPO Output Voltage
ns
ISINK = 50µA, VCC = 1V, VCC falling
ISINK = 1.6mA
ISOURCE = 1mA
ISOURCE = 100µA
VIH
VCC = 4.25V
VIL
VIH
VCC = 2.55V
VIL
V
ns
1.7
6.0
0.01
0.1
0.3
0.4
VCC - 1
VCC - 0.5
0.75 x VCC
0.8
0.9 x VCC
0.2
±1
ms
V
V
µA
_______________________________________________________________________________________
3
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.75V to +5.5V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.30
1.35
V
±0.01
±25
nA
OVERVOLTAGE COMPARATOR
OVI Input Threshold
VCC = 5V or VCC = 3V
1.25
OVI Leakage Current
OVO Output Voltage
OVO Short-Circuit Current
OVI to OVO Delay
ISINK = 3.2mA
0.4
ISOURCE = 1µA
VCC - 1
Output source current, VCC = 5.5V
10
VOD = 100mV, OVI rising
13
VOD = 100mV, OVI falling
55
50
V
µA
µs
CHIP-ENABLE GATING
VCC = 4.25V
CE IN Threshold Voltage
VCC = 2.55V
CE IN Leakage Current
VIH
VIL
VIH
VIL
0.75 x VCC
0.8
0.75 x VCC
0.2
Disabled mode
CE IN to CE OUT Resistance
Enabled mode
CE OUT Short-Circuit Current
Disabled mode, CEOUT = 0V
Chip-Enable Propagation Delay
(Note 3)
50Ω source impedance driver,
CLOAD = 50pF
Chip-Enable Output Voltage
High (Reset Active)
IOUT = -100µA
IOUT = 10µA
Reset Active to CE OUT High
VCC falling
±0.005
±1
75
150
0.2
150
300
2.5
0.4
VCC = 5V
6
10
VCC = 3V
8
13
VCC = 5V
VCC = 3V
VCC = 5V
VCC = 3V
V
0.5
0.05
VCC - 1
VCC - 0.5
µA
Ω
mA
ns
V
15
µs
MANUAL RESET
MR Minimum Pulse Width
25
MR to RESET Propagation Delay
12
MR Threshold Range
MR Pull-Up Current
µs
MR = 0V
µs
1.1
1.3
1.5
VCC = 4.25V
to VCC = 5.5V
5
23
80
VCC = 2.5V
1
V
µA
Note 1: The minimum operating voltage is 2.75V; however, the MAX792R and MAX820R are guaranteed to operate down to their
preset reset thresholds.
Note 2: Pulling RESET IN/INT below 60mV selects internal threshold mode and connects the internal voltage divider to the reset
and low-line comparators. External programming mode allows an external resistor divider to set the low-line and reset
thresholds (see Figure 4).
Note 3: The Chip-Enable Propagation delay is measured from the 50% point at CE IN to the 50% point at CE OUT.
4
_______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
OVERVOLTAGE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
50
VCC = 3V
40
30
20
50
40
VIH TO VOL
VIN = 20mV
OVERDRIVE = 15mV
VCC = 2V
10
-60
-30
0
30
60
90
120
150
-60
-30
0
30
70
60
50
VCC FALLING
15mV OVERDRIVE
EXTERNAL PROGRAMMING MODE
40
30
0
60
90
120
150
-60
-30
0
30
60
90
120
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
LOW-LINE COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
POWER-UP RESET DELAY
vs. TEMPERATURE
NOMINAL WATCHDOG TIMEOUT
PERIOD vs. VCC
250
500
VCC = 5V
DELAY (ms)
200
400
300
VCC = 3V
200
100
VCC FALLING
15mV OVERDRIVE
EXTERNAL PROGRAMMING MODE
100
-60
-30
150
0
30
60
90
TEMPERATURE (°C)
120
50
0
150
150
3.0
MAX792-5
300
MAX792-3a
600
PROPAGATION DELAY (µs)
60
PROPAGATION DELAY (µs)
60
VCC = 4V
80
NOMINAL WATCHDOG TIMEOUT PERIOD (s)
70
MAX792-4
SUPPLY CURRENT (µA)
80
70
MAX792-2
SWT = VCC
ALL OUTPUTS
UNLOADED
VCC = 5V
MAX792-1
90
PROPAGATION DELAY (µs)
100
RESET COMPARATOR
PROPAGATION DELAY vs. TEMPERATURE
MAX792-3
SUPPLY CURRENT vs. TEMPERATURE
2.5
2.0
1.5
1.0
-60
-30
0
30
60
90
TEMPERATURE (°C)
120
150
2
4
3
5
VCC (V)
_________________________________________________________________________________________________
5
MAX792/MAX820
__________________________________________Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
INTERNAL-MODE RESET THRESHOLD
vs. TEMPERATURE (NORMALIZED)
REF OUT VOLTAGE
vs. TEMPERATURE
ON-RESISTANCE (Ω)
1.31
REF OUT (V)
1.000
0.975
1.30
1.29
1.28
1.27
THE RESET THRESHOLD IS SHOWN
NORMALIZED TO 1, REPRESENTING
ALL AVAILABLE MAX792/MAX820
0.925
0.900
-30
0
30
60
90
1.26
RESET IN / INT = 0V
120
150
-30
0
30
60
90
120
60
VCC = 5V
VCE IN = 2.5V
20
-60
-30
TEMPERATURE (°C)
0
30
60
20
PROPAGATION DELAY (ns)
10k
VCC = 5V
VCC = 3V
100
10
VCC = +5V
VCE IN = 0V TO 5V
DRIVER SOURCE
IMPEDANCE = 50Ω
15
10
5
0
1n
10n
100n
CSWT (F)
1m
90
TEMPERATURE (°C)
CHIP-ENABLE PROPAGATION DELAY
vs. CE OUT LOAD CAPACITANCE
MAX792-10
100k
WATCHDOG TIMEOUT PERIOD (ms)
80
150
WATCHDOG TIMEOUT PERIOD
vs. SWT LOAD CAPACITANCE
6
100
0
-60
TEMPERATURE (°C)
1k
120
40
1.25
-60
VCC = 3V
VCE IN = 1.5V
140
MAX792-11
0.950
180
160
1.050
1.025
MAX792-8
1.32
1.075
200
MAX792-7
1.100
CHIP-ENABLE ON-RESISTANCE
vs. TEMPERATURE
1.33
MAX792-6
1.125
RESET THRESHOLD
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
0
25 50 75 100 125 150 175 200 225 250
CLOAD (pF)
_______________________________________________________________________________________
120
150
Microprocessor and Nonvolatile
Memory Supervisory Circuits
PIN
NAME
FUNCTION
1
RESET
Active-Low Reset Output goes low whenever VCC falls below the reset threshold in internal threshold programming mode, or RESET IN falls below 1.30V in external threshold programming mode.
RESET remains low for 200ms typ after the threshold is exceeded on power-up.
2
RESET
Reset is the inverse of RESET.
3
VCC
4
RESET IN/INT
Reset-Input/Internal-Mode Select. Connect this input to GND to select internal threshold mode.
Select external programming mode by pulling this input 600mV or higher through an external voltage divider.
5
LLIN/REF OUT
Low-Line Input/Reference Output connects directly to the low-line comparator in external programming mode (RESET IN/INT ≥ 600mV). Connects directly to the internal 1.30V reference in internal
threshold mode (RESET IN/INT ≤ 60mV).
6
OVO
Overvoltage Comparator Output goes low when OVI is greater than 1.30V. This is an uncommitted
comparator and has no effect on any other internal circuitry.
7
OVI
Inverting Input to the Overvoltage Comparator. When OVI is greater than 1.30V, OVO goes low.
Connect OVI to GND or VCC when not used.
8
SWT
Set Watchdog-Timeout Input. Connect this input to VCC to select the default 1.6sec watchdog
timeout period. Connect a capacitor between this input and GND to select another watchdogtimeout period. Watchdog timeout period = k x (capacitor value in nF)mV, where k = 27 for
VCC = 5V and k = 16.2 for VCC = 3V. If the watchdog function is unused, connect SWT to VCC.
9
MR
Manual-Reset Input. This input can be tied to an external momentary pushbutton switch, or to a
logic gate output. Internally pulled up to VCC.
10
LOW LINE
Low-Line Output. LOW LINE goes low 120mV above the reset threshold in internal threshold mode,
or when LLIN/REFOUT goes below 1.30V in external programming mode.
11
WDI
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout period,
WDPO pulses low and WDO goes low. WDO remains low until the next transition at WDI. Connect to
GND or VCC if unused.
12
GND
Ground
13
CE OUT
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted. If CE IN is
low when reset is asserted, CE OUT will stay low for 15µs or until CE IN goes high, whichever
occurs first.
14
CE IN
Chip-Enable Input—the input to the chip-enable transmission gate. Connect to GND or VCC if not
used.
15
WDO
Watchdog Output. WDO goes low if WDI remains either high or low longer than the watchdog timeout period. WDO returns high on the next transition at WDI.
16
WDPO
Input Supply Voltage
Watchdog-Pulse Output. Upon the absence of a transition at WDI, WDPO will pulse low for a minimum of 500µs. WDPO precedes WDO by typically 70ns.
_______________________________________________________________________________________
7
MAX792/MAX820
______________________________________________________________Pin Description
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
Detailed Description
Manual-Reset Input
Many µP-based products require manual-reset capability, allowing the operator to initiate a reset. The manual/external-reset input (MR) can connect directly to a
switch without an external pull-up resistor or debouncing network. MR internally connects to a 1.30V comparator, and has a high-impedance pull-up to VCC, as
shown in Figure 1. The propagation delay from asserting MR to reset asserted is typically 12µs. Pulsing MR
low for a minimum of 25µs asserts the reset function
(see Reset Function section). The reset output remains
active as long as MR is held low, and the reset timeout
period begins after MR returns high (Figure 2). To provide extra noise immunity in high-noise environments,
pull MR up to VCC with a 100kΩ resistor.
Use MR as either a digital logic input or as a second lowline comparator. Normal TTL/CMOS levels can be
wire-OR connected via pull-down diodes (Figure 3),
and open-drain/collector outputs can be wire-ORed
directly.
Monitoring the Regulated Supply
The MAX792/MAX820 offer two modes for monitoring
the regulated supply and providing reset and nonmaskable interrupt (NMI) signals to the µP: internal
threshold mode uses the factory preset low-line and
reset thresholds, and external programming mode
allows the low-line and reset thresholds to be programmed externally using a resistor voltage divider
(Figure 4).
Internal Threshold Mode
Connecting the reset-input/internal-mode select pin
(RESET IN/INT) to ground selects internal threshold
mode (Figure 4a). In this mode, the low-line and reset
thresholds are factory preset by an internal voltage
divider (Figure 1) to the threshold voltages specified in
the Electrical Characteristics (Reset Threshold Voltage
and Low-Line Threshold Voltage). Connect the low-line
output (LOWLINE) to the µP NMI pin, and connect the
active-high reset output (RESET) or active-low reset
output (RESET) to the µP reset input pin.
Additionally, the low-line input/reference-output pin
(LLIN/REFOUT) connects to the internal 1.30V reference in internal threshold mode. Buffer LLIN/REFOUT
with a high-impedance buffer to use it with external
circuitry. In this mode, when VCC is falling, LOWLINE is
guaranteed to be asserted prior to reset assertion.
8
External Programming Mode
Connecting RESET IN/INT to a voltage above 600mV
selects external programming mode. In this mode, the
low-line and reset comparators disconnect from the internal voltage divider and connect to LLIN/REFOUT and
RESET IN/INT, respectively (Figure 1). This mode allows
flexibility in determining where in the operating voltage
range the NMI and reset are generated. Set the low-line
and reset thresholds with an external resistor divider, as in
Figure 4b or Figure 4c. RESET typically remains valid for
VCC down to 2.5V; RESET is guaranteed to be valid with
VCC down to 1V.
Calculate the values for the resistor voltage divider in
Figure 4b using the following equations:
1) R3 = (1.30 x VCC MAX)/(VLOW LINE x IMAX)
2) R2 = [(1.30 x VCC MAX)/(VRESET x IMAX)] - R3
3) R1 = (VCC MAX/IMAX) - (R2 + R3).
First choose the desired maximum current through the
voltage divider (IMAX) when VCC is at its highest (VCC
MAX). There are two things to consider here. First, IMAX
contributes to the overall supply current for the circuit, so
you would generally make it as small as possible.
Second, IMAX cannot be too small or leakage currents will
adversely affect the programmed threshold voltages; 5µA
is often appropriate. Determine R3 after you have chosen
IMAX. Use the value for R3 to determine R2, then use both
R2 and R3 to determine R1.
For example, to program a 4.75V low-line threshold and a
4.4V reset threshold, first choose IMAX to be 5µA when
VCC = 5.5V and substitute into equation 1.
R3 = (1.30 x 5.5)/(4.75 x 5E-6) = 301.05kΩ.
301kΩ is the nearest standard 0.1% value. Substitute
into equation 2:
R2 = [(1.30 x 5.5)/(4.4 x 5E-6)] - 301kΩ = 23.95kΩ.
The nearest 0.1% resistor value is 23.7kΩ. Finally, substitute into equation 3:
R1 = (5.5/5E-6) - (23.7kΩ + 301kΩ) = 775kΩ.
The nearest 0.1% value resistor is 787kΩ. Determine the
actual low-line threshold by rearranging equation 1 and
plugging in the standard resistor values. The actual lowline threshold is 4.75V and the actual reset threshold is
4.40V. An additional resistor allows the MAX792/MAX820
to monitor the unregulated supply and provide an NMI
before the regulated supply begins to fall (Figure 4c).
Both of these thresholds will vary from circuit to circuit
with resistor tolerance, reference variation, and comparator offset variation. The initial thresholds for each circuit
will also vary with temperature due to reference and offset drift. For highest accuracy, use the MAX820.
_______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
3
2
VCC
RESET IN/
INT
*
4
MAX792/MAX820
VCC
RESET
RESET
COMPARATOR
RESET
GENERATOR
1
RESET
VCC
LLIN/
REFOUT
MR
5
10
VCC
VCC
LOW-LINE
COMPARATOR
CHIP-ENABLE
OUTPUT
CONTROL
VCC
9
LOW LINE
P
MANUAL
RESET
COMPARATOR
1.30V
VCC
INTERNAL/
EXTERNAL
MODE
CONTROL
60mV
INTERNAL
EXTERNAL
CE IN
P
13
14
TIMEBASE FOR
RESET AND
WATCHDOG
N
16
SWT
WDI
8
WATCHDOG
TIMER
11
WATCHDOG
TRANSITION
DETECTOR
VCC
OVERVOLTAGE
COMPARATOR
OVI
CE OUT
15
WDPO
WDO
MAX792
MAX820
6
OVO
7
12
GND
* SWITCHES ARE SHOWN IN INTERNAL
THRESHOLD MODE POSITION
Figure 1. MAX792/MAX820 Block Diagram
_______________________________________________________________________________________
9
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
VIN
25µs MIN
MR
3
VCC
12µs TYP
RESET
4 RESET IN/INT
RESET
2
TO µP
RESET
1
TO µP
10
TO µP NMI
CE IN OV
5
CE OUT
15µs TYP
MAX792
LLIN/REFOUT
LOW LINE
Figure 2. Manual-Reset Timing Diagram
GND
12
MANUAL RESET
9
MR
Figure 4a. Connection for Internal Threshold Mode
*
OTHER
RESET
SOURCES
*
.
.
.
VIN
MAX792
MAX820
3
R1
RESET IN/INT
* DIODES NOT REQUIRED ON OPEN-DRAIN OUTPUTS
Figure 3. Diode "OR" connections allow multiple reset sources
to connect to MR.
Low-Line Output
In internal threshold mode, the low-line comparator
monitors VCC with a threshold voltage typically 120mV
above the reset threshold, and with 15mV of hysteresis.
For normal operation (VCC above the reset threshold),
LOWLINE is pulled to VCC. Use LOWLINE to provide an NMI
to the µP, as described in the previous section, when
VCC begins to fall (Figure 4).
Reset Function
The MAX792/MAX820 provide both RESET and RESET
outputs. The RESET and RESET outputs ensure that the
µP powers up in a known state, and prevent code-execution errors during power-up, power-down, or
brownout conditions.
The reset function will be asserted during the following
conditions:
1) VCC less than the programmed reset threshold.
2) MR less than 1.30V typ.
3) Reset remains asserted for 200ms typ after VCC
rises above the reset threshold or after MR has
exceeded 1.30V typ.
10
VCC
R2
RESET
2
TO µP
1
TO µP
10
TO µP NMI
MAX792
LLIN/REFOUT
RESET
R3
LOW LINE
GND
12
R3 = 1.30V x VCC MAX
VLOW LINE x IMAX
R2 = 1.30V x VCC MAX – R3
VRESET x IMAX
IMAX = THE MAXIMUM DESIRED CURRENT
THROUGH THE VOLTAGE DIVIDED.
R1 = VCC MAX
– (R2 + R3)
IMAX
Figure 4b. Connection for External Threshold Programming Mode
When reset is asserted, all the internal counters are
reset, the watchdog output (WDO) and watchdog-pulse
output (WDPO) are set high, and the set watchdog-timeout input (SWT) is set to (VCC - 0.6V) if it is not already
connected to V CC (for internal timeouts). The chipenable transmission gate is also disabled while reset is
asserted; the chip-enable input (CE IN) becomes high
impedance and the chip-enable output (CE OUT) is
pulled up to VCC.
______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
RESET
TO µP RESET
10k
MAX792
MAX820
VCC
R3
1
RESET IN/INT
RESET 2
TO µP
RESET 1
TO µP
R1
MAX792
MAX820
R4
LLIN/REFOUT
Figure 5. Adding an external pull-down resistor ensures RESET
is valid with VCC down to GND.
R2
LOW LINE 10
VLOW LINE = 1.3
( R1R2+ R2 )
VRESET = 1.3 R3 + R4
( R4 )
TO µP NMI
GND
VOLTAGE REGULATOR
3
VCC
Figure 4c. Alternative Connection for External Programming Mode
MAX792
MAX820
Reset Outputs (RESET and RESET)
The RESET output is active low and typically sinks 1.6mA
at 0.1V. When deasserted, RESET sources 1.6mA at typically VCC - 1.5V. The RESET output is the inverse of
RESET. RESET is guaranteed to be valid down to VCC = 1V,
and an external 10kΩ pull-down resistor on RESET
ensures that it will be valid with V CC down to GND
(Figure 5). As VCC goes below 1V, the gate drive to the
RESET output switch reduces accordingly, increasing the
rDS(ON) and the saturation voltage. The 10kΩ pull-down
resistor ensures that the parallel combination of switch
plus resistor will be around 10kΩ and the saturation
voltage will be below 0.4V while sinking 40µA. When
using an external pull-down resistor of 10kΩ, the high
state for the RESET output with VCC = 4.75V is typically
4.60V.
Overvoltage Comparator
The overvoltage comparator is an uncommitted comparator that has no effect on the operation of other chip
functions. Use this input to provide overvoltage indication by connecting a voltage divider from the input supply, as in Figure 6.
Connect OVI to ground if the overvoltage function is not
used. OVO goes low when OVI goes above 1.30V. With
OVI below 1.30V, OVO is actively pulled to VCC and can
source1µA.
7 OVI
OVO 6
OVERVOLTAGE
1.30V
GND
12
Figure 6. Detecting an Overvoltage Condition
Watchdog Function
The watchdog monitors µP activity via the watchdog
input (WDI). If the µP becomes inactive, WDO and WDPO
are asserted. To use the watchdog function, connect
WDI to a µP bus line or I/O line. If WDI remains high or
low for longer than the watchdog timeout period (1.6s
nominal), WDPO and WDO are asserted, indicating a software fault condition (see Watchdog-Pulse Output and
Watchdog Output sections).
Watchdog Input
If the watchdog function is unused, connect WDI to VCC
or GND. A change of state (high-to-low, low-to-high, or
a minimum 100ns pulse) at WDI during the watchdog
period resets the watchdog timer. The watchdog timer
______________________________________________________________________________________
11
MAX792/MAX820
REGULATOR
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
1.6s
MIN 100ns (VCC = 5V)
MIN 300ns (VCC = 3V)
VCC
3
VCC
WDI
0.1µF
VCC
WDPO
µP POWER
MAX792
MAX820
70ns
RESET
WDO
WDI
WDPO
VCC = 5V
9
Figure 7. WDI, WDO, and WDPO Timing Diagram
GND
12
+5V
default is 1.6s. Select alternative timeout periods by
connecting an external capacitor from SWT to GND
(see Selecting an Alternative Watchdog Timeout section). When VCC is below the reset threshold, the watchdog function is disabled.
Watchdog Output
WDO remains high if there is a transition or pulse at WDI
during the watchdog timeout period. The watchdog
function is disabled and WDO is a logic high when VCC
is below the reset threshold. If a system reset is desired
on every watchdog fault, simply diode-OR connect WDO
to MR (Figure 8). When a watchdog fault occurs in this
mode, WDO goes low, pulling MR low and causing a
reset pulse to be issued. As soon as reset is asserted,
the watchdog timer clears and WDO goes high. With
WDO connected to MR, a continuous high or low on WDI
will cause 200ms reset pulses to be issued every
1.6sec (SWT connected to V CC). When reset is not
asserted, if no transition occurs at WDI during the
watchdog timeout period, WDO goes low 70ns after the
falling edge of WDPO and remains low until the next transition at WDI (Figure 7). A single additional flip-flop can
force the system into a hardware shutdown if there are
two successive watchdog faults (Figure 8). When the
MAX792/MAX820 are operated from a 5V supply, WDO
has a 2 x TTL output characteristic.
Watchdog-Pulse Output
As described in the preceding section, WDPO can be
used as the clock input to an external D flip-flop. Upon
the absence of a watchdog edge or pulse at WDI at the
end of a watchdog timeout period, WDPO will pulse low
for 1.7ms. The falling edge of WDPO precedes WDO by
70ns. Since WDO is high when WDPO goes low, the flipflop’s Q output remains high after WDO goes low (Figure
8). If the watchdog timer is not reset by a transition at
12
WDO
MR
1
RESET
11
I/O
16
15
D
V
CLOCK CC Q
CLEAR
*
0.1µF
Q
TWO
CONSECUTIVE
WATCHDOG
FAULT
INDICATION
REACTIVATE
4.7k
* FOR SYSTEM RESET ON EVERY
WATCHDOG FAULT, OMIT THE
FLIP-FLOP, AND DIODE–OR
CONNECT WDO TO MR.
Figure 8. Two consecutive watchdog faults latch the system in
reset.
WDI, WDO remains low and the next WDPO following a
second watchdog timeout period clocks a logic low to
the Q output, pulling MR low and causing the
MAX792/MAX820 latch in reset. If the watchdog timer is
reset by a transition at WDI, WDO will go high and the
flip-flop’s Q output will remain high. Thus a system
shutdown is only caused by two successive watchdog
faults.
Selecting an Alternative Watchdog Timeout Period
The SWT input controls the watchdog timeout period.
Connecting SWT to V CC selects the internal 1.6sec
watchdog timeout period. Select an alternative watchdog timeout period by connecting a capacitor between
SWT and GND. Do not leave SWT floating and do not
connect it to ground. The following formula determines
the watchdog timeout period:
Watchdog Timeout Period =
k x (capacitor value in nF)ms
where k = 27 for VCC = 3V, and k = 16.2 for VCC = 5V.
This applies for capacitor values in excess of 4.7nF. If
the watchdog function is unused, connect SWT to VCC.
______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
MAX792/MAX820
Chip-Enable Signal Gating
The MAX792/MAX820 provide internal gating of chipenable (CE) signals, which prevents erroneous data
from corrupting CMOS RAM in the event of an undervoltage condition. The MAX792/MAX820 use a series
transmission gate from CE IN to CE OUT (Figure 1).
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the
CMOS RAM. The 10ns max CE propagation delay from
CE IN to CE OUT enables the MAX792/MAX820 to be
used with most µPs. If CE IN is low when reset asserts,
CE OUT remains low for a short period to permit completion of the current write cycle.
Chip-Enable Input
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when VCC passes the
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the voltage at CE IN is high. If CE IN is low when reset is asserted, the CE transmission gate will disable at the moment
CE IN goes high or 15µs after reset is asserted,
whichever occurs first (Figure 9). This permits the current write cycle to complete during power-down.
During a power-up sequence, the CE transmission gate
remains disabled and CE IN remains high impedance
regardless of CE IN activity, until reset is deasserted following the reset timeout period.
While disabled, CE IN is high impedance. When the CE
transmission gate is enabled, the impedance of CE IN
will appear as a 75Ω (VCC = 5V) resistor in series with
the load at CE OUT.
The propagation delay through the CE transmission
gate depends on VCC, the source impedance of the
drive connected to CE IN, and the loading on CE OUT
(see the Chip-Enable Propagation Delay vs. CE OUT
Load Capacitance graph in the Typical Operating
Characteristics). The CE propagation delay is production tested from the 50% point on CE IN to the 50%
point on CE OUT using a 50Ω driver and 50pF of load
capacitance (Figure 10). For minimum propagation
delay, minimize the capacitive load at CE OUT, and use
a low-output-impedance driver.
VCC
RESET
THRESHOLD
CE IN
CE OUT
15µs
70µs
70µs
RESET
RESET
Figure 9. Reset and Chip-Enable Timing
+5V
3
VCC
14
MAX792
MAX820
CE IN
CE OUT
13
CLOAD
50Ω DRIVER
GND
12
Figure 10. CE Propagation Delay Test Circuit
Chip-Enable Output
When the CE transmission gate is enabled, the impedance of CE OUT is equivalent to 75Ω in series with the
source driving CE IN. In the disabled mode, the 75Ω
transmission gate is off and an active pull-up connects
from CE OUT to VCC. This source turns off when the
transmission gate is enabled.
Applications Information
Connect a 0.1µF ceramic capacitor from VCC to GND,
as close to the device pins as possible. This reduces
the probability of resets due to high-frequency powersupply transients. In a high-noise environment, additional bypass capacitance from VCC to ground may be
required. If long leads connect to the chip inputs,
ensure that these lines are free from ringing, etc., which
would forward bias the chip’s protection diodes.
______________________________________________________________________________________
13
+5V
RP*
CE
3
VCC
RAM 1
CE IN
TO OTHER
SYSTEM RESET
INPUTS
VCC
MAX792
MAX820
14
BUFFER
CE
CE OUT
CE
13
3
VCC
RAM 2
VCC
CE
RESET
1
4.7k
µP
RESET
CE
GND
12
RAM 3
MAX792
MAX820
CE
CE
RAM 4
ACTIVE-HIGH CE
LINES FROM LOGIC
Figure 11. Alternate CE Gating
Alternative Chip-Enable Gating
Using memory devices with both CE and CE inputs
allows the MAX792/MAX820 CE propagation delay
to be bypassed. To do this, connect CE IN to ground,
pull up CE OUT to VCC, and connect CE OUT to the CE
input of each memory device (Figure 11). The CE input
of each memory device then connects directly to the
chip-select logic, which does not have to be gated by
the MAX792/MAX820.
Interfacing to µPs with Bidirectional
Reset Inputs
µPs with bidirectional reset pins, such as the Motorola
68HC11 series, can contend with the MAX792/MAX820
RESET output. If, for example, the MAX792/MAX820 RESET
output is asserted high and the µP wants to pull it low,
indeterminate logic levels may result. To avoid this,
connect a 4.7kΩ resistor between the MAX792/MAX820
RESET output and the µP reset I/O, as in Figure 12.
Buffer the MAX792/MAX820 RESET output to other system components.
Negative-Going VCC Transients
While issuing resets to the µP during power-up, powerdown, and brownout conditions, these supervisors are
relatively immune to short-duration negative-going VCC
transients (glitches). It is usually undesirable to reset
the µP when VCC experiences only small glitches.
Figure 13 shows maximum transient duration vs. resetcomparator overdrive, for which reset pulses are not
generated. The graph was produced using negative14
GND
GND
12
CE
Figure 12. Interfacing to µPs with Bidirectional RESET Pins
going VCC pulses, starting at 5V and ending below the
reset threshold by the magnitude indicated (resetcomparator overdrive). The graph shows the maximum
pulse width a negative-going VCC transient may typically have without causing a reset pulse to be issued.
As the amplitude of the transient increases (i.e., goes
farther below the reset threshold), the maximum allowable pulse width decreases. Typically, a VCC transient
that goes 100mV below the reset threshold and lasts for
30µs or less will not cause a reset pulse to be issued.
A 100nF bypass capacitor mounted close to the VCC
pin provides additional transient immunity.
100
MAX791 -13
* MAXIMUM RP VALUE DEPENDS ON
THE NUMBER OF RAMS.
MINIMUM RP VALUE IS 1kΩ
MAXIMUM TRANSIENT DURATION (µs)
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
VCC = 5V
TA = +25°C
80
60
40
20
0
10
100
1000
10,000
RESET COMPARATOR OVERDRIVE, (VTH - VCC) (mV)
Figure 13. Maximum Transient Duration Without Causing a
Reset Pulse vs. Reset-Comparator Overdrive
______________________________________________________________________________________
Microprocessor and Nonvolatile
Memory Supervisory Circuits
PART**
TEMP. RANGE
PIN-PACKAGE
MAX792_EPE
MAX792_ESE
MAX792_EJE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 Plastic DIP
16 Narrow SO
16 CERDIP
MAX792_MJE
-55°C to +125°C
16 CERDIP
MAX820_CPE
-0°C to +70°C
-0°C to +70°C
-40°C to +85°C
16 Plastic DIP
16 Narrow SO
16 Plastic DIP
MAX820_CSE
MAX820_EPE
MAX820_ESE
-40°C to +85°C
TOP VIEW
RESET 1
16 WDPO
RESET 2
15 WDO
VCC 3
13
CE OUT
LLIN/REFOUT 5
12
GND
OVO 6
11
WDI
10
LOW LINE
9
16 Narrow SO
MAX820_EJE
-40°C to +85°C
16 CERDIP
OVI 7
MAX820_MJE
-55°C to +125°C
16 CERDIP
SWT 8
* Dice are tested at TA = +25°C, DC parameters only.
**These parts offer a choice of five different reset threshold voltages. Select the letter corresponding to the desired nominal
reset threshold voltage and insert it into the blank to complete
the part number.
Devices in PDIP, SO and µMAX packages are available in both
leaded and lead-free packaging. Specify lead free by adding
the + symbol at the end of the part number when ordering. Lead
free not available for CERDIP package.
RESET THRESHOLD (V)
L
M
T
S
R
4.62
4.37
3.06
2.91
2.61
MR
DIP/SO
___________________Chip Topography
RESET
RESET
SUFFIX
14 CE IN
MAX792
MAX820
RESET IN/INT 4
WDO
WDPO
CE IN
CE OUT
V CC
RESET IN/
INT
GND
LLIN/
REF OUT
0.078"
(1.981mm)
OVO
WDI
OVI
SWT MR LOW LINE
0.070"
(1.778mm)
TRANSISTOR COUNT: 950
SUBSTRATE CONNECTED TO VCC
______________________________________________________________________________________
15
MAX792/MAX820
Pin Configuration
_Ordering Information (continued)
INCHES
N
DIM
A
A1
B
C
e
E
H
L
H
E
MAX
MIN
0.093
0.104
0.004
0.012
0.014
0.019
0.013
0.009
0.050
0.299
0.291
0.394
0.419
0.016
0.050
SOICW.EPS
________________________________________________________Package Information
MILLIMETERS
MIN
2.35
0.10
0.35
0.23
MAX
2.65
0.30
0.49
0.32
1.27
7.40
7.60
10.00
10.65
0.40
1.27
VARIATIONS:
1
INCHES
TOP VIEW
DIM
D
D
D
D
D
D
A
B
e
MIN
0.398
0.447
0.496
0.598
0.697
MAX
0.413
0.463
0.512
0.614
0.713
MILLIMETERS
MIN
10.10
11.35
12.60
15.20
17.70
MAX
10.50
11.75
13.00
15.60
18.10
N MS013
16
AA
18
AB
20 AC
24 AD
28 AE
C
0∞-8∞
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .300" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
21-0042
DIM
A
A1
B
C
e
E
H
L
N
E
H
INCHES
MILLIMETERS
MAX
MIN
0.069
0.053
0.010
0.004
0.014
0.019
0.007
0.010
0.050 BSC
0.150
0.157
0.228
0.244
0.016
0.050
MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
1.27 BSC
3.80
4.00
5.80
6.20
0.40
1
B
1
SOICN .EPS
MAX792/MAX820
Microprocessor and Nonvolatile
Memory Supervisory Circuits
1.27
VARIATIONS:
1
INCHES
TOP VIEW
DIM
D
D
D
MIN
0.189
0.337
0.386
MAX
0.197
0.344
0.394
MILLIMETERS
MIN
4.80
8.55
9.80
MAX
5.00
8.75
10.00
N MS012
8
AA
14
AB
16
AC
D
A
B
e
C
0∞-8∞
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
21-0041
REV.
B
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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