19-1116; Rev 1; 11/96
Microprocessor-Compatible,
14-Bit DACs
____________________________Features
The MX7534/MX7535 are high-performance, CMOS,
monolithic, 14-bit digital-to-analog converters (DACs).
Wafer-level, laser-trimmed, thin-film resistors and temperature-compensated NMOS switches assure operation over
the full operating temperature range with exceptional linear and gain stability.
♦ 14-Bit Monotonic Over Full Temperature Range
The MX7534 accepts right-justified data in two bytes from
an 8-bit bus, while the MX7535 operates with a 14-bit data
bus with separate MS-byte and LS-byte select controls. In
addition, all digital inputs are compatible with both TTL and
5V CMOS-logic levels. The MX7534/MX7535 are intended
for unipolar operation, but may be operated as bipolar
DACs with additional external components. Both devices
are protected against CMOS latchup, and neither requires
the use of external Schottky protection diodes.
♦ Low Power Consumption
The MX7534 is available in 20-pin narrow (0.3") DIP, wide
SO, or PLCC packages. The MX7535 is available in
28-pin, 600 mil wide DIP, wide SO, or PLCC packages.
________________________Applications
Machine and Motion Control Systems
Automatic Test Equipment
Digital Audio
µP-Controlled Calibration Circuitry
Programmable-Gain Amplifiers
Digitally Controlled Filters
Programmable Power Supplies
_________________Pin Configurations
♦ Full 4-Quadrant Multiplication
♦ µP-Compatible, Double-Buffered Inputs
♦ Exceptionally Low Gain Tempco (2.5ppm/°C)
♦ Low Output Leakage (300ppm/°C) resistors.
Bipolar Operation
(4-Quadrant Multiplication)
Bipolar or 4-quadrant operation is shown in Figures 5a
and 5b. This configuration provides for offset binary
coding. Table 4 shows DAC codes and the corresponding analog outputs for Figures 5a and 5b. With
the DAC loaded to 10 0000 0000 0000, either adjust R1
for VOUT = 0V, or omit R1 and R2 and adjust the ratio of
R5 and R6 for VOUT = 0V. Adjust the amplitude of VIN
or vary the value of R7 for full-scale trimming.
Resistors R5, R6, and R7 must be matched to 0.003%.
Mismatch of R5 and R6 causes both offset and fullscale errors. For wide temperature range operation,
use resistors of the same material so that their temperature coefficients match and track.
AGNDF
Figure 3. Equivalent Analog Output Circuit
Table 1. MX7534 Logic States
A1
A2
FUNCTION
WR CS
X
1
X
X
Device not selected (Note 1)
1
X
X
X
No data transfer
0
0
0
0
DAC loaded directly from
Data Bus (Note 2)
0
0
0
1
MS Input Register loaded
from Data Bus
0
0
1
0
LS Input Register loaded
from Data Bus
0
0
1
1
DAC Register loaded from
Input Registers
Note 1: X = Don’t Care.
Note 2: When A1 = 0 and A0 = 0, all DAC registers are transparent. By placing all 0s or all 1s on the data inputs, the
user can load the DAC to zero or full-scale output in
one write operation. This simplifies system calibration.
_______________________________________________________________________________________
7
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
R1
100Ω
VIN
A0
A1
CS
WR
1
REF
16
R1
20Ω
VDD
19
2
RFB
R2
33Ω
VIN
C1
33pF
LDAC
3
15
IOUT
18
MX7534
17
D7–D0 DGND
7–14
6
4
AGNDS
AGNDF
VSS
CSMSB
A1
WR
VO
5
2
1 26
REFF REFS VDD
4
MX7535
24
8–21
Grounding Considerations
Since IOUT and the output amplifier noninverting input
are sensitive to offset voltages, connect nodes that
must be grounded directly to a single-point ground
through a separate, very-low-resistance path. Note that
the output currents at IOUT and AGNDF vary with input
code and create code-dependent error if these terminals are connected to ground (or a virtual ground)
through a resistive path.
To obtain high accuracy, it is important to use a proper
grounding technique. The two AGND pins (AGNDF‚
AGNDS) provide flexibility in this respect. In Figures 4a
and 4b, AGNDS and AGNDF are shorted together
externally and an extra op amp, A2, is not used.
Voltage-drops due to bond-wire resistance are not
compensated for in this circuit; this could create a linearity error of approximately 0.1LSB due to bond-wire
resistance alone. This can be eliminated by using the
circuits shown in Figures 6a and 6b, where A2 maintains AGNDS at signal ground potential. By using
force/sense techniques, all switch contacts on the DAC
are kept at exactly the same potential, and any error
caused by bond-wire resistance is eliminated.
Figure 7 shows a remote voltage reference driving the
MX7535. Op amps A2 and A3 compensate for voltage
drops along the reference input line and analog
ground line.
Figure 8 shows a printed circuit board (PCB) layout with
a single output amplifier for the MX7534. The input to
REF (Pin 1) is shielded to reduce AC feedthrough, while
the digital inputs are shielded to minimize digital
C1
33pF
IOUT
25
ANALOG
GROUND
Figure 4a. Unipolar Binary Operation
3
RFB
22
D13–DO DGND
20
INPUT
DATA
8
CSLSB
23
R2
10Ω
AGNDF
VSS
7
A1
5
AGNDS
VO
6
27
ANALOG
GROUND
INPUT
DATA
Figure 4b. Unipolar Binary Operation
Table 2. Unipolar Binary Code Table
BINARY NUMBER IN
DAC REGISTER
ANALOG OUTPUT
(VOUT)
MSB
11
1111
1111
LSB
1111
10
0000
0000
0000
00
0000
0000
0001
00
0000
0000
0000
(
(
(
)
)
)
-VIN 16383
16384
1
-VIN 8192 = - VIN
16384
2
1
-VIN
16384
0V
feedthrough. The traces connecting IOUT and AGNDS
to the inverting and noninverting op amp inputs are
kept as short as possible. Gain trim components, R3
and R4, are omitted.
Zero-Offset Adjustment
(Figures 6a and 6b)
1) Load DAC register with all 0s.
2) Adjust offset of amplifier A2 for minimum potential at
AGNDS. This potential should be ≤30µV with respect
to signal ground.
3) Adjust A1’s offset so that V OUT is at a minimum
(i.e., ≤30µV).
_______________________________________________________________________________________
Microprocessor-Compatible,
14-Bit DACs
MX7534/MX7535
VIN
VIN
A0
A1
CS
WR
16
R2, 33Ω
VDD
R1
100Ω
1
19
REF
2
RFB
R5 10k
IOUT
18
MX7534
7–14
6
+
AGNDS
AGNDF
D7–D0 DGND VSS
5
R7
20k
LDAC
3
15
17
C1
33pF
R1
20Ω
R6
20k
CSMSB
A1
R8, 5k,10%
4
+
WR
A2
VO
CSLSB
20
ANALOG
GROUND
INPUT
DATA
23
R2 10Ω
VDD
1
26 3
2
REFF REFS
RFB
24
IOUT
MX7535
+
AGNDS
AGNDF
D13–D0 DGND VSS
6
7
27
8–21
A1
A2
R8, 5k,10%
5
+
VO
ANALOG
GROUND
INPUT
DATA
Figure 5a. Bipolar Operation
R7
20k
R5
10k
4
22
25
R6
20k
C1
33pF
Figure 5b. Bipolar Operation
Gain Adjustment
(Figures 6a and 6b)
1) Load DAC register with all 1s.
2) Trim potentiometer R3 so that VOUT = - 16383 VIN
16384
(
)
Table 3. MX7535 Logic States
FUNCTION
CSMSB CSLSB LDAC WR
0
1
1
0
1
0
1
0
Load LS Input Register
Low-Leakage Configuration
Leakage current in the DAC flowing into the IOUT line
can cause gain, linearity, and offset errors. Leakage is
worse at high temperatures.
Negatively bias VSS for a high-temperature, low-leakage
configuration.
Load MS Input Register
0
0
1
0
Load LS and MS Input
Registers
1
1
0
X
Load DAC Register
from Input Register
0
0
0
0
All registers are
transparent.
Dynamic Considerations
1
1
1
X
No operation
In static or DC applications, the output amplifier’s AC
characteristics are not critical. In higher-speed applications, where either the reference input is an AC signal
or the DAC output must quickly settle to a new programmed value, the output op amp’s AC parameters
must be considered.
Another error source in dynamic applications is the parasitic signal coupling from the REF terminal to IOUT.
This is normally a function of board layout and lead-tolead package capacitance. Signals can also be injected into the DAC outputs when the digital inputs are
switched. This digital feedthrough depends on circuitboard layout and on-chip capacitive coupling. Minimize
layout-induced feedthrough with guard traces between
digital inputs, REF, and DAC outputs.
X
X
1
1
No operation
Note:
X = Don’t Care.
Table 4. Offset Binary Bipolar Code Table
BINARY NUMBER IN
DAC REGISTER
Analog Output
(VOUT)
MSB
11
1111
1111
LSB
1111
10
0000
0000
0001
10
0000
0000
0000
0
01
1111
1111
1111
-VIN
00
0000
0000
0000
-VIN
(
(
)
)
+VIN 8191
8192
1
+VIN
8192
1
(8192
)
8192 = -V
(8192)
IN
_______________________________________________________________________________________
9
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
VDD
VDD
R3
100Ω
R4
33Ω
1
19 2
REF VDD RFB
C1
33pF
3
MX7534
D7–D0 DGND VSS
6
20
7–14
2
1 26 3
REFF REFS VDD RFB
4
VOLTAGE
REFERENCE
RL VO
4
5
C1
33pF
IOUT
AGNDS
AGNDF
R2
10Ω
A1
+
IOUT
VIN
R1
20Ω
MX7535
+
INPUT
DATA
A1
AGNDS
AGNDF
D13–D0 DGND VSS
6
7
27
8–21
A2
+
RL VO
5
A2
+
SIGNAL
GROUND
INPUT
DATA
SIGNAL
GROUND
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
Figure 6a. Unipolar Binary Operation with Forced Ground
ANALOG
GROUND
Figure 6b. Unipolar Binary Operation with Forced Ground for
Remote Load
Table 5. Amplifier Performance Comparisons
OP AMP
INPUT OFFSET
VOLTAGE (VOS)
INPUT BIAS
CURRENT (IB)
OFFSET VOLTAGE
DRIFT (TC VOS)
SETTLING
TO 0.003% FS
MAX400
10µV
2nA
0.3µV/°C
50µs
Maxim OP07
25µV
2nA
0.6µV/°C
50µs
AD554L*
500µV
25pA
5µV/°C
5µs
HA2620*
4mV
35nA
20µV/°C
0.8µs
* AD544L is an Analog Devices part; HA2620 is a Harris Semiconductor part.
Compensation
A compensation capacitor, C1, may be needed when
the DAC is used with a high-speed output amplifier.
The capacitor cancels the pole formed by the DAC’s
output capacitance and internal feedback resistance.
Its value depends on the type of op amp used, but typical values range from 10pF to 33pF. Too small a value
causes output ringing, while excess capacitance overdamps the output. Minimize C1’s size and improve output settling performance by keeping the PC board
trace as short as possible and stray capacitance at
IOUT as small as possible.
Bypassing
Place a 1µF bypass capacitor, in parallel with a 0.01µF
ceramic capacitor, as close to the DAC’s VDD and GND
pins as possible. Use a 1µF tantalum bypass capacitor
to optimize high-frequency noise rejection. Place a
4.7µF decoupling capacitor at VSS to minimize the DAC
output leakage current.
10
The MX7534/MX7535 have high-impedance digital
inputs. To minimize noise pickup, connect them to
either VDD or GND terminals when not in use. Connect
active inputs to VDD or GND through high-value resistors (1MΩ) to prevent static charge accumulation if
these pins are left floating, as might be the case when
a circuit card is left unconnected.
Op-Amp Selection
Input offset voltage (VOS), input bias current (IB), and
offset voltage drift (TC VOS) are three key parameters in
determining the choice of a suitable amplifier. To maintain specified accuracy with VREF of 10V, VOS should
be less than 30µV and IB should be less than 2nA.
Open-loop gain should be greater than 340,000.
Maxim’s MAX400 has low V OS (10µV max), low I B
(2nA), and low TC VOS (0.3µV/°C max). This op amp
can be used without requiring any adjustments. For
______________________________________________________________________________________
Microprocessor-Compatible,
14-Bit DACs
+
A2
2
1
REFF REFS
26
MX7534/MX7535
V+
VPIN 1 AD544*
VDD
3
C1
33pF
VDD RFB
OUTPUT
4
IOUT
MX7535
+
AGNDS
AGNDF
D13–D0 DGND VSS
6
7
27
8–21
C1 LOCATION
A1
5
RL
V0
REF
VSS
VDD
INPUT
DATA
PIN 1 MX7534
A3
AGND
+
DGND
NOTE: CONTROL INPUTS OMITTED FOR CLARITY.
Figure 7. Driving the MX7535 with a Remote Voltage Reference
medium-frequency applications, the OP27 is recommended. For higher-frequency applications, the HA2620 is recommended. However, these op amps
require external offset adjustment (Table 5).
________Microprocessor Interfacing
NOTE:
LAYOUT IS FOR DOUBLE-SIDED
PCB. BOLD LINE INDICATES
TRACK ON COMPONENT SIDE.
*AD544 IS AN ANALOG DEVICES PART.
Figure 8. Suggested Layout for MX7534 Incorporating Output
Amplifier
8086 with MX7535
The MX7534/MX7535 interface to both 8-bit and 16-bit
processors. Figure 9a shows the 8086 16-bit processor
interfacing to a single MX7535. In this setup, the doublebuffering feature of the DAC is not used. AD0–AD13 of
the 16-bit data bus are connected to the DAC data bus
(D0–D13). The 14-bit word is written to the DAC in one
MOV instruction, and the analog output responds immediately. In this example, the DAC address is D000. Table
6a shows a software routine for Figure 9a.
In a multiple DAC system, the double buffering of the
DAC chips allows the user to simultaneously update all
DACs. In Figure 10, a 14-bit word is loaded to each of
the DAC’s input registers in sequence. Then, with one
instruction to the appropriate address, CS4 (i.e., LDAC)
is brought low, updating all the DACs simultaneously.
8086 with MX7534
14-bit word is loaded in two bytes, using the MOV
instruction. A further MOV loads the DAC register and
causes the analog data to appear at the converter output. For the example given here, the appropriate DAC
register addresses are D002, D004, and D006. Table
6b shows the program for loading the DAC.
8085A with MX7534
A typical interface circuit is shown in Figure 9c. The
DAC is treated as four memory locations addressed by
A0 and A1. In standard operation, three of these memory locations are used. Table 6c shows a sample program for loading the DAC with a 14-bit word. The
MX7534 has address locations 3000–3003.
The six MSBs are written into location 3001, and eight
LSBs are written to 3002. Then, with a write instruction to
3003, the full 14-bit word is loaded to the DAC register.
Figure 9b shows an interface circuit to a 16-bit microprocessor. The bottom 8 bits (AD0–AD7) of the 16-bit
data bus are connected to the DAC data bus. The
______________________________________________________________________________________
11
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
MC68000 with MX7535
Figure 11a shows an interface diagram. The following
routine writes data to the DAC input registers and then
outputs the data via the DAC register:
01000 MOVE.W #W,D0
DAC data, W, loaded
into Data Register 0.
MOVE.W
D0,$E000 Data W transferred
between D0 and DAC
Register.
MOVE.B #228,D7
Control returned to the
System.
TRAP
#14
Monitor Program
ADDRESS BUS
ALE
16-BIT
LATCH
ADDRESS
DECODE
CSMSB
CSLSB
LDAC
8086
MX7535*
WR
WR
AD13
DATA BUS
AD0–AD15
D0–D13
AD0
*SOME CIRCUITRY OMITTED FOR CLARITY
MC68000 with MX7534
Figure 11b shows the MC68000 interface diagram. The
following routine writes data to the DAC input registers
and then outputs the data via the DAC register:
.A2 E003
Address Register 2
loaded with E003.
01000 MOVE.W #W,D0
DAC data, W, loaded
into Data Register 0.
MOVEP.W D0,$0000(A2) Data W transferred
between D0 and the
DAC’s Input Register.
High-ordered byte transferred first. Memory
address specified using
the address register
indirect plus displacement addressing mode.
Address used here
(E003) is odd, so data is
transferred on the loworder half of the data
bus (D0–D7).
MOVE.W D0,$E006
This instruction provides
appropriate signals to
transfer data W from
the DAC Input Register
to the DAC Register,
which controls the R-2R
ladder switches.
MOVE.B #228,D7
Control returned to the
System.
TRAP
#14
Monitor Program
Since this interfacing system uses only the lower half of
the data bus, it is also suitable for use with the
MC68008, which provides the user with an 8-bit data
bus instead of the MC68000’s 16-bit bus.
12
Figure 9a. MX7535—8086 Interface Circuit
ADDRESS BUS ADDRESS BUS
A2
ALE
16-BIT
LATCH
ADDRESS
DECODE
A1
A1 A0
CS
MX7534*
8086
WR
WR
D0–D7
DATA BUS
AD0–AD15
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9b. MX7534—8086 Interface Circuit
ADDRESS BUS
A8–A15
AE
LATCH
ADDRESS
DECODE
MX7534*
8085A
WR
AD0–AD7
A1 A0
CS
WR
DATA BUS
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 9c. MX7534—8085A Interface Circuit
______________________________________________________________________________________
D0–D7
Microprocessor-Compatible,
14-Bit DACs
MX7534/MX7535
Table 6a. Sample Program for Loading the MX7535
00
02
04
07
0B
0E
ASSUME DS:DACLOAD,CS:DACLOAD
DACLOAD SEGMENT AT 000
8CC9
MOV CX,CS
8ED9
MOVDS,CX
BF00D0
MOVDI,#D000
C705“YZWX” MOV MEM,#YZWX
EA0000
00FF
:DEFINE DATA SEGMENT REGISTER EQUAL
:TO CODE SEGMENT REGISTER
:LOAD DI WITH D000
:DAC LOADED WITH WXYZ
:CONTROL IS RETURNED TO THE MONITOR PROGRAM
Table 6b. Sample Program for Loading the MX7534 from 8086
00
02
04
07
0A
0B
0C
0F
10
11
14
ASSUME DS:DACLOAD,CS:DACLOAD
DACLOAD SEGMENT AT 000
8CC9
MOV CX,CS
MOVDS,CX
8ED9
BF02D0
MOVDI.#D002
MOV MEM,#“MS”
C605“MS”
47
INC DI
47
INC DI
C605“LS”
MOV MEM,#“LS”
INC DI
47
47
INC DI
MOV MEM,#00
C60500
JMP MEM
EA0000
:DEFINE DATA SEGMENT REGISTER EQUAL
:TO CODE SEGMENT REGISTER
:LOAD DI WITH D002
:DAC LOADED WITH “MS”
:LS INPUT REGISTER LOADED WITH “LS”
:CONTENT OF INPUT REGISTERS ARE LOADED TO THE DAC REGISTER
:CONTROL IS RETURNED TO THE MONITOR PROGRAM
Table 6c. Sample Program for Loading
the MX7534 from 8085A
2000
01
02
03
04
05
06
07
08
09
0A
0B
0C
200D
26
30
2E
01
3E
“MS”
77
2C
3E
“LS”
77
2C
77
CF
MVIH,#30
MVIL,#01
MVIA,#“MS”
MOV M,A
INR L
MVI A#“LS”
MOV M,A
INR L
MOV M,A
RST I
Z80 with MX7534/MX7535
Figure 12a is an interface circuit for the Z80, using the
MX7535. This is an example of an 8-bit processor interface for these DACs. Figure 12b shows the schematic
for the MX7534.
MC6809 with MX7534
Figure 13a shows an interface circuit that enables the
MX7534 to be programmed using the MC6809 8-bit
microprocessor. Use the 16-bit D accumulator to simplify
data transfer. The two key processor instructions are:
LDD
Load D accumulator from memory
STD
Store D accumulator to memory
MC6502 with MX7534
Figure 13b shows an interface diagram for the MC6502
using the MX7534.
________________Digital Feedthrough
In the interface diagrams shown in Figures 9–13, the
digital inputs of the DAC are directly connected to the
microprocessor bus. Even when the device is not
selected, activity on the bus can feed through on the
DAC output through package capacitance and appear
as noise. To minimize noise, isolate the DACs from the
digital bus, as shown in Figures 14a and 14b.
______________________________________________________________________________________
13
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
ADDRESS BUS
ALE
8086
16-BIT
LATCH
ADDRESS
DECODE
A1–A23
CS1
CS4 CS3 CS2
WR
CSMSB
CSLSB
LDAC
AS
ADDRESS BUS
ADDRESS
DECODE
CSMSB
CSLSB
LDAC
MC68000
DTACK
WR
MX7535*
R/W
MX7535*
AD0–AD15
DATA BUS
WR
D0–D15
DATA BUS
D0–D13
D0–D13
CSMSB
CSLSB
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 11a. MX7535—MC68000 Interface
LDAC
WR
MX7535*
ADDRESS BUS
A1–A23
A1
D0–D13
AS
MC68000
CSMSB
CSLSB
LDAC
WR
MX7535*
A0
ADDRESS
DECODE
CS
MX7534*
DTACK
WR
D0–D7
R/W
D0–D7
DATA BUS
D0–D13
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 11b. MX7534—MC68000 Interface
Figure 10. MX7535—8086 Interface: Multiple DAC Systems
14
A2
A1
______________________________________________________________________________________
Microprocessor-Compatible,
14-Bit DACs
CSLSB
CSMSB
LDAC
ADDRESS
DECODE
MREQ
A0–A15
Z80
MREQ
A0 A1
CS
MX7534*
D0–D7
DATA BUS
ADDRESS
DECODE
WR
WR
D8–D13
D8–D7
ADDRESS BUS
Z80
MX7535*
WR
MX7534/MX7535
ADDRESS BUS
A0–A15
WR
DATA BUS
D0–D7
D0–D7
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 12a. MX7535—Z80 Interface
Figure 12b. MX7534—Z80 Interface
ADDRESS BUS
A0–A15
R/W
Q
E
ADDRESS
DECODE
A0–A15
A0 A1
R/W
CS
MX7534*
WR
ADDRESS
ADDRESS
BUS BUS
ADDRESS
DECODE
6502
A0 A1
CS
MX7534*
∅2
WR
MC6809
D0–D7
DATA BUS
D0–D7
Figure 13a. MX7534—MC6809 Interface Circuit
WR
MICROPROCESSOR
SYSTEM
D0–D7
Figure 13b. MX7534—6502 Interface
ADDRESS
DECODE
A0
DATA BUS
*SOME CIRCUITRY OMITTED FOR CLARITY
*SOME CIRCUITRY OMITTED FOR CLARITY
A0–A15
D0–D7
A0–A15
ADDRESS
DECODE
A1
EN
QUAD LATCH
EN
QUAD LATCH
A1 CS
A0
WR
MICROPROCESSOR
SYSTEM
EN
MX7534*
WR
D0–D7
D0–D7
EN
QUAD LATCH
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 14a. MX7534—Interface Circuit Using Latches to
Minimize Digital Feedthrough
16-BIT
LATCH
CSMSB
CSLSB
LDAC
WR
MX7535*
D0–D15
D0–D13
*SOME CIRCUITRY OMITTED FOR CLARITY
Figure 14b. MX7535—Interface Circuit Using Latches to
Minimize Digital Feedthrough
______________________________________________________________________________________
15
MX7534/MX7535
Microprocessor-Compatible,
14-Bit DACs
___Functional Diagrams (continued)
TOP VIEW
VDD
26
1
REFS
2
REFF
MX7535
3
4
5
6
23
14-BIT DAC
14
DAC REGISTER
6
MS
INPUT
REGISTER
8
LS
INPUT
REGISTER
8–21
D13–D0
24
7
DGND
_____Pin Configurations (continued)
28 N.C.
REFS 1
RFB
IOUT
AGNDS
AGNDF
LDAC
REFF 2
27 VSS
RFB 3
26 VDD
IOUT 4
25 WR
AGNDS 5
CSLSB
AGNDF 6
22
CSMSB
25
WR
DGND 7
(MSB) D13 8
27
VSS
_Ordering Information (continued)
PART
TEMP. RANGE
PIN PACKAGE INL (LSBs)
MX7535KN
MX7535JN
MX7535KCWI
MX7535JCWI
MX7535KP
MX7535JP
MX7535J/D
MX7535BQ
MX7535AQ
MX7535BD
MX7535AD
MX7535KEWI
MX7535JEWI
MX7535TQ
MX7535SQ
MX7535TD
MX7535SD
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
-55°C to +125°C
28 Plastic DIP
28 Plastic DIP
28 Wide SO
28 Wide SO
28 PLCC
28 PLCC
Dice*
28 CERDIP
28 CERDIP
28 Ceramic SB
28 Ceramic SB
28 Wide SO
28 Wide SO
28 CERDIP
28 CERDIP
28 Ceramic SB
28 Ceramic SB
±1
±2
±1
±2
±1
±2
±2
±1
±2
±1
±2
±1
±2
±1
±2
±1
±2
MX7535
24 CSLSB
23 LDAC
22 CSMSB
21 D0 (LSB)
D12 9
20 D1
D11 10
19 D2
D10 11
18 D3
D9 12
17 D4
D8 13
16 D5
D7 14
15 D6
DIP/SO/PLCC/Ceramic SB
*Dice are tested at +25°C, DC parameters only.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.