DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
DAVICOM Semiconductor, Inc.
DM5885
720H Decoder Mix 4 NTSC/PAL Channels
to One SD or HD Signal
DATA SHEET
Final
Version: DM5885-DS-F01
June 1, 2016
Final
Doc No: DM5885-DS-F01
June 1, 2016
1
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
REVISION HISTORY:
Date
Revision
Description
2012/02/02
1.1
Initial release
2012/02/04
1.2
Terminal assignment modified (pin28 ~ pin32)
Application schematics modified
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Table of Contents
INTRODUCTION .......................................................................................................................... 6
FEATURES ............................................................................................................................................. 7
APPLICATIONS ....................................................................................................................................... 8
TERMINAL ASSIGNMENT ............................................................................................................ 9
TERMINAL FUNCTIONS.......................................................................................................................... 10
BLOCK DIAGRAM ...................................................................................................................... 21
VIDEO DECODER ....................................................................................................................... 22
VIDEO INTERFACE ................................................................................................................................ 22
Multi-channel Time Division Multiplexing ................................................................................ 23
4-CH VIDEO DECODER ......................................................................................................................... 25
VIDEO DECODER UNIT .......................................................................................................................... 26
Video Synchronization................................................................................................................ 26
Automatic Gain Control ............................................................................................................. 26
Y/C Separation ............................................................................................................................ 27
UV demodulation........................................................................................................................ 27
Luma/Chroma Processor............................................................................................................ 27
Video Interface ........................................................................................................................... 27
Fast Switch Parameter RAM ...................................................................................................... 27
FILTER RESPONSE ................................................................................................................................. 28
Anti-alias LPF ............................................................................................................................... 28
Decimation filter ......................................................................................................................... 28
Luma notch filter ........................................................................................................................ 29
Chroma band pass filter ............................................................................................................. 29
Y sharpness filter ........................................................................................................................ 30
UV demodulation low pass filter ............................................................................................... 31
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
AUDIO CODEC ........................................................................................................................... 32
DIGITAL AUDIO FORMAT ...................................................................................................................... 34
EXTENDED DIGITAL AUDIO FORMAT....................................................................................................... 35
PLL ............................................................................................................................................ 36
HOST INTERFACE ...................................................................................................................... 37
VIDEO MIXER ............................................................................................................................ 38
OUTPUT FORMAT................................................................................................................................. 39
VIDEO MIXER BLOCK ............................................................................................................................ 40
Video Source ............................................................................................................................... 40
Channel Switch Block ................................................................................................................. 40
Capture interface ........................................................................................................................ 41
Mixer Core................................................................................................................................... 46
Mix-Out Interface ....................................................................................................................... 46
Chip-Level Output Unit............................................................................................................... 51
INTERNAL CONTROL REGISTERS ............................................................................................... 52
SYSTEM CONTROL ................................................................................................................................ 52
VIDEO ADC ......................................................................................................................................... 65
PLL .................................................................................................................................................... 72
AUDIO ADC/DAC ............................................................................................................................... 75
VIDEO DECODER .................................................................................................................................. 83
AGC .............................................................................................................................................. 84
Video Detection Misc ................................................................................................................. 85
Color Killer ................................................................................................................................... 86
2D Comb Filter ............................................................................................................................ 86
VIDEO MIXER .................................................................................................................................... 109
MIXER OUTSEL CONFIGURATION TABLE ................................................................................. 132
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
ELECTRICAL SPECIFICATIONS .................................................................................................. 137
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE.................................137
Recommended Operating Conditions ..................................................................................... 138
Crystal Specifications................................................................................................................ 139
ELECTRICAL CHARACTERISTICS ............................................................................................................. 139
DC ELECTRICAL CHARACTERISTICS........................................................................................................ 139
Analog Processing and A/D Converters .................................................................................. 140
Timing ........................................................................................................................................ 140
PACKAGING ............................................................................................................................ 144
ORDERING INFORMATION...................................................................................................... 145
DISCLAIMER .................................................................................................................................... 145
PRODUCTS...................................................................................................................................... 145
CONTACT WINDOWS.......................................................................................................................145
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Introduction
The DM5885 is a 4-channel video decoder which converts 4 channels of 6.5 MHz analog
CVBS signals to 4 channels of digital 27 MHz CCIR656 signals. The DM5885 integrates
two internal PLLs, and decodes 720H videos using the same (27MHz) external clock
source. The DM5885 also features a patented fast switch function. With the fast switch
function, the DM5885 can decode up to 8 analog CVBS with little frame rate loss.
The DM5885 includes two SD mixers and one HD mixer. Each SD/HD mixer can
multiplex up to 4 video sources. In addition to two SD CCIR656 outputs or one HD
SMPTE 274M output, the DM5885 mixer can output four D1 videos through one TDM4
interface. The mixers support image mirror and H partition functions. Both interlaced and
progressive digital video outputs are supported.
The DM5885 also includes five audio ADCs and one audio DAC.
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Features
Video Decoder
l Accepts NTSC (M,J), PAL (B, D, G, H, I, M, Nc)
l Hardware Fast Switch function
l Fast Switch also controllable by software or external pin
l Software channel ID in active region
l Four 10-bits video ADCs with built in 6.5 MHz analog low pass filter
l Automatic gain control for Luminance and Chrominance
l Programmable brightness, contrast, saturation, hue, and sharpness
l 5-H comb filter for YC separation
l Chrominance line filter for PAL phase error
l DLL for video synchronization, supports 27MHz crystal within +/-1000 ppm variance
l Advanced video synchronization for weak and noisy CVBS. Supports video signal
transmitted by 500-meter long cable
l Up to 2 CCIR656 output interfaces which could be configured as 2 sets of CCIR656
(27MHz) or 2 sets of TDM2 (54MHz) or 1 set of TDM4 (108MHz)
l Support line lock camera
Audio Codecs
l Five audio ADCs and one audio DAC are integrated
l Master I2S/DSP playback, record and audio-mixing
l Supports extended I2S/DSP format transmitting up to 16 audio channels using one
data pin
l 16-bit or 8-bit 48/24/16/8 KHz PCM format
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer
l Two SD mixers and one HD mixer. Each mixer supports up to 4 channels
l Two SD CCIR656 outputs (27MHz) or one HD SMPTE 274M output (74.25MHz)
l One TDM4 (108MHz) output
l One optional TDM4 input as mixer video sources.
l Various mixing combinations. Special H partition supported
l Video mirror supported
l Support both interlaced and progressive mixer output
l 16-bit SDRAM interface
Miscellaneous
l Use a single external 27MHz crystal to support 720H video
l Two programmable PLLs integrated
l Slave I2C bus
l Ultra low power consumption. Under 500mW for normal operation. Under 50mW for
suspend mode.
l 128-pin LQFP package (14mmx14mm)
l 1.8V core power, 3.3V analog power and 1.8V analog power
Applications
Suggested applications include
l DVR
l Car DVR
l Video capture card
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Terminal Assignment
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Terminal Functions
Analog Video/Audio Interface Pins
Pin Name
Pin Number
Type
INA0
13
A
INB0
14
A
INA1
17
A
INB1
18
A
INA2
21
A
INB2
22
A
INA3
25
A
INB3
26
A
AIN1
6
A
CVBS input A of channel 0 or
S-VIDEO Y of channel 0
CVBS input B of channel 0 or
S-VIDEO Y of channel 0
CVBS input A of channel 1 or
S-VIDEO C of channel 0
CVBS input B of channel 1 or
S-VIDEO C of channel 0
CVBS input A of channel 2 or
S-VIDEO Y of channel 1
CVBS input B of channel 2 or
S-VIDEO Y of channel 1
CVBS input A of channel 3 or
S-VIDEO C of channel 1
CVBS input B of channel 3 or
S-VIDEO C of channel 1
Audio input of channel 1
AIN2
7
A
Audio input of channel 2
AIN3
8
A
Audio input of channel 3
AIN4
9
A
Audio input of channel 4
AIN5
10
A
Audio input of channel 5
AINN
5
A
Audio input negative control
AOUT
2
A
Audio output
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Description
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Digital Video/Audio Interface Pins
Pin Name
Pin Number
98,99,100,
oCCIRD_0[7:0] 101,103,104,
105,106
85,86,87,
88,90,91,
oCCIRD_1[7:0]
92,93
76,58,75,
74,72,71
A[11:0]
70,69,64
63,62,59
122,119,109,
108,96,95,
80,79,49,
DQ[15:2]
48,47,46,
45,40
Type
O
IO
Description
Video data output of channel 0 or
SMPTE 274M Y bus output or
TDM2/TDM4 Output Data Bus
Video data output of channel 1 or
SMPTE 274M C bus output or
TDM2/TDM4 Output Data Bus
IO
SDRAM ADDRESS Bus
IO
SDRAM DATA Bus
DQ0/SADD[1]
38
IO
DQ1/SADD[0]
39
IO
SDR_CLK
77
IO
SDRAM DATA Bus DQ[0],
MSB of I2C Device ID strapping
SDRAM DATA Bus DQ[1],
LSB of I2C Device ID strapping
SDRAM CLOCK
BA[1:0]
57,56
IO
SDRAM BANK Select
WE
50
O
SDRAM Control: WE
CAS
51
O
SDRAM Control: CAS
RAS
52
O
SDRAM Control: RAS
ACLKR
111
O
Audio serial clock output of record.
ASYNR
112
O
Audio serial sync output of record.
ADATR
113
O
Audio serial data output of record.
ADATM
114
O
Audio serial data output of mixing
ACLKP
116
O
Audio serial clock output of playback
ASYNP
117
O
Audio serial sync output of playback
ADATP
118
I
Audio serial data input of playback
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
GPIO
Pin Name
Pin Number
Type
MPP4
124
IO
MPP3
125
IO
MPP2
126
IO
MPP1
127
IO
Description
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
4
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
3
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
2
FLD/ACTIVE/NOVID/FASTSW_SEL of channel
1
System Control Pins
Pin Name
Pin Number
Type
Description
HRSTZ
121
I
XI
82
I
XO
83
O
oPIXCLK
67
O
TEST_EN
37
I
System reset.
Crystal 27 MHz connection or Oscillator clock
input.
For crystal 27 MHz connection.
27/54/108MHz or SMPTE 274M 74.25MHz clock
output
Test enable, please connect it to ground
SI2CD
42
IO
Slave I2C data
SI2CLK
43
I
Slave I2C clock
iPIXCLK
54
I
CCIR656 27MHz or TMD 108 MHz clock input.
MI2CLK
66
IO
Final
Doc No: DM5885-DS-F01
June 1, 2016
Master i2c clock (open drain)
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Power, Ground and NC Pins
Pin Name
Pin Number
Type
VDDA
1,11
P
1.8V Power for analog audio DAC
VSSA
3,4
G
Ground for analog audio DAC
VDDV
12,19,20,27
P
1.8V Power for video ADC
VSSV
15,16,24
G
AGND
23
G
AVDD_1
31
P
Ground for video ADC
Analog ground (used as signal input reference,
CH_AGND)
1.8V Power for analog clock PLL1
AVSS_1
32
G
Ground for analog clock PLL1
AVDD_2
34
P
1.8V Power for analog clock PLL2
AVSS_2
35
41,60,78,94,
110,128
53,68,84,
102,120
36,44,55,65,
73,81,89,97,
107,115,123
28,29,30,33
61
G
Ground for analog clock PLL2
P
1.8V Power for internal logic.
P
3.3V Power for output driver
G
Ground for internal logic and output driver
VDDI
VDDO
VSS
NC
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Description
Not Connected
13
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Pin Usage of ITDM Video Input
Settings
CCIRINPINOPT=0
Clock
iPIXCLK (pin 54)
ITDM
Video
In
Data Bus
oCCIRD_1[7:0]
[7:0]
Pin Usage of Video Output
1
Video Out
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2
oCCIRD_0[7:0]
SD: CCIR656/TDM2/TDM4
HD: Y component
oCCIRD_1[7:0]
(Only when ITDM is disabled)
SD: CCIR656/TDM2/TDM4
HD: C component
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
l Alternative assignment
(PINCFG = 2’h3 @ REG 6A)
l Terminal functions of alternative assignment
(PINCFG = 2’h3 @ REG 6A)
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Analog Video/Audio Interface Pins
Pin Name
Pin number
Type
INA0
13
A
INB0
14
A
INA1
17
A
INB1
18
A
INA2
21
A
INB2
22
A
INA3
25
A
INB3
26
A
AIN1
AIN2
AIN3
AIN4
AIN5
AINN
AOUT
6
7
8
9
10
5
2
A
A
A
A
A
A
A
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Description
CVBS input A of channel 0 or
S-VIDEO Y of channel 0
CVBS input B of channel 0 or
S-VIDEO Y of channel 0
CVBS input A of channel 1 or
S-VIDEO C of channel 0
CVBS input B of channel 1 or
S-VIDEO C of channel 0
CVBS input A of channel 2 or
S-VIDEO Y of channel 1
CVBS input B of channel 2 or
S-VIDEO Y of channel 1
CVBS input A of channel 3 or
S-VIDEO C of channel 1
CVBS input B of channel 3 or
S-VIDEO C of channel 1
Audio input of channel 1
Audio input of channel 2
Audio input of channel 3
Audio input of channel 4
Audio input of channel 5
Audio input negative control
Audio output
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Digital Video/Audio Interface Pins
Pin Name
Pin number
98,99,100,
oCCIRD_0[7:0] 101,103,104
105,106
85,86,87,
88,90,91,
oCCIRD_1[7:0]
92,93
76,54,75,74,
A[11:0]
72,71,70,69,
80,79,67,66
64,63,62,61,
59,58,57,56,
DQ[15:2]
49,48,47,46,
45,40,
Type
O
O
SDRAM ADDRESS Bus
IO
SDRAM DATA Bus
38
I
DQ1/SADD[0]
39
I
SDR_CLK
BA[1:0]
WE
CAS
RAS
ACLKR
ASYNR
ADATR
ADATM
77
96,109
50
51
52
111
112
113
114
O
IO
O
O
O
O
O
O
O
ACLKP
116
IO
ASYNP
117
IO
ADATP
118
IO
ALINKI
119
IO
ALINKO
122
IO
Final
Video data output of channel 0 or
SMPTE 274M Y bus output or
TDM2/TDM4 Output Data Bus
Video data output of channel 1 or
SMPTE 274M C bus output or
TDM2/TDM4 Output Data Bus
IO
DQ0/SADD[1]
Doc No: DM5885-DS-F01
June 1, 2016
Description
SDRAM DATA Bus DQ[0],
MSB of I2C Device ID strapping
SDRAM DATA Bus DQ[1],
LSB of I2C Device ID strapping
SDRAM CLOCK
SDRAM BANK Select
SDRAM Control : WE
SDRAM Control : CAS
SDRAM Control : RAS
Audio serial clock output of record
Audio serial sync output of record.
Audio serial data output of record
Audio serial data output of mixing
Audio serial clock output of playback or
TDM2/TDM4 Input/output Data Bus[7]
Audio serial sync output of playback or
TDM2/TDM4 Input/output Data Bus[6]
Audio serial data input of playback or
TDM2/TDM4 Input/output Data Bus[5]
Interrupt request output,
Audio Multi-chip serial input or
TDM2/TDM4 Input/output Data Bus[4]
Audio Multi-chip serial output or
TDM2/TDM4 Input/output Data Bus[3]
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
GPIO
Pin Name
Pin number
Type
MPP4
124
IO
MPP3
125
IO
MPP2/iPIXCLK
126
IO
MPP1
127
IO
Description
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 4 or
TDM2/TDM4 Input/output Data Bus[2]
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 3 or
TDM2/TDM4 Input/output Data Bus[1]
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 2 or
TDM2/TDM4 Input/output Clock
FLD/ACTIVE/NOVID/FASTSW_SEL of
channel 1 or
TDM2/TDM4 Input/output Data Bus[0]
System Control Pins
Pin Name
Pin number
Type
HRSTZ
121
I
XI
82
I
XO
83
O
oPIXCLK
108
O
oPIXCLK1
95
O
TEST_EN
SI2CD
SI2CLK
37
42
43
I
IO
I
Final
Doc No: DM5885-DS-F01
June 1, 2016
Description
System reset
Crystal 27MHz connection or Oscillator
clock input.
Crystal 27MHz connection
27/54/108MHz or SMPTE 274M 74.25MHz
clock output.
27/54/108MHz or SMPTE 274M 74.25MHz
clock output
Test enable, please connect it to ground
Slave I2C data
Slave I2C clock
18
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Power, Ground and NC Pins
Pin Name
Pin number
Type
VDDA
VSSA
VDDV
VSSV
1,11
3,4
12,19,20,27
15,16,24
P
G
P
G
AGND
23
G
AVDD_1
AVSS_1
AVDD_2
AVSS_2
31
32
34
35
41,60,78,94,
110,128
53,68,84,
102,120
36,44,55,65,
73,81,89,97,
107,115,123
28,29,30,33
P
G
P
G
1.8V Power for analog audio DAC
Ground for analog audio DAC
1.8V Power for video ADC
Ground for video ADC
Analog ground (used as signal input
reference, CH_AGND)
1.8V Power for analog clock PLL1
Ground for analog clock PLL1
1.8V Power for analog clock PLL2
Ground for analog clock PLL2
P
1.8V Power for internal logic
P
3.3V Power for output driver
G
Ground for internal logic and output driver
VDDI
VDDO
VSS
NC
Final
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Description
Not Connected
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Pin Usage of ITDM Video Input
Settings
CCIRINPINOPT=1
Clock
MPP2/iPIXCLK (pin 126)
ITDM
Video
In
Data
Bus
Pin no. {116, 117, 118, 119,
122, 124, 125, 127}
[7:0]
Pin Usage of Video Output
Video Out
Final
Doc No: DM5885-DS-F01
June 1, 2016
1 oCCIRD_0[7:0]
SD: CCIR656/TDM2/TDM4
HD: Y component
2 oCCIRD_1[7:0]
SD: CCIR656/TDM2/TDM4
HD: C component
3 (a) Only when ITDM is disabled
(b) set CCIROPINOPT=1
(c) supporting SD:
CCIR656/TDM2/TDM4
Data Bus[7:0]:
Pin no. {116, 117, 118, 119,122,
124, 125, 127}
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Block Diagram
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Decoder
Video Interface
The DM5885 outputs 27MHz CCIR656 with 720x480/720x576 resolution. For these
video outputs, SAV (Start of Active Video) and EAV (End of Active Video) are inserted to
indicate active video interval. Each channel uses one output port to transmit video data,
that is, luminance and chrominance data are transmitted through the same port. The
output timing diagram is shown below.
The number of data cycles in active horizontal line will vary according to the output
format. The active horizontal line contains 1440 cycles.
SAV and EAV indicate the active video interval. The values of the first three bytes in
SAV and EAV are invariant preamble: 0xFF, 0x00, and 0x00. Different values are
designated to the last byte according to different conditions: Field, V time, and H time.
The MSB of this byte is always set to 1 and it’s followed by three bits to represent the
condition of F, V, and H respectively. The last four bits are used as protection bits. The
detailed code sequences of SAV and EAV are illustrated in the following table.
FVH
Value
Condition
SAV/EAV Code Sequence
Field
V time
H time
F
V
H
Odd
Odd
Odd
Odd
Even
Even
Even
Even
Active
Active
Blank
Blank
Active
Active
Blank
Blank
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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Doc No: DM5885-DS-F01
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Byte 0 Byte 1 Byte 2 Byte 3
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x9D
0xAB
0xB6
0xC7
0xDA
0xEC
0xF1
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Multi-channel Time Division Multiplexing
The DM5885 supports 2/4-channel time division multiplexed output format. Thus two or
four video channels can be transmitted through one output port. The clock rate should
be two or four times of the original sampling rate according to the number of channels to
be multiplexed.
The basic case is the non-multiplexed output. The clock rate follows the original data
rate (27 MHz). The timing diagram is illustrated below.
CLK1X
CCIR
When two-channel multiplexing is selected, two times of the original clock rate is used
(54 MHz). The timing diagram is illustrated below.
CLK2X
CH0
CH1
tsu
th
TDM2X
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
When four-channel multiplexing is selected, four times of the original clock rate is used
(108 MHz). The timing diagram is illustrated below.
In the Multi-channel Time Division Multiplexing mode, channel IDs are used to indicate
the corresponding channels. Channel IDs are defined as the last four bits in SAV/EAV
code sequence (i.e. the originally-defined protection bits). The relationship between
SAV/EAV code sequence and channel ID is illustrated in the following table.
Condition
Field
V time
FVH Value
H time
F
V
H
EAV/SAV Code Sequence
Byte 0
Byte 1
Byte 3
Byte 2
Ch0
Odd
Odd
Odd
Odd
Even
Even
Even
Even
Active
Active
Blank
Blank
Active
Active
Blank
Blank
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
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0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x90
0xA0
0xB0
0xC0
0xD0
0xE0
0xF0
Ch1
Ch2
Ch3
0x81 0x82 0x83
0x91 0x92 0x93
0xA1 0xA2 0xA3
0xB1 0xB2 0xB3
0xC1 0xC2 0xC3
0xD1 0xD2 0xD3
0xE1 0xE2 0xE3
0xF1 0xF2 0xF3
24
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
4-CH Video Decoder
The DM5885 contains four video decoders supporting up to 8 CVBS inputs.
Each CVBS has its own gain amplifier. For each pair of VINA and VINB, a 2-to-1 MUX
selects one CVBS source and passes this source to one video analog-to-digital
converter (VADC). The DM5885 has 4 VADCs and 4 video decoders (VD). The VADCs
and VDs are organized as 2 banks as shown in the above figure. Each bank can be
independently configured to operate at 27MHz.
Final
Doc No: DM5885-DS-F01
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Decoder Unit
The DM5885 video decoder contains a Video Synchronization block, an AGC block, an
YC separation block, a UV Demodulation block, a Luma/Chroma Processor block and a
BT 656 output block. A patented Fast Switch is also included.
In addition to CVBS, the DM5885 video decoder supports S-Video as well.
Video Synchronization
Video Synchronization performs video detection function. It automatically detects
NTSC(M), NTSC(443), PAL(B,D,G,H,I), PAL(M), PAL(N), PAL(60). A smart video
detection algorithm has been adopted. Therefore the DM5885 can perform fast and
stable video synchronization even if the input signal is weak or the external crystal is
with error as large as +/- 1000 ppm.
Automatic Gain Control
Automatic Gain Control (AGC) block performs both Luma AGC and Chroma AGC
(CGAC). After video synchronization, Luma AGC adjusts input Luma level to the
standard level (1Vpp). A further CAGC is performed after Luma AGC for signal with
different Luma and Chroma attenuation.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Y/C Separation
Y/C Separation is for CVBS input only. After this block CVBS signal is separated into
Luma and Chroma components. A 5-H 2D comb filter is adapted in the Y/C separation
block.
UV demodulation
After Y/C separation, the UV demodulation block performs UV demodulation to the
Chroma component. The phase and frequency of the UV demodulation is from a color
burst subcarrier tracking block for both NTSC and PAL mode. A UV demodulation LPF is
also adopted to filter out chroma noise.
Luma/Chroma Processor
This block contains a programmable Luma sharpness filter. Hue, Saturation, Brightness
and Contrast adjustment are also supported. The adjusted video is then transformed
from YUV to YCbCr domain for CCIR656 output interface.
Video Interface
The DM5885 video decoder supports 27MHz BT.656 video output format. A horizontal
cropping function also included in this block.
Fast Switch Parameter RAM
The DM5885 features a patented hardware video source fast switch function. The Fast
Switch block has a table which stores video characteristic. Each time HW switches to a
previously tracked video source it could complete video synchronization within several
lines. With this feature, the DM5885 can decode up to 8 CVBS with little frame rate loss.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Filter response
Anti-alias LPF
Decimation filter
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Luma notch filter
Chroma band pass filter
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Y sharpness filter
n
NTSC
n
PAL
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
UV demodulation low pass filter
Final
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June 1, 2016
31
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Audio CODEC
The audio codec in the DM5885 consists of five audio ADCs, one audio DAC, one audio
mixer, one I2S/DSP decoder and two I2S/DSP encoders as shown below. The I2S/DSP
decoder and encoders always operate in the master mode.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
The I2S/DSP decoder is used for playback of digital input. It generates ACLKP and
ASYNP signals and accepts serial data via ADATP from a slave device. The levels of
the five analog audio inputs (AIN1 ~ AIN5) are programmable via the registers
DAGC_GAIN1, DAGC_GAIN2, DAGC_GAIN3, DAGC_GAIN4 and DAGC_GAIN5. The
six input audio sources can be mixed by the used-defined ratio specified by registers
MIXGAIN_1, MIXGAIN_2, MIXGAIN_3, MIXGAIN_4, MIXGAIN_5, MIXGAIN_P. The
mixed audio can be output through I2S/DSP encoder or DAC.
The codec provides three interfaces for audio output. The audio DAC can output analog
audio for any one of the six input audio sources or the mixed audio. The analog output
level is adjustable via register DAGC_GAIN_P. Two I2S/DSP encoders are present to
output digital audio signal. The first one generates ACLKR, ASYNR and ADATR to
output the 4 recorded audio inputs. The second encoder uses ADATM and shares the
other two signals (ACLKR and ASYNR) to output the mixed audio.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Digital Audio Format
The 3 digital audio interfaces (decoder for playback and encoder for record or mixing)
follow the standard I2S or DSP protocol as shown below. Only master mode (codec
being the master) is supported.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Extended Digital Audio Format
The digital audio encoders also support an extended I2S/DSP format to carry multiple
audio channels through a single ADAT pin as shown below.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
PLL
The DM5885 has two internal PLLs to generate the system and pixel clocks. A
27MHz is required for the PLLs.
The default PLL setting is shown in the following table.
Crystal In clock
(MHz)
PLL out (MHz)
Function
PLL1
27
144
System/pixel clock
PLL2
27
74.25
SMPTE 274M
pixel clock
PLL default operated clock
The PLL parameters for various system configurations are shown in the following table.
Crystal(MHz)
PLL
out(MHz)
M
N
OD
27
27
27
27
27
144
108
144
108
74.25
64(62+2)
16(14+2)
64(62+2)
16(14+2)
22(20+2)
6(4+2)
2(0+2)
6(4+2)
2(0+2)
2(0+2)
1
1
1
1
2
PLL1
PLL2
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Host Interface
In the DM5885, I2C is used for setting configuration and parameters, for example,
brightness, contrast, saturation, hue, and sharpness control. The typical timing diagram
of I2C write and read access is illustrated in the following figure.
Write operation of I2C bus
Read operation of I2C bus
1
1
0
Write/Read Address
Slave Address
0
0
SADD[1] SADD[0]
R/W
0: Write; 1: Read
The external Pull-up/Pull-down resisters connected to the pins “DQ0” and “DQ1” indicate
the device address SADD[1] and SADD[0]. When pull-up resistor is connected to DQ0 or
DQ1, it indicates SADD[1] or SADD[0] with a high value. Otherwise when pull-down
resistor is connected to DQ0 or DQ1, it indicates SADD[1] or SADD[0] with a low value.
SADD[1:0]=2’h0
SADD[1:0]=2’h1
SADD[1:0]=2’h2
SADD[1:0]=2’h3
Final
Doc No: DM5885-DS-F01
June 1, 2016
Write Address
Read Address
C0
C2
C4
C6
C1
C3
C5
C7
37
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer
The video mixer in the DM5885 is composed of four capture interfaces, two mixer cores,
one SDRAM controller and two mix-out interfaces (MIX_CCIROUT_X) as shown below.
The MIX_CCIROUT_0 is the main output interface, while an auxiliary path (through
MIX_CCIROUT_1) is available for SD mode when OUTSEL is configured as 4 or 5.
SDRAM
VDOUT_0
CHSEL_0
OUT_SEL
SDRAM Controller
INV_H0
OUT_SEL
VDOUT_1
Video
Source
Channel
Switch
Scaler
Mirror
CH0
Capture I/F
CH0
CHSEL_1
OUT_SEL
INV_H1
Scaler
Mirror
CH1
VDOUT_2
Video
Source
Channel
Switch
CH1
CH2
MX_SD_0
MIX_
CCIROUT_
0
Mixer_Core_0
(HD/SD)
CH3
MX_HD_Y
MX_HD_C
Capture I/F
CHSEL_2
VDOUT_3
Video
Source
Channel
Switch
OUT_SEL
INV_H2
Scaler
Mirror
CH2
Capture I/F
CH1
ITDM_0
CHSEL_3
OUT_SEL
INV_H3
Scaler
Mirror
CH2
MIX_
CCIROUT_
1
Mixer_Core_1
(SD only)
ITDM_1
MX_SD_1
CH3
ITDM_2
ITDM_3
Video
Source
Channel
Switch
CH3
Capture I/F
OUT_SEL
MX_SD_1 is valid only when
the value of OUT_SEL is 4 or 5.
Video Mixer
Block Diagram of Video Mixer
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Output format
In addition to 27MHz BT.656 with 720x480/720x576 resolution, the DM5885 mixer can
support 74.25MHz SMPTE 274M 1920x1080 interface.
SMPTE 274M contains 16-bit data bus and 1-bit clock bus. Thus two output ports are
used for one HD format. Here luminance and chrominance data are transmitted through
different ports. The output timing diagram is shown below.
For 1920x1080 HD video outputs, the active horizontal line contains 1920 cycles. The
definition of SAV and EAV code sequences is the same as that in 720H video outputs.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Mixer Block
Video Source
The video mixer accepts eight input sources (VDOUT_0 ~ VDOUT_3, ITDM_0 ~
ITDM_3). The input source VDOUT_X, digital version of the input CVBS, comes from the
internal video decoder. As shown in the figure, users are flexible to select any one from
the input CVBS pair for VDOUT_X by programming the control registers (SW_sel_1,
SW_sel_2) of the analog MUX. The ITDM_X is the decoded TDM input for a specific
Channel ID.
Channel Switch Block
There are four capture interfaces in the video mixer. Within each capture interface, a
channel switch is used to select the desired video source. This selection is fully
programmable by registers CHSEL_0, CHSEL_1, CHSEL_2 and CHSEL_3, allowing
any one of the eight mixer inputs to be selected. The following table determines the
mapping between CHSEL_X and the selected video.
CHSEL_X
Selected
Video
0
1
2
3
4
5
6
7
VDOUT_0
VDOUT_1
VDOUT_2
VDOUT_3
ITDM_0
ITDM_1
ITDM_2
ITDM_3
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Capture interface
The following figure is the block diagram of channel video capture interface. The video
source is selected by the channel switch for the specific channel. Video signal detection
detects valid signal and format. It is then horizontally cropped, scaled, and horizontally
mirrored if necessary. The detailed functions of these modules are described in the
following sections.
Video Signal Detection
Video signal detection module detects if valid video signal exists. A timeout watchdog
module monitors the time used by the detection module. If valid signal is detected within
the pre-set time limit, the flag ‘NOVID_x’ is set to 0. Otherwise, it is set to ‘1’.
The module also detects the format of the channel signal. ‘H720_DET_x’ is 1 when
720H video source is detected. ‘L625_DET_x’ is 1 when PAL video source is detected.
‘L525_DET_x’ is 1 when NTSC video source is detected.
Horizontal Cropping
The input video source can be cropped horizontally for output. It is illustrated in the
following figure. ‘Crop_start_point’, which indicates the position to start cropping, is set in
the registers 0xC3 to 0xC6. ‘Crop_start_point’ can be specified for each channel.
‘Crop_length’, which indicates the length for cropping, is set in the registers 0xA4 and
0xA5. The same value is used for all channels. If 1/4 horizontal scaling is performed in
any channel, it should be set to a multiple of 4. Otherwise, if 1/2 horizontal scaling is
performed in any channel; it should be set to a multiple of 2.
Final
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June 1, 2016
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Scaler
DM5885 supports several kinds of partition modes. It can be configured with the register
‘OUT_SEL’ (0xA0). According to the mode selection, the output of each channel should
be scaled to be combined to a new frame for output. The following figure shows the
settings of ‘OUT_SEL’ and the corresponding output formats. Here 720H NTSC video
source is used as an example.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
The following table shows the scaling ratios at the horizontal direction and the vertical
direction with different ‘OUT_SEL’ settings.
OUT_SEL
CH0
CH1
CH2
CH3
0
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
H
V
H
V
H
V
H
V
1
1
1/2
1
1/2
-
2
1
1/2
1/2
1/2
1/2
1/2
-
3
1/2
1/2
1/4
1
1/2
1/2
1/4
1
4
1
1
-
5
1/2
1
1/2
1
-
8
1
1
1
1
1
1
1
1
When horizontal scaling is performed, decimation filter is applied on input samples. The
filtered samples are then decimated according to the scaling ratio. The following figure
shows the frequency response of the decimation filter at the horizontal scaling process.
0
-5
Gain (dB)
-10
-15
-20
-25
-30
0
Final
Doc No: DM5885-DS-F01
June 1, 2016
0.5
1
1.5
2
2.5
3
3.5
Frequency (MHz)
4
4.5
5
5.5
6
43
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
When the display width is a quarter of the original width, in addition to 1/4 down scaling
at the horizontal direction, 1/4 input frame cropping can be chose. The most significant
four bits of the register ‘Mirror Config’ (0xBD) are used to indicate the input frame
cropping. When ‘H_x_L’ is set to 1, the left quarter of channel x is cut for display. When
‘H_x_R’ is set to 1, the right quarter of channel x is cut for display. When ‘H_x_L’ and
‘H_x_R’ are both set to 0, 1/4 down scaling is performed. The following figure illustrates
the settings of ‘H_x_L’ and ‘H_x_R’.
Please note that 1/4 input frame cropping can only be supported at SD mode and
‘OUT_SEL’ is set to 3.
Vertical scaling uses simple line dropping algorithm. No averaging operation is
performed. The following figure illustrates the process. Top field is used for output.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Mirror
When horizontal mirroring is performed, the samples at each line are left-right
flipped. Please note that horizontal mirroring is only supported at SD mode. Each output
channel can be assigned to be mirrored or not. The last four bits of the register ‘Mirror
Config’ (0xBD) are used to indicate the mirrored output channels. When ‘INV_Hx’ is set
to 1, the output picture of channel x is mirrored at the horizontal direction. The following
figure illustrates the result of horizontal mirroring.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Mixer Core
There are two mixer cores mixing up to four video data (CH0, CH1, CH2 and CH3)
coming from the capture interface. The mixed video is then stored into the SDRAM. The
Mixer_Core_0 is a full-function mixer supporting both HD and SD resolution.
Mixer_Core_1 is a secondary mixer which is only valid for SD mode when OUTSEL is
programmed as 4 or 5. The mixing process is determined by the value of the register
OUTSEL as shown in the following figure.
Mix-Out Interface
The mix-out interface retrieves mixed video from the SDRAM. The mixed video then
goes to the chip-level output unit to form a variety of output combinations. Users are
flexible to specify the output format as progressive or interlaced. The MIX_CCIROUT_0
is the main mixer output unit supporting both SD and HD resolution. For SD mode,
MX_SD_0 is output. In case of HD mode, MX_HD_Y is output for luminance and
MX_HD_C is output for chrominance. Another mixed video MX_SD_1 from
MIX_CCIROUT_1 is available if OUTSEL is configured as 4 or 5. MX_SD_1 is always of
SD resolution. The combined usage of MIX_CCIROUT_0 and MIX_CCIROUT_1 is
shown in the following figure.
Final
Doc No: DM5885-DS-F01
June 1, 2016
46
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Final
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June 1, 2016
47
DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video Rendering
The output frame is divided into several partitions according to ‘OUT_SEL’. The following
table shows the coordinates of left-top point and right-bottom point of the partitions with
different values of ‘OUT_SEL’. The input video width is denoted as W and the input
video height is denoted as H.
Partition 0
Partition 1
Partition 2
Partition 3
OUT_SEL
=0
OUT_SEL
=1
OUT_SEL
=2
OUT_SEL
=3
OUT_SEL
=4
OUT_SEL
=5
OUT_SEL
=8
(0,0)
(0,0)
(0,0)
(W/4,0)
(0,0)
(0,0)
(0,0)
(W/2,H/2)
(W,H/2)
(W,H/2)
(3W/4,H/2)
(W,H)
(W/2,H)
(W,H)
(W/2,0)
(0,H/2)
(0,H/2)
(0,0)
-
(W/2,0)
(W,0)
(W,H/2)
(W,H)
(W/2,H)
(W/4,H)
-
(W,H)
(2W,H)
(0,H/2)
-
(W/2,H/2)
(W/4,H/2)
-
-
(0,H)
(W/2,H)
-
(W,H)
(3W/4,H)
-
-
(W,2H)
(W/2,H/2)
-
-
(3W/4,0)
-
-
(W,H)
(W,H)
-
-
(W,H)
-
-
(2W,2H)
The output of each channel will be rendered within the active region of the
corresponding partition. The active region in each partition can be specified by defining
its top-left coordinate (COR_Xn, COR_Yn). The length of the active region is the crop
length multiplied by the scaling ratio. The vertical coordinate of the right-bottom point of
the active region is the same as that of the corresponding partition. Channel output is
horizontally shifted if the horizontal coordinate of the top-left point of the active region is
different from that of the corresponding partition. However, if the vertical coordinate of
the top-left point of the active region is different from that of the corresponding partition,
pixel lines outside the active region are discarded. The following figure illustrated the
relationship between partitions and active regions.
Several rules should be followed when specifying the coordinate (COR_Xn, COR_Yn).
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
1. The active region should not be outside the corresponding partition. If we define the
coordinate of the left-top point of the partition to be (S_Xn,S_Yn) and the partition
width to be PWn, the following condition should be satisified:
COR_Xn + Crop_length*H_scaling_ratio [VADC_dout1/VADC_dout2] mux
VADC_doutA= VADCMX0_1 =>[VADC_dout3/VADC_dout4] mux
3’h3: will drive VADC_0 analog IP Do [15:1], selected signal to
[VADC_doutA, VADC_doutB]
3’h4: will drive VADC_1 analog IP Do [15:1], selected signal to
[VADC_doutA, VADC_doutB]
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h6F
MBIST Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
BISTGO
MBDON
E
MBERR
_4
MBERR
_3
MBERR
_2
MBERR
_1
MBERR
_0
MBERR_0: When 1, memory of group 0 has error, Set by HW, write 1 to clear.
MBERR_1: When 1, memory of group 1 has error, Set by HW, write 1 to clear.
MBERR_2: When 1, memory of group 2 has error, Set by HW, write 1 to clear.
MBERR_3: When 1, memory of group 3 has error, Set by HW, write 1 to clear.
MBERR_4: When 1, memory of group 4 has error, Set by HW, write 1 to clear.
MBDONE: MBIST has finished self-test, Set by HW, write 1 to clear.
BISTGO: Write 1to start MBIST logic. HW auto clear this bit after MBIST done.
Address= 8’h70
ITDM Control
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
CCIRITMD
CCIRINE
N
CCIRINEN: When 1, enable ITDM function.
CCIRITMD: Video source from iTDM mode selected.
2’b00: CCIR656 .
2’b01: 54 TDM digital signal.
2’b1x: 108 TDM digital signal.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h71
CCIROUT_0 Otdm Configuration 1
7-bit
6-bit
0
5-bit
4-bit
3’h1
3-bit
2-bit
0
1-bit
0-bit
3’h0
CCIROMX0_1
CCIROMX0_0
CCIROMX0_0: The mux of CCIROUT_0’s channel 0 at OTDM mode.
CCIROMX0_1: The mux of CCIROUT_0’s channel 1 at OTDM mode.
Address= 8’h72
CCIROUT_0 Otdm Configuration 2
7-bit
6-bit
0
5-bit
4-bit
3’h3
3-bit
2-bit
0
1-bit
0-bit
3’h2
CCIROMX0_3
CCIROMX0_2
CCIROMX0_2: The mux of CCIROUT_0’s channel 2 at OTDM mode.
CCIROMX0_3: The mux of CCIROUT_0’s channel 3 at OTDM mode.
Address= 8’h73
CCIROUT_1 Otdm Configuration 1
7-bit
6-bit
0
5-bit
3’h1
CCIROMX1_1
4-bit
3-bit
0
2-bit
1-bit
0-bit
3’h0
CCIROMX1_0
CCIROMX1_0: The mux of CCIROUT_1’s channel 0 at OTDM mode.
CCIROMX1_1: The mux of CCIROUT_1’s channel 1 at OTDM mode.
Final
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DM5885
720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h74
CCIROUT_1 Otdm Configuration 2
7-bit
6-bit
0
5-bit
4-bit
3-bit
3’h3
2-bit
1-bit
0
0-bit
3’h2
CCIROMX1_3
CCIROMX1_2
CCIROMX1_2: The mux of CCIROUT_1’s channel 2 at OTDM mode.
CCIROMX1_3: The mux of CCIROUT_1’s channel 3 at OTDM mode.
Address= 8’h75
IO/Clock Configuration
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
VMCLKSEL
ACLKP
OE
IRQOE
IRQOE: If using DQ14 as IRQ, set this bit as ‘1’
Otherwise, this bit is “don’t care”
ACLKPOE: Set as ‘1’ when I2S playback is to be enabled.
VMCLKSEL: Clock selection for video mixer.
2’h0: Mixer clock sources from internal PLL (PLL1). (Normal operation)
2’h1: Mixer clock sources from PLL1 with frequency divided by 2.
2’h2: Mixer clock sources from external pin No.126.
2’h3: Mixer clock sources from external pin No.126 with frequency divided
by 2.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h77
CHIP Status
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
PWRON
PWRON: Power On status. (RO)
Address= 8’h78
I2C Master Configuration
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
8’hB8
CH device address
CH0~CH3: i2c slave device address. (R/W)
-DM5885 device address will be {4’hC,4’h0}
-I2CMaster_0: device address will be {4’hC,4’h2}
-I2CMaster_1: device address will be {4’hC,4’h4}
-I2CMaster_2: device address will be {4’hC,4’h6}
-I2CMaster_3: device address will be {4’hC,4’h8}
-For broadcast I2CMaster_CH0~I2CMaster_CH3, device address
{4’HC,4’HE}
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h79
I2CM status
7-bit
6-bit
5-bit
0
0
MI2CRD
CMD
4-bit
3-bit
2-bit
1-bit
0-bit
2’h0
0
0
0
0
MI2CSEL
CHNAC
K3
CHNAC
K2
CHNAC
K1
CHNAC
K0
CHNACK0: CH0 I2C fail (RO, WC) .
CHNACK1: CH1 I2C fail (RO, WC) .
CHNACK2: CH2 I2C fail (RO, WC) .
CHNACK3: CH3 I2C fail (RO, WC) .
MI2CSEL: The device address is 0xCA and select which channel will be set.
-I2CMaster_CH0: device address will be {4’hC 4’ha} & {MI2CSEL=2’b00}.
-I2CMaster_CH1: device address will be {4’hC 4’ha} & {MI2CSEL=2’b01}.
-I2CMaster_CH2: device address will be {4’hC 4’ha} & {MI2CSEL=2’b10}.
-I2CMaster_CH3: device address will be {4’hC 4’ha} & {MI2CSEL=2’b11}.
MI2CRDCMD: When 1, the MI2C restart command enable.
Address= 8’h7F
SW FAST SWITCH
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
OFASTS
W_OPT
OFASTS
W_SEL3
OFASTS
W_SEL2
OFASTS
W_SEL1
OFASTS
W_SEL0
OFASTW_SEL0:valid when VD0 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN1A as VD0 CVBS source
set 1, select VIN1B as VD0 CVBS source
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
OFASTW_SEL1:valid when VD1 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN2A as VD1 CVBS source
set 1, select VIN2B as VD1 CVBS source
OFASTW_SEL2:valid when VD2 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN3A as VD2 CVBS source
set 1, select VIN3B as VD2 CVBS source
OFASTW_SEL3:valid when VD3 REG04[4]=1 and OFASTSW_OPT=1
set 0, select VIN4A as VD3 CVBS source
set 1, select VIN4B as VD3 CVBS source
OFASTSW_OPT: valid when REG04[4]=1
Set 0, VD0-VD3 SW FASTSW control signal from OFASTSW_SEL0OFASTSW_SEL3
Set 1, VD0-VD3 SW FASTSW control signal from input pin
MPP0~MPP3
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Video ADC
Address= 8’h80
Video ADC 0 Configuration 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWGAIN
_0
pd_v2
pd_v1
SW_sel_
2
SW_sel_
1
pd_v1: Power down VIN1A & VIN1B, active high.
pd_v2: Power down VIN2A & VIN2B, active high.
SWGAIN_0: Software programs VADC 0’s gain setting, active high. When low, the
VADC 0’ gain setting programmed by Hardware auto.
SW_sel_1: Software select active CVBS input. (0: VIN1A, 1: VIN1B)
SW_sel_2: Software select active CVBS input. (0: VIN2A, 1: VIN2B)
Address= 8’h81
Video ADC 0 Configuration 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
4’hA
0
0
0
0
bias_vadc12
SvideoC
_2B
SvideoC
_2A
SvideoC
_1B
SvideoC
_1A
bias_vadc12: VADC 0’s bias setting.
SvideoC_1A: Channel VIN1A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_1B: Channel VIN1B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_2A: Channel VIN2A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_2B: Channel VIN2B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h82
Video ADC 0 Configuration 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain1B
SW_gain1A
SW_gain1A: VIN1A’s gain value, valid when REG80[2]=1.
SW_gain1B: VIN1B’s gain value, valid when REG80[2]=1.
Minimum gain is set by 4’h0. Maximum gain is set by 4’hf.
The characteristic is the same as REG83
Address= 8’h83
Video ADC 0 Configuration 4
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain2B
SW_gain2A
SW_gain2A: VIN2A’s gain value, valid when REG80[2]=1.
SW_gain2B: VIN2B’s gain value, valid when REG80[2]=1.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h84
Video ADC 0 Configuration 5
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
clmp1B
clmp1A
Clmp1A: VIN1A’s clamp value.
Clmp1B: VIN1B’s clamp value.
The clamp can be used to adjust the sync tip value to the nominal value of 20.
Address= 8’h85
Video ADC 0 Configuration 6
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
Clmp2B
clmp2A
Clmp2A: VIN2A’s clamp value.
Clmp2B: VIN2B’s clamp value.
Address= 8’h86
Video ADC 1 Configuration 1
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SWGAIN
_1
pd_v4
pd_v3
SW_sel_
4
SW_sel_
3
pd_v3: Power down VIN3A & VIN3B, active high.
pd_v4: Power down VIN4A & VIN4B, active high.
Final
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SWGAIN_1: Software programs VADC 1’s gain setting, active high. When low, the
VADC 1’ gain setting programmed by Hardware auto.
SW_sel_3: Software select active CVBS input. (0: VIN3A, 1: VIN3B)
SW_sel_4: Software select active CVBS input. (0: VIN4A, 1: VIN4B)
Address= 8’h87
Video ADC 1 Configuration 2
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
4’hA
0
0
0
0
bias_vadc34
SvideoC
_4B
SvideoC
_4A
SvideoC
_3B
SvideoC
_3A
bias_vadc34: VADC 1’s bias setting.
SvideoC_3A: Channel VIN3A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_3B: Channel VIN3B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_4A: Channel VIN4A chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
SvideoC_4B: Channel VIN4B chroma clamping. When 1, the analog clamping level is
set to 50% for chroma signal processing.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h88
Video ADC 1 Configuration 3
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain3B
SW_gain3A
SW_gain3A: VIN3A’s gain value, valid when REG86[2]=1.
SW_gain3B: VIN3B’s gain value, valid when REG86[2]=1.
Address= 8’h89
Video ADC 1 Configuration 4
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
SW_gain4B
SW_gain4A
SW_gain4A: VIN4A’s gain value, valid when REG86[2]=1.
SW_gain4B: VIN4B’s gain value, valid when REG86[2]=1.
Address= 8’h8A
Video ADC 1 Configuration 5
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
Clmp3B
Clmp3A
Clmp3A: VIN3A’s clamp value.
Clmp3B: VIN3B’s clamp value.
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
Address= 8’h8B
Video ADC 1 Configuration 6
7-bit
6-bit
5-bit
4-bit
3-bit
2-bit
1-bit
0-bit
0
0
0
0
0
0
0
0
1-bit
0-bit
Clmp4B
Clmp4A
Clmp4A: VIN4A’s clamp value.
Clmp4B: VIN4B’s clamp value.
Address= 8’h8C
Video ADC LPF Option
7-bit
6-bit
5-bit
4-bit
0
0
0
0
3-bit
2-bit
2’h0
2’h0
lpf_34
lpf_12
lpf_12: VADC 0 LPF selected.
lpf_34: VADC 1 LPF selected.
lpf_xx: 2’h0: 6MHz
2’h1: 9MHz
Others: bypass
Address= 8’h8D
VADC Clk Delay Configuration 1
7-bit
6-bit
0
5-bit
3’h0
DLYMUX_ANA34
Final
Doc No: DM5885-DS-F01
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4-bit
3-bit
0
2-bit
1-bit
0-bit
3’h0
DLYMUX_ANA12
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DLYMUX_ANA12: Programmable delay of digcore aclk_out0 from aclk_0.
(3’h0: zero delay è 3’h7: max delay, add 0.6ns at every step)
DLYMUX_ANA34: Programmable delay of digcore aclk_out1 from aclk_1.
(3’h0: zero delay è 3’h7: max delay, add 0.6ns at every step)
Address= 8’h8E
VADC Clk Delay Configuration 2
7-bit
6-bit
0
5-bit
4-bit
3-bit
3’h0
2-bit
0
1-bit
0-bit
3’h0
DLYMUX_ANA54
DLYMUX_ANA27
DLYMUX_ANA27: Programmable delay of digcore aclk27_out from aclk27.
(3’h0: zero delay è 3’h7: max delay, add 0.6ns at every step)
DLYMUX_ANA54: Programmable delay of digcore aclk54_out from aclk54.
(3’h0: zero delay è 3’h7: max delay, add 0.6ns at every step)
Address= 8’h8F
VADC Digcore Config
7-bit
6-bit
5-bit
4-bit
3-bit
0
0
0
0
0
2-bit
1-bit
0-bit
3’h0
DLYMUX_VD
DLYMUX_VD: Programmable delay of VD clk.
(3’h0: zero delay è 3’h7: max delay, add 0.6ns at every step)
Final
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720H Decoder Mix 4 NTSC/PAL Channels to One SD or HD Signal
PLL
Formula:
CLK_OUT = XIN * (M+2)/[(N+2)*OD*2]
Where CLK_OUT: PLL output frequency
XIN: PLL input frequency.
M: The numerator of PLL formula.
[N, OD]: The denominator of PLL formula.
Attention:
1. 100MHz
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