PRELIMINARY DATA SHEET
256M bits DDR SDRAM with Super Self-Refresh
EDD2516KCTA (16M words × 16 bits)
Specifications
• Density: 256M bits • Organization ⎯ 4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5 • Precharge: auto precharge operation for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, super self-refresh with Auto Temperature Compensated Self-refresh (ATCSR) function • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.8μs • Operating ambient temperature range ⎯ TA = 0°C to +70°C
Pin Configurations
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS SF VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS
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Features
• Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • SSR Flag function available
Document No. E0641E20 (Ver.2.0) Date Published December 2005 (K) Japan Printed in Japan URL: http://www.elpida.com
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This product became EOL in April, 2007.
©Elpida Memory, Inc. 2005
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A0 to A12 BA0, BA1
DQ0 to DQ15
(Top view)
UDQS/LDQS /CS /RAS /CAS /WE UDM/LDM CK /CK CKE VREF VDD VSS VDDQ VSSQ NC SF
Address input Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection SSR Flag
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EDD2516KCTA
Ordering Information
Part number EDD2516KCTA-6BS-E EDD2516KCTA-7AS-E EDD2516KCTA-7BS-E Mask version C Organization (words × bits) 16M × 16 Internal banks 4 Data rate Mbps (max.) 333 266 266 JEDEC speed bin (CL-tRCD-tRP) DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Package 66-pin Plastic TSOP (II)
Part Number
E D D 25 16 K C TA - 6B S - E
Elpida Memory
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Type D: Monolithic Device Product Family D: DDR SDRAM Density / Bank 25: 256M / 4-bank Organization 16: x16 Power Supply, Interface K: 2.5V, SSTL_2, Super self-refresh with SSR flag
Preliminary Data Sheet E0641E20 (Ver.2.0)
Environment Code E: Lead Free Spec Detail S: 0 to +70°C Speed 6B: DDR333B (2.5-3-3) 7A: DDR266A (2-3-3) 7B: DDR266B (2.5-3-3) Package TA: TSOP (II) Die Rev.
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EDD2516KCTA
CONTENTS Specifications ................................................................................................................................................ 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................. 11 Pin Function ................................................................................................................................................ 12 Command Operation................................................................................................................................... 14 Simplified State Diagram ............................................................................................................................ 21 Operation of the DDR SDRAM ................................................................................................................... 22 Timing Waveforms ...................................................................................................................................... 42 Package Drawing........................................................................................................................................ 49 Recommended Soldering Conditions ......................................................................................................... 50
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Preliminary Data Sheet E0641E20 (Ver.2.0)
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EDD2516KCTA
Electrical Specifications
• All voltages are referenced to VSS (GND). • After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD IOS PD TA Tstg Rating –1.0 to +3.6 –1.0 to +3.6 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Note
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Parameter Supply voltage Input reference voltage Termination voltage Input high voltage Input low voltage Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to +70°C)
Symbol VDD, VDDQ VSS, VSSQ VREF VTT min. 2.3 0 0.49 × VDDQ VREF – 0.04 typ. 2.5 0 0.50 × VDDQ VREF — max. 2.7 0 0.51 × VDDQ VREF + 0.04 VDDQ + 0.3 VREF – 0.15 VDDQ + 0.3 Unit V V V V V V V 2 3 4 Notes 1
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VIH (DC) VIL (DC) VIN (DC) VIX (DC) VID (DC)
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VREF + 0.15 –0.3 — –0.3 — 0.5 × VDDQ − 0.2V 0.36 —
0.5 × VDDQ
0.5 × VDDQ + 0.2V V VDDQ + 0.6 V 5, 6
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Notes: 1. 2. 3. 4. 5. 6.
VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement.
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Preliminary Data Sheet E0641E20 (Ver.2.0)
EDD2516KCTA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
max. Parameter Operating current (ACTPRE) Operating current (ACT-READ-PRE) Idle power down standby current Symbol IDD0 IDD1 IDD2P -6B -7A, -7B -6B -7A, -7B Grade -6B -7A, -7B -6B -7A, -7B × 16 110 100 140 130 3 35 30 30 25 20 -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B 55 50 205 180 205 180 200 175 150 Unit mA mA mA mA mA mA mA mA mA mA µA Test condition Notes
CKE ≥ VIH, 1, 2, 9 tRC = tRC (min.) CKE ≥ VIH, BL = 4,CL = 2.5, 1, 2, 5 tRC = tRC (min.) CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 2.5 CKE ≥ VIH, BL = 2 CL = 2.5 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH TA ≤ 70°C, Input ≥ VDD – 0.2V, Input ≤ 0.2V TA = 25°C, typical condition Input ≥ VDD – 0.2V, Input ≤ 0.2V Input ≥ VDD – 0.2V, Input ≤ 0.2V 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6
Floating idle standby current IDD2F Quiet idle standby current Active power down standby current Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto Refresh current IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6SSR
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Super self-refresh current Operating current (4 banks interleaving)
Notes: 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one clock cycle. 6. DQ, DM and DQS transition twice per one clock cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycle. 10. Command/Address stable at ≥ VIH or ≤ VIL. 11. IDD6SSR varies automatically with TA. 12. IDD6SSRENT is average current during tSSRENT. Do not switch to low current power supply with less than IDD6SSRENT during tSSRENT. 13. IDD6SSREX is average current during “Exiting SSR”. Use high current power supply with more than IDD6SSREX during “Exiting SSR”. . 14. Typical value only for reference.
Preliminary Data Sheet E0641E20 (Ver.2.0)
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IDD6SSRPEAK IDD6SSRENT IDD6SSREX IDD7A -6B -7A, -7B
11, 15
40 3.5 3
µA mA mA mA mA
11, 14, 15 15 12 13
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250 350 300
BL = 4
1, 5, 6, 7
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EDD2516KCTA
15. In super self-refresh state, burst refresh period and standby period repeat alternately. IDD6SSR is the average current during whole super self-refresh period (average current for burst refresh period and standby period). IDD6SSRPEAK is the average current during burst refresh period.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter Input leakage current Output leakage current Output high current Output low current Symbol ILI ILO IOH IOL min. –2 –5 –15.2 15.2 max. 2 5 — — Unit µA µA mA mA Test condition VDD ≥ VIN ≥ VSS VDDQ ≥ VOUT ≥ VSS VOUT = 1.95V VOUT = 0.35V Notes
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Parameter Input capacitance Delta input capacitance
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)
Symbol CI1 CI2 Cdi1 Cdi2 CI/O Pins CK, /CK All other input pins CK, /CK All other input-only pins DQ, DM, DQS min. 2.0 2.0 — — 4.0 — typ. — — — — — — max. 3.0 3.0 0.25 0.5 5 0.5 Unit pF pF pF pF pF pF Notes 1 1 1 1 1, 2 1
Data input/output capacitance
Delta input/output capacitance
Notes: 1. These parameters are measured on conditions: TA = +25°C. 2. DOUT circuits are disabled.
Preliminary Data Sheet E0641E20 (Ver.2.0)
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DQ, DM, DQS
f = 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V,
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EDD2516KCTA
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-6B Parameter Clock cycle time (CL = 2) (CL = 2.5) CK high-level width CK low-level width CK half period DQ output access time from CK, /CK DQS output access time from CK, /CK DQS to DQ skew DQ/DQS output hold time from DQS Data hold skew factor Symbol tCK tCK tCH tCL tHP tAC tDQSCK tDQSQ tQH tQHS min. 7.5 6 0.45 0.45 min (tCH, tCL) –0.7 –0.6 — max. 12 12 0.55 0.55 — 0.7 0.6 0.45 -7A min. 7.5 7.5 0.45 0.45 min (tCH, tCL) –0.75 –0.75 — max. 12 12 0.55 0.55 — 0.75 0.75 0.5 -7B min. 10 7.5 0.45 0.45 min (tCH, tCL) –0.75 –0.75 — max 12 12 0.55 0.55 — 0.75 0.75 0.5 Unit ns ns tCK tCK tCK ns ns ns ns ns ns ns tCK tCK ns ns ns ns tCK tCK tCK tCK tCK tCK tCK ns ns ns 8 8 7 9 8 8 7 5, 11 6, 11 2, 11 2, 11 3 Notes 10
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Read preamble Read postamble DQ and DM input setup time DQ and DM input hold time Write preamble setup time Write preamble Write postamble Write command to first DQS latching transition DQS input high pulse width DQS input low pulse width Active to Read/Write delay
tHP – tQHS — — –0.7 –0.7 0.9 0.4 0.45 0.45 1.75 0.55 0.7 0.7 1.1 0.6 — — —
tHP – tQHS — — –0.75 –0.75 0.9 0.4 0.5 0.5 1.75 0 0.75 0.75 0.75 1.1 0.6 — — — — — 0.6 1.25 — —
tHP – tQHS — — –0.75 –0.75 0.9 0.4 0.5 0.5 1.75 0 0.25 0.4 0.75 0.2 0.2 0.75 0.75 0.75 1.1 0.6 — — — — — 0.6 1.25 — — — — — — —
Data-out high-impedance time from tHZ CK, /CK Data-out low-impedance time from tLZ CK, /CK
DQ and DM input pulse width
DQS falling edge to CK setup time tDSS DQS falling edge hold time from CK
Address and control input setup time Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period Auto refresh to Active/Auto refresh command period Precharge to active command period
Address and control input hold time tIH tIPW tMRD tRAS tRC tRFC tRCD tRP
Preliminary Data Sheet E0641E20 (Ver.2.0)
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tRPRE tRPST tDS tDH tDIPW tWPRE tWPST tDQSS tDSH tDQSH tDQSL tIS
tWPRES 0
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— 0.25 — 0.25 0.4 0.6 0.4 0.75 0.2 1.25 — 0.75 0.2 0.2 0.35 0.35 0.75 0.75 2.2 2 42 60 72 18 18 — 0.2 — 0.35 — 0.35 — 0.9 — 0.9 — 2.2 2 45 67.5 75 20 20 — 120000 — — — —
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— 0.35 — 0.35 — 0.9 — 0.9 — 2.2 2 — 120000 — — — — 45 67.5 75 20 20
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— tCK 120000 — ns ns — ns — ns — ns
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EDD2516KCTA
-6B Parameter Active to Autoprecharge delay Active to active command period Write recovery time Symbol tRAP tRRD tWR min. tRCD min. 12 15 max. — — — -7A min. tRCD min. 15 15 max. — — — -7B min. tRCD min. 15 15 max — — — Unit ns ns ns tCK tCK µs s ms 14 13 Notes
Auto precharge write recovery and tDAL precharge time Internal write to Read command tWTR delay Average periodic refresh interval Super self-refresh entry time tREF
(tWR/tCK)+ — (tRP/tCK) 1 — — 7.8 30 —
(tWR/tCK)+ — (tRP/tCK) 1 — — 200 — 7.8 30 —
(tWR/tCK)+ — (tRP/tCK) 1 — — 200 — 7.8 30 —
tSSRENT — 200
SSR exit command to non refresh command delay tSSREX (SSRX command during “super self-refresh“) (SSRX command during “Entering tSSREX SSR”) SSR flag hold time tSSRFH tSSRFD tFDSSR SSR flag delay time
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SSR exit flag delay time
1.5 1 — — 0.2 0.2 —
— — 40 40 200 1.5 1
1.5 1 — — 0.2 0.2 —
— — 40 40 200 1.5 1
1.5 1 — — 0.2 0.2 —
— — 40 40 200 1.5 1
ms µs ns ns ms ms µs
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SSR exit flag hold time (SSRX command during “super tFHSSR self-refresh“) (SSRX command during “Entering tFHSSR SSR”) Flag reset delay time by SSR tFRD command
14 14
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see ‘Timing Waveforms’ section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle.
Preliminary Data Sheet E0641E20 (Ver.2.0)
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EDD2516KCTA
13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For -7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks 14. When the memory is in “Exiting SSR” state, any command except SSR is ignored. If SF pin is monitored by the system and as soon as it returns to low (tFHSSR), any command for IDLE state will be accepted by the memory. (tSSREX is "Don't care" in this case. ) If SF pin is not monitored, tSSREX has to be satisfied. (Issue auto refresh command repeatedly at less than 7.8μs interval during tSSREX.) Test Conditions
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Parameter Input reference voltage Termination voltage Input high voltage Input low voltage Input signal slew rate
Symbol VREF VTT VIH (AC) VIL (AC) VID (AC) VIX (AC)
Value VDDQ/2 VREF VREF + 0.31 VREF − 0.31 0.62 VREF 1
Unit V V V V V V V/ns
Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs
Preliminary Data Sheet E0641E20 (Ver.2.0)
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CK VID /CK
SLEW
tCK
VDD VREF VSS
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tCL tCH VIX VIH VIL Δt VTT Measurement point DQ CL = 30pF RT = 50Ω
VDD VREF VSS
SLEW = (VIH (AC) – VIL (AC))/Δt
Input Waveforms and Output Load
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EDD2516KCTA
Timing Parameter Measured in Clock Cycle
Number of clock cycle tCK Parameter Symbol 6ns min. 4 + BL/2 BL/2 2 + BL/2 — 3 — 2.5 — 3 + BL/2 — 2.5 1 3 0 2 1 1 max. — — — — — — 2.5 — — — 2.5 1 — 0 — 1 — 7.5ns min. 3 + BL/2 BL/2 2 + BL/2 2 3 2 2.5 2 + BL/2 3 + BL/2 2 2.5 1 2 0 2 1 1 max. — — — — — 2 2.5 — — 2 2.5 1 — 0 — 1 — Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
Write to pre-charge command delay (same bank) tWPD Read to pre-charge command delay (same bank) tRPD Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) (CL = 2.5) Burst stop command to DQ High-Z (CL = 2) tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tDMD tMRD tPDEN tPDEX
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(CL = 2.5) (CL = 2.5) (CL = 2.5) Write recovery DM to data in latency Power down entry
Read command to write command delay (to output all data) (CL = 2) Pre-charge command to High-Z (CL = 2) Write command to data in latency
Mode register set command cycle time
Power down exit to command input
Preliminary Data Sheet E0641E20 (Ver.2.0)
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EDD2516KCTA
Block Diagram
CK /CK CKE
Clock generator
Bank 3 Bank 2 Bank 1
A0 to A12, BA0, BA1
Mode register
Row address buffer and refresh counter
Row decoder
Memory cell array Bank 0
Command decoder
/CS /RAS /CAS /WE
Control logic
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Sense amp. Column address buffer and burst counter Column decoder
Preliminary Data Sheet E0641E20 (Ver.2.0)
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Data control circuit
Latch circuit
DQS
Pr
CK, /CK DLL
Input & Output buffer
DM
DQ
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EDD2516KCTA
Pin Function
CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /CS (input pin) When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the /CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0 to the A8 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This column address becomes the starting address of a burst operation. [Address Pins Table]
Part number EDD2516KCTA
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Bank 0 Bank 1 Bank 2 Bank 3
A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0 L H L H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E0641E20 (Ver.2.0)
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Address (A0 to A12) Column address AY0 to AY8
Row address AX0 to AX12
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BA1 L L H H
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EDD2516KCTA
CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low. CKE controls power down and super self-refresh. The power down and the super self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or write access. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold time tIH. UDM, LDM (input pin) DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DMs provide the byte mask function. In × 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM controls the upper byte (DQ8 to DQ15) of write data. When DM = High, the data input at the same timing are masked while the internal burst counter will be count up.
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DQ0 to DQ15 (input and output pins) Data is input to and output from these pins.
UDQS, LDQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. SF (SSR Flag, output pin) SSR Flag has 3 purposes. • SSR identification flag: To show the memory is SSR (High for tSSRFH when MRS/EMRS command is issued). • SSR exit flag: To show “Exiting SSR” duration. • SSR uncorrectable flag: To show error correction result (returns to low if success, keeps high if fail. (If fail, flag is reset by EMRS/MRS command.))
Preliminary Data Sheet E0641E20 (Ver.2.0)
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EDD2516KCTA
Command Operation
Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal.
CKE Command Ignore command No operation Burst stop in read command Column address and read command Read with auto-precharge Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL REF SSR MRS n–1 H H H H H H H H H H H H H H n H H H H H H H H H H H L H H /CS H L L L L L L L L L L L L L /RAS /CAS /WE × H H H H H H L L L L L L L × H H L L L L H H H L L L L × H L H H L L H L L H H L L BA1 × × × V V V V V V × × × L L BA0 × × × V V V V V V × × × L H AP × × × L H L H V L H × × L L Address × × × V V V V V × × × × V V
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Write with auto-precharge Precharge select bank Precharge all bank Refresh Super self-refresh Mode register set
Column address and write command
Row address strobe and bank active
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input Note: The CKE level must be kept for 1 CK cycle at least. Ignore command [DESL] When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal status is held. No operation [NOP] As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST] This command stops a burst read operation, which is not applicable for a burst write operation. Column address strobe and read command [READ] This command starts a read operation. The start address of the burst read is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation, the output buffer becomes High-Z. Read with auto-precharge [READA] This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT] This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
EMRS
Pr
14
od
t uc
EDD2516KCTA
Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 L H L H BA1 L L H H
EO
CKE Truth Table
Current state Idle Idle Power down
Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SSR] This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is super self-refresh. For details, refer to the CKE truth table section. Mode register set/Extended mode register set [MRS/EMRS] The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode register set cycle. For details, refer to "Mode register and extended mode register set".
Idle or Exiting SSR Super self-refresh entry (SSR) Power down entry (PDEN)
Entering SSR or Super self-refresh exit (SSRX) Super self-refresh Power down exit (PDEX)
Remark: H: VIH. L: VIL. ×: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Command
Auto-refresh command (REF)
Pr
CKE n–1 n /CS H H L H L L H L L H L L H H L L H H L L L H H H
/RAS L L H ×
/CAS L L H ×
/WE H H H ×
Address × × × × × × × ×
Notes 2 2
od
H × × H × × × × H H
H
H
t uc
15
EDD2516KCTA
Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM.
Current state Precharging*1 /CS H L L L L L L L
2
/RAS /CAS /WE × H H H H L L L × × H H L L H H L × H H L L H H × H L H L H L × × H L H L H L
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × MODE × × × ×
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP ILLEGAL*
11
Next state ldle ldle — — — — ldle — ldle ldle
11 11
ILLEGAL*11 ILLEGAL*
11 11
ILLEGAL* NOP ILLEGAL
EO
Idle* H L L L L L L L L Refresh (auto-refresh)*3 H L L L L Activating*4 H L L L L L L L Active*5 H L L L L L L L
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL REF, SSR MRS DESL NOP BST
NOP NOP ILLEGAL* ILLEGAL*
H H H H
— — — Active ldle ldle/ Super selfrefresh ldle ldle ldle — — — Active Active — — — — — — Active
ILLEGAL*11 Activating NOP Refresh/ Super self-refresh*12 Mode register set*12 NOP NOP ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL*11
11
L L
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
L L H L L × H H H L × H H H H L L L × H H H H L L L L × H × H L × H L × × × × H H L H L H L × × H L H L H L × H L L H H L × H H L L H H L
Pr
× × DESL NOP BST × × BA, CA, A10 READ/READA WRIT/WRITA ACT BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × PRE, PALL DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
od
ILLEGAL*11 ILLEGAL*11
11
ILLEGAL*
ILLEGAL*
ILLEGAL
t uc
NOP NOP Active ILLEGAL Active Starting read operation Read/READA Write Starting write operation recovering/ precharging ILLEGAL*11 — Pre-charge Idle ILLEGAL —
16
EDD2516KCTA
Current state Read*
6
/CS H L L L L L L L
/RAS /CAS /WE × H H H H L L L × × H H L L H H L × H H L L H H L × H L H L H L × × H L H L H L ×
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × × × ×
Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
Operation NOP NOP BST Interrupting burst read operation to start new read ILLEGAL*13 ILLEGAL*
11
Next state Active Active Active Active — — Precharging — Precharging Precharging — — — — — — Write recovering Write recovering — Read/ReadA
14
Interrupting burst read operation to start pre-charge ILLEGAL
EO
Read with auto-preH charge*7 L L L L L L L Write*
8
DESL NOP BST READ/READA WRIT/WRITA ACT PRE, PALL
NOP NOP ILLEGAL ILLEGAL*14 ILLEGAL* ILLEGAL*11, 14 ILLEGAL* ILLEGAL
11, 14
H H H H
L L L ×
Write recovering*
9
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
H × × L H H H L L L H H H L H L L L L H L L L L L L L H L L L × H H H H L L L L L H H L × × H L H L H L × H L × H H L L H H L
DESL NOP BST
NOP NOP ILLEGAL Interrupting burst write operation to start read operation. Interrupting burst write operation to start new write operation. ILLEGAL*11 Interrupting write operation to start precharge.
Pr
BA, CA, A10 BA, CA, A10 BA, RA ACT BA, A10 × × × × PRE, PALL DESL NOP BST BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × ACT PRE/PALL
READ/READA
WRIT/WRITA
Write/WriteA — Idle — Active Active —
od
ILLEGAL NOP NOP ILLEGAL READ/READA WRIT/WRITA ILLEGAL*
11 11
t uc
Starting read operation. Read/ReadA Write/WriteA Starting new write operation. ILLEGAL* — — ILLEGAL —
17
EDD2516KCTA
Current state Write with autopre-charge*10
/CS H L L L L L L L
/RAS /CAS /WE × H H H H L L L × H H L L H H L × H L H L H L ×
Address × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
Command DESL NOP BST READ/READA WRIT/WRIT A ACT PRE, PALL
Operation NOP NOP ILLEGAL ILLEGAL* ILLEGAL*
14 14
Next state Precharging Precharging — — — — — —
ILLEGAL*11, 14 ILLEGAL* ILLEGAL
11, 14
Remark: Notes: 1. 2. 3. 4. 5. 6.
H: VIH. L: VIL. ×: VIH or VIL The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.) The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below.
EO
From command Read w/AP Write w/AP
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Read or Read w/AP Write or Write w/AP Read or Read w/AP Write or Write w/AP
To command (different bank, noninterrupting command)
Precharge or Activate
Precharge or Activate
Pr
BL/2 1 BL/2 1
od
Minimum delay (Concurrent AP supported) CL(rounded up)+ (BL/2) 1 + (BL/2) + tWTR
Units tCK tCK tCK tCK
t uc
tCK tCK
18
EDD2516KCTA
Command Truth Table for CKE
CKE Current State Super self-refresh n–1 n H L L L L L Entering super self*2 refresh H L × H H H H L × H H H H L H H L /CS × H L L L × × H L L L × H L L /RAS /CAS /WE Address × × H H L × × × H H L × × H L × × H L × × × × H L × × × H L L × × H L × × × × × × H L L × × H L L × × × × × × × × × × × × × × × × × H × × × × × × × × × × × × H L × × × H L × × × × × × × × × × × × × × × × × × × × × × × × × × × Operation INVALID, CK (n-1) would exit super self-refresh Exit super self-refresh Exit super self-refresh ILLEGAL ILLEGAL Maintain super self-refresh INVALID, CK (n-1) would exit super self-refresh Exit super self-refresh Exit super self-refresh ILLEGAL ILLEGAL Continue super self-refresh entry (super self-refresh after tSSRENT) Idle after tFHSSR Idle after tFHSSR Super self-refresh entry ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes
EO
L L L L Exiting super self*3 refresh H H H H H H H H H Power down H L L L All banks idle H H H H H H H H H H L Row active H L
Remark: H: VIH. L: VIL. ×: VIH or VIL
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
H L H L H L L H × L L L × H H L H H H H H L L L L L × × × L H L × H L × × × × H L L L × H L L L × × × L H L × H H L L L L H L L L L × × ×
Pr
× × × × H H ×
INVALID, CK (n – 1) would exit power down EXIT power down → Idle
Maintain power down mode
od
CBR (auto) refresh Super self-refresh Power down Power down
Refer to operations in Function Truth Table Refer to operations in Function Truth Table
Refer to operations in Function Truth Table
OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table
OPCODE Refer to operations in Function Truth Table
Refer to operations in Function Truth Table
t uc
1 1 1
19
EDD2516KCTA
Notes: 1. Super self-refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. The device is in “Entering super self-refresh” state during tSSRENT. 3. The device is in “Exiting super self-refresh” state during tFHSSR. Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 7.8 μs. The output buffer becomes High-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command. Super self-refresh entry [SSR] This command starts super self-refresh. The super self-refresh operation continues as long as CKE is held Low. During the super self-refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A super self-refresh is terminated by a super self-refresh exit command. Power down mode entry [PDEN] tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. Super self-refresh exit [SSRX] This command is executed to exit from super self-refresh mode (After tFHSSR from SSRX command, the device becomes IDLE). If SSR Exit flag is not monitored by the system, issue auto refresh command repeatedly at less than 7.8μs interval during tSSREX. Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
EO
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Pr
20
od t uc
EDD2516KCTA
Simplified State Diagram
SUPER SELF REFRESH ENTERING SSR SSRX SSR SSR SSRX
EXITING SSR
EO
POWER APPLIED
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKE CKE_ ACTIVE CKE_ CKE ROW ACTIVE IDLE POWER DOWN
ACTIVE POWER DOWN
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Write WRITE WRITE WITH AP WRITEA POWER ON
BST READ
WRITE WRITE WITH AP READ READ WITH AP READ WITH AP
Read
READ
Automatic transition after completion of command. Transition resulting from command input.
Pr
PRECHARGE READA PRECHARGE PRECHARGE
PRECHARGING
READ WITH AP
od t uc
21
PRECHARGE
EDD2516KCTA
Operation of the DDR SDRAM
Power-up Sequence (1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 µs. (3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device. (8) Issue 2 or more auto-refresh commands. (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL.
(4) (5) (6) (7) (8) (9)
EO
CK /CK
Command
PALL
EMRS
MRS
PALL tRP
REF REF tRFC
REF tRFC
MRS 2 cycles (min.)
Any command
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters shown in the table bellow are allowed to input to the registers.
L
2 cycles (min.) DLL enable
2 cycles (min.) 2 cycles (min.) DLL reset with A8 = High
Disable DLL reset with A8 = Low 200 cycles (min)
Power-up Sequence after CKE Goes High
Pr
A8 DR A7 0 A6 A5 0 0 LMODE 1 1 0 2.5
od
A4 A3 A2 BT A3 Burst Type 0 Sequential 1 Interleave 0 0 0 0 1 1
BA0 0
BA1 0
A12 0
A11 A10 A9 0
A1 BL
A0
MRS
t uc
A2 A1 A0 1 0 1 Burst Length BT=0 BT=1 2 2 4 4 8 8
A8 DLL Reset A6 A5 A4 CAS Latency 2 010 0 No 1 Yes
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
Preliminary Data Sheet E0641E20 (Ver.2.0)
22
EDD2516KCTA
BA0 BA1 1 0 A12 A11 A10 A9 0 0 0 0 A8 0 A7 0 A6 0 A5 0 A4 0 A3 0 A2 0 A1 DS A0 DLL
EMRS A1 Driver Strength 0 Normal 1 Weak A0 DLL Control 0 DLL Enable 1 DLL Disable
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0) Burst Operation The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2 A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 7, 0, 1, 2, 3, 4, 5, 6, A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
EO
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1
Starting Ad. Addressing(decimal)
Burst length = 8 Starting Ad.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
0 1 0 1 0 1 0 1
A0 Sequence
Pr
6, 7, 0, 1, 2, 3, 4, 5,
4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0,
od t uc
23
Read/Write Operations
Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued. Read operation The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble.
t0 t1 t4 t5 t6 t7 t8 t9
CK
/CK
Command
Address
DQS DQ
Preliminary Data Sheet E0641E20 (Ver.2.0)
; ;;
EDD2516KCTA
tRCD
EO
NOP
L
ACT Row BL = 2 BL = 4 BL = 8
NOP
READ
NOP
Column
tRPRE
Pr
24
out0 out1
tRPST
out0 out1 out2 out3
Read Operation (Burst Length)
od
out0 out1 out2 out3 out4 out5 out6 out7
CL = 2 BL: Burst length
t uc
;;;; ;
EDD2516KCTA
t5 t5.5 t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 CK /CK Command READ NOP tRPRE tRPST DQS VTT CL = 2 tAC,tDQSCK DQ out0 out1 out2 out3 VTT tRPRE tRPST DQS VTT CL = 2.5 tAC,tDQSCK DQ out0 out1 out2 out3 VTT
; ;
Command NOP ACT NOP WRITE NOP
EO
t0 CK /CK Address DQS DQ
Read Operation (/CAS Latency)
Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
t1 tRCD Row BL = 2 BL = 4 BL = 8
Pr
tn tn+0.5 tn+1 tn+2 Column tWPRE tWPRES in0 in1 in0 in1 in2 in0 in1 in2
tn+3
tn+4
tn+5
Write Operation
od
tWPST in3 in3 in4 in5 in6
t uc
in7 BL: Burst length
25
EDD2516KCTA
Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed.
t0 CK /CK t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5
Command
READ
BST tBSTZ
NOP 2 cycles
EO
DQS CL = 2 DQ DQS CL = 2.5 DQ
out0
out1 2.5 cycles
tBSTZ
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
26
out0
out1
CL: /CAS latency
Burst Stop during a Read Operation
Pr
od t uc
EDD2516KCTA
Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. Refer to ‘Function truth table and related note(Notes.*14).
CK /CK tRAP (min) = tRCD (min) tRPD 2 cycles (= BL/2) tRP (min)
EO
Command ACT DQS DQ
READA
NOP
ACT
tAC,tDQSCK out0 out1 out2 out3
Note: Internal auto-precharge starts at the timing indicated by "
Write with auto-precharge The precharge is automatically performed after completing a burst write operation. The precharge operation is started (BL/ 2 + 3) cycles after WRITA command issued. A column command to the other banks can be issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with Auto-Precharge Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14).
L
tRCD (min) ACT NOP
".
Read with auto-precharge
Pr
tRAS (min) WRITA NOP BL/2 + 3 cycles in1 in2 in3 ". in4
od
Burst Write (BL = 4) 27
CK /CK
tRP ACT
Command
t uc
BL = 4
DM DQS
DQ
Note: Internal auto-precharge starts at the timing indicated by "
Preliminary Data Sheet E0641E20 (Ver.2.0)
Command Intervals
A Read command to the consecutive Read command Interval
Destination row of the consecutive read command Bank address 1. Same
2.
Same
3.
Different
Preliminary Data Sheet E0641E20 (Ver.2.0)
; ;;; ;
EDD2516KCTA
Row address State Operation Same ACTIVE Different — Any ACTIVE IDLE The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank without interrupting the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued.
t0 t3 t4 t5 t6 t7 t8 t9 CK /CK Command ACT NOP READ READ NOP
EO
Address BA Row DQ DQS Bank0 Active
L
Column A Column B
READ to READ Command Interval (same ROW address in the same bank)
Pr
out out A0 A1 Column = A Column = B Read Read
out B0
out B1
out B2
out B3
Column = A Dout
Column = B Dout
od
28
CL = 2 BL = 4 Bank0
t uc
EDD2516KCTA
t0 CK /CK Command ACT Row0 NOP ACT Row1 NOP READ READ NOP t1 t2 t3 t4 t5 t6 t7 t8 t9
Address BA
Column A Column B
DQ Column = A Column = B Read Read
out out A0 A1 Bank0 Dout
out out out out B0 B1 B2 B3 Bank3 Dout
EO
DQS Bank0 Active
Bank3 Active
Bank0 Read
Bank3 Read
CL = 2 BL = 4
READ to READ Command Interval (different bank)
Preliminary Data Sheet E0641E20 (Ver.2.0)
L Pr od t uc
29
A Write command to the consecutive Write command Interval
Destination row of the consecutive write command Bank address 1. Same Row address State
2.
Same
3.
Different
CK
/CK
Command
Address
BA
DQ
DQS
Preliminary Data Sheet E0641E20 (Ver.2.0)
;;;;;
EDD2516KCTA
Operation Same ACTIVE Different — Any ACTIVE IDLE The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A write command to the consecutive precharge interval’ section. The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued.
t0 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 ACT Row NOP WRIT WRIT NOP Column A Column B
EO
Bank0 Active
L
inA0 inA1 inB0 inB1 inB2 inB3 Column = B Write
WRITE to WRITE Command Interval (same ROW address in the same bank)
Pr
Column = A Write
BL = 4 Bank0
od
30
t uc
CK /CK Command
Address BA
DQ
DQS
;;;; ;;
EDD2516KCTA
tn+4 tn+5 t0 t1 t2 tn tn+1 tn+2 tn+3 ACT NOP ACT NOP WRIT WRIT NOP Row0 Row1 Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Write Bank3 Write Bank0 Active Bank3 Active BL = 4 Bank0, 3
EO
WRITE to WRITE Command Interval (different bank)
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Pr
31
od
t uc
EDD2516KCTA
A Read command to the consecutive Write command interval with the BST command
Destination row of the consecutive write command Bank address 1. Same Row address State Same ACTIVE Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A read command to the consecutive precharge interval’ section. Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
EO
t0 CK /CK Command READ DM DQ High-Z DQS
t1
t2
t3
t4
t5
t6
t7
t8
BST
NOP tBSTW (≥ tBSTZ)
WRIT
NOP
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
tBSTZ (= CL)
Pr
out0 out1 in0 in1 OUTPUT
in2
in3
READ to WRITE Command Interval
od
INPUT
BL = 4 CL = 2
t uc
32
EDD2516KCTA
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read command Bank address 1. Same Row address State Same ACTIVE Operation To complete the burst operation, the consecutive read command should be performed tWRD (= BL/ 2 + 2) after the write command. Precharge the bank tWPD after the preceding write command. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. To complete a burst operation, the consecutive read command should be performed tWRD (= BL/ 2 + 2) after the write command. Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued.
2.
Same
Different
—
3.
Different
Any
ACTIVE IDLE
EO
t0 CK /CK Command WRIT DM DQ DQS
t1
t2
t3
t4
t5
t6
NOP tWRD (min) tWTR*
READ
NOP
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
in0
BL/2 + 2 cycle
Pr
in1 in2 in3
out0
out1
out2
od
33
INPUT
OUTPUT BL = 4 CL = 2
WRITE to READ Command Interval
t uc
EDD2516KCTA
A Write command to the consecutive Read command interval: To interrupt the write operation
Destination row of the consecutive read command Bank address 1. 2. 3. Same Same Different Row address State Same Different Any ACTIVE — ACTIVE IDLE Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. —*1 DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. —*1
Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Same bank, same ROW address)
t0 t1 t2 t3 t4 t5 t6 t7 t8
EO
CK /CK Command WRIT DM DQ DQS
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
READ 1 cycle in0 in1
NOP
CL=2
Data masked
Pr
in2
out0 out1 out2 out3
High-Z High-Z
[WRITE to READ delay = 1 clock cycle]
od
34
BL = 4 CL= 2
t uc
EDD2516KCTA
t0 CK /CK t1 t2 t3 t4 t5 t6 t7 t8
Command
WRIT
NOP 2 cycle
READ CL=2
NOP
DM
DQ
in0
in1
in2
in3
out0 out1 out2 out3
High-Z High-Z
EO
DQS
t0 CK /CK Command WRIT DM DQ DQS
Data masked
BL = 4 CL= 2
[WRITE to READ delay = 2 clock cycle]
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
t1 NOP in0 in1
t2
t3
t4
t5
t6
t7
t8
Pr
READ 3 cycle CL=2 tWTR* in2 in3 Data masked
NOP
[WRITE to READ delay = 3 clock cycle]
od
35
out0 out1 out2 out3
BL = 4 CL= 2
t uc
EDD2516KCTA
A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued.
t0 CK /CK Command NOP
READ
t1
t2
t3
t4
t5
t6
t7
t8
NOP
PRE/ PALL
NOP
DQ
out0 out1 out2 out3
DQS
EO
t0 CK /CK Command NOP DQ DQS
tRPD = BL/2
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
t1
t2
t3
t4
t5
t6
t7
t8
READ
NOP
PRE/ PALL
NOP
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2.5, BL = 4)
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
tRPD = BL/2
out0 out1 out2 out3
Pr
36
od t uc
EDD2516KCTA
READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP (= CL) after the precharge command.
t0 CK /CK Command NOP READ PRE/PALL NOP High-Z t1 t2 t3 t4 t5 t6 t7 t8
DQ
out0 out1
DQS
High-Z
EO
t0 CK /CK Command DQ DQS
tHZP
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 2, 4, 8)
t1
t2
t3
t4
t5
t6
t7
t8
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2.5, BL = 2, 4, 8)
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
NOP
READ
PRE/PALL CL = 2.5 out0 out1
NOP High-Z
High-Z
Pr
tHZP
od t uc
37
A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command.
t0 t1 t2 t3 t4 t5 t6
CK
/CK
Command
DM
DQS
DQ
Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM.
CK
/CK
Command
DM
DQS
DQ
Preliminary Data Sheet E0641E20 (Ver.2.0)
;;;;;;; ;; ;
EDD2516KCTA
t7 WRIT NOP PRE/PALL NOP tWPD tWR in0 in1 in2 in3 Last data input
EO
t0 WRIT
WRITE to PRECHARGE Command Interval (same bank) (BL = 4)
L
t1 in0 in1
Precharge Termination in Write Cycles (same bank) (BL = 4)
Pr
t2 t3 t4 NOP tWR in2 in3 Data masked
t5
t6
t7
PRE/PALL
NOP
od
38
t uc
EDD2516KCTA
Bank active command interval
Destination row of the consecutive ACT command Bank address 1. 2. Same Different Row address Any Any State ACTIVE ACTIVE IDLE Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued. tRRD after an ACT command, the next ACT command can be issued.
CK /CK
EO
Command ACTV ACT Address ROW: 0 BA Bank0 Active
Preliminary Data Sheet E0641E20 (Ver.2.0)
ACT
NOP
PRE
NOP
ACT
NOP
ROW: 1
ROW: 0
tRRD
Bank3 Active tRC
Bank0 Precharge
Bank0 Active
Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD.
CK /CK Command
L
MRS Address CODE
Bank Active to Bank Active
Mode Register Set
Pr
NOP tMRD
ACT
NOP
od
BS and ROW Bank3 Active
t uc
39
EDD2516KCTA
DM Control DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data, respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0.
t1 DQS t2 t3 t4 t5 t6
DQ
Mask
Mask
EO
DM
Preliminary Data Sheet E0641E20 (Ver.2.0)
Write mask latency = 0
DM Control
L Pr od t uc
40
EDD2516KCTA
SSR-Flag Function This function is to show that the memory is SSR. When MRS or EMRS command is issued, SF becomes high after tSSRFD delay and returns to low when tSSRFH is satisfied. If another MRS/EMRS command follows previous MRS/EMRS command with less than tSSRFH interval, SF stays high until tSSRFH for later MRS/EMRS command is satisfied.
CK /CK Command
MRS or EMRS
NOP tSSRFD
NOP
NOP
NOP
NOP
NOP
SF
EO
CK /CK Command EMRS SF
CK /CK CKE Command
SSR
tSSRFH
NOP tMRD tSSRFD
MRS
NOP
NOP
NOP
NOP
SSR Re-Entry during “Exiting SSR” State
When SSR command is issued during “Exiting SSR” state, SF is driven low after tFRD delay.
L
NOP
tSSRFH-1 tSSRFH-2
Pr
SSRX NOP tFDSSR
SSR Identification Flag Function
od
tFRD
SSR
NOP
NOP
t uc
tFHSSR
SF
Preliminary Data Sheet E0641E20 (Ver.2.0)
41
Timing Waveforms
Command and Addresses Input Timing Definition
CK /CK
Read Timing Definition
/CK CK
DQS
DQ (Dout)
Write Timing Definition
/CK CK
DQS
DQ (Din)
DM
Preliminary Data Sheet E0641E20 (Ver.2.0)
;;;;;;
EDD2516KCTA
tIS tIH Command (/RAS, /CAS, /WE, /CS) VREF tIS tIH Address VREF
EO
tCK
tCH
tCL
tDQSCK
tDQSCK
tDQSCK
tDQSCK tRPST
tRPRE
tDQSQ
tLZ
tAC
tQH tAC
tDQSQ
tAC
tQH tHZ
L
tCK tDQSS tWPRES tWPRE tDS tDS
tQH
tDQSQ tQH
tDQSQ
Pr
tDSS tDQSL tDH tDH
tDSH
tDSS
VREF
tDQSH
tWPST
od
tDIPW tDIPW tDIPW
VREF
VREF
t uc
42
EDD2516KCTA
Read Cycle
tCK tCH tCL
; ;; ; ;; ; ;;
CK /CK VIH tRC CKE tRCD tRAS tRP tIS tIH tIS tIH tIS tIH tIS tIH /CS tIS tIH tIS tIH tIS tIH tIS tIH /RAS
; ;; ;; ; ;
A10 tIS tIH tIS tIH tIS tIH Address
EO
tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH DM DQS DQ (output) Bank Bank 0 Active
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
High-Z High-Z
Pr
tRPRE Bank 0 Read
tRPST
od
Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = VIH or VIL
t uc
43
;;; ;; ; ; ;
EDD2516KCTA
Write Cycle
tCK tCH tCL CK /CK VIH tRC CKE tRAS tRCD tRP tIS tIH tIS tIH tIS tIH tIS tIH /CS tIS tIH tIS tIH tIS tIH tIS tIH /RAS
EO
tIS tIH /CAS tIS tIH /WE tIS tIH BA tIS tIH A10 tIS tIH Address DQS (input) DM DQ (input) Bank Bank 0 Active
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
tIS tIH Bank 0 Write
tIS tIH
tDQSS
tDQSL
tWPST
Pr
tDQSH tDS tDS
tDH
tDS
tDH
od
tWR
tDH
Bank 0 Precharge
CL = 2 BL = 4 Bank0 Access = VIH or VIL
t uc
44
EDD2516KCTA
Mode Register Set Cycle (SSR-Flag Function)
/CK CK CKE /CS /RAS /CAS /WE VIH
EO
BA Address DM valid DQS DQ (output) SF
code code R: b C: b
High-Z High-Z b
Read/Write Cycle
/CK CK CKE /CS /RAS /CAS /WE BA Address DM DQS DQ (output) DQ (input) Bank 0 Active R:a
VIH
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
tRP Precharge If needed
C:a R:b High-Z
tSSRFD tSSRFH Bank 3 Active Bank 3 Read Bank 3 Precharge CL = 2 BL = 4 = VIH or VIL
MRS or EMRS command
Pr
a tRWD Bank 0 Bank 3 Read Active
od
C:b b Bank 3 Write tWRD
C:b''
t uc
b’’ Bank 3 Read Read cycle CL = 2 BL = 4 =VIH or VIL
45
EDD2516KCTA
Auto Refresh Cycle
/CK CK CKE /CS /RAS /CAS /WE VIH
EO
BA Address DM DQS DQ (output) DQ (input)
A10=1
R: b
C: b
b High-Z tRFC Bank 0 Active Bank 0 Read CL = 2 BL = 4 = VIH or VIL tRP
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Precharge If needed
Auto Refresh
Pr od
46
t uc
EDD2516KCTA
Super Self-Refresh Cycle SSR Exit-Flag Function: When the error correction is successful.
/CK CK CKE /CS /RAS
tIS CKE = low
tIH
/CAS
EO
/WE BA Address A10=1
R: b
L
High-Z High-Z High-Z
DM DQS DQ (output)
Pr
tSSRENT
DQ (input) SF tRP
tSSREX tFDSSR tFHSSR
Precharge If needed
SSR command
SSRX command
Auto Refresh
Auto Refresh
Bank 0 Active = VIH or VIL
od
Preliminary Data Sheet E0641E20 (Ver.2.0)
t uc
47
EDD2516KCTA
SSR Uncorrectable-Flag Function: When the error correction fails.
/CK CK CKE /CS /RAS tIS CKE = low
tIH
/CAS
/WE
BA
code
EO
Address A10=1 DM DQS
code
High-Z High-Z High-Z
DQ (output)
DQ (input)
L
tRP tSSRENT
SF
tSSREX tFDSSR tFHSSR
tSSRFH
Precharge If needed
SSR command
SSRX command
Auto Refresh
Auto Refresh
MRS/EMRS command
SSR Uncorrectable flag reset = VIH or VIL
Preliminary Data Sheet E0641E20 (Ver.2.0)
Pr od
48
t uc
EDD2516KCTA
Package Drawing
66-pin Plastic TSOP (II) Solder plating: Lead free (Sn-Bi)
Unit: mm
22.22 ± 0.10 *1
A
66
34
PIN#1 ID
1
0.65
33
B 0.80 Nom 0 to 8°
0.17 to 0.32
0.13 M S A B
11.76 ± 0.20
10.16
1.0 ± 0.05
1.20 max
0.09 to 0.20
S
0.10 S
0.10 +0.08 −0.05
EO
0.91 max.
0.25
Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. ECA-TS2-0029-01
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
0.60 ± 0.15
Pr
49
od t uc
EDD2516KCTA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD2516KCTA. Type of Surface Mount Device EDD2516KCTA: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) >
EO
Preliminary Data Sheet E0641E20 (Ver.2.0)
L Pr od t uc
50
EDD2516KCTA
N OTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
EO
2 3
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Pr
51
CME0107
od t uc
EDD2516KCTA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Preliminary Data Sheet E0641E20 (Ver.2.0)
L
Pr
52
M01E0107
od t uc
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