EDJ1116BABG-AG-E

DATA SHEET 1G bits DDR3 SDRAM EDJ1108BABG (128M words × 8 bits) EDJ1116BABG (64M words × 16 bits) Specifications • Density: 1G bits Organization  16M words × 8 bits × 8 banks (EDJ1108BABG)  8M words × 16 bits × 8 banks (EDJ1116BABG) • Package  78-ball FBGA (EDJ1108BABG)  96-ball FBGA (EDJ1116BABG)  Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 1.5V ± 0.075V • Data rate  1600Mbps/1333Mbps/1066Mbps/800Mbps (max.) • 1KB page size (EDJ1108BABG)  Row address: A0 to A13  Column address: A0 to A9 • 2KB page size (EDJ1116BABG)  Row address: A0 to A12  Column address: A0 to A9 • Eight internal banks for concurrent operation • Interface: SSTL_15 • Burst lengths (BL): 8 and 4 with Burst Chop (BC) • Burst type (BT):  Sequential (8, 4 with BC)  Interleave (8, 4 with BC) • /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11 • /CAS Write Latency (CWL): 5, 6, 7, 8 • Precharge: auto precharge option for each burst access • Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω) • Refresh: auto-refresh, self-refresh Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • On-Die Termination (ODT) for better signal quality  Synchronous ODT  Dynamic ODT  Asynchronous ODT • Multi Purpose Register (MPR) for temperature read out • ZQ calibration for DQ drive and ODT • Programmable Partial Array Self-Refresh (PASR) • /RESET pin for Power-up sequence and reset function • SRT range:  Normal/extended  Auto/manual self-refresh • Programmable Output driver impedance control • Refresh cycles  Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range  TC = 0°C to +95°C Document No. E1248E40 (Ver. 4.0) Date Published April 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007-2009 EDJ1108BABG, EDJ1116BABG Ordering Information Part number EDJ1108BABG-GL-E EDJ1108BABG-GN-E EDJ1108BABG-DG-E EDJ1108BABG-DJ-E EDJ1108BABG-AC-E EDJ1108BABG-AE-E EDJ1108BABG-AG-E EDJ1108BABG-8A-E EDJ1108BABG-8C-E EDJ1116BABG-DG-E EDJ1116BABG-DJ-E EDJ1116BABG-AC-E EDJ1116BABG-AE-E EDJ1116BABG-AG-E EDJ1116BABG-8A-E EDJ1116BABG-8C-E Die revision Organization (words × bits) Internal banks JEDEC speed bin (CL-tRCD-tRP) DDR3-1600J (10-10-10) DDR3-1600K (11-11-11) DDR3-1333G (8-8-8) DDR3-1333H (9-9-9) DDR3-1066E (6-6-6) DDR3-1066F (7-7-7) DDR3-1066G (8-8-8) DDR3-800D (5-5-5) DDR3-800E (6-6-6) DDR3-1333G (8-8-8) DDR3-1333H (9-9-9) DDR3-1066E (6-6-6) DDR3-1066F (7-7-7) DDR3-1066G (8-8-8) DDR3-800D (5-5-5) DDR3-800E (6-6-6) Package A 128M × 8 8 78-ball FBGA 64M × 16 96-ball FBGA Part Number E D J 11 08 B A BG - GL - E Elpida Memory Type D: Monolithic Device Environment code E: Lead Free (RoHS compliant) Product Family J: DDR3 Density / Bank 11: 1Gb / 8-bank Organization 08: x8 16: x16 Speed GL: DDR3-1600J (10-10-10) GN: DDR3-1600K (11-11-11) DG: DDR3-1333G (8-8-8) DJ: DDR3-1333H (9-9-9) AC: DDR3-1066E (6-6-6) AE: DDR3-1066F (7-7-7) AG: DDR3-1066G (8-8-8) 8A: DDR3-800D (5-5-5) 8C: DDR3-800E (6-6-6) Package BG: FBGA Power Supply, Interface B: 1.5V, SSTL_15 Die Rev. Data Sheet E1248E40 (Ver. 4.0) 2 EDJ1108BABG, EDJ1116BABG Pin Configurations (×8 configuration) /xxx indicates active low signal. 78-ball FBGA (×8 configuration) 1 A 2 3 NC 7 8 9 VDD VSS B VDD NU/(/TDQS) VSS VSS VSSQ C DQ0 DQS /DQS DQ4 /RAS /CAS /WE BA2 A0 A2 DM/TDQS VSSQ VDDQ VDDQ D DQ2 DQ6 DQ1 VDD DQ7 CK /CK A10(AP) NC DQ3 VSS DQ5 VSS VDD ZQ VSSQ VSSQ E VSSQ VDDQ NC VREFDQ VDDQ F NC G VSS VDD /CS BA0 A3 A5 ODT H CKE NC NC J VSS K VREFCA VSS VDD VSS VDD L A12(/BC) BA1 A1 A4 VSS M N VDD A7 A9 A11 NC (Top view) A6 A8 VDD VSS /RESET A13 VSS Pin name A0 to A13* 3 Function Address inputs A10 (AP): Auto precharge A12(/BC): Burst chop 3 Pin name /RESET* VDD VSS VDDQ VSSQ VREFDQ VREFCA ZQ NC* NU* 1 2 3 Function Active low asynchronous reset Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage Reference pin for ZQ calibration No connection Not usable BA0 to BA2* DQ0 to DQ7 DQS, /DQS Bank select Data input/output Differential data strobe Termination data strobe Chip select 3 TDQS, /TDQS /CS* 3 /RAS, /CAS, /WE* CKE* 3 Command input Clock enable Differential clock input Write data mask CK, /CK DM ODT* 3 ODT control Notes: 1. Not internally connected with die. 2. Don’t connect. Internally connected. 3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination. Data Sheet E1248E40 (Ver. 4.0) 3 EDJ1108BABG, EDJ1116BABG Pin Configurations (×16 configuration) /xxx indicates active low signal. 96-ball FBGA 1 2 3 7 8 9 A VDDQ DQU5 DQU7 DQU4 VDDQ VSS B VSSQ VDD VSS /DQSU DQU6 VSSQ DQSU DQU2 VDDQ DQU0 VSSQ DML VDD C VDDQ DQU3 DQU1 D E VSSQ VDDQ DMU VSS VSSQ DQL0 VSSQ VDDQ F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ VDD VSS VSSQ G VSSQ DQL6 /DQSL H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ CK VSS NC CKE J NC VSS VDD /CS /RAS K ODT /CAS /WE /CK A10(AP) VDD ZQ L NC NC M VSS BA0 A3 A5 A7 BA2 A0 A2 A9 NC VREFCA VSS VDD N VDD A12(/BC) BA1 A1 A11 P VSS R VDD A4 A6 VSS VDD VSS T VSS /RESET NC NC A8 (Top view) Pin name A0 to A12* 2 Function Address inputs A10(AP): Auto precharge A12(/BC): Burst chop Bank select Data input/output Differential data strobe Chip select 2 Pin name /RESET* VDD VSS VDDQ VSSQ VREFDQ VREFCA ZQ NC* 2 Function Active low asynchronous reset Supply voltage for internal circuit Ground for internal circuit Supply voltage for DQ circuit Ground for DQ circuit Reference voltage for DQ Reference voltage Reference pin for ZQ calibration No connection BA0 to BA2 DQU0 to DQU7 DQL0 to DQL7 DQSU, /DQSU DQSL, /DQSL /CS* 2 /RAS, /CAS, /WE* CKE* 2 Command input Clock enable Differential clock input Write data mask ODT control CK, /CK DMU, DML ODT* 2 Note: 1. Not internally connected with die. 2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination. Data Sheet E1248E40 (Ver. 4.0) 4 EDJ1108BABG, EDJ1116BABG CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations (×8 configuration) ............................................................................................................3 Pin Configurations (×16 configuration) ..........................................................................................................4 Electrical Conditions ......................................................................................................................................7 Absolute Maximum Ratings .......................................................................................................................... 7 Operating Temperature Condition ................................................................................................................ 7 Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................... 8 AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V)....................... 8 VREF Tolerances ......................................................................................................................................... 9 Input Slew Rate Derating ............................................................................................................................ 10 AC and DC Logic Input Levels for Differential Signals ................................................................................ 16 Single-Ended Requirements for Differential Signals ................................................................................... 18 AC and DC Output Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) .................. 21 AC Overshoot/Undershoot Specification..................................................................................................... 23 Output Driver Impedance............................................................................................................................ 24 On-Die Termination (ODT) Levels and I-V Characteristics ......................................................................... 26 ODT Timing Definitions............................................................................................................................... 28 IDD Measurement Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................... 32 Electrical Specifications...............................................................................................................................43 DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 43 DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ................................................. 44 Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V) ..................................................................... 45 Standard Speed Bins .................................................................................................................................. 46 AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V)....................... 50 Block Diagram .............................................................................................................................................63 Pin Function.................................................................................................................................................64 Command Operation ...................................................................................................................................66 Command Truth Table ................................................................................................................................ 66 CKE Truth Table ......................................................................................................................................... 70 Simplified State Diagram .............................................................................................................................71 RESET and Initialization Procedure ............................................................................................................72 Power-Up and Initialization Sequence ........................................................................................................ 72 Reset and Initialization with Stable Power .................................................................................................. 73 Programming the Mode Register.................................................................................................................74 Mode Register Set Command Cycle Time (tMRD) ..................................................................................... 74 MRS Command to Non-MRS Command Delay (tMOD) ............................................................................. 74 Data Sheet E1248E40 (Ver. 4.0) 5 EDJ1108BABG, EDJ1116BABG DDR3 SDRAM Mode Register 0 [MR0] ...................................................................................................... 75 DDR3 SDRAM Mode Register 1 [MR1] ...................................................................................................... 76 DDR3 SDRAM Mode Register 2 [MR2] ...................................................................................................... 77 DDR3 SDRAM Mode Register 3 [MR3] ...................................................................................................... 78 Burst Length (MR0) .................................................................................................................................... 79 Burst Type (MR0) ....................................................................................................................................... 79 DLL Enable (MR1) ...................................................................................................................................... 80 DLL-off Mode .............................................................................................................................................. 80 DLL on/off switching procedure .................................................................................................................. 81 Additive Latency (MR1)............................................................................................................................... 83 Write Leveling (MR1) .................................................................................................................................. 84 TDQS, /TDQS function (MR1) .................................................................................................................... 87 Extended Temperature Usage (MR2) ......................................................................................................... 88 Multi Purpose Register (MR3)..................................................................................................................... 90 Operation of the DDR3 SDRAM ..................................................................................................................98 Read Timing Definition................................................................................................................................ 98 Read Operation ........................................................................................................................................ 102 Write Timing Definition.............................................................................................................................. 109 Write Operation......................................................................................................................................... 110 Write Timing Violations ............................................................................................................................. 116 Write Data Mask ....................................................................................................................................... 117 Precharge ................................................................................................................................................. 118 Auto Precharge Operation ........................................................................................................................ 119 Auto-Refresh............................................................................................................................................. 120 Self-Refresh.............................................................................................................................................. 121 Power-Down Mode ................................................................................................................................... 122 Input Clock Frequency Change during Precharge Power-Down............................................................... 129 On-Die Termination (ODT)........................................................................................................................ 130 ZQ Calibration........................................................................................................................................... 142 Package Drawing ......................................................................................................................................144 Recommended Soldering Conditions........................................................................................................146 Data Sheet E1248E40 (Ver. 4.0) 6 EDJ1108BABG, EDJ1116BABG Electrical Conditions • All voltages are referenced to VSS (GND) • Execute power-up and Initialization sequence before proper device operation is achieved. Absolute Maximum Ratings Parameter Power supply voltage Power supply voltage for output Input voltage Output voltage Reference voltage Reference voltage for DQ Storage temperature Power dissipation Short circuit output current Symbol VDD VDDQ VIN VOUT VREFCA VREFDQ Tstg PD IOUT Rating −0.4 to +1.975 −0.4 to +1.975 −0.4 to +1.975 −0.4 to +1.975 −0.4 to 0.6 × VDD −0.4 to 0.6 × VDDQ −55 to +100 1.0 50 Unit V V V V V V °C W mA Notes 1, 3 1, 3 1 1 3 3 1, 2 1 1 Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be no greater than 0.6 × VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Condition Parameter Operating case temperature Symbol TC Rating 0 to +95 Unit °C Notes 1, 2, 3 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to +85°C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85°C and +95°C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9µs. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]). Data Sheet E1248E40 (Ver. 4.0) 7 EDJ1108BABG, EDJ1116BABG Recommended DC Operating Conditions (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) Parameter Supply voltage Supply voltage for DQ Input reference voltage Input reference voltage for DQ Symbol VDD VDDQ VREFCA (DC) VREFDQ (DC) min. 1.425 1.425 0.49 × VDD 0.49 × VDDQ typ. 1.5 1.5 0.50 × VDD max. 1.575 1.575 0.51 × VDD Unit V V V V Notes 1, 2 1, 2 3, 4 3, 4 0.50 × VDDQ 0.51 × VDDQ Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ±1% VDD (for reference: approx ±15 mV). 4. For reference: approx. VDD/2 ± 15 mV. AC and DC Input Measurement Levels (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) Single-Ended AC and DC Input Levels for Command and Address Parameter DC input logic high DC input logic low AC input logic high AC input logic low AC input logic high AC input logic low Symbol VIHCA (DC) VILCA (DC) VIHCA (AC) VILCA (AC) min. VREF + 0.100 VSS VREF + 0.175 * 2 typ.       max. VDD VREF − 0.100 * * 2 Unit V V V V V V Notes 1 1 1 1 1 1 VREF − 0.175 2 VIHCA (AC150) VREF + 0.150 VILCA (AC150) * 2 VREF − 0.150 Notes: 1. For input only pins except /RESET; VREF = VREFCA. 2. See Overshoot and Undershoot Specifications section. Single-Ended AC and DC Input Levels for DQ and DM Parameter DC input logic high DC input logic low AC input logic high DDR3-800, 1066 DDR3-1333, 1600 AC input logic low DDR3-800, 1066 DDR3-1333, 1600 Symbol VIHDQ (DC) VILDQ (DC) VIHDQ (AC) VIHDQ (AC) VILDQ (AC) VILDQ (AC) min. VREF + 0.100 VSS VREF + 0.175 VREF + 0.150 * * 2 2 typ.       max. VDD VREF − 0.100 * * 2 2 Unit V V V V V V Notes 1 1 1, 3 1, 3 1, 3 1, 3 VREF − 0.175 VREF − 0.150 Notes: 1. For DQ and DM: VREF = VREFDQ. 2. See Overshoot and Undershoot Specifications section. 3. Single-ended swing requirement for DQS, /DQS is 350 mV (peak to peak). Differential swing requirement for DQS, /DQS is 700 mV (peak to peak). Data Sheet E1248E40 (Ver. 4.0) 8 EDJ1108BABG, EDJ1116BABG VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are shown in Figure VREF(DC) Tolerance and VREF AC-Noise Limits. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table of(Single-Ended AC and DC Input Levels for Command and Address). Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD. voltage VDD VREF AC-noise VREF(DC) VREF(t) VREF(DC)max. VDD/2 VREF(DC)min. VSS time VREF(DC) Tolerance and VREF AC-Noise Limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. VREF shall be understood as VREF(DC), as defined in figure above, VREF(DC) Tolerance and VREF AC-Noise Limits. This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (±1% of VDD) are included in DRAM timings and their associated deratings. Data Sheet E1248E40 (Ver. 4.0) 9 EDJ1108BABG, EDJ1116BABG Input Slew Rate Derating For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the ∆tIS, ∆tDS and ∆tIH, ∆tDH derating value respectively. Example: tDS (total setup time) = tDS (base) + ∆tDS. Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF (DC) to AC region’, use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is later than the nominal slew rate line anywhere between shaded ‘VREF (DC) to AC region’, the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure of Slew Rate Definition Tangent). Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between shaded ‘DC level to VREF (DC) region’, use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘DC to VREF (DC) region’, the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value (see the figure of Slew Rate Definition Tangent). For a valid transition the input signal has to remain above/below VIH/VIL(AC) for some time tVAC (see the table of Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL (AC). For slew rates in between the values listed in the tables below, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [Address/Command Setup and Hold Base-Values for 1V/ns] DDR3-800 tIS(base) tIH(base) tIS(base) AC150 200 275 200 + 150 DDR3-1066 125 200 125 + 150 DDR3-1333 65 140 65 + 125 DDR3-1600 45 120 45 + 125 Unit ps ps ps Reference VIH/VIL(AC) VIH/VIL(DC) VIH/VIL(AC) Notes: 1 AC/DC referenced for 1V/ns Address/Command slew rate and 2V/ns differential CK, /CK slew rate. 2. The tHS (base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv − 150mv)/1V/ns] Data Sheet E1248E40 (Ver. 4.0) 10 EDJ1108BABG, EDJ1116BABG [Derating Values of tIS/tIH AC/DC Based (DDR3-800, 1066, 1333, 1600)] ∆tIS, ∆tIH derating in [ps] AC/DC based AC175 Threshold -> VIH(AC)=VREF(DC)+175mV, VIL(AC)=VREF(DC)-175mV CK, /CK differential slew rate 4.0 V/ns ∆tIS 2.0 1.5 CMD, ADD slew rate (V/ns) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 +88 +59 0 −2 −6 −11 −17 −35 −62 ∆tIH +50 +34 0 −4 −10 −16 −26 −40 −60 3.0 V/ns ∆tIS +88 +59 0 −2 −6 −11 −17 −35 −62 ∆tIH +50 +34 0 −4 −10 −16 −26 −40 −60 2.0 V/ns ∆tIS +88 +59 0 −2 −6 −11 −17 −35 −62 ∆tIH +50 +34 0 −4 −10 −16 −26 −40 −60 1.8 V/ns ∆tIS +96 +67 +8 +6 +2 −3 −9 −27 −54 ∆tIH +58 +42 +8 +4 −2 −8 −18 −32 −52 1.6 V/ns ∆tIS ∆tIH 1.4 V/ns ∆tIS ∆tIH 1.2 V/ns ∆tIS ∆tIH 1.0 V/ns ∆tIS ∆tIH Unit +104 +66 +75 +16 +14 +10 +5 −1 −19 −46 +50 +16 +12 +6 0 −10 −24 −44 +112 +74 +83 +24 +22 +18 +13 +7 −11 −38 +58 +24 +20 +14 +8 −2 −16 −36 +120 +84 +91 +32 +30 +26 +21 +15 −2 −30 +68 +34 +30 +24 +18 +8 −6 −26 +128 +100 ps +99 +40 +38 +34 +29 +23 +5 −22 +84 +50 +46 +40 +34 +24 +10 −10 ps ps ps ps ps ps ps ps [Derating Values of tIS/tIH AC/DC based-Alternate AC150 Threshold (DDR3-800, 1066, 1333, 1600)] ∆tIS, ∆tIH derating in [ps] AC/DC based Alternate AC150 Threshold -> VIH(AC)=VREF(DC)+150mV, VIL(AC)=VREF(DC)-150mV CK, /CK differential slew rate 4.0 V/ns ∆tIS 2.0 1.5 CMD, ADD slew rate (V/ns) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 +75 +50 0 0 0 0 −1 −10 −25 ∆tIH +50 +34 0 −4 −10 −16 −26 −40 −60 3.0 V/ns ∆tIS +75 +50 0 0 0 0 −1 −10 −25 ∆tIH +50 +34 0 −4 −10 −16 −26 −40 −60 2.0 V/ns ∆tIS +75 +50 0 0 0 0 −1 −10 −25 ∆tIH +50 +34 0 −4 −10 −16 −26 −40 −60 1.8 V/ns ∆tIS +83 +58 +8 +8 +8 +8 +7 −2 −17 ∆tIH +58 +42 +8 +4 −2 −8 −18 −32 −52 1.6 V/ns ∆tIS +91 +66 +16 +16 +16 +16 +15 +6 −9 ∆tIH +66 +50 +16 +12 +6 0 −10 −24 −44 1.4 V/ns ∆tIS +99 +74 +24 +24 +24 +24 +23 +14 −1 ∆tIH +74 +58 +24 +20 +14 +8 −2 −16 −36 1.2 V/ns ∆tIS ∆tIH 1.0 V/ns ∆tIS ∆tIH Unit +107 +84 +82 +32 +32 +32 +32 +31 +22 7 +68 +34 +30 +24 +18 +8 −6 −26 +115 +100 ps +90 +40 +40 +40 +40 +39 +30 15 +84 +50 +46 +40 +34 +24 +10 −10 ps ps ps ps ps ps ps ps [Required time tVAC above VIH(AC) {below VIL(AC)} for Valid Transition] tVAC @ 175 mV[ps] Slew rate (V/ns) >2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 2.0 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 4.0 4.0 3.0 2.0 1.8 1.6 1.4 1.2 1.0 One Bank Activate -> Precharge IDD1 Operating Current 1 -> One Bank Activate -> Read -> Precharge Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL /CS  H on tCK min (IDD) tRC min (IDD) tRAS min (IDD) N/A N/A N/A N/A SWITCHING (see Definition of SWITCHING table); only exceptions are Activate and Precharge commands; example of IDD0 pattern: A0 D /D /D D D /D /D D D /D/D D D /D P0 (DDR3-800: tRAS = 37.5ns between (A)ctivate and (P)recharge to bank 0; Definition of D and /D: see Definition of SWITCHING table Row addresses SWITCHING (see Definition of SWITCHING table); A10 must be L all the time! Bank address is fixed (bank 0) Figure IDD1 Example H on tCK min (IDD) tRC min (IDD) tRAS min (IDD) tRCD min (IDD) N/A CL(IDD) 0 SWITCHING (see Definition of SWITCHING table); only exceptions are Activate, Read and Precharge commands; example of IDD1 pattern: A0 D /D /D D R0 /D /D D D /D/D D D /D P0 (DDR3-800 -555: tRCD = 12.5ns between (A)ctivate and (R)ead to bank 0; Definition of D and /D: see Definition of SWITCHING table Row addresses SWITCHING (see Definition of SWITCHING table);A10 must be L all the time! Bank address is fixed (bank 0) Read Data: output data switches every clock, which means that Read data is stable during one clock cycle. To achieve IOUT = 0mA the output buffer should be switched off by MR1 bit A12 set to “1”. When there is no read data burst from DRAM the DQ I/O should be FLOATING. off / 1 disabled / [0,0,0] / [0,0] 8 fixed / MR0 bits [A1, A0] = {0,0} one ACT-READ-PRE loop all other N/A H between. Activate and Precharge Commands H between Activate, Read and Precharge Command inputs (/CS, /RAS, /CAS, /WE) Row, column addresses Bank addresses Data I/O SWITCHING (see Definition of SWITCHING table) Output Buffer DQ, DQS / MR1 bit A12 ODT / MR1 bits [A9, A6, A2] / MR2 bits [A1, A0] Burst length Active banks Idle banks Precharge Power-down Mode / MR0 bit A12 off / 1 disabled / [0,0,0] / [0,0] N/A one ACT-PRE loop all other N/A Data Sheet E1248E40 (Ver. 4.0) 33 EDJ1108BABG, EDJ1116BABG T0 CK /CK BA 0 to 2 0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 Address (A0 to A9) Address (A10) Address (A11 to A12) L 000 3FF 000 3FF 000 3FF 00 11 00 11 00 00 /CS /RAS /CAS /WE Command ACT D /D /D D READ /D /D D D /D /D D D /D PRE D D /D /D DQ 0 0 1 1 0 0 1 1 DM IDD1 measurement loop IDD1 Example* (DDR3-800-555, 512Mb ×8) Note: Data DQ is shown but the output buffer should be switched off (per MR1 bit A12 = 1) to achieve IOUT = 0mA. Address inputs are split into 3 parts. Data Sheet E1248E40 (Ver. 4.0) 34 EDJ1108BABG, EDJ1116BABG IDD Measurement Conditions for IDD2N, IDD2P (1), IDD2P (0) and IDD2Q Symbol IDD2N Precharge standby current IDD2P (1)* 1 IDD2P (0)* 1 IDD2Q Name Precharge power-down current (fast exit MR0 bit A12= 1) Precharge power-down current Precharge quiet standby current (slow exit MR0 bit A12= 0) Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL /CS Bank address, row address and command inputs Data inputs Output buffer DQ, DQS / MR1 bit A12 ODT / MR1 bits [A9, A6, A2] / MR2 bits [A1, A0] Burst length Active banks Idle banks Precharge Power-down Mode / MR0 bit A12 Figure IDD2N/IDD3N Example H on tCK min (IDD) N/A N/A N/A N/A N/A N/A H  L on tCK min (IDD) N/A N/A N/A N/A N/A N/A STABLE  L on tCK min (IDD) N/A N/A N/A N/A N/A N/A STABLE STABLE FLOATING off / 1 disabled / [0,0,0] / [0,0] N/A none all  H on tCK min (IDD) N/A N/A N/A N/A N/A N/A H STABLE FLOATING off / 1 disabled / [0,0,0] / [0,0] N/A none all SWITCHING (see Definition of SWITCHING STABLE table) SWITCHING off / 1 disabled / [0,0,0] / [0,0] N/A none all FLOATING off / 1 disabled / [0,0,0] / [0,0] N/A none all Fast exit / 1 (any valid command 2 after tXP* ) N/A Slow exit / 0 Slow exit N/A (READ and ODT commands must satisfy tXPDLL-AL) Notes: 1. In DDR3 the MR0 bit A12 defines DLL-on/off behaviors only for precharge power-down. There are two different precharge power-down states possible: one with DLL-on (fast exit, bit A12 = 1) and one with DLL-off (slow exit, bit A12 = 0). 2. Because it is an exit after precharge power-down the valid commands are: bank activate (ACT), autorefresh (REF), mode register set (MRS), self-refresh (SELF). Data Sheet E1248E40 (Ver. 4.0) 35 EDJ1108BABG, EDJ1116BABG T0 CK /CK BA 0 to 2 T1 T2 T3 T4 T5 T6 T7 T8 T9 0 7 0 Address (A0 to A12) /CS /RAS H 0000 1FFF 0000 /CAS /WE Command /D /D D D /D /D D D /D /D D DQ 0 to 7 DM FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 IDD2N/ IDD3N measurement loop IDD2N/IDD3N Example (DDR3-800-555, 512Mb ×8) Data Sheet E1248E40 (Ver. 4.0) 36 EDJ1108BABG, EDJ1116BABG IDD Measurement Conditions for IDD3N, IDD3P (fast exit) Symbol Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL /CS Address and command inputs Data inputs Output buffer DQ, DQS / MR1 bit A12 ODT / MR1 bits [A9, A6, A2] / MR2 bits [A1, A0] Burst length Active banks Idle banks Precharge Power-down Mode / MR0 bit A12 Figure IDD2N/IDD3N Example H on tCK min (IDD) N/A N/A N/A N/A N/A N/A H SWITCHIN (see Definition of SWITCHING table) SWITCHING (see Definition of SWITCHING table) off / 1 disabled / [0,0,0] / [0,0] N/A all none N/A  L on tCK min (IDD) N/A N/A N/A N/A N/A N/A STABLE STABLE FLOATING off / 1 disabled / [0,0,0] / [0,0] N/A all none N/A (Active Power-down Mode is always “Fast Exit” with DLL-on) IDD3N Active standby current IDD3P (1) Active power-down current* (always fast exit) Note: DDR3 will offer only one active power-down mode with DLL-on (-> fast exit). MR0 bit A12 will not be used for active power-down. Instead bit A12 will be used to switch between two different precharge power-down modes. Data Sheet E1248E40 (Ver. 4.0) 37 EDJ1108BABG, EDJ1116BABG IDD Measurement Conditions for IDD4R, IDD4W and IDD7 Symbol Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD CL AL /CS IDD4R Example H on tCK min (IDD) N/A N/A N/A N/A CL (IDD) 0 H between valid commands SWITCHING (see Definition of SWITCHING table); only exceptions are read commands -> IDD4R pattern: R0 D /D /D R1 D /D /D R2 D /D /D R3 D /D /D R4 ..... Rx = Read from bank x; Definition of D and /D: see Definition of SWITCHING table Column addresses SWITCHING (see Definition of SWITCHING table); A10 must be L all the time! bank address cycling (0 -> 1 -> 2 -> 3 ...)  H on tCK min (IDD) N/A N/A N/A N/A CL (IDD) 0 H between valid commands  H on tCK min (IDD) tRC min. (IDD) tRAS min. (IDD) tRCD min. (IDD) tRRD min. (IDD) CL (IDD) tRCD min. − 1tCK H between valid commands IDD4R Operating current (Burst read operating) IDD4W Operating current (Burst write operating) IDD7 All bank interleave read current Command inputs (/CS, /RAS, /CAS, /WE) Row, column addresses Bank addresses SWITCHING (see Definition of SWITCHING table); only exceptions are write commands -> IDD4W pattern: For patterns see pattern in IDD7 W0 D /D /D W1 D /D /D W2 D /D Timing Patterns section /D W3 D /D /D W4... Wx = Write to bank x; Definition of D and /D: see Definition of SWITCHING table Column addresses SWITCHING (see Definition of SWITCHING STABLE during DESELECTs table); A10 must be L all the time! bank address cycling bank address cycling (0 -> 1 -> 2 -> 3 ...), see pattern (0 -> 1 -> 2 -> 3 ...) in IDD7 Timing Patterns section Read data (BL8): output data switches every clock, which means that Read data is stable during one clock cycle. To achieve IOUT = 0mA the output buffer should be switched off by MR1 bit A12 set to “1”. off / 1 disabled / [0,0,0] / [0,0] 8 fixed / MR0 bits [A1, A0] = {0,0} all, rotational none N/A Data I/O Seamless read data burst (BL8): output data switches every Seamless write data burst (BL8): clock, which means that Read input data switches every clock, data is stable during one clock which means that write data is cycle. stable during one clock cycle. To achieve IOUT = 0mA the DM is low all the time output buffer should be switched off by MR1 bit A12 set to “1”. Output Buffer DQ, DQS / MR1 bit A12 ODT / MR1 bits [A9, A6, A2] / MR2 bits [A1, A0] Burst length Active banks Idle banks Precharge Power-down Mode / MR0 bit A12 off / 1 disabled / [0,0,0] / [0,0] 8 fixed / MR0 [A1, A0] = {0,0} all none N/A off / 1 disabled / [0,0,0] / [0,0] 8 fixed / MR0 bits [A1, A0] = {0,0} all none N/A Data Sheet E1248E40 (Ver. 4.0) 38 EDJ1108BABG, EDJ1116BABG T0 CK /CK BA 0 to 2 Address (A0 to A9) Address (A10) Address (A11 to A12) 0 1 2 3 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 000 3FF 000 3FF L 00 11 00 11 /CS /RAS /CAS /WE Command 0 to 2 DQ 0 to 7 DM READ D /D /D READ D /D /D READ D /D /D READ D 00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF Start of measurement loop IDD4R Example* (DDR3-800-555, 512Mb ×8) Note: Data DQ is shown but the output buffer should be switched off (per MR1 bit A12 = 1) to achieve IOUT = 0mA. Address inputs are split into 3 parts. Data Sheet E1248E40 (Ver. 4.0) 39 EDJ1108BABG, EDJ1116BABG IDD7 Timing Patterns The detailed timings are shown in the IDD7 Timing Patterns for 8 Banks tables. Speed bins DDR3-800 Bin all all tFAW Organization (ns) ×8 ×16 40 50 tFAW (tCK) 16 20 tRRD (ns) 10 10 tRRD (tCK) 4 4 Timing Patterns A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D DD A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D DD A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D D D D A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D DD A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D D A7 RA7 D D D D D D D DDR3-1066 all ×8 37.5 20 7.5 4 all ×16 50 27 10 6 DDR3-1333 all ×8 30 20 6 4 all ×16 45 30 7.5 5 DDR3-1600 all ×8 30 24 6 5 Remark: Ax = Active command for bank x. RAx = Read with auto precharge command from bank x. ex. RA0 = READA command from bank 0 Notes: 1. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) and tFAW (IDD) using a burst length = 8. 2. Control and address bus inputs are STABLE during DESELECTs. 3. IOUT = 0mA. Data Sheet E1248E40 (Ver. 4.0) 40 EDJ1108BABG, EDJ1116BABG IDD Measurement Conditions for IDD5B Symbol Name Measurement Condition Timing Diagram Example CKE External Clock tCK tRC tRAS tRCD tRRD tRFC CL AL /CS Address and command inputs Data inputs Output buffer DQ, DQS / MR1 bit A12 ODT / MR1 bits [A9, A6, A2] / MR2 bits [A1, A0] Burst length Active banks Idle banks Precharge Power-down Mode / MR0 bit A12 H on tCK min. (IDD) N/A N/A N/A N/A tRFC min. (IDD) N/A N/A H between valid commands SWITCHING SWITCHING off / 1 disabled / [0,0,0] / [0,0] N/A Refresh command every tRFC = tRFC (min.) none N/A IDD5B Burst refresh current Data Sheet E1248E40 (Ver. 4.0) 41 EDJ1108BABG, EDJ1116BABG IDD Measurement Conditions for IDD6 and IDD6ET Symbol Name Measurement Condition Temperature Auto Self-refresh (ASR) / MR2 bit A6 Self-Refresh Temperature Range (SRT) / MR2 bit A7 CKE External Clock tCK tRC tRAS tRCD tRRD CL AL /CS Command inputs /RAS, /CAS, /WE) Row, column addresses Bank addresses Data I/O Output Buffer DQ, DQS / MR1 bit A12 ODT / MR1 bits [A9, A6, A2] / MR2 bits [A1, A0] Burst length Active banks Idle banks Precharge Power-down Mode / MR0 bit A12 TC = +85°C Disabled / 0 Disabled / 0 L OFF; CK and /CK at L N/A N/A N/A N/A N/A N/A N/A FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 disabled / [0,0,0] / [0,0] 8 fixed / MR0 bits [A1, A0] = {0,0} all during self-refresh actions all between self-refresh actions N/A TC = +95°C Disabled / 0 Enabled / 1 L OFF; CK and /CK at L N/A N/A N/A N/A N/A N/A N/A FLOATING FLOATING FLOATING FLOATING FLOATING off / 1 disabled / [0,0,0] / [0,0] 8 fixed / MR0 bits [A1, A0] = {0,0} all during self-refresh actions all between self-refresh actions N/A IDD6 IDD6ET Self-refresh current extended temperature Self-refresh current normal temperature range range TC = 0 to +85°C TC = 0 to +95°C IDD6 Current Definition Parameter Symbol Parameter/Condition CKE ≤ 0.2V; external clock off, CK and /CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled. Applicable for MR2 settings A6 = 0 and A7 = 0. CKE ≤ 0.2V; external clock off, CK and /CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled. Applicable for MR2 settings A6 = 0 and A7 = 1 CKE ≤ 0.2V; external clock off, CK and /CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs are FLOATING, PASR disabled. Applicable when ASR is enabled by MR2 settings A6 = 1 and A7 = 0. Normal temperature range selfIDD6 refresh current Extended temperature range self-refresh current Auto self-refresh current IDD6ET IDD6TC Data Sheet E1248E40 (Ver. 4.0) 42 EDJ1108BABG, EDJ1116BABG Electrical Specifications DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ×8 Parameter Operating current (ACT-PRE) Symbol Data rate (Mbps) max. 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 1600 1333 1066 800 TBD 120 110 100 TBD 140 125 115 TBD 40 35 30 TBD 14 13 12 TBD 70 60 50 TBD 75 65 55 TBD 45 40 35 TBD 85 75 65 TBD 220 180 140 TBD 240 200 160 TBD 335 315 295 TBD 345 285 260 × 16 max.  140 130 115  170 155 140  40 35 30  14 13 12  70 60 50  75 65 55  45 40 35  95 85 75  290 230 180  330 270 220  335 315 295  380 330 315 Unit Notes IDD0 mA Operating current (ACT-READ-PRE) IDD1 mA IDD2PF Precharge power-down standby current IDD2PS mA Fast PD Exit mA Slow PD Exit Precharge quiet standby current IDD2Q mA Precharge standby current IDD2N mA Active power-down current IDD3P (Always fast exit) mA Active standby current IDD3N mA Operating current (Burst read operating) IDD4R mA Operating current (Burst write operating) IDD4W mA Burst refresh current IDD5B mA All bank interleave read current IDD7R mA Data Sheet E1248E40 (Ver. 4.0) 43 EDJ1108BABG, EDJ1116BABG Self-Refresh Current (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) ×8 Parameter Symbol Grade max. 10 18 18 × 16 max. 10 18 18 Unit mA mA mA Notes Self-refresh current IDD6S normal temperature range Self-refresh current extended temperature IDD6ET range Auto self-refresh current IDD6TC DC Characteristics 2 (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V) Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 Unit µA µA Notes VDD ≥ VIN ≥ VSS VDDQ ≥ VOUT ≥ VSS Data Sheet E1248E40 (Ver. 4.0) 44 EDJ1108BABG, EDJ1116BABG Pin Capacitance (TC = 25°C, VDD, VDDQ = 1.5V ± 0.075V) Parameter Input pin capacitance, CK and /CK DDR3-1600, 1333 DDR3-1066, 800 Delta input pin capacitance, CK and /CK DDR3-1600, 1333 CDCK DDR3-1066, 800 Input pin capacitance, control pins DDR3-1600, 1333 DDR3-1066, 800 Input pin capacitance, address and command pins DDR3-1600, 1333 DDR3-1066, 800 Delta input pin capacitance, control pins DDR3-1600, 1333 DDR3-1066, 800 Delta input pin capacitance, address and command pins CDIN_ADD_CMD DDR3-1600, 1333 DDR3-1066, 800 Input/output pin capacitance DDR3-1600 DDR3-1333 DDR3-1066, 800 Delta input/output pin capacitance DDR3-1600, 1333 DDR3-1066, 800 Delta input/output pin capacitance DDR3-1600, 1333 DDR3-1066, 800 Input/output pin capacitance of ZQ CZQ ZQ CDDQS DQS, /DQS CDIO CIO DQ, DQS, /DQS, TDQS, /TDQS DM CDIN_CTRL /CS, CKE, ODT CIN_CTRL Symbol CCK CK, /CK Pins min. 0.8 0.8 0 0 /CS, CKE, ODT 0.75 0.75 0.75 0.75 −0.4 −0.5 −0.4 −0.5 1.5 1.5 1.5 −0.5 −0.5 0 0  max. 1.4 1.6 0.15 0.15 1.3 1.5 1.3 1.5 0.2 0.3 0.4 0.5 2.3 2.5 3.0 0.3 0.3 0.15 0.2 3 Unit pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF Notes 1, 3 1, 3 1, 2 1, 2 1 1 1 1 1, 4 1, 4 1, 5 1, 5 1, 6 1, 6 1, 6 1, 7, 8 1, 7, 8 1, 10 1, 10 1, 9 CIN_ADD_CMD /RAS, /CAS, /WE, Address /RAS, /CAS, /WE, Address Notes: 1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the pin under test) floating. VDD = VDDQ =1.5V, VBIAS=VDD/2 2. Absolute value of CCK(CK-pin) − CCK(/CK-pin) 3. CCK (min.) will be equal to CIN (min.) 4. CDIN_CTRL = CIN_CTRL − 0.5 × (CCK(CK-pin) + CCK(/CK-pin)) 5. CDIN_ADD_CMD = CIN_ADD_CMD − 0.5 × (CCK(CK-pin) + CCK(/CK-pin)) 6. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS. 7. DQ should be in high impedance state. 8. CDIO = CIO (DQ, DM) −0.5 × (CIO(DQS-pin) + CIO(/DQS-pin)). 9. Maximum external load capacitance on ZQ pin: 5pF. 10 Absolute value of CIO(DQS) − CIO(/DQS) Data Sheet E1248E40 (Ver. 4.0) 45 EDJ1108BABG, EDJ1116BABG Standard Speed Bins [DDR3-1600 Speed Bins] Speed Bin CL-tRCD-tRP Symbol tAA tRCD tRP tRC tRAS tCK (avg)@CL=5 CWL = 5 /CAS write latency DDR3-1600 10-10-10 min. 12.5 12.5 12.5 47.5 35 2.5 max. 20    9 × tREFI 3.3 Reserved 3.3 Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved < 1.875 Reserved Reserved < 1.875 < 1.5 Reserved < 1.5 Optional DDR3-1600 11-11-11 min. 13.75 13.75 13.75 48.75 35 Reserved Reserved 2.5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1.875 Reserved Reserved Reserved Reserved Reserved Reserved 1.5 Reserved Reserved 1.25 1.25 6, 8, 10, 11 5, 6, 7, 8 max. 20    9 × tREFI Reserved Reserved 3.3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved < 2.5 Reserved Reserved Reserved Reserved Reserved Reserved < 1.875 Reserved Reserved < 1.5 < 1.5 nCK nCK Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 1, 2, 3, 4, 8 4 1, 2, 3, 8 1, 2, 3, 4, 8 4 4 1, 2, 3, 4, 8 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3, 8 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3, 4 1, 2, 3, 4 4 1, 2, 3 5 4 1, 2, 3 5 Notes CWL = 6, 7, 8 Reserved tCK (avg)@CL=6 CWL = 5 CWL = 6 CWL = 7, 8 tCK (avg)@CL=7 CWL = 5 CWL = 6 CWL = 7 CWL = 8 tCK (avg)@CL=8 CWL = 5 CWL = 6 CWL = 7 CWL = 8 tCK (avg)@CL=9 CWL = 5, 6 CWL= 7 CWL= 8 tCK (avg)@CL=10 CWL = 5, 6 CWL= 7 CWL= 8 tCK (avg)@CL=11 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.875 Reserved Reserved Reserved 1.5 Reserved Reserved 1.5 1.25 CWL = 5, 6, 7 Reserved CWL= 8 CWL= 8 1.25 Optional 5, 6, 7, 8, 9, 10 5, 6, 7, 8 Supported CL settings Supported CWL settings Data Sheet E1248E40 (Ver. 4.0) 46 EDJ1108BABG, EDJ1116BABG [DDR3-1333 Speed Bins] Speed Bin CL-tRCD-tRP Symbol tAA tRCD tRP tRC tRAS tCK (avg)@CL=5 CWL = 5 CWL = 6, 7 tCK (avg)@CL=6 CWL = 5 CWL = 6 CWL = 7 tCK (avg)@CL=7 CWL = 5 CWL = 6 CWL = 7 tCK (avg)@CL=8 CWL = 5 CWL = 6 CWL = 7 tCK (avg)@CL=9 CWL = 5, 6 CWL= 7 tCK (avg)@CL=10 CWL = 5, 6 CWL= 7 CWL= 7 Supported CL settings Supported CWL settings /CAS write latency DDR3-1333G 8-8-8 min. 12 12 12 48.0 36 2.5 Reserved 2.5 Reserved Reserved Reserved 1.875 Reserved Reserved 1.875 1.5 Reserved 1.5 Reserved 1.5 Optional 5, 6, 7, 8, 9, 10 5, 6, 7 max. 20    9 × tREFI 3.3 Reserved 3.3 Reserved Reserved Reserved < 2.5 Reserved Reserved < 2.5 < 1.875 Reserved < 1.875 Reserved < 1.875 Optional DDR3-1333H 9-9-9 min. 13.5 13.5 13.5 49.5 36 Reserved Reserved 2.5 Reserved Reserved Reserved Reserved Reserved Reserved 1.875 Reserved Reserved < 1.5 Reserved 1.5 Optional 6, 8, 9, 10 5, 6, 7 max. 20    9 × tREFI Reserved Reserved 3.3 Reserved Reserved Reserved Reserved Reserved Reserved < 2.5 Reserved Reserved < 1.875 Reserved < 1.875 Optional Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 9 1, 2, 3, 4, 7 4 1, 2, 3, 7 1, 2, 3, 4, 7 4 4 1, 2, 3, 4, 7 1, 2, 3, 4 4 1, 2, 3, 7 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 5 Notes Data Sheet E1248E40 (Ver. 4.0) 47 EDJ1108BABG, EDJ1116BABG [DDR3-1066 Speed Bins] Speed Bin CL-tRCD-tRP Symbol tAA tRCD tRP tRC tRAS tCK (avg)@CL=5 CWL = 5 CWL = 6 tCK (avg)@CL=6 CWL = 5 CWL = 6 tCK (avg)@CL=7 CWL = 5 CWL = 6 tCK (avg)@CL=8 Supported CL settings Supported CWL settings CWL = 5 CWL = 6 /CAS write latency DDR3-1066E 6-6-6 min. 11.25 11.25 11.25 48.75 37.5 2.5 Reserved 2.5 1.875 Reserved 1.875 Reserved 1.875 5, 6, 7, 8 5, 6 max. 20    9 × tREFI 3.3 Reserved 3.3 < 2.5 Reserved < 2.5 Reserved < 2.5 DDR3-1066F 7-7-7 min. 13.125 13.125 13.125 50.625 37.5 Reserved Reserved 2.5 Reserved Reserved 1.875 Reserved 1.875 6, 7, 8 5, 6 max. 20    9 × tREFI Reserved Reserved 3.3 Reserved Reserved < 2.5 Reserved < 2.5 DDR3-1066G 8-8-8 min. 15 15 15 52.50 37.5 Reserved Reserved 2.5 Reserved Reserved Reserved Reserved 1.875 6, 8 5, 6 max. 20    9 × tREFI Reserved Reserved 3.3 Reserved Reserved Reserved Reserved < 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns nCK nCK 9 1, 2, 3, 4, 6 4 1, 2, 3, 6 1, 2, 3, 4 4 1, 2, 3, 4 4 1, 2, 3 Notes [DDR3-800 Speed Bins] Speed Bin CL-tRCD-tRP Symbol tAA tRCD tRP tRC tRAS tCK (avg)@CL=5 tCK (avg)@CL=6 Supported CL settings Supported CWL settings CWL = 5 CWL = 5 /CAS write latency DDR3-800F 5-5-5 min. 12.5 12.5 12.5 50 37.5 2.5 2.5 5, 6 5 max. 20    9 × tREFI 3.3 3.3 DDR3-800E 6-6-6 min. 15 15 15 52.5 37.5 Reserved 2.5 6 5 max. 20    9 × tREFI Reserved 3.3 Unit ns ns ns ns ns ns ns nCK nCK 9 1, 2, 3, 4 1, 2, 3 Notes Notes: 1 The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next ‘Supported CL’. 3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg) (max.) corresponding to CL selected. Data Sheet E1248E40 (Ver. 4.0) 48 EDJ1108BABG, EDJ1116BABG 4. ‘Reserved’ settings are not allowed. User must program a different value. 5. 'Optional' settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1066 Speed Bins which are not subject to production tests but verified by design/characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1333 Speed Bins which is not subject to production tests but verified by design/characterization. 8 Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3-1600 Speed Bins which is not subject to production tests but verified by design/characterization. 9. tREFI depends on operating case temperature (TC). Data Sheet E1248E40 (Ver. 4.0) 49 EDJ1108BABG, EDJ1116BABG AC Characteristics (TC = 0°C to +85°C, VDD, VDDQ = 1.5V ± 0.075V, VSS, VSSQ = 0V) • New units tCK(avg) and nCK, are introduced in DDR3. tCK(avg): actual tCK(avg) of the input clock under operation. nCK: one clock cycle of the input clock, counting the actual clock edges. AC Characteristics [DDR3-1600, 1333] -GL, -GN Data rate (Mbps) Parameter Average clock cycle time Minimum clock cycle time (DLL-off mode) Average CK high-level width Average CK low-level width Symbol tCK (avg) 1600 min. 1250 max. 3333  0.53 0.53    9 × tREFI              225 225 225 225 100  -DG, -DJ 1333 min. 1500 8 0.47 0.47 12 (DG) 13.5 (DJ) 12 (DG) 13.5 (DJ) 48 (DG) 49.5 (DJ) 36 6 4 7.5 4 30 45 140 65 65 + 125 65 30 620 400  −500  −500  4 max. 3333  0.53 0.53    9 × tREFI              250 250 250 250 125  Unit ps ns tCK (avg) tCK (avg) ns ns ns ns ns nCK ns nCK ns ns ps ps ps ps ps ps ps ps ps ps ps ps nCK 26 26 26 26 26, 27 26, 27 26, 27 26, 27 26 26 16, 23 16, 23 16, 23, 31 17, 25 17, 25 32 32 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13 6 Notes tCK (DLL-off) 8 tCH (avg) tCL (avg) 0.47 0.47 12.5 (GL) 13.75 (GN) 12.5 (GL) 13.75 (GN) 47.5 (GL) 48.75 (GN) 35 6 4   30  120 45 45 + 125 45 10 560 360  −450  −450  4 Active to read or write command delay tRCD Precharge command period tRP Active to active/auto-refresh command tRC time Active to precharge command Active bank A to active bank B command period (x8) Active bank A to active bank B command period (x16) Four active window (x8) (x16) Address and control input hold time (VIH/VIL (DC) levels) Address and control input setup time (VIH/VIL (AC) levels) Address and control input setup time (VIH/VIL (AC150) levels) DQ and DM input hold time (VIH/VIL (DC) levels) DQ and DM input setup time (VIH/VIL (AC) levels) Control and Address input pulse width for each input DQ and DM input pulse width for each input DQ high-impedance time DQ low-impedance time tRAS tRRD tRRD tRRD tRRD tFAW tFAW tIH (base) tIS (base) tIS (base) AC150 tDH (base) tDS (base) tIPW tDIPW tHZ (DQ) tLZ (DQ) DQS, /DQS high-impedance time tHZ (DQS) (RL + BL/2 reference) DQS, /DQS low-impedance time tLZ (DQS) (RL − 1 reference) DQS, /DQS to DQ skew, per group, per tDQSQ access /CAS to /CAS command delay tCCD Data Sheet E1248E40 (Ver. 4.0) 50 EDJ1108BABG, EDJ1116BABG -GL, -GN Data rate (Mbps) Parameter DQ output hold time from DQS, /DQS DQS, /DQS rising edge output access time from rising CK, /CK DQS latching rising transitions to associated clock edges DQS falling edge hold time from rising CK DQS falling edge setup time to rising CK DQS input high pulse width DQS input low pulse width DQS output high time DQS output low time Symbol tQH tDQSCK tDQSS tDSH tDSS tDQSH tDQSL tQSH tQSL 1600 min. 0.38 −225 −0.27 0.18 0.18 0.45 0.45 0.40 0.40 4 15 12 0.9 0.3 0.9 0.3 15 max.  225 0.27   0.55 0.55           -DG, -DJ 1333 min. 0.38 −255 −0.25 0.2 0.2 0.45 0.45 0.40 0.40 4 15 12 0.9 0.3 0.9 0.3 15 max.  255 0.25   0.55 0.55           Unit Notes 12, 13, tCK (avg) 38 12, 13, ps 37 tCK (avg) 24 tCK (avg) 24, 36 tCK (avg) 24, 36 tCK (avg) 34, 35 tCK (avg) 33, 35 12, 13, 38 12, 13, tCK (avg) 38 tCK (avg) nCK ns nCK tCK (avg) 27 27 Mode register set command cycle time tMRD Mode register set command update delay tMOD tMOD Read preamble Read postamble Write preamble Write postamble Write recovery time Auto precharge write recovery + precharge time Multi-Purpose register recovery time Read to write command delay (BC4MRS, BC4OTF) (BL8MRS, BL8OTF) Internal write to read command delay tRPRE tRPST tWPRE tWPST tWR tDAL tMPRR tRTW tRTW tWTR tWTR Internal read to precharge command delay tRTP tRTP Active to READ with auto precharge tRAP command delay Minimum CKE low width for self-refresh tCKESR entry to exit timing Valid clock requirement after selftCKSRE refresh entry or power-down entry tCKSRE 1, 19, 38 11, 12, tCK (avg) 13, 38 tCK (avg) 1 tCK (avg) 1 ns nCK nCK 29 26 WR + RU  (tRP/tCK (avg)) 1  RL + tCCD/2 +  2nCK − WL RL + tCCD +  2nCK − WL 7.5 4 7.5 4 tRCD min tCKE (min.) +1nCK 10 5         WR + RU  (tRP/tCK (avg)) 1  RL + tCCD/2 +  2nCK − WL RL + tCCD +  2nCK − WL 7.5 4 7.5 4 tRCD min tCKE (min.) +1nCK 10 5         ns nCK ns nCK 18, 26, 27 18, 26, 27 26, 27 26, 27 28 ns nCK 27 27 Data Sheet E1248E40 (Ver. 4.0) 51 EDJ1108BABG, EDJ1116BABG -GL, -GN Data rate (Mbps) Parameter Valid clock requirement before selfrefresh exit or power-down exit Exit self-refresh to commands not requiring a locked DLL Symbol tCKSRX tCKSRX tXS tXS 1600 min. 10 5 tRFC (min.) + 10 5 tDLLK (min.) 110   5 3 max.       7.8 3.9     9 × tREFI         -DG, -DJ 1333 min. 10 5 tRFC (min.) + 10 5 tDLLK (min.) 110   5.625 3 max.       7.8 3.9     9 × tREFI         ns nCK ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK 9 9 10 10 20, 21 20 20 Unit ns nCK ns nCK nCK ns µs µs ns nCK ns nCK nCK 15 2 2 27 27 27 27 27 27 Notes 27 27 27 27 Exit self-refresh to commands requiring tXSDLL a locked DLL Auto-refresh to active/auto-refresh tRFC command time Average periodic refresh interval tREFI (0°C ≤ TC ≤ +85°C) (+85°C < TC ≤ +95°C) CKE minimum pulse width (high and low pulse width) Exit reset from CKE high to a valid command DLL locking time Power-down entry to exit time Exit precharge power-down with DLL frozen to commands requiring a locked DLL Exit power-down with DLL on to any valid command; Exit precharge powerdown with DLL frozen to commands not requiring a locked DLL Command pass disable/enable delay Timing of last ACT command to powerdown entry Timing of last PRE command to powerdown entry Timing of last READ/READA command to power-down entry Timing of last WRIT command to power-down entry (BL8MRS, BL8OTF, BC4OTF) (BC4MRS) Timing of last WRITA command to power-down entry (BL8MRS, BL8OTF, BC4OTF) (BC4MRS) tREFI tCKE tCKE tXPR tXPR tDLLK tPD tXPDLL tXPDLL tXP tXP tCPDED tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRPDEN tWRAPDEN tWRAPDEN tRFC (min.)+10  5 512 tCKE (min.) 24 10 6 3 1 1 1 RL + 4 + 1 tRFC (min.)+10  5 512 tCKE (min.) 24 10 6 3 1 1 1 RL + 4 + 1 WL + 4 +  tWR/tCK (avg) WL + 2 +  tWR/tCK (avg) WL + 4 + WR + 1 WL + 2 + WR + 1 1 tMOD (min.)     WL + 4 +  tWR/tCK (avg) WL + 2 +  tWR/tCK (avg) WL + 4 + WR + 1 WL + 2 + WR + 1 1 tMOD (min.)     Timing of last REF command to powertREFPDEN down entry Timing of last MRS command to tMRSPDEN power-down entry Data Sheet E1248E40 (Ver. 4.0) 52 EDJ1108BABG, EDJ1116BABG ODT AC Electrical Characteristics [DDR3-1600, 1333] -GL, -GN Data rate (Mbps) Parameter RTT turn-on Asynchronous RTT turn-on delay (power-down with DLL frozen) RTT_Nom and RTT_WR turn-off time from ODTLoff reference Asynchronous RTT turn-off delay (power-down with DLL frozen) ODT to power-down entry/exit latency ODT turn-on Latency ODT turn-off Latency ODT Latency for changing from RTT_Nom to RTT_WR ODT Latency for change from RTT_WR to RTT_Nom (BC4) ODT Latency for change from RTT_WR to RTT_Nom (BL8) ODT high time without WRIT command or with WRIT command and BC4 ODT high time with WRIT command and BL8 RTT dynamic change skew Symbol tAON tAONPD tAOF tAOFPD tANPD ODTLon ODTLoff ODTLcnw 1600 min. −225 2 0.3 2 WL – 1.0 WL – 2 WL – 2 WL – 2 max. 225 8.5 0.7 8.5  WL – 2 WL – 2 WL – 2 4 + ODTLoff -DG, -DJ 1333 min. −250 2 0.3 2 WL – 1.0 WL – 2.0 WL – 2.0 WL – 2.0  max. 250 8.5 0.7 8.5  WL – 2.0 WL – 2.0 WL – 2.0 4 + ODTLoff Unit ps ns tCK (avg) ns nCK nCK nCK nCK nCK 8, 12, 37 Notes 7, 12, 37 ODTLcwn4  ODTLcwn8  6 + ODTLoff  6 + ODTLoff nCK ODTH4 ODTH8 tADC 4 6 0.3 512 256 64   0.7    4 6 0.3 512 256 64   0.7    nCK nCK tCK (avg) nCK nCK nCK 30 12, 37 Power-up and reset calibration time tZQinit Normal operation full calibration time Normal operation short calibration time tZQoper tZQCS Write Leveling Characteristics [DDR3-1600, 1333] -GL, -GN 1600 Parameter First DQS pulse rising edge after write leveling mode is programmed DQS, /DQS delay after write leveling mode is programmed Write leveling setup time from rising CK, /CK crossing to rising DQS, /DQS crossing Write leveling hold time from rising DQS, /DQS crossing to rising CK, /CK crossing Write leveling output delay Write leveling output error Symbol tWLMRD tWLDQSEN tWLS min. 40 25 165 max.    -DG, -DJ 1333 min. 40 25 195 max.    Unit nCK nCK ps Notes 3 3 tWLH tWLO tWLOE 165 0 0  7.5 2 195 0 0  9 2 ps ns ns Data Sheet E1248E40 (Ver. 4.0) 53 EDJ1108BABG, EDJ1116BABG AC Characteristics [DDR3-1066, 800] -AC, -AE, -AG Data rate (Mbps) Parameter Clock cycle time Average CL = X Minimum clock cycle time (DLL-off mode) Average duty cycle high-level Average duty cycle low-level Symbol tCK(avg) 1066 min. 1875 max. 3333  0.53 0.53  -8A, -8C 800 min. 2500 8 0.47 0.47 12.5 (8A) 15 (8C) 12.5 (8A) 15 (8C) 50 (8A) 52.5 (8C) 37.5 10 4 10 4 40 50 275 200 200 + 150 150 75 900 600  −800  −800  4 0.38 max. 3333  0.53 0.53  Unit ps ns tCK (avg) tCK (avg) ns 26 6 Notes tCK(DLL-off) 8 tCH (avg) tCL (avg) 0.47 0.47 11.25 (AC) 13.1 (AE) 15 (AG) 11.25 (AC) 13.1 (AE) 15 (AG) 48.75 (AC) 50.6 (AE) 52.5 (AG) 37.5 7.5 4 10 4 37.5 50 200 125 125 + 150 100 25 780 490  −600  −600  4 0.38 Active to read or write command delay tRCD Precharge command period tRP   ns 26 Active to active/auto-refresh command tRC time Active to precharge command Active bank A to active bank B command period (x8) Active bank A to active bank B command period (x16) Four active window (x8) (x16) Address and control input hold time (VIH/VIL (DC) levels) Address and control input setup time (VIH/VIL (AC) levels) Address and control input setup time (VIH/VIL (AC150) levels) DQ and DM input hold time (VIH/VIL (DC) levels) DQ and DM input setup time (VIH/VIL (AC) levels) Control and Address input pulse width for each input DQ and DM input pulse width for each input DQ high-impedance time DQ low-impedance time tRAS tRRD tRRD tRRD tRRD tFAW tFAW tIH (base) tIS (base) tIS (base) AC150 tDH (base) tDS (base) tIPW tDIPW tHZ (DQ) tLZ (DQ)  9 × tREFI              300 300 300 300 150    9 × tREFI              400 400 400 400 200   ns ns ns nCK ns nCK ns ns ps ps ps ps ps ps ps ps ps ps ps ps nCK tCK (avg) 26 26 26, 27 26, 27 26, 27 26, 27 26 26 16, 23 16, 23 16, 23, 31 17, 25 17, 25 32 32 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13 DQS, /DQS high-impedance time tHZ (DQS) (RL + BL/2 reference) DQS, /DQS low-impedance time tLZ (DQS) (RL − 1 reference) DQS, /DQS -DQ skew, per group, per tDQSQ access /CAS to /CAS command delay DQ output hold time from DQS, /DQS tCCD tQH 12, 13, 38 Data Sheet E1248E40 (Ver. 4.0) 54 EDJ1108BABG, EDJ1116BABG -AC, -AE, -AG Data rate (Mbps) Parameter DQS, /DQS rising edge output access time from rising CK, /CK DQS latching rising transitions to associated clock edges DQS falling edge hold time from rising CK DQS falling edge setup time to rising CK DQS input high pulse width DQS input low pulse width DQS output high time DQS output low time Symbol tDQSCK tDQSS tDSH tDSS tDQSH tDQSL tQSH tQSL 1066 min. −300 −0.25 0.2 0.2 0.45 0.45 0.38 0.38 4 15 12 0.9 0.3 0.9 0.3 15 max. +300 0.25   0.55 0.55           -8A, -8C 800 min. −400 −0.25 0.2 0.2 0.45 0.45 0.38 0.38 4 15 12 0.9 0.3 0.9 0.3 15 max. +400 0.25   0.55 0.55           Unit ps Notes 12, 13, 37 tCK (avg) 24 tCK (avg) 24, 36 tCK (avg) 24, 36 tCK (avg) 34, 35 tCK (avg) 33, 35 12, 13, 38 12, 13, tCK (avg) 38 tCK (avg) nCK ns nCK tCK (avg) 27 27 Mode register set command cycle time tMRD Mode register set command update delay tMOD tMOD Read preamble Read postamble Write preamble Write postamble Write recovery time Auto precharge write recovery + precharge time Multi-Purpose register recovery time Read to write command delay (BC4MRS, BC4OTF) (BL8MRS, BL8OTF) Internal write to read command delay tRPRE tRPST tWPRE tWPST tWR tDAL tMPRR tRTW tRTW tWTR tWTR Internal read to precharge command delay Active to READ with auto precharge command delay Minimum CKE low width for selfrefresh entry to exit timing Valid clock requirement after selfrefresh entry or power-down entry Valid clock requirement before selfrefresh exit or power-down exit Exit self-refresh to commands not requiring a locked DLL tRTP tRTP tRAP tCKESR tCKSRE tCKSRE tCKSRX tCKSRX tXS tXS 1, 19, 38 11, 12, tCK (avg) 13, 38 tCK (avg) 1 tCK (avg) 1 ns nCK nCK 29 26 WR + RU  (tRP/tCK (avg)) 1  RL + tCCD/2 +  2nCK − WL RL + tCCD +  2nCK − WL 7.5 4 7.5 4 tRCD min tCKE (min.) +1nCK 10 5 10 5 tRFC (min.) + 10 5             WR + RU  (tRP/tCK (avg)) 1  RL + tCCD/2 +  2nCK − WL RL + tCCD +  2nCK − WL 7.5 4 7.5 4 tRCD min tCKE (min.) +1nCK 10 5 10 5 tRFC (min.) + 10 5             ns nCK ns nCK 18, 26, 27 18, 26, 27 26, 27 26, 27 28 ns nCK ns nCK ns nCK 27 27 27 27 27 27 Data Sheet E1248E40 (Ver. 4.0) 55 EDJ1108BABG, EDJ1116BABG -AC, -AE, -AG Data rate (Mbps) Parameter Exit self-refresh to commands requiring a locked DLL Auto-refresh to active/auto-refresh command time Average periodic refresh interval (0°C ≤ TC ≤ +85°C) (+85°C < TC ≤ +95°C) CKE minimum pulse width (high and low pulse width) Exit reset from CKE high to a valid command DLL locking time Power-down entry to exit time Symbol tXSDLL tRFC tREFI tREFI tCKE tCKE tXPR tXPR tDLLK tPD 1066 min. tDLLK (min.) 110   5.625 3 max.   7.8 3.9   -8A, -8C 800 min. tDLLK (min.) 110   7.5 3 max.   7.8 3.9   Unit nCK ns µs µs ns nCK ns nCK nCK 15 ns nCK ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK 9 9 10 10 20, 21 20 20 2 2 27 27 27 27 27 27 Notes tRFC(min.)+10  5 512 tCKE (min.) 24 10 7.5 3 1 1 1 RL + 4 + 1   9 × tREFI         tRFC(min.)+10  5 512 tCKE (min.) 24 10 7.5 3 1 1 1 RL + 4 + 1   9 × tREFI         Exit precharge power-down with DLL frozen to commands requiring a locked tXPDLL DLL tXPDLL Fast exit/active precharge power-down tXP to any command tXP Command pass disable/enable delay Timing of last ACT command to power-down entry Timing of last PRE command to power-down entry Timing of last READ/READA command to power-down entry Timing of last WRIT command to power-down entry (BL8MRS, BL8OTF, BC4OTF) (BC4MRS) Timing of last WRITA command to power-down entry (BL8MRS, BL8OTF, BC4OTF) (BC4MRS) Timing of last REF command to power-down entry Timing of last MRS command to power-down entry tCPDED tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRPDEN tWRAPDEN tWRAPDEN tREFPDEN tMRSPDEN WL + 4 +  tWR/tCK (avg) WL + 2 +  tWR/tCK (avg) WL + 4 + WR +  1 WL + 2 + WR +  1 1 tMOD (min.)   WL + 4 +  tWR/tCK (avg) WL + 2 +  tWR/tCK (avg) WL + 4 + WR + 1  WL + 2 + WR +  1 1 tMOD (min.)   Data Sheet E1248E40 (Ver. 4.0) 56 EDJ1108BABG, EDJ1116BABG ODT AC Electrical Characteristics [DDR3-1066, 800] -AC, -AE, -AG Data rate (Mbps) Parameter RTT turn-on Asynchronous RTT turn-on delay (power-down with DLL frozen) RTT_Nom and RTT_WR turn-off time from ODTLoff reference ODT turn-off (power-down mode) ODT to power-down entry/exit latency ODT turn-on Latency ODT turn-off Latency ODT Latency for changing from RTT_Nom to RTT_WR ODT Latency for change from RTT_WR to RTT_Nom (BC4) ODT Latency for change from RTT_WR to RTT_Nom (BL8) ODT high time without WRIT command or with WRIT command and BC4 ODT high time with WRIT command and BL8 RTT dynamic change skew Normal operation full calibration time Normal operation short calibration time Symbol tAON tAONPD tAOF tAOFPD tANPD ODTLon ODTLoff ODTLcnw ODTLcwn4 1066 min. –300 2 0.3 2 WL – 1.0 WL – 2.0 WL – 2.0 WL – 2.0  max. 300 8.5 0.7 8.5  WL – 2.0 WL – 2.0 WL – 2.0 4 + ODTLoff -8A, -8C 800 min. –400 2 0.3 2 WL – 1.0 WL – 2.0 WL – 2.0 WL – 2.0  max. 400 8.5 0.7 8.5  WL – 2.0 WL – 2.0 WL – 2.0 4 + ODTLoff Unit ps ns tCK (avg) 8, 12, 37 ns nCK nCK nCK nCK nCK Notes 7, 12, 37 ODTLcwn8  6 + ODTLoff  6 + ODTLoff nCK ODTH4 ODTH8 tADC 4 6 0.3 512 256 64   0.7    4 6 0.3 512 256 64   0.7    nCK nCK tCK (avg) 12, 37 nCK nCK nCK 30 Power-up and reset calibration time tZQinit tZQoper tZQCS Write Leveling Characteristics [DDR3-1066, 800] -AC, -AE, -AG 1066 Parameter First DQS pulse rising edge after write leveling mode is programmed DQS, /DQS delay after write leveling mode is programmed Write leveling setup time from rising CK, /CK crossing to rising DQS, /DQS crossing Write leveling hold time from rising DQS, /DQS crossing to rising CK, /CK crossing Write leveling output delay Write leveling output error Symbol tWLMRD tWLDQSEN tWLS min. 40 25 245 max.    -8A, -8C 800 min. 40 25 325 max.    Unit nCK nCK ps Notes 3 3 tWLH tWLO tWLOE 245 0 0  9 2 325 0 0  9 2 ps ns ns Data Sheet E1248E40 (Ver. 4.0) 57 EDJ1108BABG, EDJ1116BABG Notes for AC Electrical Characteristics Notes: 1. Actual value dependent upon measurement level definitions that are TBD. 2. Commands requiring locked DLL are: READ (and READA) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rounded-up to next integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon. 8. ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is when the bus is in high impedance. Both are measured from ODTLoff. 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer. 10. WR in clock cycles as programmed in MR0. 11. The maximum read postamble is bound by tDQSCK(min.) plus tQSH(min.) on the left side and tHZ(DQS)(max.) on the right side. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD. 13. Value is only valid for RON34. 14. Single ended signal parameter. Refer to the section of tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes for definition and measurement method. 15. tREFI depends on operating case temperature (TC). 16. tIS(base) and tIH(base) values are for 1V/ns command/address single-ended slew rate and 2V/ns CK, /CK differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except /RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, /DQS differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except /RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and Slew Rate Derating section. 18. Start of internal write transaction is definited as follows: For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL. 19. The maximum read preamble is bound by tLZ(DQS)(min.) on the left side and tDQSCK(max.) on the right side. 20. CKE is allowed to be registered low while operations such as row activation, precharge, auto precharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Although CKE is allowed to be registered low after a refresh command once tREFPDEN(min.) is satisfied, there are cases where additional time such as tXPDLL(min.) is also required. See Figure Power-Down Entry/Exit Clarifications - Case 2. 22. tJIT(duty) = ± { 0.07 × tCK(avg) – [(0.5 - (min (tCH(avg), tCL(avg))) × tCK(avg)] }. For example, if tCH/tCL was 0.48/0.52, tJIT(duty) would calculate out to ±125ps for DDR3-800. The tCH(avg) and tCL(avg) values listed must not be exceeded. 23. These parameters are measured from a command/address signal (CKE, /CS, /RAS, /CAS, /WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24 These parameters are measured from a data strobe signal ((L/U/T)DQS, /DQS) crossing to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 25. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/T)DQS/DQS) crossing. Data Sheet E1248E40 (Ver. 4.0) 58 EDJ1108BABG, EDJ1116BABG 26. For these parameters, the DDR3 SDRAM device is characterized and verified to support tnPARAM [nCK] = RU{tPARAM [ns] / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP =RU{tRP / tCK(avg)} = 6, i.e. as long as the input clock jitter specifications are met, precharge command at Tm and active command at Tm+6 is valid even if (Tm+6 − Tm) is less than 15ns due to input clock jitter. 27. These parameters should be the larger of the two values, analog (ns) and number of clocks (nCK). 28 The tRAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. 29 Defined between end of MPR read burst and MRS which reloads MPR or disables. 30 One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: ZQCorrection (Tsens × Tdriftrate) + (Vsens × Vdriftrate) where TSens = max.(dRTTdT, dRONdTM) and VSens = max.(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/°C, VSens = 0.15%/mV, Tdriftrate = 1°C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as: 0.5 = 0.133 = 128ms (1.5 × 1) + (0.15 × 15) 31 The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100ps of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mV − 150mV)/1V/ns]. 32 Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 33 tDQSL describes the instantaneous differential input low pulse width on DQS − /DQS, as measured from one falling edge to the next consecutive rising edge. 34 tDQSH describes the instantaneous differential input high pulse width on DQS −/DQS, as measured from one rising edge to the next consecutive falling edge. 35 tDQSH,act + tDQSL,act = 1tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 36 tDSH,act + tDSS,act = 1tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 37 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 ≤ m ≤ 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = −172ps and tERR(mper),act,max = +193ps, then tDQSCK,min(derated) = tDQSCK,min − tERR(mper),act,max = −400ps − 193ps = −593ps and tDQSCK,max(derated) =tDQSCK,max − tERR(mper),act,min = 400ps + 172ps = +572ps. Similarly, tLZ(DQ) forDDR3-800 derates to tLZ(DQ),min(derated) = −800ps − 193ps = −993ps and tLZ(DQ),max(derated) = 400ps + 172ps = +572ps. Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 ≤ n ≤ 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 ≤ n ≤ 12. 38 When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500ps, tJIT(per),act,min = − 72ps and tJIT(per),act,max = +93ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 × tCK(avg),act + tJIT(per),act,min = 0.9 × 2500ps − 72ps = +2178ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 × tCK(avg),act + tJIT(per),act,min = 0.38 × 2500ps − 72ps = + 878ps. Data Sheet E1248E40 (Ver. 4.0) 59 EDJ1108BABG, EDJ1116BABG Clock Jitter [DDR3-1600, 1333] -GL, -GN Data rate (Mbps) Parameter Average clock period Absolute clock period Clock period jitter Clock period jitter during DLL locking period Cycle to cycle period Jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n = 13, 14…49, 50 cycles Average high pulse width Average low pulse width Absolute clock high pulse width Absolute clock low pulse width Duty cycle jitter Symbol tCK (avg) tCK (abs) tJIT (per) tJIT (per, lck) tJIT (cc) tJIT (cc, lck) tERR (2per) tERR (3per) tERR (4per) tERR (5per) tERR (6per) tERR (7per) tERR (8per) tERR (9per) 1600 min. 1250 max. 3333 -DG, -DJ 1333 min. 1500 max. 3333 Unit ps Notes 1 2 6 6 7 7 8 8 8 8 8 8 8 8 8 8 8 9 3 4 10, 11 10, 12 5 tCK(avg)min + tCK(avg)max+ tCK(avg)min + tCK(avg)max+ ps tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max −70 −60   −103 −122 −136 −147 −155 −163 −169 −175 70 60 140 120 103 122 136 147 155 163 169 175 180 184 188 −80 −70   −118 −140 −155 −168 −177 −186 −193 −200 −205 −210 −215 80 70 160 140 118 140 155 168 177 186 193 200 205 210 215 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK (avg) tCK (avg) tCK (avg) tCK (avg) ps tERR (10per) −180 tERR (11per) −184 tERR (12per) −188 tERR (nper) tCH (avg) tCL (avg) tCH (abs) tCL (abs) tJIT (duty) tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max 0.47 0.47 0.43 0.43  0.53 0.53    0.47 0.47 0.43 0.43  0.53 0.53    Data Sheet E1248E40 (Ver. 4.0) 60 EDJ1108BABG, EDJ1116BABG Clock Jitter [DDR3-1066, 800] -AC, -AE, -AG Data rate (Mbps) Parameter Average clock period Absolute clock period Clock period jitter Clock period jitter during DLL locking period Cycle to cycle period jitter Cycle to cycle clock period jitter during DLL locking period Cumulative error across 2 cycles Cumulative error across 3 cycles Cumulative error across 4 cycles Cumulative error across 5 cycles Cumulative error across 6 cycles Cumulative error across 7 cycles Cumulative error across 8 cycles Cumulative error across 9 cycles Cumulative error across 10 cycles Cumulative error across 11 cycles Cumulative error across 12 cycles Cumulative error across n=13, 14…49,50 cycles Average high pulse width Average low pulse width Absolute clock high pulse width Absolute clock low pulse width Duty cycle jitter Symbol tCK (avg) tCK (abs) tJIT (per) tJIT (per, lck) tJIT (cc) tJIT (cc, lck) tERR (2per) tERR (3per) tERR (4per) tERR (5per) tERR (6per) tERR (7per) tERR (8per) tERR (9per) tERR (10per) tERR (11per) tERR (12per) tERR (nper) tCH (avg) tCL (avg) tCH (abs) tCL (abs) tJIT (duty) 1066 min. 1875 max. 3333 -8A, -8C 800 min. 2500 max. 3333 Unit ps Notes 1 2 6 6 7 7 8 8 8 8 8 8 8 8 8 8 8 9 3 4 10, 11 10, 12 5 tCK(avg)min + tCK(avg)max+ tCK(avg)min + tCK(avg)max+ ps tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max −90 −80   −132 −157 −175 −188 −200 −209 −217 −224 −231 −237 −242 90 80 180 160 132 157 175 188 200 209 217 224 231 237 242 −100 −90   −147 −175 −194 −209 −222 −232 −241 −249 −257 −263 −269 100 90 200 180 147 175 194 209 222 232 241 249 257 263 269 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK (avg) tCK (avg) tCK (avg) tCK (avg) ps tERR (nper) min. = (1+0.68in(n)) x tJIT(per) min tERR (nper) max. = (1+0.68in(n)) x tJIT(per) max 0.47 0.47 0.43 0.43  0.53 0.53    0.47 0.47 0.43 0.43  0.53 0.53    Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window, where each clock period is calculated from rising edge to rising edge. Σ N j=1 tCKj N N = 200 2. tCK (abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK (abs) is not subject to production test. 3. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. Σ N j=1 tCHj (N × tCK(avg)) N = 200 Data Sheet E1248E40 (Ver. 4.0) 61 EDJ1108BABG, EDJ1116BABG 4. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. Σ N j=1 tCLj (N × tCK(avg)) N = 200 5. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg). tJIT (duty) is not subject to production test. tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where: tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200} tJIT (CL) = {tCLj- tCL (avg) where j = 1 to 200} 6. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg). tJIT (per) = Min./Max. of { tCKj − tCK (avg) where j = 1 to 200} tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not subject to production test. 7. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT (cc) = Max. of {tCKj+1 - tCKj} tJIT (cc) is defines the cycle when the DLL is already locked. tJIT (cc, lck) uses the same definition for cycle-to-cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not subject to production test. 8. tERR (nper) is defined as the cumulative error across n multiple consecutive cycles from tCK (avg). tERR (nper) is not subject to production test. 9 n = from 13 cycles to 50 cycles. This row defines 38 parameters. 10. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing hold at all times. (minimum and maximum of spec values are to be used for calculations in the table below.) Parameter Absolute clock period Absolute clock high pulse width Absolute clock low pulse width Symbol tCK (abs) tCH (abs) tCL (abs) min. tCK (avg), min. + tJIT (per),min. tCH (avg), min. × tCK (avg),min. + tJIT (duty),min. tCL (avg), min. × tCK (avg),min. + tJIT (duty),min. max. Unit tCK (avg), max. + tJIT (per),max. ps tCH (avg), max. × tCK (avg),max. ps + tJIT (duty),max. tCL (avg), max. × tCK (avg),max. ps + tJIT (duty),max. 11 tCH (abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 12 tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. Data Sheet E1248E40 (Ver. 4.0) 62 EDJ1108BABG, EDJ1116BABG Block Diagram CK /CK CKE Clock generator Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Row decoder Address, BA0, BA1, BA2 Mode register Row address buffer and refresh counter Memory cell array Bank 0 Sense amp. Command decoder /CS /RAS /CAS /WE Column address buffer and burst counter Column decoder Control logic Data control circuit Latch circuit DQS, /DQS CK, /CK DLL Input & Output buffer TDQS, /TDQS ODT DM DQ Data Sheet E1248E40 (Ver. 4.0) 63 EDJ1108BABG, EDJ1116BABG Pin Function CK, /CK (input pins) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A13 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table] Address (A0 to A13) Part number EDJ1108BABG EDJ1116BABG Page size 1KB 2KB Row address (RA) AX0 to AX13 AX0 to AX12 Column address (CA) AY0 to AY9 AY0 to AY9 1 Note Note: A13 pin is NC for x16 organization. A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto precharge should be performed to the accessed bank after the read/write operation. (high: auto precharge; low: no auto precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12(/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) See command truth table for details. BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine which mode register (MR0 to MR3) is to be accessed during a MRS cycle. [Bank Select Signal Table] BA0 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 L H L H L H L H BA1 L L H H L L H H BA2 L L L L H H H H Remark: H: VIH. L: VIL. Data Sheet E1248E40 (Ver. 4.0) 64 EDJ1108BABG, EDJ1116BABG CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DM, DMU, DML (input pins) DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a write access. DM is sampled on both edges of DQS. For ×8 configuration, the function of DM or TDQS, /TDQS is enabled by mode register A11 setting in MR1. DQ, DQU, DQL (input/output pins) Bi-directional data bus. DQS, /DQS, DQSU, /DQSU, DQSL, /DQSL (input/output pins) Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data. The data strobe DQS is paired with differential signal /DQS to provide differential pair signaling to the system during READs and WRITEs. TDQS, /TDQS (output pins) TDQS and /TDQS is applicable for ×8 configuration only. When enabled via mode register A11 = 1 in MR1, DRAM will enable the same termination resistance function on TDQS, /TDQS as is applied to DQS, /DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and /TDQS is not used. In ×16 configuration, the TDQS function must be disabled via mode register A11 = 0 in MR1. /RESET (input pin) /RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD (1.20V for DC high and 0.30V for DC low). It is negative active signal (active low) and is referred to GND. There is no termination required on this signal. It will be heavily loaded across multiple chips. /RESET is destructive to data contents. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM/TDQS, NU(/TDQS) (when TDQS is enabled via mode register A11 = 1 in MR1) signal for ×4/×8 configuration. For ×16 configuration ODT is applied to each DQ, DQSU, /DQSU, DQSL, /DQSL, DMU, and DML signal. The ODT pin will be ignored if the mode register (MR1) is programmed to disable ODT. ZQ (supply) Reference pin for ZQ calibration. VDD, VSS, VDDQ, VSSQ (power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VREFCA, VREFDQ (power supply) Reference voltage Data Sheet E1248E40 (Ver. 4.0) 65 EDJ1108BABG, EDJ1116BABG Command Operation Command Truth Table The DDR3 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. CKE Function Mode register set Auto-refresh Self-refresh entry Self-refresh exit Symbol MRS REF SELF SREX Previous Current cycle cycle /CS H H H L L Single bank precharge Precharge all banks Bank activate Write (Fixed BL) Write (BC4, on the fly) Write (BL8, on the fly) Write with auto precharge (Fixed BL) Write with auto precharge (BC4, on the fly) Write with auto precharge (BL8, on the fly) Read (Fixed BL) Read (BC4, on the fly) Read (BL8, on the fly) Read with auto precharge (Fixed BL) Read with auto precharge (BC4, on the fly) Read with auto precharge (BL8, on the fly) No operation Device deselect Power-down mode entry PRE PALL ACT WRIT WRS4 WRS8 WRITA H H H H H H H H H L H H H H H H H H H H H H H H H H H H H L L H H H H L L L H L L L L L L L L L L L L L L L L L H H L H L L L /RAS /CAS /WE L L L × H L L L H H H H H H H H H H H H H × × H × H H H L L L × H H H H L L L L L L L L L L L L H × × H × H H H L H H × H L L H L L L L L L H H H H H H H × × H × H L L BA0 to BA2 BA V V × V BA V BA BA BA BA BA BA BA BA BA BA BA BA BA V × × V × V × × A12 (/BC) op-code V V × V V V RA V L H V L H V L H V L H V × × V × V × × L L L H H H L L L H H H V × × V × V H L CA CA CA CA CA CA CA CA CA CA CA CA V × × V × V × × 5, 11 9 10 5, 11 V V × V L H V V × V V V 12 6, 8, 11 6, 7, 8, 11 A10 (AP) Address Notes WRAS4 H WRAS8 H READ RDS4 RDS8 H H H READA H RDAS4 RDAS8 NOP DESL PDEN H H H H H H Power-down mode exit PDEX L L ZQ calibration long ZQ calibration short ZQCL ZQCS H H Remark: H = VIH. L = VIL. × = Don't care (defined or undefined (including floating around VREF)) logic level. V = VIH or VIL (defined logic level). BA = Bank addresses. RA = Row Address. CA = Column Address. /BC = Burst Chop. Data Sheet E1248E40 (Ver. 4.0) 66 EDJ1108BABG, EDJ1116BABG Notes: 1. All DDR3 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the clock. The most significant bit (MSB) of BA, RA, and CA are device density and configuration dependent. 2. /RESET is an active low asynchronous signal that must be driven high during normal operation 3. Bank Addresses (BA) determine which bank is to be operated upon. For MRS, BA selects an mode register. 4. Burst READs or WRITEs cannot be terminated or interrupted and fixed/on the fly BL will be defined by MRS. 5. The power-down mode does not perform any refresh operations. 6. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 7. Self-refresh exit is asynchronous. 8. VREF (Both VREFDQ and VREFCA) must be maintained during self-refresh operation. 9. The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 10. The DESL command performs the same function as a NOP command. 11. Refer to the CKE Truth Table for more detail with CKE transition. 12. No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. No Operation Command [NOP] The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as a burst read or write cycle. The no operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP (/CS low, /RAS, /CAS, /WE high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Device Deselect Command [DESL] The deselect function (/CS high) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected. Mode Register Set Command [MR0 to MR3] The mode registers are loaded via row address inputs. See mode register descriptions in the Programming the Mode Register section. The mode register set command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. Bank Activate Command [ACT] This command is used to open (or activate) a row in a particular bank for a subsequent access. The values on the BA inputs select the bank, and the address provided on row address inputs selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. Note: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. Data Sheet E1248E40 (Ver. 4.0) 67 EDJ1108BABG, EDJ1116BABG Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8] The read command is used to initiate a burst read access to an active row. The values on the BA inputs select the bank, and the address provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Write Command [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8] The write command is used to initiate a burst write access to an active row. The values on the BA inputs select the bank, and the address provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be written to memory; if the DM signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. Precharge Command [PRE, PALL] The precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA select the bank. Otherwise BA are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. A precharge command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. Auto precharge Command [READA, WRITA] Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the read or write command is issued, then the auto precharge function is engaged. During auto precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. (This timing is equal to the rising edge which is (AL* + BL/2) cycles later from the read with auto precharge command.) Auto precharge can also be implemented during write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The tRAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Note: AL (Additive Latency), refer to Posted /CAS description in the Register Definition section. Auto-Refresh Command [REF] Auto-refresh is used during normal operation of the DDR3 SDRAM and is analogous to /CAS-before-/RAS (CBR) refresh in FPM/EDO DRAM. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an auto-refresh command. A maximum of eight auto-refresh commands can be posted to any given DDR3, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 × tREFI. This maximum absolute interval is to allow DDR3 output drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes. Data Sheet E1248E40 (Ver. 4.0) 68 EDJ1108BABG, EDJ1116BABG Self-Refresh Command [SELF] The self-refresh command can be used to retain data in the DDR3, even if the rest of the system is powered down. When in the self-refresh mode, the DDR3 retains data without external clocking. The self-refresh command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled upon entering self-refresh and is automatically enabled and reset upon exiting self-refresh. The active termination is also disabled upon entering self-refresh and enabled upon exiting self-refresh. (512 clock cycles must then occur before a read command can be issued). Input signals except CKE are "Don't Care" during self-refresh. The procedure for exiting self-refresh requires a sequence of commands. First, CK and /CK must be stable prior to CKE going back high. Once CKE is high, the DDR3 must have NOP commands issued for tXSDLL because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and out-put calibration is to apply NOPs for 512 clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. ZQ calibration Command [ZQCL, ZQCS] ZQ calibration command (short or long) is used to calibrate DRAM RON and ODT values over PVT. ZQ Calibration Long (ZQCL) command is used to perform the initial calibration during power-up initialization sequence. ZQ Calibration Short (ZQCS) command is used to perform periodic calibrations to account for VT variations. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh. Data Sheet E1248E40 (Ver. 4.0) 69 EDJ1108BABG, EDJ1116BABG CKE Truth Table CKE Current state* Power-down 2 *3 Previous 1 cycle (n-1)* L L Current *1 cycle (n) L H L H L L L L L L L H Command (n) /CS, /RAS, /CAS, /WE × DESL or NOP × DESL or NOP DESL or NOP DESL or NOP DESL or NOP DESL or NOP DESL or NOP DESL or NOP REFRESH Operation (n) *3 Notes 14, 15 11, 14 15, 16 8, 12, 16 11, 13, 14 11, 13, 14, 17 11, 13, 14, 17 11, 13, 14, 17 11 11, 13, 14, 18 9, 13, 18 10 Maintain power-down Power-down exit Maintain self-refresh Self-refresh exit Active power-down entry Power-down entry Power-down entry Power-down entry Precharge power-down entry Precharge power-down entry Self-refresh entry Self-refresh L L Bank Active Reading Writing Precharging Refreshing All banks idle Any state other than listed above H H H H H H H H Refer to the Command Truth Table Remark: H = VIH. L = VIL. × = Don’t care Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n−1) is the state of CKE at the previous clock edge. 2. Current state is the state of the DDR3 SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n). ODT is not included here. 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 6. CKE must be registered with the same value on tCKE (min.) consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKE (min.) clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (min.) + tIH. 7. DESL and NOP are defined in the Command Truth Table. 8. On self-refresh exit, DESL or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT command may be issued only after tXSDLL is satisfied. 9. Self-refresh mode can only be entered from the all banks idle state. 10. Must be a legal command as defined in the Command Truth Table. 11. Valid commands for power-down entry and exit are NOP and DESL only. 12. Valid commands for self-refresh exit are NOP and DESL only. 13. Self-refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. See section Power-Down and self-refresh Command for a detailed list of restrictions. 14. The power-down does not perform any refresh operations. 15. “×” means “don’t care” (including floating around VREF) in self-refresh and power-down. It also applies to address pins. 16. VREF (Both VREFDQ and VREFCA) must be maintained during self-refresh operation. 17. If all banks are closed at the conclusion of the read, write or precharge command, the precharge powerdown is entered, otherwise active power-down is entered. 18. Idle state means that all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress. CKE is high and all timings from previous operation are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXPDLL, etc). Data Sheet E1248E40 (Ver. 4.0) 70 EDJ1108BABG, EDJ1116BABG Simplified State Diagram CKE_L POWER APPLIED POWER ON RESET PROCEDURE INITIALIZATION MRS, MPR, WRITE LEVELING SELF SELFX REF SELF REFRESH MRS FROM ANY STATE RESET ZQ CALIBRATION ZQCL ZQCS IDLE REFRESHING ACT PDEN PDEX ACTIVE POWER DOWN ACTIVATING PRECHARGE POWER DOWN CKE_L PDEN PDEX CKE_L BANK ACTIVE WRIT WRIT WRITA WRITING READ READ READA READ READING WRIT WRITA WRITA WRITING READA READA PRE, PALL READING PRE, PALL PRE, PALL PRECHARGING Automatic sequence Command sequence Data Sheet E1248E40 (Ver. 4.0) 71 EDJ1108BABG, EDJ1116BABG RESET and Initialization Procedure Power-Up and Initialization Sequence 1. Apply power (/RESET is recommended to be maintained below 0.2 × VDD, (all other inputs may be undefined). ) /RESET needs to be maintained for minimum 200µs with stable power. CKE is pulled low anytime before /RESET being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD (min.) must be no greater than 200ms; and during the ramp, VDD > VDDQ and (VDD − VDDQ) < 0.3V. • VDD and VDDQ are driven from a single power converter output AND • The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power ramp is finished, AND • VREF tracks VDDQ/2. OR • Apply VDD without any slope reversal before or at the same time as VDDQ. • Apply VDDQ without any slope reversal before or at the same time as VTT and VREF. • The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After /RESET is de-asserted, wait for another 500µs until CKE become active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clocks (CK, /CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also a NOP or DESL command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered “high” after Reset, CKE needs to be continuously registered high until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3 SDRAM will keep its on-die termination in high-impedance state during /RESET being asserted at least until CKE being registered high. Therefore, the ODT signal may be in undefined state until tIS before CKE being registered high. After that, the ODT signal must be kept inactive (low) until the power-up and initialization sequence is finished, including expiration of tDLLK and tZQinit. 5. After CKE being registered high, wait minimum of tXPR, before issuing the first MRS command to load mode register. (tXPR = max. (tXS ; 5 × tCK) 6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide low to BA0 and BA2, high to BA1.) 7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide low to BA2, high to BA0 and BA1.) 8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue DLL Enable command, provide low to A0, high to BA0 and low to BA1 and BA2). 9. Issue MRS command to load MR0 with all application settings and DLL reset. (To issue DLL reset command, provide high to A8 and low to BA0 to BA2). 10. Issue ZQCL command to start ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3 SDRAM is now ready for normal operation. Data Sheet E1248E40 (Ver. 4.0) 72 EDJ1108BABG, EDJ1116BABG Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, /CK tCKSRX max. (10 ns; 5tCK) VDD, VDDQ 200ms 500ms /RESET 10ns tIS CKE * tXPR tIS Command BA 2 tDLLK tMRD tMRD tMRD tMOD tZQinit *1 tIS MRS MR2 MRS MR3 MRS MR1 MRS MR0 ZQcal ODT DRAM_RTT Notes: 1. From time point "Td" until "Tk", NOP or DESL commands must be applied between MRS and ZQcal commands. 2. tXPR = max. (tXS; 5tCK) : VIH or VIL Reset and Initialization Sequence at Power-On Ramping Reset and Initialization with Stable Power The following sequence is required for /RESET at no power interruption initialization. 1. Assert /RESET below 0.2 × VDD anytime when reset is needed (all other inputs may be undefined). /RESET needs to be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time 10ns). 2. Follow Power-Up Initialization Sequence steps 2 to 12. 3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation. Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, /CK tCKSRX max. (10 ns; 5tCK) VDD, VDDQ 100ns /RESET 500ms 10ns CKE tIS * tXPR tIS Command BA 2 tDLLK tMRD tMRD tMRD tMOD ZQCL tZQinit *1 tIS MRS MR2 MRS MR3 MRS MR1 MRS MR0 ODT DRAM_RTT Notes: 1. From time point "Td" until"Tk", NOP or DESL commands must be applied between MRS and ZQCL commands. 2. tXPR = max. (tXS; 5tCK) : VIH or VIL Reset Procedure at Power Stable Condition Data Sheet E1248E40 (Ver. 4.0) 73 EDJ1108BABG, EDJ1116BABG Programming the Mode Register For application flexibility, various functions, features and modes are programmable in four mode registers, provided by the DDR3 SDRAM, as user defined variables, and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, content of mode registers must be fully initialized and/or re-initialized, i.e. written, after Power-up and/or reset for proper operation. Also the contents of the mode registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset does not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents. The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands. The MRS command to non-MRS command delay, tMOD, is required for the DRAM to update the features except DLL reset and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL. The mode register contents can be changed using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is already high prior to writing into the mode register. The mode registers are divided into various fields depending on the functionality and/or modes. Mode Register Set Command Cycle Time (tMRD) tMRD is the minimum time required from an MRS command to the next MRS command. As DLL enable and DLL reset are both MRS commands, tMRD is applicable between MRS to MR1 for DLL enable and MRS to MR0 for DLL reset, and not tMOD. /CK CK Command MRS NOP tMRD MRS NOP tMRD Timing MRS Command to Non-MRS Command Delay (tMOD) tMOD is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL. Note that additional restrictions may apply, for example, MRS to MR0 for DLL reset followed by read. /CK CK Command MRS NOP tMOD non-MRS NOP Old setting Updating New Setting tMOD Timing Data Sheet E1248E40 (Ver. 4.0) 74 EDJ1108BABG, EDJ1116BABG DDR3 SDRAM Mode Register 0 [MR0] The mode register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, /CAS latency, test mode, DLL reset, WR and DLL control for precharge power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the states of address pins according to the table below. BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field 0*1 0 0 0*1 PPD WR DLL TM /CAS latency RBT CL BL Mode register 0 A8 0 1 BA1 BA0 0 0 1 1 0 1 0 1 DLL reset No Yes A7 0 1 Mode Normal Test A3 0 1 Read burst type Nibble sequential Interleave Burst length A1 0 0 1 1 A0 0 1 0 1 BL 8 (Fixed) 4 or 8 (on the fly) 4 (Fixed) Reserved MRS mode MR0 MR1 MR2 MR3 Write recovery for autoprecharge A11 0 0 0 0 1 1 1 1 A10 0 0 1 1 0 0 1 1 A9 0 1 0 1 0 1 0 1 WR Reserved 5*2 6*2 7*2 8*2 10*2 12*2 Reserved /CAS latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 A2 0 0 0 0 0 0 0 0 Latency Reserved 5 6 7 8 9 10 Reserved A12 DLL Control for Precharge PD 0 1 Slow exit (DLL off) Fast exit (DLL on) Notes: 1. BA2 and A13 are reserved for future use and must be programmed to 0 during MRS. 2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.). WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR (min.) [cycles] = roundup tWR (ns) / tCK (ns)). (The WR value in the mode register must be programmed to be equal or larger than WR (min.) This is also used with tRP to determine tDAL. MR0 Programming Data Sheet E1248E40 (Ver. 4.0) 75 EDJ1108BABG, EDJ1116BABG DDR3 SDRAM Mode Register 1 [MR1] The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins according to the table below BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0*1 0 Address field Mode register 1 1 0*1 Qoff TDQS 0*1 Rtt_Nom 0*1 Level Rtt_Nom D.I.C AL Rtt_Nom D.I.C DLL A11 TDQS enable 0 Disabled 1 Enabled A7 0 1 Write leveling enable Disabled Enabled A9 0 0 0 0 1 1 1 1 A4 A3 00 01 10 11 A6 0 0 1 1 0 0 1 1 A2 RTT_Nom*5 0 ODT Disabled RZQ/4 1 RZQ/2 0 RZQ/6 1 0 RZQ/12*4 RZQ/8*4 1 Reserved 0 Reserved 1 A5 0 0 1 1 A0 0 1 DLL enable Enable Disable Qoff A12 Output buffers enabled 0 1 Output buffers disabled*2 Additive Latency 0 (AL disabled) CL-1 CL-2 Reserved A1 0 1 0 1 Output driver impedance control RZQ/6 RZQ/7 RZQ/TBD RZQ/TBD Notes: 1. BA2, A8, A10 and A13 are reserved for future use (RFU) and must be programmed to 0 during MRS. 2. Outputs disabled - DQ, DQS, /DQS. 3. RZQ = 2409 4. If RTT_Nom is used during writes, only the values RZQ/2, RZQ/4 and RAQ/6 are allowed. 5. In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7] =1) with MR1[bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed MR1 Programming Data Sheet E1248E40 (Ver. 4.0) 76 EDJ1108BABG, EDJ1116BABG DDR3 SDRAM Mode Register 2 [MR2] The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and /CAS write latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and low on BA0, while con-trolling the states of address pins according to the table below. BA2 BA1 BA0 A13 A12 A11 A10 0*1 1 0 0*1 A9 A8 A7 A6 A5 A4 CWL A3 A2 A1 A0 Address field Mode register 2 Rtt_WR*2 0*1 SRT ASR PASR* 2 A7 0 1 Self-refresh range Normal self-refresh Extend temperture self-refresh (Optional) A6 0 1 Auto self-refresh method Manual SR reference (SRT) ASR enable (Optional) Partial array self-refresh A2 0 0 0 0 1 1 1 1 A1 A0 00 01 10 11 00 01 10 11 Refresh array Full Half : Quarter: 1/8 : 3/4 : Half : Quarter: 1/8 : Bank 0 to Bank 3 Bank 0 and Bank 1 Bank 0 Bank 2 to Bank 7 Bank 4 to Bank 7 Bank 6 and Bank 7 Bank 7 (BA [2:0] = 000, 001, 010, 011) (BA [2:0] = 000, 001) (BA [2:0] = 000) (BA [2:0] = 010, 011, 100, 101,110 ,111) (BA [2:0] = 100, 101, 110, 111) (BA [2:0] = 110, 111) (BA [2:0] = 111) ¾ A10 A9 0 0 0 1 1 1 0 1 Rtt_WR Dynamic ODT off (write does not affect Rtt value) RZQ/4 RZQ/2 Reserved A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 CAS write Latency (CWL) 5 (tCK ³ 2.5ns) 6 (2.5ns > tCK ³ 1.875ns) 7 (1.875ns > tCK ³ 1.5ns) 8 (1.5ns > tCK ³ 1.25ns) Reserved Reserved Reserved Reserved Notes: 1. BA2, A8, and A11 to A13 are RFU and must be programmed to 0 during MRS. 2. The Rtt_WR value can be applied during writes even when Rtt_Nom is desabled. Dring write leveling, Dynamic ODT is not avaiable. 3. Optiona in DDR3 SDRAM: If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self-refresh is entered. Data integrity will be maintained if tREF conditions are met and no self-refresh command is issued. MR2 Programming Data Sheet E1248E40 (Ver. 4.0) 77 EDJ1108BABG, EDJ1116BABG DDR3 SDRAM Mode Register 3 [MR3] The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and BA0, while controlling the states of address pins according to the table below. BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address field Mode register 3 0*1 1 1 0*1 MPR MPR Loc MPR Address MPR location A1 A0 MPR Operation 0 0 1 0 1 Predefined pattern*2 RFU RFU RFU A2 0 1 MPR Normal operation*3 Data flow from MPR 0 1 1 Notes : 1. BA2, A3 to A13 are reserved for future use (RFU) and must be programmed to 0 during MRS. 2. The predefined pattern will be used for read synchronization. 3 . When MPR control is set for normal operation, MR3 A[2]=0, MR3 A[1:0] will be ignored. MR3 Programming Data Sheet E1248E40 (Ver. 4.0) 78 EDJ1108BABG, EDJ1116BABG Burst Length (MR0) Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as shown in the figure MR0 Programming. The burst length determines the maximum number of column locations that can be accessed for a given read or write command. Burst length options include fixed BC4, fixed BL8, and on the fly which allows BC4 or BL8 to be selected coincident with the registration of a read on write command Via A12 (/BC). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Burst Chop In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on the fly via A12(/BC), the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. Burst Type (MR0) [Burst Length and Sequence] Burst length 4 (burst chop) Operation READ Starting address (A2, A1, A0) 000 001 010 011 100 101 110 111 WRITE 0VV 1VV 8 READ 000 001 010 011 100 101 110 111 WRITE VVV Sequential addressing (decimal) 0, 1, 2, 3, T, T, T, T 1, 2, 3, 0, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 0, 1, 2, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 6, 7, 4, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 4, 5, 6, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 0, 5, 6, 7, 4 2, 3, 0, 1, 6, 7, 4, 5 3, 0, 1, 2, 7, 4, 5, 6 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 4, 1, 2, 3, 0 6, 7, 4, 5, 2, 3, 0, 1 7, 4, 5, 6, 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 Interleave addressing (decimal) 0, 1, 2, 3, T, T, T, T 1, 0, 3, 2, T, T, T, T 2, 3, 0, 1, T, T, T, T 3, 2, 1, 0, T, T, T, T 4, 5, 6, 7, T, T, T, T 5, 4, 7, 6, T, T, T, T 6, 7, 4, 5, T, T, T, T 7, 6, 5, 4, T, T, T, T 0, 1, 2, 3, X, X, X, X 4, 5, 6, 7, X, X, X, X 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 Remark: T: Output driver for data and strobes are in high impedance. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins. X: Don’t Care. Notes: 1. Page length is a function of I/O organization and column addressing 2. 0...7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst. Data Sheet E1248E40 (Ver. 4.0) 79 EDJ1108BABG, EDJ1116BABG DLL Enable (MR1) The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering selfrefresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any write operation. DDR3 does not require DLL to be locked prior to any write operation. DDR3 requires DLL to be locked only for read operation and to achieve synchronous ODT timing. DLL-off Mode DDR3 DLL-off mode is entered by setting MR1 bit A0 to 1; this will disable the DLL for subsequent operations until A0 bit set back to 0. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLLoff mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of /CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL = 6 and CWL = 6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the Data Strobe to Data relationship (tDQSQ, tQH, tQHS). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL + CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL + CL − 1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCK (min.). and tDQSCK (max.) is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation are shown at following Timing Diagram (CL = 6, BL8): T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK, /CK Command BA DQSdiff_DLL-on RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 READ A DQ_DLL-on RL (DLL-off) = AL + (CL - 1) = 5 CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 tDQSCK(DLL-off)_min DQSdiff_DLL-off DQ_DLL-off CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 tDQSCK(DLL-off)_max DQSdiff_DLL-off DQ_DLL-off CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 DLL-Off Mode Read Timing Operation Data Sheet E1248E40 (Ver. 4.0) 80 EDJ1108BABG, EDJ1116BABG DLL on/off switching procedure DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0 bit set back to “0”. DLL “on” to DLL “off” Procedure To switch from DLL “on” to DLL “off” requires the frequency to be changed during self-refresh outlined in the following procedure: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL.) 2. Set MR1 Bit A0 to “1” to disable the DLL. 3. Wait tMOD. 4. Enter self-refresh mode; wait until (tCKSRE) satisfied. 5. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. After stable clock, wait tCKSRX before issuing SRX command. 7. Starting with the self-refresh exit command, CKE must continuously be registered high until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when selfrefresh mode was entered, the ODT signal must continuously be registered low until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when self-refresh mode was entered, ODT signal can be registered low or high. 8. Wait tXS, then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be necessary. A ZQCL command may also be issued after tXS). 9. Wait for tMOD, then DRAM is ready for next command. Ta CK /CK tMOD tCKSRE tCKSRX tXS tMOD MRS Valid Tb Tc Tc+1 Tc+2 Td Te Tf Tf+1 Tf+2 Tg Tg+1 Th Command MRS SRE NOP SRX tCKESR CKE ODT Change Frequency DLL Switch Sequence from DLL-on to DLL-off Data Sheet E1248E40 (Ver. 4.0) 81 EDJ1108BABG, EDJ1116BABG DLL “off” to DLL “on” Procedure To Switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.) 2. Enter Self-refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section. 4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the self-refresh exit command, CKE must continuously be registered high until all tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self-refresh mode was entered, the ODT signal must continuously be registered low until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was entered, ODT signal can be registered low or high. 6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL. 7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset. 8. Wait tMRD, and then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be necessary. After tMOD is satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK.) 9. Wait for tMOD, and then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued. Ta CK /CK tCKSRE tCKSRX tXS tMRD MRS Tb Tc Tc+1Tc+2 Td Te Tf Tf+1 Tf+2 Tg tDLLK tMRD MRS Command SRE NOP SRX MRS Valid tCKESR CKE ODTLoff + 1x tCK ODT Change Frequency DLL Switch Sequence from DLL-Off to DLL-On Data Sheet E1248E40 (Ver. 4.0) 82 EDJ1108BABG, EDJ1116BABG Additive Latency (MR1) A posted /CAS read or write command when issued is held for the time of the Additive Latency (AL) before it is issued inside the device. The read or write posted /CAS command may be issued with or without auto precharge. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). The value of AL is also added to compute the overall Write Latency (WL). MRS (1) bits A4 and A3 are used to enable Additive latency. MRS1 A4 0 0 1 1 A3 0 1 0 1 AL* 0 (posted CAS disabled) CL − 1 CL − 2 Reserved Note: AL has a value of CL − 1 or CL − 2 as per the CL value programmed in the /CAS latency MRS setting. Data Sheet E1248E40 (Ver. 4.0) 83 EDJ1108BABG, EDJ1116BABG Write Leveling (MR1) For better signal integrity, DDR3 memory module adopts fly by topology for the commands, addresses, control signals and clocks. The fly by topology has benefits for reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes Controller hard to maintain tDQSS, tDSS and tDSH specification. Therefore, the controller should support ’write leveling’ in DDR3 SDRAM to compensate the skew. Write leveling is a scheme to adjust DQS to CK relationship by the controller, with a simple feedback provided by the DRAM. The memory controller involved in the leveling must have adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay established through this exercise would ensure tDQSS, tDSS and tDSH specification. A conceptual timing of this scheme is shown as below. Source diff_Clock diff_DQS Destination diff_Clock diff_DQS DQ X 0 0 Push DQS to capture 0-1 transition DQ X 1 1 Write leveling concept DQS, /DQS driven by the controller during leveling mode must be terminated by the DRAM, based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits should carry the leveling feedback to the controller across the DRAM configurations, ×8 and ×16. On a ×16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS (diff_DQSU) to clock relationship whereas the lower data bits would indicate the lower diff_DQS (diff_DQSL) to clock relationship. DRAM Setting for Write Leveling and DRAM Termination Function in That Mode DRAM enters into Write leveling mode if A7 in MR1 set 1. And after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set 0 (MR1 Setting Involved in the Leveling Procedure table). Note that in write leveling mode, only DQS/DQS terminations are activated and deactivated via ODT pin, not like normal operation (refer to the DRAM Termination Function in The Leveling Mode table) [MR1 Setting Involved in the Leveling Procedure] Function Write leveling enable Output buffer mode (Qoff) MR1 bit A7 A12 Enable 1 0 Disable 0 1 1 Note Note: 1. Output buffer mode definition is consistent with DDR2 [DRAM Termination Function in The Leveling Mode] ODT pin@DRAM De-asserted Asserted DQS, /DQS termination Off On DQs termination Off Off Note: In Write Leveling Mode with its output buffer disabled (MR1 [bit7] = 1 with MR1 [bit12] = 1) all RTT_Nom settings are allowed; in Write Leveling Mode with its output buffer enabled (MR1 [bit7] = 1 with MR1 [bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. Data Sheet E1248E40 (Ver. 4.0) 84 EDJ1108BABG, EDJ1116BABG Write Leveling Procedure Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. Since the controller levelizes rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal. Controller may drive DQS low and /DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these signals. After tWLMRD, controller provides a single DQS, /DQS edge which is used by the DRAM to sample CK driven from controller. tWLMRD timing is controller dependent. DRAM samples CK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS, /DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS delay setting and launches the next DQS, /DQS pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS delay setting and write leveling is achieved for the device. The below figure describes detailed timing diagram for overall procedure and the timing parameters are shown in below figure. tWLS T1 tWLS T2 tWLH CK*5 /CK Command *2 *2 MRS tWLH *3 *4 NOP NOP NOP NOP NOP NOP NOP NOP *3 NOP NOP NOP tMOD ODT tWLDQSEN *6 *6 tDQSL (min.) tDQSH (min.) tDQSL (min.) tDQSH (min.) diff_DQS*4 tWLOE All DQs, Prime DQ*1 Remaining DQs tWLMRD tWLO tWLO Notes:1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state through out the leveling procedure. 2. MRS : Load MR1 to enter write leveling mode. 3. NOP : NOP or deselec 4. diff_DQS is the differential data strobe (DQS, /DQS). Timing reference points are the zero crossing. DQS is shown with solid line, /DQS is shown with dotted line. 5. CK, /CK : CK is shown with solid dark line, where as /CK is drawn with dotted line. 6. DQS needs to fulfill minimum pulse width requirements tDQSH (min.) and tDQSL (min.) as defined for regular writes; the max pulse width is system dependent. Timing Details Write leveling Sequence Data Sheet E1248E40 (Ver. 4.0) 85 EDJ1108BABG, EDJ1116BABG Write Leveling Mode Exit The following sequence describes how the Write Leveling Mode should be exited: 1. After the last rising strobe edge(see T111), stop driving the strobe signals (see ~T128). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (T145). 2. Drive ODT pin low (tIS must be satisfied) and continue registering low (see T128). 3. After the RTT is switched off: disable Write Level Mode via MR command (see T132). 4. After tMOD is satisfied (T145), any valid commands may be registered. (MR commands may already be issued after tMRD (T136). T111 T112 T116 T117 T128 T131 T132 T136 T145 CK, /CK Command WL_off MRS Valid tMOD BA tIS 1 Valid Valid Valid tMRD ODT tODTL_off RTT_DQS-/DQS DQS-/DQS RTT_DQ tWLO + tWLOE DQ Result = 1 Timing Details Write leveling Exit Data Sheet E1248E40 (Ver. 4.0) 86 EDJ1108BABG, EDJ1116BABG TDQS, /TDQS function (MR1) TDQS (Termination Data Strobe) is a feature of ×8 DDR3 SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. TDQS is not supported in ×16 configurations. When enabled via the mode register, the same termination resistance function is applied to the TDQS and /TDQS pins that are applied to the DQS and /DQS pins. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data strobe function of RDQS is not provided by TDQS. The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided and the /TDQS pin is not used. See Table TDQS, /TDQS function for details. The TDQS function is available in ×8 DDR3 SDRAM only and must be disabled via the mode register A11 = 0 in MR1 for ×16 configurations. [TDQS, /TDQS function] A11@MR1 0 1 TDQS enable Disable Enable Notes: 1. If TDQS is enabled, the DM function is disabled. 2. When not used, TDQS function can be disabled to save termination power 3. TDQS function is only available for ×8 DRAM and must be disabled for ×16 [Function matrix] A11@MR1 (TDQS enable) 0 1 DM/TDQS DM TDQS NU/ /TDQS High-Z /TDQS Data Sheet E1248E40 (Ver. 4.0) 87 EDJ1108BABG, EDJ1116BABG Extended Temperature Usage (MR2) [Mode Register Description] Field Bits Description Description Auto self-refresh (ASR) (Optional) when enabled, DDR3 SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TC during subsequent self-refresh operation Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TC during subsequent self-refresh operation If ASR = 1, SRT bit must be set to 0 ASR A6 0 1 Manual SR Reference (SRT) ASR enable (optional) SRT A7 0 1 Normal operating temperature range Extended (optional) operating temperature range Partial Array Self-Refresh (PASR) Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in figure of MR2 programming will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is issued. /CAS Write Latency (CWL) The /CAS Write Latency is defined by MR2 bits [A3, A5], as shown in figure of MR2 programming. /CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + /CAS Write Latency (CWL); WL = AL + CWL. For more information on the sup-ported CWL and AL settings based on the operating clock frequency, refer to “Standard Speed Bins”. For detailed Write operation refer to “WRITE Operation”. Auto Self-Refresh Mode - ASR Mode (optional) DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6 = 1 and MR2 bit A7 = 0. The DRAM will manage self-refresh entry in either the Normal or Extended (optional) Temperature Ranges. In this mode, the DRAM will also manage self-refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0. If the ASR mode is not enabled (MR2 bit A6 = 0), the SRT bit (MR2 A7) must be manually programmed with the operating temperature range required during self-refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Self- Refresh Temperature Range - SRT (optional) If ASR = 0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT = 0, then the DRAM will set an appropriate refresh rate for self-refresh operation in the Normal Temperature Range. If SRT = 1 then the DRAM will set an appropriate, potentially different, refresh rate to allow self-refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table for details. For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0 and the DRAM should not be operated outside the Normal Temperature Range. Data Sheet E1248E40 (Ver. 4.0) 88 EDJ1108BABG, EDJ1116BABG [Self-Refresh Mode Summary] MR2 A6 0 A7 0 Self-refresh operation Self-refresh rate appropriate for the Normal Temperature Range Self-refresh rate appropriate for either the Normal or Extended Temperature Ranges. The DRAM must support Extended Temperature Range. The value of the SRT bit can effect selfrefresh power consumption, please refer to the Self- refresh Current for details. ASR enabled (for devices supporting ASR and Normal Temperature Range). Self-refresh power consumption is temperature dependent ASR enabled (for devices supporting ASR and Extended Temperature Range). Self-refresh power consumption is temperature dependent Illegal Allowed operating temperature range for self-refresh mode Normal (0°C to +85°C) 0 1 Normal and Extended (0°C to +95°C) 1 0 Normal (0°C to +85°C) 1 1 0 1 Normal and Extended (0°C to +95°C) Dynamic ODT (Rtt_WR) DDR3 SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. MR2 register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”. Data Sheet E1248E40 (Ver. 4.0) 89 EDJ1108BABG, EDJ1116BABG Multi Purpose Register (MR3) The Multi Purpose Register (MPR) function is used to read out predefined system timing calibration bit sequence. Memory Core MR3 A2: MPR-off MPR Read Multi Purpose Register Pre-defined data for Reads DQ, DM, DQS, /DQS Pads Pre-defined data pattern can be loaded into Multi Purpose Register (MPR) and read out by external read command. · MR3 bit A2 defines dataflow from normal memory core or MPR. Once the dataflow defined, the MPR contents can be continuously read out by regular READ or READ with Auto Precharge command. · Conceptual Block Diagram of Multi Purpose Register To enable the MPR, a mode register set (MRS) command must be issued to MR3 register with bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP/tRPA met). Once the MPR is enabled, any subsequent READ or READA commands will be redirected to the multi purpose register. The resulting operation when a READ or READA command is issued is defined by MR3 bits [A1: A0] when the MPR is enabled. When the MPR is enabled, only READ or READA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power-down mode, self-refresh, and any other nonREAD/READA command are not allowed during MPR enable mode. The /RESET function is supported during MPR enable mode. [Functional Description of MR3 Bits for MPR] MR3 A2 MPR 0 1 A [1:0] MPR-Loc Don’t care (0 or 1) MR3 A [1:0] Function Notes Normal operation, no MPR transaction. All subsequent reads will come from DRAM array. All subsequent WRITEs will go to DRAM array. Enable MPR mode, subsequent READ/READA commands defined by MR3 A [1:0] 1 bits. Note: 1. See Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register table Data Sheet E1248E40 (Ver. 4.0) 90 EDJ1108BABG, EDJ1116BABG One bit wide logical interface via all DQ pins during READ operation  Register Read on ×8: DQ [0] drives information from MPR. DQ [7:1] either drive the same information as DQ [0], or they drive 0.  Register Read on ×16: DQL [0] and DQU [0] drive information from MPR. DQL [7:1] and DQU [7:1] either drive the same information as DQL [0], or they drive 0. Note: A standardization of which DQ is used by DDR3 SDRAM for MPR reads is strongly recommended to ensure functionality also for AMB2 on DDR3 FB-DIMM. • Addressing during Multi Purpose Register reads for all MPR agents:  BA [2:0]: don’t care.  A [1:0]: A [1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed  A [2]: For BL8, A [2] must be equal to 0. 1 Burst order is fixed to [0,1,2,3,4,5,6,7] * For Burst Chop 4 cases, the burst order is switched on nibble base 1 A [2] = 0, Burst order: 0,1,2,3 * A [2] = 1, Burst order: 4,5,6,7 *1  A [9:3]: don’t care  A10(AP): don’t care  A12(/BC): Selects burst chop mode on-the-fly, if enabled within MR0  A11: don’t care • Regular interface functionality during register reads:  Support two burst ordering which are switched with A2 and A [1:0] = 00.  Support of read burst chop (MRS and on-the-fly via A12(/BC).  All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3 SDRAM.  Regular read latencies and AC timings apply.  DLL must be locked prior to MPR Reads. Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Data Sheet E1248E40 (Ver. 4.0) 91 EDJ1108BABG, EDJ1116BABG Functional Block Diagrams Figures below provide functional block diagrams for the multi purpose register in ×8 and ×16 DDR3 SDRAM. Memory Array 8× 8 8× 8 64 Copy to DQ[7:0] 8 Q MPR DQ[7:0] Read Path DQS /DQS DM ByteLane Functional Block Diagram of Multi Purpose Register in ×8 DDR3 SDRAM Data Sheet E1248E40 (Ver. 4.0) 92 EDJ1108BABG, EDJ1116BABG Memory Array 8× 8 8× 8 DQU[7:0] Read Path DQSU /DQSU 8× 8 64 DMU ByteLaneUpper Copy to DQU[7:0] 8× 8 8 8× 8 64 Copy to DQL[7:0] 8 DQL[7:0] Read Path DQSL /DQSL Q MPR DML ByteLaneLower Functional Block Diagram of Multi Purpose Register in ×16 DDR3 SDRAM Data Sheet E1248E40 (Ver. 4.0) 93 EDJ1108BABG, EDJ1116BABG Register Address Table The table below provides an overview of the available data locations, how they are addressed by MR3 A [1:0] during a MR0 to MR3, and how their individual bits are mapped into the burst order bits during a multi purpose register read. [Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register] MR3 A [2] MR3 A [1:0] Function Burst Length Read Address Burst Order and Data Pattern A [2:0] 000 000 100 000 000 100 000 000 100 000 000 100 Burst order 0,1,2,3,4,5,6,7 Pre-defined pattern [0,1,0,1,0,1,0,1] Burst order 0,1,2,3, Pre-defined pattern [0,1,0,1] Burst order 4,5,6,7 Pre-defined pattern [0,1,0,1] Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3 Burst order 4,5,6,7 Burst order 0,1,2,3,4,5,6,7 Burst order 0,1,2,3, Burst order 4,5,6,7 Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 00 BL8 Read predefined pattern for BC4 system calibration BC4 BL8 1 01 RFU BC4 BC4 BL8 1 10 RFU BC4 BC4 BL8 1 11 RFU BC4 BC4 Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Relevant Timing Parameters The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD and tMPRR. Besides these timings, all other timing parameters needed for proper operation of the DDR3 SDRAM need to be observed. [MPR Recovery Time tMPRR] Symbol Description tMPRR Multi Purpose Register Recovery Time, defined between end of MPR read burst and MRS which reloads MPR or disables MPR function Data Sheet E1248E40 (Ver. 4.0) 94 EDJ1108BABG, EDJ1116BABG Protocol Examples Protocol Example: Read Out Predetermined Read-Calibration Pattern Multiple reads from Multi Purpose Register, in order to do system level read timing calibration based on predetermined and standardized pattern. Protocol Steps: • Precharge All • Wait until tRP is satisfied • MRS MR3, op-code “A2 = 1 “ and “A[1:0] = 00“  Redirect all subsequent reads into the Multi Purpose Register, and load Pre-defined pattern into MPR. • Wait until tMRD and tMOD are satisfied (Multi Purpose Register is then ready to be read). During the period MR3 A2 =1, no data write operation is allowed. • Read:  A [1:0] = ‘00’ (Data burst order is fixed starting at nibble, always 00 here)  A [2] = ‘0’ (For BL8, burst order is fixed as 0,1,2,3,4,5,6,7)  A12(/BC) = 1 (use regular burst length of 8)  All other address pins (including BA [2:0] and A10(AP)): don’t care. • After RL = AL + CL, DRAM bursts out the predefined Read Calibration Pattern. • Memory controller repeats these calibration reads until read data capture at memory controller is optimized. • After end of last MPR read burst wait until tMPRR is satisfied. • MRS MR3, op-code “A2 = 0“ and “A[1:0] = valid data but value are don’t care“  All subsequent read and write accesses will be regular READs and WRITEs from/to the DRAM array. • Wait until tMRD and tMOD are satisfied • Continue with “regular” DRAM commands, like activate a memory bank for regular read or write access, T0 T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T39 CK /CK tMRD Command tMOD *1 READ NOP PALL NOP MRS NOP MRS NOP tRP tMOD tMPRR Valid BA A[1:0] A[2] A[9:3] A10(AP) A[11] A12(/BC) A[15:13] 3 0 3 Valid 0 *2 1 00 1 0 0 *2 0 00 0 0 0 0 Valid Valid Valid Valid Valid 0 0 0 *1 DQS, /DQS RL DQ Notes: 1. READ with BL8 either by MRS or OTF 2. Memory Control must drive 0 on A[2:0] VIH or VIL MPR Readout of Predefined Pattern, BL8 fixed Burst Order, Single Readout Data Sheet E1248E40 (Ver. 4.0) 95 EDJ1108BABG, EDJ1116BABG T0 CK /CK tMRD Command PALL NOP MRS NOP *1 READ NOP *1 READ NOP T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T43 tMOD MRS NOP tRP BA A[1:0] A[2] A[9:3] A10, AP A[11] A12(/BC) A[15:13] DQS, /DQS 1 3 0 1 00 0 0 0 0 tMOD Valid *2 *2 tCCD Valid tMPRR 3 Valid *2 *2 0 0 0 0 0 00 0 0 0 0 Valid Valid Valid Valid Valid *1 Valid Valid Valid Valid Valid *1 RL RL DQ Notes: 1. READ with BL8 either by MRS or OTF 2. Memory Control must drive 0 on A[2:0] VIH or VIL MPR Readout of Predefined Pattern, BL8 Fixed Burst Order, Back-to-Back Readout T0 CK /CK T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T43 tMRD Command PALL NOP tMOD *1 READ NOP *1 READ NOP MRS NOP MRS NOP tRP tMOD tCCD Valid Valid *2 *3 *2 *4 tMPRR BA A[1:0] A[2] A[9:3] A10(AP) A[11] A12(/BC) A[15:13] 3 0 1 00 1 3 Valid 0 0 0 1 0 00 0 0 0 0 Valid Valid Valid Valid Valid *1 Valid Valid Valid Valid Valid *1 0 0 0 0 DQS, /DQS RL RL DQ VIH or VIL Notes:1. READ with BC4 either by MRS or OTF 2. Memory Control must drive 0 on A[1:0] 3. A[2] = 0 selects lower 4 nibble bits 0 ... 3 4. A[2] = 1 selects upper 4 nibble bits 4 ... 7 MPR Readout Predefined Pattern, BC4, Lower Nibble Then Upper Nibble Data Sheet E1248E40 (Ver. 4.0) 96 EDJ1108BABG, EDJ1116BABG T0 CK, /CK T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T43 tMRD Command PALL NOP tMOD READ MRS NOP *1 NOP READ *1 NOP MRS NOP tRP tMOD tCCD Valid Valid tMPRR BA A[1:0] A[2] A[9:3] A10, AP A[11] A12(/BC) A[15:13] 3 0 1 00 1 3 Valid 0 1 *2 *4 0 0 *2 *3 0 00 0 0 0 0 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid 0 0 0 0 *1 *1 DQS, /DQS RL RL DQ Notes:1. READ with BC4 either by MRS or OTF 2. Memory Control must drive 0 on A[1:0] 3. A[2] = 0 selects lower 4 nibble bits 0 ... 3 4. A[2] = 1 selects upper 4 nibble bits 4 ... 7 VIH or VIL MPR Readout of Predefined Pattern, BC4, Upper Nibble Then Lower Nibble Data Sheet E1248E40 (Ver. 4.0) 97 EDJ1108BABG, EDJ1116BABG Operation of the DDR3 SDRAM Read Timing Definition Read timing is shown in the following Figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: • tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, /CK. • tDQSCK is the actual position of a rising strobe edge relative to CK, /CK. • tQSH describes the DQS, /DQS differential output high time. • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: • tQSL describes the DQS, /DQS differential output low time. • tDQSQ describes the latest valid transition of the associated DQ pins. • tQH describes the earliest invalid transition of the associated DQ pins. tDQSQ; both rising/falling edges of DQS, no tAC defined. /CK CK tDQSCK(min.) tDQSCK(min.) tDQSCK(max.) tDQSCK(max.) Rising Strobe Region Rising Strobe Region tDQSCK tQSH tQSL tDQSCK /DQS DQS tQH tDQSQ tQH tDQSQ Associated DQ Pins READ Timing Definition Data Sheet E1248E40 (Ver. 4.0) 98 EDJ1108BABG, EDJ1116BABG • • • • • CK, /CK crossing to DQS, /DQS crossing tDQSCK; rising edges only of CK and DQS tQSH; rising edges of DQS to falling edges of DQS tQSL; rising edges of / DQS to falling edges of /DQS tLZ (DQS), tHZ (DQS) for preamble/postamble (see tHZ (DQS), tLZ (DQS) RL Measured to this point CK /CK tDQSCK(min.) tDQSCK(min.) tDQSCK(min.) tDQSCK(min.) tLZ(DQS)(min.) tQSH tQSL tRPRE tRPST DQS, /DQS Early strobe Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 tDQSCK(max.) tDQSCK(max.) tDQSCK(max.) tDQSCK(max.) tLZ(DQS)(max.) tQSH tQSL tHZ(DQS)(max.) tRPRE tRPST DQS, /DQS Late strobe Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Notes: Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min.) or tDQSCK(max.). Instead, rising strobe edge can vary between tDQSCK(min.) or tDQSCK(max.) within a burst. Likewise tLZ(DQS)(min.) and tHZ(DQS)(min.) are not tied to tDQSCK(min.) (early strobe case) and tLZ(DQS)(max.) and tHZ(DQS)(max.) are not tied to tDQSCK(max.) (late strobe case). The minimum pulse width of read preamble is defined by tRPRE(min.). The minimum pulse width of read preamble is defined by tRPST(min.). DDR3 Clock to Data Strobe Relationship Data Sheet E1248E40 (Ver. 4.0) 99 EDJ1108BABG, EDJ1116BABG • DQS, /DQS crossing to Data Output • tDQSQ; both rising/falling edges of DQS, no tAC defined T0 /CK CK Command*3 READ T4 T5 T6 T7 T8 T9 T10 NOP RL = AL + CL Address*4 Bank Coln tRPRE tQH tQH tRPST DQS, /DQS tDQSQ(max.) tLZ(DQ)(max.) tDQSQ(max.) tHZ(DQ)(max.) DQ*2 (Last data valid) tLZ(DQ)(min.) Dout n Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 DQ*2 (First data no longer valid) Dout n Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 All DQS collectively Dout n Dout n+1 Dout n+2 Dout n+3 Dout n+4 Dout n+5 Dout n+6 Dout n+7 Data valid Data valid VIH or VIL Notes: 1. BL8, RL = 5(AL = 0, CL = 5). 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] and A12 = 1 during READ command at T0. 5. Output timings are referenced to VDDQ/2, and DLL on for locking. 6. tDQSQ defines the skew between DQS, /DQS to data and does not define DQS, /DQS to clock. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary(either early or late) within a busy. DDR3 Data Strobe to Data Relationship Data Sheet E1248E40 (Ver. 4.0) 100 EDJ1108BABG, EDJ1116BABG tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ). The figure below shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as singled ended. tLZ (DQS): CK-/CK rising crossing at RL-1 tLZ (DQ): CK-/CK rising crossing at RL tHZ (DQS), tHZ (DQ) with BL8: CK-/CK rising crossing at RL + 4nCK tHZ (DQS), tHZ (DQ) with BL4: CK-/CK rising crossing at RL + 2nCK CK CK /CK tLZ VTT + 2x mV VTT + x mV tLZ (DQS), tLZ (DQ) VTT − x mV VTT − 2x mV /CK tLZ VOH − x mV VOH − 2x mV tHZ (DQS), tHZ (DQ) T2 T2 T1 VOL + 2x mV VOL + x mV T1 tLZ (DQS), tLZ (DQ) begin point = 2 ´ T1 - T2 tHZ (DQS), tHZ (DQ) end point = 2 ´ T1 - T2 Method for Calculating Transitions and Endpoints Data Sheet E1248E40 (Ver. 4.0) 101 EDJ1108BABG, EDJ1116BABG Read Operation During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (auto precharge can be enabled or disabled). • A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) • A12 = 1, BL8 A12 will be used only for burst length control, not a column address. The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register 0 (MR0), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the mode register 1 T0 CK /CK Command*3 READ NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Address*4 Bank Col n tRPRE tRPST DQS, /DQS DQ*2 CL = 5 RL = AL + CL Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 VIH or VIL Notes: 1. BL8, AL = 0, RL = 5, CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Operation, RL = 5 Data Sheet E1248E40 (Ver. 4.0) 102 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 READ NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Address*4 Bank Col n tRPRE tRPST DQS, /DQS*2 DQ AL = 4 RL = AL + CL CL = 5 Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 VIH or VIL Notes: 1. BL8, RL = 9, AL = (CL − 1), CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Operation, RL = 9 T0 CK /CK Command*3 READ NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 READ NOP tCCD Address*4 Bank Col n Bank Col b tRPRE tRPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7 RL = 5 VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and T4. READ (BL8) to READ (BL8) Data Sheet E1248E40 (Ver. 4.0) 103 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 READ NOP T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 READ NOP tCCD Address*4 Bank Col n Bank Col b tRPRE tRPST tRPRE tRPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout n n+1 n+2 n+3 Dout Dout Dout Dout b b+1 b+2 b+3 RL = 5 VIH or VIL Notes: 1. BC4, RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and T4. READ (BC4) to READ (BC4) T0 CK /CK Command*3 READ T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 NOP WRIT NOP tWR tBL = 4 clocks tWTR READ to WRIT command delay = RL + tCCD + 2tCK − WL Address*4 Bank Col n Bank Col b tRPRE tRPST tWPRE tWPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and WRIT command T6. READ (BL8) to WRITE (BL8) Data Sheet E1248E40 (Ver. 4.0) 104 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 READ NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 WRIT NOP tBL = 4 clocks tWR tWTR READ to WRIT Command delay = RL + tCCD/2 + 2tCK − WL Address*4 Bank Col n Bank Col b tRPRE tRPST tWPRE tWPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout n n+1 n+2 n+3 Din b Din b+1 Din b+2 Din b+3 WL = 5 VIH or VIL Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and WRIT command T4. READ (BC4) to WRITE (BC4) OTF T0 CK /CK Command*3 READ NOP T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 READ NOP tCCD Address*4 Bank Col n Bank Col b tRPRE tRPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 RL = 5 VIH or VIL Notes: 1. RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. READ (BL8) to READ (BC4) OTF Data Sheet E1248E40 (Ver. 4.0) 105 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 READ NOP T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 READ NOP tCCD Address*4 Bank Col n Bank Col b tRPRE tRPST tRPRE tRPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout n n+1 n+2 n+3 Dout Dout Dout Dout Dout Dout Dout Dout b b+1 b+2 b+3 b+4 b+5 b+6 b+7 RL = 5 Notes: 1. RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T4. VIH or VIL READ (BC4) to READ (BL8) OTF T0 CK /CK Command*3 READ NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 WRIT NOP tWR READ to WRIT command delay = RL + tCCD/2 + 2tCK − WL tBL = 4 clocks tWTR Address*4 Bank Col n Bank Col b tRPRE tRPST tWPRE tWPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout n n+1 n+2 n+3 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 VIH or VIL Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n , Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4. READ (BC4) to WRITE (BL8) OTF Data Sheet E1248E40 (Ver. 4.0) 106 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 READ NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 WRIT NOP tBL = 4 clocks tWR tWTR READ to WRIT command delay = RL + tCCD + 2tCK − WL Address*4 Bank Col n Bank Col b tRPRE tRPST tWPRE tWPST DQS, /DQS DQ*2 RL = 5 Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Din b Din b+1 Din b+2 Din b+3 WL = 5 VIH or VIL Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, n Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T6. READ (BL8) to WRITE (BC4) OTF T0 CK /CK Command*3 READ NOP tRTP = 4 nCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 PRE NOP tRP Address*4 Bank Col n tRPRE tRPST DQS, /DQS DQ*2 CL = 5 RL = AL + CL Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 VIH or VIL Notes: 1. BL8, AL = 0, RL = 5, CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Precharge Operation, RL = 5 Data Sheet E1248E40 (Ver. 4.0) 107 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 READ NOP tRTP = 4 nCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 PRE tRP NOP Address*4 Bank Col n tRPRE tRPST DQS, /DQS*2 DQ AL = 4 RL = AL + CL CL = 5 Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 Internal Read command starls here VIH or VIL Notes: 1. BL8, RL = 9, AL = (CL - 1), CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Precharge Operation, RL = 9 Data Sheet E1248E40 (Ver. 4.0) 108 EDJ1108BABG, EDJ1116BABG Write Timing Definition /CK*1 CK T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Command*3 WRIT NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP WL = AL + CWL Address*4 Bank, Col n tDQSS tDSH tWPRE (min) tDSH tDSH tDQSS(min) DQS, /DQS tDQSL tDQSH (min) tDSH tWPST (min) tDQSH tDQSH tDQSH tDQSH tDQSL tDQSL tDQSL tDQSL (min) tDSS DQ*2 Din n Din n+1 tDSS Din n+2 Din n+3 tDSS Din n+4 Din n+5 tDSS Din n+6 Din n+7 tDSS tWPRE (min) DQS, /DQS tDSH tDSH tDSH tDSH tWPST (min) tDQSH tDQSH tDQSH tDQSH tDQSL tDQSL tDQSL tDQSL (min) tDQSL tDQSH (min) tDSS DQ*2 Din n tDSS Din n+1 Din n+2 tDSS Din n+3 Din n+4 tDSS Din n+5 Din n+6 tDSS Din n+7 tDQSS tDSH tDSH tDSH tDSH tWPST (min) tDQSS(max) DQS, /DQS tWPRE (min) tDQSHtDQSLtDQSHtDQSLtDQSH tDQSLtDQSHtDQSL tDQSH (min) tDQSL (min) tDSS DQ*2 Din n tDSS Din n+1 Din n+2 tDSS Din n+3 Din n+4 tDSS Din n+5 Din n+6 tDSS Din n+7 Notes: 1. 2. 3. 4. 5. BL8, WL = 5 (AL = 0, CWL = 5) VIH or VIL Din n = data-in from column n. NOP commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. tDQSS must be met at each rising clock edge. Write Timing Definition Data Sheet E1248E40 (Ver. 4.0) 109 EDJ1108BABG, EDJ1116BABG Write Operation During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (auto precharge can be enabled or disabled). • A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) • A12 = 1, BL8 A12 will be used only for burst length control, not a column address. The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is equal to (AL + CWL). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR). T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP WL = AL + CWL Address*4 Bank Col n tWPRE tWPST DQS, /DQS DQ*2 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 VIH or VIL Notes: 1. BL8, WL = 5 (AL = 0, CWL = 5) 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. Burst Write Operation, WL = 5 Data Sheet E1248E40 (Ver. 4.0) 110 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP Address*4 Bank Col n tWPRE tWPST DQS, /DQS DQ*2 AL = 4 WL = AL + CWL CWL = 5 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 VIH or VIL Notes: 1. BL8, WL = 9 (AL = (CL − 1), CL = 5, CWL = 5) 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRITcommand at T0. Burst Write Operation, WL = 9 T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Tn Tn+1 Tn+2 NOP tWTR*5 READ Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 RL = 5 Notes: 1. BC4, WL = 5, RL = 5. 2. Din n = data-in from column n; Dout b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0 and READ command at Tn. 5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7. VIH or VIL Write to Read Operation Data Sheet E1248E40 (Ver. 4.0) 111 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Tn Tn+1 Tn+2 NOP tWR*5 PRE Address*4 Bank Col n tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 Notes: VIH or VIL 1. BC4, WL = 5, RL = 5. 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0. 5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies the last burst write cycle until the precharge command can be issued to the same bank . Write to Precharge Operation T0 CK /CK Command*3 WRIT NOP tCCD T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 WRIT NOP tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS DQ*2 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 WL = 5 Notes: 1. BL8, WL = 5 (CWL = 5, AL = 0) VIH or VIL 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0 and T4. WRITE (BL8) to WRITE (BL8) Data Sheet E1248E40 (Ver. 4.0) 112 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP tCCD WRIT NOP tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 Din b Din b+1 Din b+2 Din b+3 WL = 5 Notes: 1. BC4, WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by either MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0 and T4. VIH or VIL WRITE (BC4) to WRITE (BC4) T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP tWTR READ NOP Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 RL = 5 Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0) VIH or VIL 2. Din n = data-in from column n; DOUT b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13. WRITE (BL8) to READ (BC4/BL8) Data Sheet E1248E40 (Ver. 4.0) 113 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP tBL = 4 clocks tWTR READ NOP Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 RL = 5 Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0) 2. Din n = data-in from column n; Dout b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0. READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13. VIH or VIL WRITE (BC4) to READ (BC4/BL8) T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP tCCD WRIT NOP tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 Din b Din b+1 Din b+2 Din b+3 WL = 5 Notes: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T4. VIH or VIL WRITE (BL8) to WRITE (BC4) Data Sheet E1248E40 (Ver. 4.0) 114 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command*3 WRIT T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP tCCD WRIT NOP tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST tWPRE tWPST DQS, /DQS DQ*2 WL = 5 Din n Din n+1 Din n+2 Din n+3 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 Notes: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4. VIH or VIL WRITE (BC4) to WRITE (BL8) Data Sheet E1248E40 (Ver. 4.0) 115 EDJ1108BABG, EDJ1116BABG Write Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However it is desirable for certain minor violations, that the DRAM is guaranteed not to "hang up" and error to be limited to that particular operation. For the following it will be assumed that there are no timing violations w.r.t to the write command itself (including ODT etc.) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with this write command. In the example (Figure Write Timing Parameters) the relevant strobe edges for write burst A are associated with the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH tDQSS) be violated for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. In the example (Figure Write Timing Parameters) the relevant strobe edges for write burst A are associated with the clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5 and T9. Any timing requirements starting and ending on one of these strobe edges are T8, T8.5, T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5 and T13. Some edges are associated with both bursts. T0 CK /CK Command*3 WRIT NOP WRIT T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 NOP Address*4 A B /CS ODTL WL tDQSS tDSS tDQSL tWPRE tDSH tDQSH tWPST BL/2 + 2 + ODTL DQS, /DQS tDH tDS DQ*2 VIH or VIL Write Timing Parameters Data Sheet E1248E40 (Ver. 4.0) 116 EDJ1108BABG, EDJ1116BABG Write Data Mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs, Consistent with the implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to ensure matched system timing. DM is not used during read cycles. T1 DQS /DQS DQ T2 T3 T4 T5 T6 in in in in in in in in DM Write mask latency = 0 Data Mask Timing /CK CK [tDQSS(min.)] Command WRIT WL tWR NOP tDQSS DQS, /DQS DQ DM WL in0 in2 in3 [tDQSS(max.)] tDQSS DQS, /DQS DQ DM in0 in2 in3 Data Mask Function, WL = 5, AL = 0 shown Data Sheet E1248E40 (Ver. 4.0) 117 EDJ1108BABG, EDJ1116BABG Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge command is triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank independently or all banks simultaneously. Four address bits A10, BA0, BA1 and BA2 are used to define which bank to precharge when the command is issued. [Bank Selection for Precharge by Address Bits] A10 L L L L L L L L H BA0 L H L H L H L H × BA1 L L H H L L H H × BA2 L L L L H H H H × Precharged Bank(s) Bank 0 only Bank 1 only Bank 2 only Bank 3 only Bank 4 only Bank 5 only Bank 6 only Bank 7 only All banks 0 to 7 Remark: H: VIH, L: VIL, ×: VIH or VIL Data Sheet E1248E40 (Ver. 4.0) 118 EDJ1108BABG, EDJ1116BABG Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto precharge function is engaged. During auto precharge, a read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. Auto precharge can also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Burst Read with Auto Precharge If A10 is high when a Read Command is issued, the Read with Auto precharge function is engaged. The DDR3 SDRAM starts an auto precharge operation on the rising edge which is (AL + BL/2) cycles later from the read with AP command when tRAS (min.) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point of auto precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst Write with Auto precharge If A10 is high when a write command is issued, the Write with auto precharge function is engaged. The DDR3 SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time (tWR). The bank-undergoing auto precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. Data Sheet E1248E40 (Ver. 4.0) 119 EDJ1108BABG, EDJ1116BABG Auto-Refresh The refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command is non persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires refresh cycles at an average periodic interval of tREFI. When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters a refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the refresh command can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during a refresh command. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the refresh command and the next valid command, except NOP or DESL, must be greater than or equal to the minimum refresh cycle time tRFC(min) as shown in the following figure. Note that the tRFC timing parameter depends on memory density. In general, a refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 refresh commands can be postponed during operation of the DDR3 SDRAM, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. In case that 8 refresh commands are postponed in a row, the resulting maximum interval between the surrounding refresh commands is limited to 9 × tREFI. A maximum of 8 additional refresh commands can be issued in advance (“pulled in”), with each one reducing the number of regular refresh commands required later by one. Note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 × tREFI. At any given time, a maximum of 16 REF commands can be issued within tREFI. Before entering self-refresh mode, all postponed refresh commands must be executed. T0 /CK CK VIH T1 T2 T3 CKE ≥ tRP ≥ tRFC ≥ tRFC Command PRE NOP REF REF NOP Any Command Refresh Command Timing tREFI 9 × tRER t tRFC 8 × REF-Commands postponed Postponing Refresh Command tREFI 9 × tRER t tRFC 8 × REF-Commands postponed Pulling-in Refresh Command Data Sheet E1248E40 (Ver. 4.0) 120 EDJ1108BABG, EDJ1116BABG Self-Refresh The self-refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the system is powered down. When in the self-refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM device has a built-in timer to accommodate self-refresh operation. The Self-Refresh Entry (SELF) command is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Before issuing the self-refresh entry command, the DDR3 SDRAM must be idle with all bank precharge state with tRP satisfied. Also, on-die termination must be turned off before issuing Self-refresh entry command, by either registering ODT pin low “ODTL + 0.5tCK” prior to the self-refresh entry command or using MRS to MR1 command. Once the self-refresh entry command is registered, CKE must be held low to keep the device in self-refresh mode. The DLL is automatically disabled upon entering Self-refresh and is automatically enabled (including a DLL-Reset) upon exiting self-refresh. When the DDR3 SDRAM has entered self-refresh mode all of the external control signals, except CKE and /RESET, are “don’t care”. For proper self-refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VREFCA and VREFDQ) must be at valid levels. The DRAM initiates a minimum of one refresh command internally within tCKESR period once it enters self-refresh mode. The clock is internally disabled during self-refresh operation to save power. The minimum time that the DDR3 SDRAM must remain in self-refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock tCKSRE clock cycles after self-refresh entry is registered, however, the clock must be restarted and stable tCKSRX clock cycles before the device can exit self-refresh operation. To protect DRAM internal delay on CKE line to block the input signals, one NOP (or DESL) command is needed after self-refresh entry. The procedure for exiting self-refresh requires a sequence of events. First, the clock must be stable tCKSRX prior to CKE going back high. Once a Self-Refresh Exit command (SREX, combination of CKE going high and either NOP or DESL on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements (TBD) must be satisfied. CKE must remain high for the entire self-refresh exit period tXSDLL for proper operation except for self-refresh reentry. Upon exit from self-refresh, the DDR3 SDRAM can be put back into Self-refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or DESL commands must be registered on each positive clock edge during the self-refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of Self-refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from self-refresh mode. Upon exit from self-refresh, the DDR3 SDRAM requires a minimum of one extra refresh command before it is put back into self-refresh mode. Ta Tb Tc Tc+1Tc+2 Td Te Tf Tf+1 Tf+2 Tg Tg+1 Th Th+1 CK, /CK tRP tCKSRE tCKSRX tXSDLL *4 Command PALL tXS SREX SELF NOP *1 *2 *2 *3 *3 Valid Valid Valid Valid tCKESR CKE ODTLoff + 0.5 x tCK ODT Notes: 1. 2. 3. 4. Only NOP or DESL commands. Valid commands not requiring a locked DLL. Valid commands requiring a locked DLL. One NOP or DESL commands. Self-Refresh Entry and Exit Timing Data Sheet E1248E40 (Ver. 4.0) 121 EDJ1108BABG, EDJ1116BABG Power-Down Mode Power-down is synchronously entered when CKE is registered low (along with NOP or DESL command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. During power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after in-progress commands are completed, the device will be in active power-down mode. Entering power-down deactivates the input and output buffers, excluding CK, /CK, ODT, CKE and /RESET. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or DESL commands are needed during the CKE switch off and cycle(s) after this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED has expired. [Power-Down Entry Definitions] Status of DRAM Active (A bank or more Open) Precharged (All banks Precharged) Precharged (All Banks Precharged) MR0 bit A12 Don’t Care DLL On PD Exit Fast Relevant Parameters tXP to any valid command tXP to any valid command. Since it is in precharge state, commands here will be ACT, AR, MRS, PRE or PALL . tXPDLL to commands who need DLL to operate, such as READ, READA or ODT control line. tXP to any valid command 0 Off Slow 1 On Fast Also the DLL is disabled upon entering precharge power-down for slow exit mode, but the DLL is kept enabled during precharge power-down for fast exit mode or active power-down. In power-down mode, CKE low, RESET high and a stable clock signal must be maintained at the inputs of the DDR3 SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care” (If RESET goes low during power-down, the DRAM will be out of PD mode and into reset state). CKE low must be maintained until tPD has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or DESL command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC Characteristics table of this data sheet. Data Sheet E1248E40 (Ver. 4.0) 122 EDJ1108BABG, EDJ1116BABG Timing Diagrams for Proposed CKE with Power-Down Entry, Power-Down Exit /CK CK Command BA T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 Tx Tx+1 READ Valid NOP NOP tRDPDEN tCPDED tIS CKE VIH RL = CL + AL = 5 (AL = 0) tPD out 2 out out 3 4 out 3 out out 5 6 out 7 DQ(BL8) DQ(BC4) out 0 out 0 out 1 out out 1 2 Power-Down Entry after Read and Read with Auto Precharge T0 CK /CK Command BA WRITA Valid T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T14 T15 T16 T17 T18 Tn NOP NOP NOP tCPDED tIS CKE tWRAPDEN WL=5 DQ(BL8) DQ(BC4) in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 tWR* tPD in 0 in 1 in 2 in 3 Note: tWR is programmed through MRS. Start Internal Precharge Power-Down Entry After Write with Auto Precharge Data Sheet E1248E40 (Ver. 4.0) 123 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command BA WRITE Valid NOP NOP T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Tx Tx+1 Tx+2 Tx+3 tCPDED tIS CKE tWRPDEN WL=5 tWR tPD DQ(BL8) DQ(BC4) in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 0 in 1 in 2 in 3 Power-Down Entry after Write T0 CK /CK T1 Tn Tn+1 Tx Ty tIH tPD tIH CKE tIS tIS tCPDED Command Valid NOP NOP tCKE (min.) NOP NOP NOP NOP NOP Valid NOP NOP NOP NOP N tXP Enter power-down mode Exit power-down Note: Valid command at T0 is ACT, NOP, DESL or precharge with still one bank remaining open after completion of precharge command. Active Power-Down Entry and Exit Timing Diagram T0 CK /CK tIH T1 Tn Tn+1 Tx Ty tPD tIH CKE tIS tIS tCPDED Command NOP NOP tCKE (min.) NOP NOP NOP NOP NOP Valid NOP NOP NOP1 NOP N Enter power-down mode tXP Exit power-down Precharge Power-Down (Fast Exit Mode) Entry and Exit Data Sheet E1248E40 (Ver. 4.0) 124 EDJ1108BABG, EDJ1116BABG T0 CK /CK tIH tIH T1 Tn Tn+1 Tx Ty CKE tIS tIS tPD tCPDED tCKE (min.) NOP NOP NOP NOP NOP NOP Valid NOP Valid NOP NO Command NOP NOP NOP tXP tXPDLL Enter power-down mode Exit power-down Precharge Power-Down (Slow Exit Mode) Entry and Exit T0 CK /CK Command REF T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP tCPDED tREFPDEN tIS CKE Refresh Command to Power-Down Entry T0 CK /CK Command ACT T1 T2 T3 T4 Tn Tn+1 Tn+2 End NOP NOP tCPDED tPD tACTPDEN tIS CKE Active Command to Power-Down Entry Data Sheet E1248E40 (Ver. 4.0) 125 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command PRE/ PALL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 End NOP NOP tCPDED tPREPDEN tIS CKE Precharge/Precharge All Command to Power-Down Entry T0 CK /CK Command T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 Tn+4 Tn+5 Tn+6 Tn+7 MRS NOP NOP NOP NOP NOP tCPDED tMRSPDEN tIS CKE MRS Command to Power-Down Entry Data Sheet E1248E40 (Ver. 4.0) 126 EDJ1108BABG, EDJ1116BABG Timing Values tXXXPDEN Parameters Status of DRAM Idle or Active Idle or Active Active Active Active Active Active Idle Idle Last Command before CKE_low Activate Precharge READ/READA WRIT for BL8MRS, BL8OTF, BC4OTF WRIT for BC4MRS WRITA for BL8MRS, BL8OTF, BC4OTF WRITA for BC4MRS Refresh Mode Register Set Parameter tACTPDEN tPRPDEN tRDPDEN tWRPDEN tWRPDEN tWRAPDEN tWRAPDEN tREFPDEN tMRSPDEN Parameter Value 1 1 RL + 4 + 1 WL + 4 + (tWR/tCK (avg)) * WL + 2 + (tWR/tCK (avg))* WL + 4 + WR* + 1 WL + 2 + WR* + 1 1 tMOD 2 2 1 1 Unit nCK nCK nCK nCK nCK nCK nCK nCK Notes: 1. tWR is defined in ns, for calculation of tWRPDEN, it is necessary to round up tWR / tCK to next integer. 2. WR in clock cycles as programmed in mode register. Power-Down Entry and Exit Clarification Case 1: When CKE registered low for power-down entry, tPD must be satisfied before CKE can be registered high for powerdown exit. Case 1a: After power-down exit, tCKE must be satisfied before CKE can be registered low again. T0 CK /CK tIH tIH T1 Tn Tn+1 Tx Ty CKE tIS tIS tPD tCKE tCPDED Command NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP N Enter power-down Exit power-down Power-Down Entry/Exit Clarifications (1) Data Sheet E1248E40 (Ver. 4.0) 127 EDJ1108BABG, EDJ1116BABG Case 2: For certain CKE intensive operations, for example, repeated "PD Exit - Refresh - PD Entry" sequence, the number of clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL updated. Therefore the following conditions must be met in addition to tPD in order to maintain proper DRAM operation when Refresh commands is issued in between PD Exit and PD Entry. Power-down mode can be used in conjunction with Refresh command if the following conditions are met: 1. tXP must be satisfied before issuing the command 2. tXPDLL must be satisfied (referenced to registration of PD exit) before next power-down can be entered. T0 T1 Tn Tn+1 Tx Ty CK /CK tIH tIH CKE tIS tIS tCPDED tXPDLL (min.) tCKE (min.) tPD Command NOP NOP NOP NOP NOP REF NOP NOP NOP NOP NOP NOP NOP tXP Enter power-down Exit power-down Power-Down Entry/Exit Clarifications (2) Case 3: If an early PD Entry is issued after Refresh command, once PD Exit is issued, NOP or DESL with CKE high must be issued until tRFC from the refresh command is satisfied. This means CKE cannot be de-asserted twice within tRFC window. T0 CK /CK tIH CKE tIS tPD tCPDED Command REF NOP NOP T1 Tn Tn+1 Tx Ty tIH tIS tXPDLL tCKE (min.) NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid N tRFC (min.) Enter power-down Exit power-down Note: * Synchronous ODT Timing starts at the end of tXPDLL (min.) Power-Down Entry/Exit Clarifications (3) Data Sheet E1248E40 (Ver. 4.0) 128 EDJ1108BABG, EDJ1116BABG Input Clock Frequency Change during Precharge Power-Down Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be “stable” during almost all states of normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (Spread Spectrum Clocking) specifications. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self-refresh mode and (2) precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3 SDRAM has been successfully placed in to SelfRefresh mode and tCKSRE has been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the self-refresh entry and exit specifications must still be met as outlined in Self-Refresh section. The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit mode.) ODT must be at a logic low ensuring RTT is in an off state prior to entering Precharge Power-down mode and CKE must be at a logic low. A minimum of tCKSRE must occur after CKE goes low before the clock frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable low levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL relock period, ODT must remain low. After the DLL lock time, the DRAM is ready to operate with new clock frequency. This process is depicted in the figure Clock Frequency Change in Precharge Power-Down Mode. Previous clock frequency T0 /CK CK tIH CKE tCPDED Command NOP NOP NOP NOP NOP MRS NOP Valid New clock frequency Tb Tc Tc+1 Td Td+1 Te Te+1 T1 T2 Ta tIS tCKSRE tCKSRX Address tAOFPD/tAOF ODT DQS, /DQS DQ High-Z High-Z tXP DLL RESET Valid tDLLK DM Enter precharge power-down mode Frequency change Exit precharge power-down mode Notes: 1. Applicable for both slow exit and fast exit precharge power-down. 2. tCKSRE and tCKSRX are self-refresh mode specifications but the values they represent are applicable here. 3. tAOFPD and tAOF must be satisfied and outputs high-z prior to T1; refer to ODT timing for exact requirements. Clock Frequency Change in Precharge Power-Down Mode Data Sheet E1248E40 (Ver. 4.0) 129 EDJ1108BABG, EDJ1116BABG On-Die Termination (ODT) ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, /DQS and DM for ×8 configuration (and TDQS, /TDQS for ×8 configuration, when enabled via A11=1 in MR1) via the ODT control pin. For ×16 configuration ODT is applied to each DQU, DQL, DQSU, /DQSU, DQSL, /DQSL, DMU and DML signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown in figure Functional Representation of ODT. ODT To other circuitry like RCV, ... VDDQ/2 RTT Switch DQ, DQS, DM, TDQS Functional Representation of ODT The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information, see below. The value of RTT is determined by the settings of Mode Register bits (see MR1 programming figure in the section Programming the Mode Register). The ODT pin will be ignored if the Mode Register MR1 is programmed to disable ODT and in self-refresh mode. ODT Mode Register and ODT Truth Table The ODT Mode is enabled if either of MR1 bits A2 or A6 or A9 are non-zero. In this case the value of RTT is determined by the settings of those bits. Application: Controller sends WRIT command together with ODT asserted. • One possible application: The rank that is being written to provide termination. • DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR) • DRAM does not use any write or read command decode information • The Termination Truth Table is shown in the Termination Truth Table [Termination Truth Table] ODT pin 0 1 DRAM Termination State OFF ON, (OFF, if disabled by MR1 bits A2, A6 and A9 in general) Data Sheet E1248E40 (Ver. 4.0) 130 EDJ1108BABG, EDJ1116BABG Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes are: • Active mode • Idle mode with CKE high • Active power-down mode (regardless of MR0 bit A12) • Precharge power-down mode if DLL is enabled during precharge power-down by MR0 bit A12. In synchronous ODT mode, RTT will be turned on or off ODTLon clock cycles after ODT is sampled high by a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency (WL) by: ODTLon = WL – 2; ODTLoff = WL – 2. ODT Latency and Posted ODT In Synchronous ODT mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL − 2; ODTLoff = CWL + AL − 2. For details, refer to DDR3 SDRAM latency definitions. [ODT Latency Table] Parameter ODT turn-on Latency ODT turn-off Latency Symbol ODTLon ODTLoff Value WL – 2 = CWL + AL – 2 WL – 2 = CWL + AL – 2 Unit nCK nCK Synchronous ODT Timing Parameters In synchronous ODT mode, the following timing parameters apply (see Synchronous ODT Timing Examples (1)): ODTLLow, ODTLLoff, tAON,(min.), (max.), tAOF,(min.),(max.) Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min ) is the point in time when the device starts to turn-off the ODT resistance. Maximum RTT turn-off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL4) or ODTH8 (BL8) after the Write command (see figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a Write command until ODT is registered low. Data Sheet E1248E40 (Ver. 4.0) 131 EDJ1108BABG, EDJ1116BABG T0 CK /CK CKE ODTH4 (min.) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 END ODT AL = 3 AL = 3 IntODT ODTLon = CWL + AL – 2 ODTLoff = CWL + AL – 2 CWL – 2 tAON (max.) tAON (min.) tAOF (max.) tAOF (min.) RTT RTT Synchronous ODT Timing Examples (1): AL=3, CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6 T0 CK /CK CKE Command WRS4 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 ODTH4 ODTH4 ODTH4 ODT ODTLoff = WL – 2 ODTLoff = WL – 2 ODTLon = WL – 2 ODTLon = WL – 2 tAON (max.) tAON (min.) tAOF (max.) tAOF (min.) RTT tAOF (max.) tAOF (min.) DRAM_RTT RTT tAON (max.) tAON (min.) Synchronous ODT Timing Examples (2)*: BC4, WL = 7 ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BC4) or ODTH8 (BL8) after write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered high at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the write command at T7. Data Sheet E1248E40 (Ver. 4.0) 132 EDJ1108BABG, EDJ1116BABG ODT during Reads As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. RTT may nominally not be enabled until one clock cycle after the end of the post-amble as shown in the example in the figure below. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example in the figure below. ODT must be disabled externally during Reads by driving ODT low. (example: CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL -2 = 8; ODTLoff = CWL + AL - 2 = 8) T0 CK /CK Command Address READ A T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 End RL = AL + CL ODT ODTLoff = WL – 2 = CWL + AL – 2 ODTLon = WL – 2 = CWL + AL – 2 tAOF (max.) tAOF (min.) tAON (min.) tAON (max.) RTT DRAM_RTT DQS, /DQS DQ RTT out out out out out out out out 01234567 Example of ODT during Reads Data Sheet E1248E40 (Ver. 4.0) 133 EDJ1108BABG, EDJ1116BABG Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by the “Dynamic ODT” feature as described as follows: Functional Description: The Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to ’1’. The function and is described as follows: • Two RTT values are available: RTT_Nom and RTT_WR.  The value for RTT_Nom is pre-selected via bits A[9,6,2] in MR1  The value for RTT_WR is pre-selected via bits A[10,9] in MR2 • During operation without write commands, the termination is controlled as follows:  Nominal termination strength RTT_Nom is selected.  Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff. • When a write command (WRIT, WRITA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows:  A latency ODTLcnw after the write command, termination strength RTT_WR is selected.  A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the write command, termination strength RTT_Nom is selected.  Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff. Table Latencies and Timing Parameters Relevant for Dynamic ODT shows latencies and timing parameters, which are relevant for the on-die termination control in Dynamic ODT mode: When ODT is asserted, it must remain high until ODTH4 is satisfied. If a write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BC4) or ODTH8 (BL8) after the write command (see the figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. [Latencies and Timing Parameters Relevant for Dynamic ODT] Parameters ODT turn-on Latency ODT turn-off Latency ODT latency for changing from RTT_Nom to RTT_WR ODT latency for change from RTT_WR to RTT_Nom (BC4) ODT latency for change from RTT_WR to RTT_Nom (BL8) Minimum ODT high time after ODT assertion Minimum ODT high time after Write (BC4) Minimum ODT high time after Write (BL8) RTT change skew Symbols ODTLon ODTLoff ODTLcnw ODTLcwn4 Defined from Registering external ODT signal high Registering external ODT signal low Registering external write command Registering external write command Registering external write command Defined to Turning termination on Turning termination off Definition for all DDR3 speed bins ODTLon = WL – 2.0 ODTLoff = WL – 2.0 Unit nCK nCK nCK nCK Change RTT strength from ODTLcnw = WL – 2.0 RTT_Nom to RTT_WR Change RTT strength from ODTLcwn4 = RTT_WR to RTT_Nom 4 + ODTLoff Change RTT strength from ODTLcwn8 = RTT_WR to RTT_Nom 6 + ODTLoff ODTH4 (min.) = 4 ODTH4 (min.) = 4 ODTH8 (min.) = 6 0.3ns to 0.7ns ODTLcwn8 ODTH4 ODTH4 ODTH8 tADC nCK nCK nCK nCK tCK (avg) registering ODT high ODT registered low registering Write with ODT registered low ODT high registering Write with ODT registered low ODT high ODTLcnw RTT valid ODTLcwn Data Sheet E1248E40 (Ver. 4.0) 134 EDJ1108BABG, EDJ1116BABG Mode Register Settings for Dynamic ODT Mode: The table Mode Register for RTT Selection shows the Mode Register bits to select RTT_Nom and RTT_WR values. [Mode Register for RTT Selection] MR1 A9 0 0 0 0 1 1 1 1 A6 0 0 1 1 0 0 1 1 A2 0 1 0 1 0 1 0 1 RTT_Nom (RZQ) off RZQ/4 RZQ/2 RZQ/6 RZQ/12* RZQ/8* 2 2 MR2 RTT_Nom (Ω) off 60 120 40 20 30 Reserved Reserved A10 0 0 1 1     A9 0 1 0 1     RTT_WR (RZQ) RTT_WR* (Ω) 1 Dynamic ODT OFF: Write does not affect RTT value RZQ/4 RZQ/2 Reserved     60 120 Reserved     Reserved Reserved Notes: 1. RZQ = 240Ω. 2. If RTT_Nom is used during WRITEs, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed. ODT Timing Diagrams T0 CK /CK ODTLcnw T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 Command WRS4 ODTH4 ODTH4 ODT ODTLon tAON (min.) tADC (min.) RTT_WR ODTLoff tADC (min.) RTT_Nom tAOF (min.) RTT RTT_Nom tAON (max.) tADC (max.) tADC (max.) tAOF (max.) ODTLcwn4 DQS, /DQS DQ WL in in in in 0123 Dynamic ODT: Behavior with ODT Being Asserted Before and after the Write* Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the write command. In this example ODTH4 would be satisfied if ODT is low at T8 (4 clocks after the write command). Data Sheet E1248E40 (Ver. 4.0) 135 EDJ1108BABG, EDJ1116BABG T0 CK /CK Command ODTH4 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 ODT ODTLon ODTLoff tAON (min.) tAOF (min.) RTT_Nom RTT tAON (max.) tAOF (max.) DQS, /DQS DQ Dynamic ODT*: Behavior without Write Command; AL = 0, CWL = 5 Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. T0 CK /CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 ODTLcnw Command WRS8 ODTH8 ODT ODTLon ODTLoff tAON (min.) tAOF (min.) RTT tADC (max.) ODTLcwn8 RTT_WR tAOF (max.) DQS, /DQS DQ WL in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for Duration of 6 Clock Cycles Note: Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH8 = 6 is exactly satisfied. Data Sheet E1248E40 (Ver. 4.0) 136 EDJ1108BABG, EDJ1116BABG T0 CK /CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 ODTLcnw Command WRS4 ODTH4 ODT ODTLon ODTLoff tAON (min.) tADC (min.) tAOF (min.) RTT_WR RTT_Nom RTT tADC (max.) ODTLcwn4 tADC (max.) tAOF (max.) DQS, /DQS DQ WL in 0 in 1 in 2 in 3 Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for a Duration of 6 Clock Cycles, Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. T0 CK /CK T1 T2 T3 T4 T5 T6 T7 T8 T9 ODTLcnw Command WRS4 ODTH4 ODT ODTLon tAON (min.) tAOF (min.) ODTLoff RTT tADC (max.) RTT_WR tAOF (max.) ODTLcwn4 DQS, /DQS DQ WL in 0 in 1 in 2 in 3 Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for Duration of 4 Clock Cycles Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH4 = 4 is exactly satisfied. Data Sheet E1248E40 (Ver. 4.0) 137 EDJ1108BABG, EDJ1116BABG Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLL-on mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Precharge power-down mode if DLL is disabled during precharge power-down by MR0 bit A12. In asynchronous ODT timing mode, internal ODT command is not delayed by Additive Latency (AL) relative to the external ODT command. In asynchronous ODT mode, the following timing parameters apply (see figure Asynchronous ODT Timings): tAONPD (min.), (max.), tAOFPD (min.),(max.) Minimum RTT turn-on time (tAONPD (min.)) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to turn on. Maximum RTT turn-on time (tAONPD (max.)) is the point in time when the ODT resistance is fully on. tAONPD (min.) and tAONPD (max.) are measured from ODT being sampled high. Minimum RTT turn-off time (tAOFPD (min.)) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn-off time (tAOFPD (max.)) is the point in time when the on-die termination has reached high impedance. tAOFPD (min.) and tAOFPD (max.) are measured from ODT being sampled low. CK /CK CKE tIH tIS tIH tIS ODT tAONPD (max.) tAOFPD (min.) DRAM_RTT tAONPD (min.) RTT tAOFPD (max.) Asynchronous ODT Timings on DDR3 SDRAM with Fast ODT Transition: AL is Ignored In precharge power-down, ODT receiver remains active, however no read or write command can be issued, as the respective address/command receivers may be disabled. [Asynchronous ODT Timing Parameters for All Speed Bins] Symbol tAONPD tAOFPD Parameters Asynchronous RTT turn-on delay (power-down with DLL frozen) Asynchronous RTT turn-off delay (power-down with DLL frozen) min. 2 2 max. 8.5 8.5 Unit ns ns [ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period] Description ODT to RTT turn-on delay min. min {ODTLon × tCK + tAON(min.); tAONPD(min.) } min { (WL − 2.0) × tCK + tAON(min.); tAONPD(min.) } min { ODTLoff × tCK +tAOF(min.); tAOFPD(min.) } min { (WL − 2.0) × tCK +tAOF(min.); tAOFPD(min.) } WL − 1.0 max. max {ODTLon × tCK + tAON(max.); tAONPD(max.) } max {(WL − 2.0) × tCK + tAON(max.); tAONPD(max.) } max { ODTLoff × tCK + tAOF(max.); tAOFPD(max.) } max {(WL − 2.0) × tCK + tAOF(max.); tAOFPD(max.) } ODT to RTT turn-off delay tANPD Data Sheet E1248E40 (Ver. 4.0) 138 EDJ1108BABG, EDJ1116BABG Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0 there is a transition period around power-down entry, where the DDR3 SDRAM may show either synchronous or asynchronous ODT behavior. This transition period ends when CKE is first registered low and starts tANPD before that. If there is a Refresh command in progress while CKE goes low, then the transition period ends tRFC after the refresh command. tANPD is equal to (WL − 1.0) and is counted (backwards) from the clock cycle where CKE is first registered low. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.) and (ODTLon × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.) and (ODTLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period. CK /CK Command CKE PD entry transition period tANPD REF NOP NOP ODT ODT_A_sync ODTLoff tRFC tAOF (max.) tAOF (min.) DRAM_RTT_A_sync ODT_B_tran RTT ODTLoff + tAOFPD (max.) tAOFPD (max.) ODTLoff + tAOFPD (min.) tAOFPD (min.) DRAM_RTT_B_tran ODT_C_async tAOFPD (max.) tAOFPD (min.) DRAM_RTT_C_async RTT Synchronous to Asynchronous Transition During Precharge Power-Down (with DLL Frozen) Entry (AL = 0; CWL = 5; tANPD = WL − 1 = 4) Data Sheet E1248E40 (Ver. 4.0) 139 EDJ1108BABG, EDJ1116BABG Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0, there is also a transition period around power-down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL − 1.0) and is counted backward from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.) and (ODTLon × tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon × tCK + tAON(max.)). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.) and (ODTLoff × tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff × tCK + tAOF(max.)). See ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period table. Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response. T1 CK /CK Command CKE PD exit transition period ODT_C_async tANPD tAOFPD (max.) tAOFPD (min.) DRAM_RTT_C_async ODT_B_tran tAOFPD (min.) ODTLoff + tAOF (min.) ODTLoff + tAOF (max.) tAOFPD (max.) DRAM_RTT_B_tran ODT_A_sync ODTLoff tAOF (max.) tAOF (min.) DRAM_RTT_A_sync RTT RTT T3 T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 T29 T31 T33 T35 NOP NOP tXPDLL Asynchronous to Synchronous Transition during Precharge Power-Down (with DLL Frozen) Exit (CL = 6; AL = CL - 1; CWL = 5; tANPD= WL − 1 = 9) Data Sheet E1248E40 (Ver. 4.0) 140 EDJ1108BABG, EDJ1116BABG Asynchronous to Synchronous ODT Mode during Short CKE high and Short CKE Low Periods If the total time in precharge power-down state or idle state is very short, the transition periods for power-down entry and power-down exit may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the power-down entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period). If the total time in idle state is very short, the transition periods for power-down exit and power-down entry may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the power-down exit transition period to the end of the power-down entry transition period. Note that in the bottom part of figure below it is assumed that there was no refresh command in progress when idle state was entered. CK /CK Command CKE REF NOP NOP NOP NOP tANPD tRFC PD entry transition period PD exit transition period tANPD tXPDLL short CKE low transition period CKE tANPD tANPD tXPDLL tXPDLL short CKE high transition period Transition Period for Short CKE Cycles with Entry and Exit Period Overlapping (AL = 0, WL = 5, tANPD = WL − 1 = 4) Data Sheet E1248E40 (Ver. 4.0) 141 EDJ1108BABG, EDJ1116BABG ZQ Calibration ZQ calibration command is used to calibrate DRAM RON and ODT values. DDR3 SDRAM needs longer time to calibrate RON and ODT at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM I/O which gets reflected as updated RON and ODT values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper. ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: ZQCorrection (Tsens × Tdriftrate) + (Vsens × Vdriftrate) where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/°C, VSens = 0.15%/mV, Tdriftrate = 1°C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as: 0.5 = 0.133 = 128ms (1.5 × 1) + (0.15 × 15) No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper or tZQCS. The quiet time on the DRAM channel allows in accurate calibration of RON and ODT. Once DRAM calibration is achieved the DRAM should disable ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh. Upon selfrefresh exit, DDR3 SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self-refresh exit is tXS. In dual rank systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper or tZQinit or tZQCS between ranks. CK Command A10 Address ZQCL A10 = H X NOP/DESL Valid ZQCS A10 = L X NOP/DESL Valid CKE tZQinit or tZQ oper tZQCS DQ Bus*2 Hi-Z Activities Hi-Z Activities Notes: 1. ODT must be disabled via ODT signal or MRS during calibration procedure. 2. All device connected to DQ bus should be High impedance during calibration. ZQ Calibration Data Sheet E1248E40 (Ver. 4.0) 142 EDJ1108BABG, EDJ1116BABG ZQ External Resistor Value and Tolerance DDR3 SDRAM has a 240Ω, ±1% tolerance external resistor connecting from the DDR3 SDRAM ZQ pin to ground. The resister can be used as single DRAM per resistor. Data Sheet E1248E40 (Ver. 4.0) 143 EDJ1108BABG, EDJ1116BABG Package Drawing 78-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Unit: mm 8.6 ± 0.1 INDEX MARK 0.2 S B 13.0 ± 0.1 0.2 S A 0.2 S 1.20 max. S 0.1 S 0.35 ± 0.05 78-φ0.45 ± 0.05 φ0.15 M S A B B A 9.6 1.6 0.8 6.4 INDEX MARK 0.8 ECA-TS2-0242-01 Data Sheet E1248E40 (Ver. 4.0) 144 EDJ1108BABG, EDJ1116BABG 96-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) 8.6 ± 0.1 INDEX MARK Unit: mm 0.2 S B 13.5 ± 0.1 0.2 S A 0.2 S 1.20 max. S 0.1 S 0.35 ± 0.05 96-φ0.45 ± 0.05 φ0.15 M S A B B 1.6 0.8 INDEX MARK 6.4 0.4 12.0 A 0.8 ECA-TS2-0243-01 Data Sheet E1248E40 (Ver. 4.0) 145 EDJ1108BABG, EDJ1116BABG Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDJ1108BABG, EDJ1116BABG. Type of Surface Mount Device EDJ1108BABG: 78-ball FBGA < Lead free (Sn-Ag-Cu) > EDJ1116BABG: 96-ball FBGA < Lead free (Sn-Ag-Cu) > Data Sheet E1248E40 (Ver. 4.0) 146 EDJ1108BABG, EDJ1116BABG N OTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Data Sheet E1248E40 (Ver. 4.0) 147 EDJ1108BABG, EDJ1116BABG The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0706 Data Sheet E1248E40 (Ver. 4.0) 148