DATA SHEET
128M bits SDRAM
EDS1232CATA (4M words × 32 bits)
Description
The EDS1232CA is a 128M bits SDRAM organized as 1,048,576 words × 32 bits × 4 banks. All inputs and outputs are synchronized with the positive edge of the clock. It is packaged in 86-pin plastic TSOP (II).
Pin Configurations
/xxx indicate active low signal.
86-pin Plastic TSOP(II) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /WE /CAS /RAS /CS A11 BA0 BA1 A10(AP) A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ28 DQ27 VDDQ DQ26 DQ25 VSSQ DQ24 VSS
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Features
• • • • •
2.5V power supply Clock frequency: 100MHz (max.) Single pulsed /RAS ×32 organization 4 banks can operate simultaneously and independently • Burst read/write operation and burst read/single write operation capability • Programmable burst length (BL): 1, 2, 4, 8 and full page • 2 variations of burst sequence ⎯ Sequential (BL = 1, 2, 4, 8, full page) ⎯ Interleave (BL = 1, 2, 4, 8) • Programmable /CAS latency (CL): 2, 3 • Byte control by DQM • Refresh cycles: 4096 refresh cycles/64ms • 2 variations of refresh ⎯ Auto refresh ⎯ Self refresh
Document No. E0388E11 (Ver. 1.1) Date Published May 2003 (K) Japan URL: http://www.elpida.com
L
Pr
A0 to A11, BA0, BA1
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2003
od
(Top view)
DQM0 to DQM3 DQ mask enable
Address inputs Bank select DQ0 to DQ31 Data input/output Chip select /CS Row address strobe /RAS /CAS Column address strobe /WE Write enable
CKE CLK VDD VSS
VDDQ VSSQ
Clock enable Clock input
Supply voltage Ground Supply voltage for DQ
t uc
NC Ground for DQ No connection
EDS1232CATA
Ordering Information
Part number EDS1232CATA-1A EDS1232CATA-1AL Supply voltage 2.5V Organization (words × bits) Internal Banks 4M × 32 4 Clock frequency MHz (max.) 100 /CAS latency 2, 3 Package 86-pin plastic TSOP (II)
Part Number
E D S 12 32 C A TA - 1A L
Elpida Memory
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Type
D: Monolithic Device
Product Code S: SDRAM
Spec. Detail Blank: Normal L: Low Power
Density / Bank 12: 128M / 4-bank Bit Organization 32: x32
Speed 1A: 100MHz/CL2,3
Voltage, Interface C: 2.5V, LVTTL Die Rev.
Data Sheet E0388E11 (Ver. 1.1)
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2
Package TA: TSOP (II)
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EDS1232CATA
CONTENTS Description .................................................................................................................................................... 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................... 9 Pin Function ................................................................................................................................................ 10 Command Operation................................................................................................................................... 11 Truth Table.................................................................................................................................................. 15 Simplified State Diagram ............................................................................................................................ 21 Programming Mode Registers .................................................................................................................... 22 Mode Register............................................................................................................................................. 23 Power-up sequence .................................................................................................................................... 26 Operation of the SDRAM ............................................................................................................................ 27 Timing Waveforms ...................................................................................................................................... 43 Package Drawing........................................................................................................................................ 50 Recommended Soldering Conditions ......................................................................................................... 51
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Data Sheet E0388E11 (Ver. 1.1)
L
Pr od t uc
3
EDS1232CATA
Electrical Specifications
• All voltages are referenced to VSS (GND). • After power up, execute power up sequence and initialization sequence before proper device operation is achieved (refer to the Power up sequence). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VT VDD, VDDQ IOS PD TA Tstg Rating –0.5 to +3.6 –0.5 to +3.6 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Note
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Caution
Parameter
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to +70°C)
Symbol min. typ. max. Unit Notes
L
VSS VIH VIL
Supply voltage
VDD, VDDQ
2.3
0 1.7 –0.3
2.5
0 ⎯ ⎯
2.7
0 VDD + 0.3* 0.7
1
V
V V V
Input high voltage Input low voltage
Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width ≤ 5ns). 2. VIL (min.) = –1.5V (pulse width ≤ 5ns).
Pr od t uc
4
Data Sheet E0388E11 (Ver. 1.1)
EDS1232CATA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Parameter /CAS latency Operating current (CL = 2) (CL = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Symbol IDD1 IDD1 IDD2P IDD2PS Grade max. 100 100 1 1 Unit mA mA mA mA Test condition Burst length = 1 tRC ≥ tRC (min.) IO = 0mA One bank active CKE ≤ VIL (max.) tCK = 15ns CKE ≤ VIL (max.) tCK = ∞ CKE ≥ VIH (min.) tCK = 15ns CS ≥ VIH (min.) Input signals are changed one time during 30ns CKE ≥ VIH (min.) tCK = ∞ CKE ≤ VIL (max.) tCK = 15ns CKE ≤ VIL (max.), tCK = ∞ CKE ≥ VIH (min.), tCK = 15 ns, /CS ≥ VIH (min.), Input signals are changed one time during 30ns. CKE ≥ VIH (min.), tCK = ∞, tCK ≥ tCK (min.), IO = 0mA, All banks active tRC ≥ tRC (min.) VIH ≥ VDD − 0.2V, VIL ≤ GND + 0.2V 2 3 Notes 1
IDD2N
20
mA
EO
Burst operating current Refresh current Self refresh current Self refresh current (L-version) Parameter Input leakage current Output leakage current Output high voltage Output low voltage
Data Sheet E0388E11 (Ver. 1.1)
Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable)
IDD2NS IDD3P IDD3PS
8 5 4
mA mA mA
IDD3N
25
mA
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.). 2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.). 3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Symbol ILI ILO VOH VOL min. –1.0 –1.5 2.0 — max. Unit
L
IDD3NS IDD4 IDD5 IDD6 IDD6 -xxL
15 130 200 2.0
mA mA mA mA mA
Pr
0.6 1.0 1.5 — 0.4 V V
od
Test condition µA µA IOH = –1mA IOL = 1mA
Notes
0 = VIN = VDDQ, VDDQ = VDD, All other pins not under test = 0V
0 = VIN = VDDQ DOUT is disabled
t uc
5
EDS1232CATA
Pin Capacitance (TA = 25°C, f = 1MHz)
Parameter Input capacitance Symbol Pins CI1 CI2 Data input/output capacitance CI/O Address min. 2.5 Typ — — — max. 4.0 4.0 6.5 Unit pF pF pF Notes
CLK, CKE, /CS, /RAS, 2.5 /CAS, /WE, DQM DQ 4.0
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
-1A Parameter Symbol tCK tCK tCH tCL tAC tOH tLZ tHZ tSI tHI tCKSP tRC min. 10 10 3 3 — 2 0 2 2 1 2 70 max. — — — — 6 — — 6 — — — ⎯ ⎯ 120000 ⎯ ⎯ ⎯ — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes
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System clock cycle time (CL = 2) (CL = 3) CLK high pulse width CLK low pulse width Access time from CLK Data-out hold time Input setup time Input hold time (refresh) Last data into active latency Mode register set cycle time Transition time (rise and fall) Refresh period (4096 refresh cycles)
Data Sheet E0388E11 (Ver. 1.1)
CLK to Data-out low impedance CLK to Data-out high impedance
CKE setup time (Power down exit)
ACT to REF/ACT command period (operation)
Active to Precharge command period
Active command to column command (same bank) tRCD Precharge to active command period tRP
Write recovery or data-in to precharge lead time
Active (a) to Active (b) command period
L
Pr
tRC 70 tRAS 50 20 20 tDPL 20 tDAL tRRD tRSC tT tREF 2CLK + 20ns 20 2 0.5 —
od
— ⎯ 30 64
ns CLK ns ms
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6
EDS1232CATA
Test Conditions • AC high level input voltage / low level input voltage: 2.1V / 0.3V • Input timing measurement reference level: 1.2V • Transition time (Input rise and fall time): 1ns • Output timing measurement reference level: 1.2V • Termination voltage (Vtt): 1.2V
tCK tCH CLK 2.1V 1.2V 0.3V tSETUP tHOLD 2.1V 1.2V 0.3V tAC tOH tCL
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Data Sheet E0388E11 (Ver. 1.1)
Input
Output
L
Output
Vtt Z = 50 Ω 50 Ω
30pF
Pr
7
Input Waveforms and Output Load
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EDS1232CATA
Relationship Between Frequency and Minimum Latency
Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Active command to active command (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CL = 2) (CL = 3) Last data out to active command (Auto precharge, same bank) Last data out to precharge (early precharge) (CL = 2) (CL = 3) Symbol lRCD lRC lRAS lRP lDPL lRRD lSREX lDAL lSEC lHZP lHZP lAPR lEP lEP -1A 100 10 2 7 5 2 2 2 1 4 7 2 3 1 –1 –2 1 77 13 2 6 4 2 2 2 1 4 6 2 3 1 –1 –2 1 Unit tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK Notes 1 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
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DQM to data in DQM to data out CKE to CLK disable /CS to command disable
Data Sheet E0388E11 (Ver. 1.1)
Column command to column command Write command to data in latency
Register set to active command
Power down exit to command input
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
L
Pr
lCCD lWCD lDID 0 0 0 0 lDOD lCLE 2 2 1 1 lMRD lCDD lPEC 2 0 1 2 0 1
od
tCK tCK
t uc
8
EDS1232CATA
Block Diagram
CLK CKE
Clock Generator Bank 3 Bank 2 Bank 1 Row Address Buffer & Refresh Counter
Address
Mode Register
Row Decoder
Bank 0
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Command Decoder
Sense Amplifier
Control Logic
/CS
/RAS /CAS /WE
Data Control Circuit
Input & Output Buffer
Latch Circuit
Column Address Buffer & Burst Counter
Column Decoder & Latch Circuit
DQM
DQ
Data Sheet E0388E11 (Ver. 1.1)
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EDS1232CATA
Pin Function
CLK (input pin) CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE (input pins) CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Synchronous DRAM suspends operation. When the Synchronous DRAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS (input pins) /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 to A11 (input pins) Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. Column Address is determined by A0 to 7 at the CLK rising edge in the read or write command cycle. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. BA0 and BA1 (input pin) BA0 and BA1 are bank select signal. (See Bank Select Signal Table) [Bank Select Signal Table]
Bank 0 Bank 1 Bank 2 Bank 3 BA0 L
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Data Sheet E0388E11 (Ver. 1.1)
Remark: H: VIH. L: VIL.
DQM (input pins) DQM controls I/O buffers. DQM0 controls DQ0 to 7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, DQM3 controls DQ24 to DQ31. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 to DQ31 (input/output pins) DQ pins have the same function as I/O pins on a conventional DRAM.
VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers.
L
H L H
Pr
10
BA1 L L H H
od
t uc
EDS1232CATA
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE) The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through A11 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this command, the Synchronous DRAM cannot accept any other commands.
CLK CKE /CS /RAS /CAS H
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Data Sheet E0388E11 (Ver. 1.1)
/WE BA0, BA1
(Bank select)
A10 Add
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High) The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling.
L
CLK CKE /CS H
Row Address Strobe and Bank Activate Command
Pr
/RAS /CAS /WE BA0, BA1 A10 Add
(Bank select)
Row Row
od t uc
11
EDS1232CATA
Precharge command (/CS, /RAS, /WE = Low, /CAS = High) This command begins precharge operation of the bank selected by BA0 and BA1. When A10 is High, all banks are precharged, regardless of BA0 and BA1. When A10 is Low, only the bank selected by BA0 and BA1 is precharged. After this command, the Synchronous DRAM can’t accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM’s /RAS rising.
CLK CKE /CS /RAS /CAS /WE H
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Data Sheet E0388E11 (Ver. 1.1)
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Precharge Command
Write command (/CS, /CAS, /WE = Low, /RAS = High) If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks.
L
CLK CKE /CS /RAS H
Pr
/CAS /WE BA0, BA1 A10 Add
(Bank select)
Col.
Column Address and Write Command
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12
EDS1232CATA
Read command (/CS, /CAS = Low, /RAS, /WE = High) Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address.
CLK CKE /CS /RAS /CAS /WE BA0, BA1
(Bank select)
H
A10 Add Col.
EO
Data Sheet E0388E11 (Ver. 1.1)
Column Address and and Read Command
CBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally. Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the Synchronous DRAM cannot accept any other command
CLK CKE /CS /RAS /CAS H
L
Pr
/WE BA0, BA1 A10 Add
(Bank select)
CBR (auto) Refresh Command
od t uc
13
EDS1232CATA
Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the Synchronous DRAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged.
CLK CKE /CS /RAS /CAS /WE
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Data Sheet E0388E11 (Ver. 1.1)
BA0, BA1
(Bank select)
A10 Add
Self Refresh Entry Command
Burst stop command (/CS = /WE = Low, /RAS, /CAS = High) This command can stop the current burst operation.
CLK CKE /CS /RAS /CAS /WE H
No operation (/CS = Low, /RAS, /CAS, /WE = High) This command is not an execution command. No operations begin or terminate by this command.
CLK
L
Pr
BA0, BA1 A10 Add
(Bank select)
Burst Stop Command in Full Page Mode
CKE /CS
/RAS /CAS
/WE BA0, BA1
(Bank select)
A10 Add
No Operation
od
H
t uc
14
EDS1232CATA
Truth Table
Command Truth Table
CKE Function Device deselect No operation Burst stop Read Read with auto precharge Write Write with auto precharge Bank activate Symbol DESL NOP BST READ READA WRIT WRITA ACT PRE PALL MRS n–1 H H H H H H H H H H H n × × × × × × × × × × × /CS H L L L L L L L L L L /RAS × H H H H H H L L L L /CAS × H H L L L L H H H L /WE × H L H H L L H L L L BA0, BA1 × × × V V V V V V × L A10 × × × L H L H V L H L A9 - A0, A11 × × × V V V V V × × V
EO
Precharge select bank Precharge all banks Mode register set
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data DQM Truth Table
CKE Symbol ENB MASK ENB0 ENB1 ENB2 ENB3 n–1 H H H H H H n × × × × × × × × × ×
DQM 0 L H L × × × H × × × 1 L H × L × × × H × × 2 L H × × L × × × H × 3 L H × × × L × × × H
L
Function
Data write / output enable
Data mask / output disable
DQ0 to DQ7 write enable/output enable DQ8 to DQ15 write enable/output enable
DQ16 to DQ23 write enable/output enable DQ24 to DQ31 write enable/output enable DQ0 to DQ7 write inhibit/output disable
DQ8 to DQ15 write inhibit/output disable
DQ16 to DQ23 write inhibit/output disable DQ24 to DQ31 write inhibit/output disable
Remark: H: VIH. L: VIL. ×: VIH or VIL
Pr
MASK0 H MASK 1 H MASK 2 MASK 3 H H
od
15
t uc
Data Sheet E0388E11 (Ver. 1.1)
EDS1232CATA
CKE Truth Table
CKE Current state Activating Any Clock suspend Idle Idle Self refresh Function Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR (auto) refresh command Self refresh entry Self refresh exit REF SELF Symbol n–1 H L L H H L L Idle Power down entry H H L L n L L H H L H H L L H H /CS × × × L L L H L H H L /RAS × × × L L H × H × × H /CAS × × × L L H × H × × H /WE × × × H H H × H × × H Address × × × × × × × × × × ×
EO
Power down
Data Sheet E0388E11 (Ver. 1.1)
Power down exit
Remark: H: VIH. L: VIL. ×: VIH or VIL
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16
EDS1232CATA
Function Truth Table*
Current state Idle /CS H L L L L L L L Row active H L
1
/RAS /CAS /WE Address × H H H L L L L × × H L L H H L L × H L L H H L L × × × H L H L H L × × H L H L H L × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OPCODE × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OPCODE × × ×
Command DESL NOP or BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT
Operation Nop or power down Nop or power down ILLEGAL ILLEGAL Row activating Nop CBR (auto) refresh or self refresh Mode register accessing Nop Nop Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read: Determine AP
Notes 2 2 3 3
4
EO
H L L H H L L L L L L L L Read H L L × H H L L L L L L Write H L L L L L L L L H H L L L L × H H H H L L L L
Data Sheet E0388E11 (Ver. 1.1)
5 5 3 6
L
H H L H L L H H L L × H H L L H H L L H L BA, CA, A10 BA, CA, A10 BA, RA H L BA, A10 H L × OPCODE × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OPCODE H L H L H L H L
7
Terminate burst, begin write: Determine AP 7, 8 ILLEGAL Terminate burst, Precharging 3
Pr
PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
ILLEGAL ILLEGAL Continue burst to end → Write recovering
od
ILLEGAL ILLEGAL ILLEGAL
Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read : Determine AP 7, 8 7 3 9
Terminate burst, new write : Determine AP
Terminate burst, Precharging
t uc
17
EDS1232CATA
Current state Read with auto precharge
/CS H L L L L L L L L
/RAS /CAS /WE Address × H H H H L L L L × × H H L L H H L L × × H L H L H L H L × × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OPCODE × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10
Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL
Operation Continue burst to end → Precharging Continue burst to end → Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end → Write recovering with auto precharge Continue burst to end → Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL ILLEGAL
Notes
3 3 3 3
EO
Write with auto precharge H L L H H L L L H H L L L L L L L Precharging H L L L L L L L L Row activating H L L L L L L L L × H H H H L L L L × H H H H L L L L
Data Sheet E0388E11 (Ver. 1.1)
H H L L H H
H L H L H L
NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST
3 3 3 3
L
L H L × L × H H L L H H L L × H H L L H H L L × H L × × × H L H L H L × H L H L H L H L × × × × ×
OPCODE
Pr
BA, CA, A10 READ/READA WRIT/WRITA ACT BA, CA, A10 BA, RA BA, A10 PRE/PALL REF/SELF OPCODE MRS DESL NOP BST BA, CA, A10 BA, CA, A10 BA, RA BA, A10 READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS OPCODE
3 3 3
ILLEGAL ILLEGAL
Nop → Enter idle after tRP
od
ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Nop → Enter bank active after tRCD
Nop → Enter bank active after tRCD
3 3
t uc
3, 10 3
18
EDS1232CATA
Current state Write recovering
/CS H L L L L L L L L
/RAS /CAS /WE Address × H H H H L L L L × × H H L L H H L L × H H L L H H L × H L H L H L H L × H L H L H L H L × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 × OPCODE × × × BA, CA, A10 BA, CA, A10 BA, RA BA, A10 ×
Command DESL NOP BST READ/READA WRIT/ WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/READA
Operation Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL Nop → Enter row active after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL
Notes
8
3 3
EO
Write recovering with auto H L H precharge L H L L L H H L L L L L L L Refresh H L L L L Mode register accessing H L L L L × H H H H × H H H L
Data Sheet E0388E11 (Ver. 1.1)
3, 8 3 3
Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data BA: Bank Address, CA: Column Address, RA: Row Address
Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Power down mode. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), the Synchronous DRAM will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus trun around, and/or write recovery requirements. 9. Must mask preceding data which don’t satisfy tDPL. 10. Illegal if tRRD is not satisfied.
L
L × × × H H L H L × × × × H L L × H H L L × × H L × × × × H L
OPCODE
Pr
DESL NOP BST READ/READA
ACT/PRE/PALL ILLEGAL REF/SELF/MRS ILLEGAL Nop → Enter idle after tRSC
Nop → Enter idle after tRSC ILLEGAL
ILLEGAL
od
ACT/PRE/PLL/ ILLEGAL REF/SELF/MRS
t uc
19
EDS1232CATA
Command Truth Table for CKE
CKE Current State Self refresh n–1 n H L L L L L Self refresh recovery H H H × H H H H L H H H H L L L L × H H L /CS × H L L L × H L L L H L L L × H L × /RAS /CAS /WE Address × × H H L × × H H L × H H L × × × × × × H L × × × H L × × H L × × × H × × × H L × × × × × × × × × × × × × × × × H × × × × × × × × × × × × × × × × × × × × × × Operation INVALID, CLK (n – 1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Continue self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK (n – 1) would exit power down EXIT power down EXIT power down Continue power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table CBR (auto) Refresh Notes
EO
H H H H H Power down H L L L All banks idle H H H H H H H H H H L L Row active H L Any state other than listed above H H L L
Data Sheet E0388E11 (Ver. 1.1)
Remark: H = VIH, L = VIL, × = VIH or VIL Notes: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. Must be legal command as defined in Function Truth Table.
L
H H H L L H H H H L L L L L H L × × H L H L H L L L L L H L × H L L L L × × × × × × × × L L × × × × × × × ×
Pr
H L L × × × × × H L L × × × × × × × × H L × × × × × × × × × × × × × × × ×
OPCODE Refer to operations in Function Truth Table Begin power down next cycle Refer to operations in Function Truth Table Refer to operations in Function Truth Table Self refresh 1
od
Exit power down next cycle Power down Clock suspend Maintain clock suspend
OPCODE Refer to operations in Function Truth Table
1
Refer to operations in Function Truth Table 1
Refer to operations in Function Truth Table Begin clock suspend next cycle Exit clock suspend next cycle
t uc
2
20
EDS1232CATA
Simplified State Diagram
Self Refresh
SE LF LF exi t
SE
Mode Register Set
MRS IDLE
REF
CBR(auto) Refresh
CK E
ACT
CK
Wr
Au
to
ite wit pre h ch arg
PR E( Pre cha rge ter min atio n)
EO
WRITE SUSPEND CKE WRITEA SUSPEND CKE POWER ON
E
Power Down
CKE ROW ACTIVE
BS T
CKE
Re BS ad T
Active Power Down
Write
W
e rit
Au h wit ad arge Re ch pre to PRE
Read
e
Data Sheet E0388E11 (Ver. 1.1)
L
WRITE CKE WRITEA CKE Precharge
Read
CKE READ CKE
Write
READ SUSPEND
Pr
n) atio min ter rge cha Pre E( PR
CKE READA CKE
READA SUSPEND
Precharge
od t uc
Automatic sequence Manual input
21
EDS1232CATA
Programming Mode Registers
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0 and BA1 as data inputs. The registers retain data until it is re-programmed, or the device loses power. The mode register has three fields; Options /CAS latency Wrap type Burst length : : : : A11 through A7, BA0, BA1 A6 through A4 A3 A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
EO
Data Sheet E0388E11 (Ver. 1.1)
/CAS Latency /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. ”Relationship between Frequency and Latency” shows the relationship of /CAS latency to the clock period and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. “Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
L
Pr
22
od t uc
EDS1232CATA
Mode Register
BA0 BA1 A11 0 0 0 A10 0 A10 x A10 A9 0 A9 1 A9 A8 0 A8 0 A8 1 BA0 BA1 A11 x x x A10 x A10 0 A9 x A9 0 A8 1 A8 0 A7 1 A7 0 A7 0 A7 1 A7 0 A6 V A6 A5 V A5 LTMODE A4 V A4 A3 V A3 WT A2 V A2 A1 V A1 BL A0 V A0 Mode Register Set Vender Specific V = Valid x = Don’t care A6 A6 A5 LTMODE A5 A4 A4 A3 WT A3 A2 A2 A1 BL A1 A0 Use in future A0 Burst Read and Single Write (for Write Through Cache) A6 A5 A4 A3 A2 A1 A0 JEDEC Standard Test Set (refresh counter test)
BA0 BA1 A11 x x x
BA0 BA1 A11
BA0 BA1 A11 0 0 0
EO
Data Sheet E0388E11 (Ver. 1.1)
Burst length
Bits2-0 000 001 010 011 100 101 110 111 0 1
WT = 0 1 2 4 8 R R R Full page
WT = 1 1 2 4 8 R R R R
L
CLK CKE /CS /RAS /CAS /WE A0 - A11, BA0, BA1
Wrap type
Sequential Interleave
Latency mode
Bits6-4 000 001 010 011 100 101 110 111
/CAS latency R R 2 3 R R R R
Pr
23
Remark R : Reserved
od
Mode Register Set Timing
Mode Register Set
t uc
EDS1232CATA
Burst Length and Sequence [Burst of Two]
Starting address (column address A0, binary) 0 1 Sequential addressing sequence (decimal) 0, 1 1, 0 Interleave addressing sequence (decimal) 0, 1 1, 0
[Burst of Four]
Starting address (column address A1 to A0, binary) 00 Sequential addressing sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave addressing sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
EO
01 10 11
[Burst of Eight]
Starting address (column address A2 to A0, binary) 000 001 010 011 100 101 110 111
Sequential addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3
Interleave addressing sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
Data Sheet E0388E11 (Ver. 1.1)
L
Pr
5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6
od t uc
24
EDS1232CATA
Address Bits of Bank-Select and Precharge
Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1 BA0 BA1 0 0 1 1 BA0 0 1 0 1 Result Select Bank 0 “Activate” command Select Bank 1 “Activate” command Select Bank 2 “Activate” command Select Bank 3 “Activate” command
(Activate command)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
BA1 BA0 A10 0 0 0 0 1 BA1 0 0 1 1 x BA0 0 1 0 1 x Result Precharge Bank 0 Precharge Bank 1 Precharge Bank 2 Precharge Bank 3 Precharge All Banks
(Precharge command)
EO
Col. A0 A1 A2 A3 (/CAS strobes)
x : Don’t care
0 A4 A5 A6 A7 A8 A9 A10 x BA1 BA0 1
disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst)
Data Sheet E0388E11 (Ver. 1.1)
L
BA1 0 0 1 1
BA0 0 1 0 1
Result enables Read/Write commands for Bank 0 enables Read/Write commands for Bank 1 enables Read/Write commands for Bank 2 enables Read/Write commands for Bank 3
Pr
25
od t uc
EDS1232CATA
Power-up sequence
Power-up sequence The SDRAM should be goes on the following sequence with power up. The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence. The CKE and DQM is driven to high between power stabilizes and the initialization sequence. This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up, the large current flows from these pins to VDD through the diodes. Initialization sequence When 200 µs or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed with a number of device.
Power up sequence 100 μs 0V Initialization sequence 200 μs
EO
VDD, VDDQ CKE, DQM CLK /CS, DQ
Data Sheet E0388E11 (Ver. 1.1)
L
Low Low Low
Pr
Power stabilize
Power-up sequence and Initialization sequence
od t uc
26
EDS1232CATA
Operation of the SDRAM
Read/Write Operations Bank active Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address and the bank select address at the read command set cycle. In a read operation, data output starts after the number of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3. When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the successive burst-length data has been output. The /CAS latency and burst length must be specified at the mode register.
CLK
EO
Command Address DQ CL = 2 CL = 3
CLK Command Address
ACT Row
tRCD
READ
ACT
BL = 1
DQ
BL = 2 BL = 4
out 0 out 1 out 2
BL = 8
Data Sheet E0388E11 (Ver. 1.1)
L
Row
Column
out 0
out 1 out 0
out 2 out 1
out 3 out 2 out 3 CL = /CAS latency Burst Length = 4
Pr
/CAS Latency
tRCD
READ
od t uc
BL : Burst Length /CAS Latency = 2
Column
out 0 out 0 out 1
out 0 out 1 out 2 out 3
out 3 out 4 out 5 out 6 out 7
Burst Length
27
EDS1232CATA
Write operation Burst write or single write mode is selected by the OPCODE of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4 and 8, like burst read operations. The write start address is specified by the column address and the bank select address at the write command set cycle.
CLK
tRCD
Command Address
ACT
WRIT
Row
Column
BL = 1 BL = 2 BL = 4 BL = 8
in 0 in 0 in 0 in 0 in 1 in 1 in 1
in 2 in 2
EO
DQ
in 3 in 3 in 4 in 5 in 6 in 7
CL = 2, 3
Burst write
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is only written to the column address and the bank select address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
Data Sheet E0388E11 (Ver. 1.1)
L
CLK Command Address DQ
tRCD WRIT
ACT
Pr
Row Column
in 0
Single write
od t uc
28
EDS1232CATA
Auto Precharge Read with auto-precharge In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is required before execution of the next command. [Clock cycle time]
/CAS latency 3 2
CLK
Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output
EO
CL=2 Command ACT DQ CL=3 Command ACT DQ
READA lRAS out0 out1 out2 out3
ACT
lAPR READA lRAS out0 out1 out2 out3 ACT
Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge "
lAPR
Write with auto-precharge In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is required between the final valid data input and input of next command.
Command
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
Data Sheet E0388E11 (Ver. 1.1)
L
CLK
ACT
".
Burst Read (BL = 4)
Pr
WRITA
ACT
lRAS DQ
Burst Write (BL = 4)
od
in0 in1 in2 in3 lDAL
t uc
29
EDS1232CATA
CLK Command
ACT ACT
WRITA
lRAS DQ in lDAL Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
EO
Data Sheet E0388E11 (Ver. 1.1)
Single Write
L Pr od t uc
30
EDS1232CATA
Burst Stop Command During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command.
CLK Command DQ (CL = 2) DQ (CL = 3)
READ BST High-Z
out
out
out
out
out
out
High-Z
Burst Stop at Read
EO
CLK Command DQ
Data Sheet E0388E11 (Ver. 1.1)
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command.
WRITE in in in in
BST
High-Z
L
Burst Stop at Write
Pr od t uc
31
EDS1232CATA
Command Intervals Read command to Read command interval 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK Command
Address
BS
ACT READ READ
Row
Column A Column B
EO
DQ
out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout
Bank0 Active
CL = 3 BL = 4 Bank 0
READ to READ Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid.
CLK
Command
Address
BS
DQ
Bank0 Active
Data Sheet E0388E11 (Ver. 1.1)
L
ACT
Row 0
ACT
Row 1
READ READ
Column A Column B
READ to READ Command Interval (different bank)
Pr
Bank3 Bank0 Bank3 Active Read Read Bank0 Bank3 Dout Dout
out A0 out B0 out B1 out B2 out B3
CL = 3 BL = 4
od t uc
32
EDS1232CATA
Write command to Write command interval 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. In the case of burst writes, the second write command has priority.
CLK Command
Address
ACT WRIT WRIT
Row
Column A Column B
BS
DQ
in A0 Bank0 Active in B0 in B1 in B2 in B3
EO
CLK Command
ACT
Column =A Column =B Write Write
Burst Write Mode BL = 4 Bank 0
WRITE to WRITE Command Interval (same ROW address in same bank)
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. In the case of burst write, the second write command has priority.
Address
BS
DQ
Bank0 Active
Data Sheet E0388E11 (Ver. 1.1)
L
ACT
Row 0
Row 1
WRIT
WRIT
WRITE to WRITE Command Interval (different bank)
Pr
Column A Column B
in A0
in B0
in B1
in B2
in B3
Bank3 Bank0 Bank3 Active Write Write
Burst Write Mode BL = 4
od t uc
33
EDS1232CATA
Read command to Write command interval 1. Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. However, DQM must be set High so that the output buffer becomes High-Z before data input.
CLK Command
CL=2
READ WRIT
DQM
CL=3
in B0 High-Z in B3
DQ (input)
in B1
in B2
DQ (output)
BL = 4 Burst write
EO
DQ
Data Sheet E0388E11 (Ver. 1.1)
READ to WRITE Command Interval (1)
CLK
READ WRIT
Command
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. However, DQM must be set High so that the output buffer becomes High-Z before data input.
L
DQM
CL=2 CL=3
2 clock
out out out out out in in in in in in in in
Pr
34
READ to WRITE Command Interval (2)
od
t uc
EDS1232CATA
Write command to Read command interval: 1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed.
CLK Command DQM
DQ (input)
WRIT
READ
in A0 out B0 Column = A Write Column = B Read out B1 out B2 out B3
Burst Write Mode CL = 2 BL = 4 Bank 0
EO
DQ (output)
CLK Command DQM DQ (input) DQ (output)
/CAS Latency Column = B Dout
WRITE to READ Command Interval (1)
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
Data Sheet E0388E11 (Ver. 1.1)
L
WRIT in A0 Column = A Write
READ
in A1 out B0 out B1 out B2 out B3 Burst Write Mode CL = 2 BL = 4 Bank 0
Pr
Column = B Read
/CAS Latency
Column = B Dout
WRITE to READ Command Interval (2)
od
35
t uc
EDS1232CATA
Read with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second command.
CLK Command BS DQ bank0 Read A bank3 Read ". out A0 out A1 out B0 out B1 CL= 3 BL = 4 READA READ
EO
CLK Command BS DQ
Data Sheet E0388E11 (Ver. 1.1)
Note: Internal auto-precharge starts at the timing indicated by "
Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts 2 clocks later from the second command.
Note: Internal auto-precharge starts at the timing indicated by "
2. Same bank: The consecutive write command (the same bank) is illegal.
L
WRITA in A0 bank0 Write A in A1
WRIT
in B0 bank3 Write
in B1
in B2
in B3 BL= 4
Write with Auto Precharge to Write Command Interval (Different bank)
Pr
36
".
od t uc
EDS1232CATA
Read with auto precharge to Write command interval 1. Different bank: When some banks are in the active state, the second write command (another bank) is executed. However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal autoprecharge of one bank starts at the next clock of the second command.
CLK Command BS CL = 2 DQM CL = 3 in B0 in B1 in B2 in B3 READA WRIT
DQ (input)
EO
CLK Command BS DQM DQ (input) DQ (output)
Data Sheet E0388E11 (Ver. 1.1)
DQ (output) bank0 ReadA bank3 Write
High-Z BL = 4 ".
Note: Internal auto-precharge starts at the timing indicated by "
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command. Write with auto precharge to Read command interval 1. Different bank: When some banks are in the active state, the second read command (another bank) is executed. However, in case of a burst write, data will continue to be written until one clock before the read command is executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
L
WRITA in A0 bank0 WriteA
Note: Internal auto-precharge starts at the timing indicated by "
Write with Auto Precharge to Read Command Interval (Different bank)
Pr
READ
od
out B0 out B1
out B2
out B3 CL = 3 BL = 4 ".
bank3 Read
t uc
37
EDS1232CATA
Read command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by lHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution.
CLK
Command
READ
PRE/PALL
DQ
out A0
out A1
out A2
out A3
CL=2
lEP = -1 cycle
EO
CLK Command DQ
CLK Command DQ CLK Command DQ
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4)
READ
PRE/PALL
out A0
out A1
out A2
out A3
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 1, 2, 4, 8)
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 1, 2, 4, 8)
Data Sheet E0388E11 (Ver. 1.1)
L
READ READ
CL=3
lEP = -2 cycle
Pr
PRE/PALL High-Z out A0 lHZP = 2 PRE/PALL out A0 lHZP =3
od
High-Z
t uc
38
EDS1232CATA
Write command to Precharge command interval (same bank) When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK Command WRIT
PRE/PALL
DQM
DQ
tDPL
EO
CLK Command DQM DQ
CLK Command DQM DQ
WRIT
PRE/PALL
in A0
in A1
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))
Data Sheet E0388E11 (Ver. 1.1)
L
WRIT in A0
tDPL
Pr
in A1 in A2 in A3
PRE/PALL
od
tDPL
t uc
39
EDS1232CATA
Bank active command interval 1. Same bank: The interval between the two bank active commands must be no less than tRC. 2. In the case of different bank active commands: The interval between the two bank active commands must be no less than tRRD.
CLK Command ACT ACT
Address
ROW
ROW
BS
tRC
Bank 0 Active
EO
Data Sheet E0388E11 (Ver. 1.1)
Bank 0 Active
Bank Active to Bank Active for Same Bank
CLK ACT ROW:0 ACT ROW:1
Command Address
Mode register set to Bank active command interval The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
L
BS
Command Address
tRRD Bank 0 Active Bank 3 Active
Mode register set to Bank active command interval
Pr
MRS OPCODE lMRD Mode Register Set
Bank Active to Bank Active for Different Bank
od
ACT
BS & ROW
Bank Active
t uc
40
EDS1232CATA
DQM Control The DQM mask the DQ data. The UDQM and LDQM mask the upper and lower bytes of the DQ data, respectively. The timing of UDQM/LDQM is different during reading and writing. Reading When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM during reading is 2 clocks. Writing Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when DQM is set to High, the corresponding data is not written, and the previous data is held. The latency of DQM during writing is 0 clock.
EO
CLK DQM DQ
CLK DQM DQ
Data Sheet E0388E11 (Ver. 1.1)
High-Z out 0 out 1 out 3
lDOD = 2 Latency
L
in 0
Reading
Pr
in 1 lDID = 0 Latency
in 3
od
Writing
t uc
41
EDS1232CATA
Refresh Auto-refresh All the banks must be precharged before executing an auto-refresh command. Since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not required. The refresh cycles are required to refresh all the ROW addresses within tREF (max.). The output buffer becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. Self-refresh After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During selfrefresh operation, all ROW addresses are refreshed by the internal refresh timer. A self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tREF (max.) period on the condition 1 and 2 below. 1. Enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. Start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode.
EO
Others
Data Sheet E0388E11 (Ver. 1.1)
Note: tREF (max.) / refresh cycles.
Power-down mode The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock suspend mode By driving CKE to Low during a bank active or read/write operation, the SDRAM enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
L
Pr
42
od t uc
EDS1232CATA
Timing Waveforms
Read Cycle
tCK tCH t CL
CLK
t RC VIH
CKE
tRCD tSI tHI tSI tHI
tRAS tSI tHI
t RP tSI tHI
/CS
tSI tHI tSI tHI tSI tHI tSI tHI
/RAS
EO
/CAS /WE BS A10 Address DQM DQ (input) DQ (output)
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
Data Sheet E0388E11 (Ver. 1.1)
L
tSI
Bank 0 Active
tHI
Pr
tAC tAC t AC tOH tOH tOH
Bank 0 Read
tAC
tHZ
tOH
tLZ
Bank 0 Precharge
/CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL
od t uc
43
EDS1232CATA
Write Cycle
tCK tCH tCL
CLK
tRC
VIH
CKE
tRCD tSI tHI tSI tHI tSI tHI tSI tHI tRAS tRP
/CS
tSI tHI tSI tHI tSI tHI tSI tHI
/RAS
tSI tHI tSI tHI tSI tHI tSI tHI
/CAS
EO
/WE BS A10 Address DQM DQ (input) DQ (output)
0
tSI tHI
tSI tHI tSI tHI tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI tSI tHI
tSI tHI tSI tHI
tSI tHI
tSI tHI
tSI tHI
Mode Register Set Cycle
1 2
L
tSI tSI Bank 0 Active
tHI
t HI
tSI
tHI tSI
tHI
tSI
tHI
tDPL
Pr
Bank 0 Write
Bank 0 Precharge
CL = 2 BL = 4 Bank 0 access = VIH or VIL
od
7 8 9 10 11 12 13 14 C: b C: b’ b High-Z b+3
Output mask Bank 3 Read
3
4
5
6
15
16
17
18
19
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
lRP
Precharge If needed Mode register Set
VIL
t uc
b’ b’+1 b’+2 b’+3 lRCD = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
valid
code
R: b
lMRD
Bank 3 Active
lRCD
Data Sheet E0388E11 (Ver. 1.1)
44
EDS1232CATA
Read Cycle/Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Bank 0 Active Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VIH
Read cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
R:a
C:a
R:b a
C:b a+1 a+2 a+3
Bank 3 Bank 0 Read Precharge
C:b' b
High-Z
Bank 3 Read
C:b" b'+1 b" b"+1 b"+2 b"+3
Bank 3 Precharge
b+1 b+2 b+3 b'
Bank 3 Read
EO
CKE /CS
VIH
/RAS /CAS
Write cycle /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
/WE
BS
Address
R:a
C:a
R:b
C:b
High-Z
C:b'
C:b"
DQM
DQ (output)
DQ (input)
a
Bank 0 Write
a+1 a+2 a+3
Bank 3 Active
b
Bank 3 Write
b+1 b+2 b+3 b'
Bank 0 Precharge Bank 3 Write
b'+1 b"
Bank 3 Write
b"+1 b"+2 b"+3
Bank 3 Precharge
Data Sheet E0388E11 (Ver. 1.1)
L
Bank 0 Active
Pr od t uc
45
EDS1232CATA
Read/Single Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output) a
Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VIH
R:a
C:a
R:b
C:a' C:a a a+1 a+2 a+3
Bank 0 Bank 0 Write Read
a
a+1 a+2 a+3
Bank 0 Precharge Bank 3 Precharge
EO
Bank 0 Active
CKE /CS
VIH
/RAS /CAS /WE BS
Address DQM
R:a
C:a
R:b
C:a a a a+1 a+3
Bank 0 Write
C:b C:c b c
DQ (input)
DQ (output)
Data Sheet E0388E11 (Ver. 1.1)
L
Bank 0 Active Bank 0 Read
Bank 3 Active
Bank 0 Bank 0 Write Write
Bank 0 Precharge
Read/Single write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Pr od
46
t uc
EDS1232CATA
Read/Burst Write Cycle
0 CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) a a
Bank 0 Read Bank 3 Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:a
C:a
R:b
C:a' a+1 a+2 a+3
Bank 0 Precharge Bank 3 Precharge
EO
DQ (output)
Bank 0 Active
a+1 a+2 a+3
Clock suspend
Bank 0 Write
CKE /CS
VIH
/RAS /CAS
/WE BS
L
R:a C:a
Bank 0 Active Bank 0 Read
Address DQM DQ (input) DQ (output)
R:b
C:a a a a+1 a+3
Bank 0 Write Bank 0 Precharge
a+1 a+2 a+3
Bank 3 Active
Pr
3 4 5 6 7 8 9 10 11 High-Z
Read/Burst write /RAS-/CAS delay = 3 /CAS latency = 3 Burst length = 4 = VIH or VIL
Auto Refresh Cycle
0 1 2
12
13
14
15
16
17
18
19
20
od
R:a
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (input) DQ (output)
A10=1
VIH
t uc
C:a a a+1
Active Bank 0 Read Bank 0
t RP
Precharge If needed Auto Refresh
t RC
Auto Refresh
t RC
Refresh cycle and Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
Data Sheet E0388E11 (Ver. 1.1)
47
EDS1232CATA
Self Refresh Cycle
CLK CKE /CS /RAS /CAS /WE BS Address DQM
A10=1
lSREX
CKE Low
EO
DQ (input) DQ (output)
High-Z
t RP
Self refresh entry command Self refresh exit ignore command or No operation
t RC
Next clock enable Self refresh entry command
t RC
Auto Next clock refresh enable
Precharge command If needed
Self refresh cycle /RAS-/CAS delay = 3 CL = 3 BL = 4 = VIH or VIL
Clock Suspend Mode
L
tSI
tHI
tSI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Read cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
Pr
C:a R:b a a+1 a+2
High-Z
Active clock Bank0 suspend end Read Bank3 Active
Read suspend start
Read suspend end
R:a
C:b b b+1 b+2 b+3
a+3
od
Bank3 Read Bank0 Precharge Earliest Bank3 Precharge
Bank0 Active clock Active suspend start
CKE /CS /RAS /CAS /WE BS Address DQM DQ (output) DQ (input)
Bank0 Active
Active clock suspend start
Write cycle /RAS-/CAS delay = 2 /CAS latency = 2 Burst length = 4 = VIH or VIL
R:a
C:a R:b
C:b
t uc
Earliest Bank3 Precharge
High-Z
a
a+1 a+2
Write suspend start
a+3 b
Write suspend end
b+1 b+2 b+3
Active clock Bank0 Bank3 supend end Write Active
Bank3 Bank0 Write Precharge
Data Sheet E0388E11 (Ver. 1.1)
48
EDS1232CATA
Power Down Mode
CLK CKE /CS /RAS /CAS /WE BS Address DQM
A10=1
CKE Low
R: a
EO
Initialization Sequence
0
DQ (input)
High-Z
DQ (output) tRP
Precharge command If needed Power down entry
Power down /RAS-/CAS delay = 3 mode exit Active Bank 0 /CAS latency = 3
Power down cycle Burst length = 4 = VIH or VIL
L
1 2 3 VIH valid VIH tRP All banks Precharge
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
CLK CKE /CS
Pr
High-Z t RC Auto Refresh tRC Auto Refresh
/RAS /CAS /WE Address DQM DQ
code
Valid
od
49
lMRD Bank active If needed
Mode register Set
t uc
Data Sheet E0388E11 (Ver. 1.1)
EDS1232CATA
Package Drawing
86-pin Plastic TSOP (II)
Unit: mm
22.22 ± 0.10 86 A
*1
44
PIN#1 ID
1
43 0.50 0.10 M S A B
B
0.15 to 0.30 0.81 max.
11.76 ± 0.20
10.16
1.0 ± 0.05
1.2 max.
0.10 S
0.10 +0.08 −0.05
S
0.09 to 0.20
EO
Data Sheet E0388E11 (Ver. 1.1)
0.80 Nom 0 to 8°
0.25
Note: 1. This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side.
L
0.60 ± 0.15
Pr
50
ECA-TS2-0030-01
od t uc
EDS1232CATA
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDS1232CA. Type of Surface Mount Device EDS1232CATA: 86-pin Plastic TSOP (II)
EO
Data Sheet E0388E11 (Ver. 1.1)
L Pr od t uc
51
EDS1232CATA
N OTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
EO
2 3
Data Sheet E0388E11 (Ver. 1.1)
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
L
Pr
52
CME0107
od t uc
EDS1232CATA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Data Sheet E0388E11 (Ver. 1.1)
L
Pr
53
M01E0107
od
t uc
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