merging Memory & Logic Solutions Inc.
Document Title
512K x8 bit Super Low Power and Low Voltage Full CMOS Static RAM
EM641FV8FS Series
Low Power, 512Kx8 SRAM
Revision History
Revision No.
0.0 0.1
History
Initial Draft 2’nd Draft Add Pb-free part number
Draft Date
May 25 , 2003 February 13 , 2004
Remark
Preliminary
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160 Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1
merging Memory & Logic Solutions Inc.
FEATURES
• • • • • • Process Technology : 0.18µ m Full CMOS Organization : 512K x 8 bit Power Supply Voltage : 2.7V ~ 3.6V Low Data Retention Voltage : 1.5V(Min) Three state output and TTL Compatible Package Type : 32-sTSOP1
EM641FV8FS Series
Low Power, 512Kx8 SRAM
GENERAL DESCRIPTION
The EM641FV8FS families are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation Product Family EM641FV8FS Operating Temperature Industrial (-40 ~ 85oC) Vcc Range Speed Standby (ISB1 , Typ) 1 µA2) Operating (I CC1.Max) 3 mA PKG Type
2.7V~3.6V
551) / 70ns
32- sTSOP1
1. The parameter is measured with 30pF test load. 2. Typical values are measured at Vcc=3.3V, T A =25o C and not 100% tested.
PIN DESCRIPTION
A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 OE A10 CS IO8 IO7 IO6 IO5 IO4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
23 22 21 20 19 18 17
R ow S elec t
32 - sTSOP Type1 - Forward
26 25 24
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
VC C VSS
Memory Array 2048 x 2048
I/O1 ~ I/O4 I/O5 ~ I/O8
Data Cont Data Cont
I/O Circuit Column Select
N ame CS OE A 0 ~A18 I/O1 ~I/O 8
Function Chip select inputs O utput Enable input A ddress Inputs D ata Inputs/outputs
Name WE Vcc Vss NC
Function Write Enable input Power Supply Ground
W E A A A13 A1 A A A A 11 12 4 15 16 17 18
No Connection
O E CS
Control Logic
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merging Memory & Logic Solutions Inc.
ABSOLUTE MAXIMUM RATINGS * Parameter
Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature
EM641FV8FS Series
Low Power, 512Kx8 SRAM
Symbol
VIN , VOUT VCC PD TA
Ratings
-0.2 to Vcc+0.3(Max.4.0V) -0.2 to 4.0V 1.0 -40 to 85
Unit
V V W
oC
* Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS H L L L OE X H L X WE X H H L I/O High-Z High-Z Data Out Data In Mode Deselected Output Disabled Read Write Power Stand by Active Active Active
Note: X means don’t care. (Must be low or high state)
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merging Memory & Logic Solutions Inc.
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter Supply voltage Ground Input high voltage Input low voltage
1. 2. 3. 4.
EM641FV8FS Series
Low Power, 512Kx8 SRAM
Symbol VCC VSS VIH VIL
Min 2.7 0 2.2 -0.2 3)
Typ 3.3 0 -
Max 3.6 0 VCC + 0 .22) 0.6
Unit V V V V
TA= -40 to 85oC, otherwise specified Overshoot: V CC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f =1MHz, TA=25oC)
Item Input capacitance Input/Ouput capacitance
1. Capacitance is sampled, not 100% tested
Symbol C IN CIO
Test Condition VIN=0V VIO =0V
Min -
Max 8 10
Unit pF pF
DC AND OPERATING CHARACTERISTICS
Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC I CC1 Average operating current I CC2 Output low voltage Output high voltage Standby Current (TTL) VOL VOH ISB
C ycle time = Min, I IO =0mA, 100% duty, CS = VIL , V IN=V IL o r V IH I OL = 2 .1mA I O H = - 1.0mA C S =VIH , Other inputs=VIH o r VIL C S >V CC -0.2V, V IN=V SS t o V CC C S =VIH o r OE = VIH or WE =V IL, VIO =VSS t o V CC I IO=0mA, CS = VIL , VIN = VIH o r V IL C ycle time=1 µs, 100% duty, I IO=0mA, CS V cc-0.2V
CS GND
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merging Memory & Logic Solutions Inc.
PACKAGE DIMENSIONS
EM641FV8FS Series
Low Power, 512Kx8 SRAM
Unit : millimeters/Inches
( 32-sTSOP1-0813.4F )
+0.10 - 0.05 0.008 +0.004 - 0.002
0.20
13.40 +/-0.20 0.528 +/- 0.008
0.10 0.004 MAX
#32
#1
( 0.25 ) 0.010 8.40 0.331MAX 8.00 0.315
0.50 0.0197
#16
#17
1.00 +/-0.10 0.039 +/- 0.004 0.25 TYP 0.010 11.80 0.465
+/-0.10 +/- 0.004 +0.10 - 0.05 0.006 +0.004 - 0.002
0.05 0.002 MIN
0.15
1.20 MAX 0.047
0~8 0.45~0.75 0.018~0.030 0.50 ( 0.020 )
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merging Memory & Logic Solutions Inc.
MEMORY FUNCTION GUIDE
EM641FV8FS Series
Low Power, 512Kx8 SRAM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory 2. Device Type 3. Density 4. Option 5. Technology 6. Operating Voltage
1. Memory Component 2. Device Type 6 ------------------------ Low Power SRAM 7 ------------------------ STRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 16 ----------------------- 16M 32 ----------------------- 32M 64 ----------------------- 64M 4. Mode Option 0 -------- Dual CS 1 -------- Single CS 2 -------- Multiplexed Address 3 -------- Single CS with LB ,UB (tBA=tOE) 4 -------- Single CS with LB ,UB (tBA=tCO) 5 -------- Dual CS with LB ,UB (tBA=tOE) 6 -------- Dual CS with LB ,UB (tBA=tCO) 5. Technology Blank ------------------ CMOS F ------------------------ Full CMOS 6. Operating Voltage Blank ------------------- 5V V ------------------------- 2.7V~3.6V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 10
11. Power 10. Speed
9. Packages 8. Version 7. Orgainzation
7. Orginzation 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 8. Version Blank ----------------- Mother Die A ----------------------- First revision B ----------------------- Second revision C ----------------------- Third revision D ----------------------- Fourth revision E ----------------------- Fifth revision F ----------------------- Sixth revision 9. Package Blank ---------------------- FPBGA S ---------------------------- 32 sTSOP1 T ---------------------------- 32 TSOP1 U ---------------------------- 44 TSOP2 W ---------------------------- Wafer
10. Speed 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 10 --------------------- 100ns 12 --------------------- 120ns 11. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-free) L ---------------------- Low Power S ---------------------- Standard Power
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