V61558S

EM MICROELECTRONIC- MARIN SA V6155 Extremely Accurate Power Surveillance, Software Monitoring and Sleep Mode Detection Features n Can-bus sleep mode detector n Standby mode, maximum current 50 mA n Reset output guaranteed for V DD voltage down to 1.2 V n Comparator for voltage monitoring,voltage reference 1.275 V n ± 1.2% voltage reference accuracy at +25 ° C n ± 2.5% voltage reference accuracy from −40 to +85 ° C (3 to 5.5 V) n Programmable reset voltage monitoring n Programmable power-on reset (POR) delay n Watchdog with programmable time windows guarantees a minimum time and a maximum time between software clearing of the watchdog n Time base accuracy ± 10% n System enable output offers added security n TTL / CMOS compatible n -40 to +85 °C temperature range n On request extended temperature range, −40 to +125 ° C n DIP8 and SO8 packages Applications n n n n n n Automotive systems Cellular telephones Security systems Battery powered products High efficiency linear power supplies Industrial electronics Typical Operating Configuration VDD V6155 R VIN TCL VSS RES EN 100 nF Description The V6155 offers a high level of integration by voltage monitoring and software monitoring in an 8 lead package. A comparator monitors the voltage applied at the VIN input comparing it with an internal 1.275 V reference. The power-on reset function is initialized after VIN reaches 1.275 V and takes the reset output inactive after T depending of external resistance. The reset POR output goes active low when the VIN voltage is less than 1.275 V. The RES and EN outputs are guaranteed to be in a correct state for a supply voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. The system enable output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system. If the microcontroller does not work that means no signal on the TCL input the V6155 goes in a standby mode (CAN-bus sleep detector). GND Fig. 1 Pin Assignment DIP8 / SO8 EN RES TCL VSS V6155 VIN R VDD NC Fig. 2 1 V6155 Absolute Maximum Ratings Parameter Maximum voltage at V DD Minimum voltage at V DD Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions Symbol Conditions VDDmax VDDmin VMAX VMIN TSTO VSmax TSmax VSS + 8 V VSS − 0.3 V VDD + 0.3 V VSS − 0.3 V -65 to+150 °C 1000 V 250 °C x 10 s within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Operating temperature Supply voltage 2) RES & EN guaranteed3) Comparator input voltage RC-oscillator programming 1) Symbol Min. Typ. Max. Units 1) +125 s °C -40 T VDD VDD VIN R A 1.2 1.2 0 10 7.0 V V V VDD 1000 Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. kΩ Table 2 The maximum operating temperature is confirmed by sampling at initial device qualification. In production, all devices are tested at +85 °C. On request devices tested at +125 °C can be supplied. A 100 nF decoupling capacitor is required on the supply voltage VDD for stability. RES must be pulled up externally to VDD even if it is unused. (Note: RES and EN are used as inputs by EM test.) Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept 2) 3) Electrical Characteristics 3 ≤ V DD ≤ 5.5 V, C = 100 nF, TA = -40 to +85 °C, unless otherwise specified Parameter Supply current in standby mode (switched to R INT) Supply current RES and EN Output Low Voltage Symbol ISS ISS Test Conditions REXT = don’t care, TCL = V DD VIN = V DD REXT = 100 kΩ , I/Ps at V DD Min. Typ. 34 55 Max. 50 100 Units µA µA EN Output High Voltage TCL and VIN TCL Input Low Level TCL Input High Level Leakage current TCL input VIN input resistance Comparator reference 1) Comparator hysteresis1) 1) VOL VOL VOL VOL VOH VOH VOH VIL VIH ILI RVIN VREF VREF VREF VHY VDD = 4.5 V, IOL = 20 mA VDD = 4.5 V, IOL = 8 mA VDD = 2.0 V, IOL = 4 mA VDD = 1.2 V, IOL = 0.5 mA VDD = 4.5 V, IOH = −1mA VDD = 2.0 V, IOH = −100 µA VDD = 1.2 V, IOH = −30 µA 3.5 1.8 1.0 VSS 2.0 VSS ≤ VTCL ≤ VDD TA = +25 ° C TA = −40 to +125 ° C 1.25 1.24 1.22 0.4 0.2 0.2 0.05 4.1 1.9 1.1 0.4 0.4 0.2 V V V V V V V 0.05 100 1.275 2 0.8 VDD 1 1.30 1.31 1.31 V V µA MΩ V V V mV Table3 The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference voltage plus the comparator hysteresis (see Fig. 6). 2 V6155 ISS Standby versus Temperature at VDD = 5.5 V 40 38 ISS [µA] 36 34 32 30 28 −40 +25 TA [° C] +85 +125 Fig. 3 Timing Characteristics V DD = 5.0 V ± 3%, C = 100 nF, TA = −40 to +85 °C, unless otherwise specified Parameter Propagation delays: TCL to Output Pins VIN sensitivity Logic Transition Times on all Output Pins Power-on Reset delay Watchdog Time Open Window Percentage Closed Window Time Open Window Time Watchdog Reset Pulse TCL Input Pulse Width Reset Pulse when switched to R internal Watchdog Reset Pulse with R internal (R I) Symbol TDIDO TSEN TTR TPOR TWD OWP TCW TCW TOW TOW TWDR TWDR TTCL TRI TRIR Test Conditions Min . Typ. 250 5 30 100 100 ±0.2 TWD 0.8 TWD 80 0.4 TWD 40 TWD / 40 2.5 0.9 TRI/320 Max. 500 20 100 110 110 88 44 Units ns µs ns ms ms ms ms ms ns s s Table 4 Load 10 kΩ , 50 pF REXT = 110 kΩ , ±1% REXT = 110 kΩ , ±1% REXT = 110 kΩ , ±1% REXT = 110 kΩ , ±1% REXT = 110 kΩ , ±1% 1 90 90 72 36 150 0.3 2.3 TRI versus Temperature at VDD = 5 V 2.5 2.0 1.5 1.0 0.5 0 −40 +25 +85 +125 TRI [s] TA [° C] Fig. 4 3 V6155 Timing Waveforms Watchdog Timeout Period TWD = T POR − OWP − 20% + OWP + 20% Condition: REXT = 100 kΩ Watchdog timer reset TCW – closed window 80 TOW – open window t [ms] 100 120 Fig. 5 Voltage Monitoring VIN VREF Conditions: VDD ≥ 3 V No timeout VHY TSEN TSEN TPOR TSEN TPOR TSEN RES Fig. 6 Timer Reaction Conditions: V IN > VREF after power-up sequence TCW TCL RES EN TOW TCW TCW+TOW TCW+TOW TTCL TWDR 1 2 3 TCW+TOW TCW+TOW TRI TRIR TCW+TOW TWDR 3 correct TCL services EN goes active low Timeout After 3 reset pulse periods After one edge (falling or rising) switch to R internal on TCL input switch to R input Fig. 7 - Watchdog timer reset 4 V6155 Combined Voltage and Timer Reaction VIN VREF Condition: VOUTPUT ≥ 3 V TPOR=TWD TCL RES EN 1 2 3 TOW TCW TRI TRIR TCW+TOW TCL too early - Watchdog timer reset 3 correct TCL service EN goes active low After 3 reset pulse periods switch to R internal Fig. 8 Block Diagram Enable Logic EN Voltage Reference VIN VREF − + Comparator Reset Control RES Open drain output RES R R1 ≅ 1 MΩ Switch Current Controlled Oscillator Controller Timer TCL  Fig. 9 5 V6155 Pin Description Pin Name 1 EN 2 RES 3 4 5 6 7 8 TCL VSS NC VDD R VIN Function Push-pull active low enable output Open drain active low reset output. RES must be pulled up to V DD even if unused Watchdog timer clear input signal GND terminal No connection Voltage supply REXT input for RC oscillator tuning Voltage comparator input Table 5 Watchdog Timeout Period Description The watchdog timeout period is divided into two parts, a “closed” window and an “open” window (see Fig. 5) and is defined by two parameters, TWD and the Open Window Percentage (OWP). The closed window starts just after the watchdog timer resets and is defined by TCW = TWD − OWP(TWD ). The open window starts after the closed time window finishes and lasts till TWD + OWP(TWD). The open window time is defined by TOW = 2 x OWP(TWD). For example if TWD = 100 ms (actual value) and OWP = ± 20% this means the closed window lasts during first the 80 ms (TCW = 80 ms = 100 ms − 0.2 (100 ms)) and the open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms). The watchdog can be serviced between 80 ms and 120 ms after the timer reset. However as the time base is ± 10% accurate, software must use the following calculation for servicing signal TCL during the open window: Related to curves (Fig. 11 to Fig. 21), especially Fig. 20 and Fig. 21, the relation between T a nd REXT could WD easely be defined. Let us take an example describing the variations due to production and temperature: 1. Choice, TWD = 26 ms. 2. Related to Fig. 21, the coefficient (T WD to R EXT) is 1.025 where R EXT is in kW and TWD in ms. 3. R EXT (typ.) = 26 x 1.025 = 26.7 kW. 4. 26 ms at +25 ° C a) Functional Description VIN Monitoring The power-on reset and the power-down reset are generated as a response to the external voltage level on the VIN input. The external voltage level is typically obtained from a voltage divider as shown in Fig. 10. The user uses an external voltage divider to set the desired threshold level for power-on reset and power-down reset in his system. The internal comparator reference voltage is typically 1.275 V. At power-up the reset output (RES) is held low (see Fig. 6). When VIN becomes greater than VREF, the RES output is held low for an additional power-on reset (POR) delay which is equal to the watchdog time TWD (typically 100 ms with an external resistor of 110 kW connected at R pin). The POR delay prevents repeated toggling of RES even if VIN and the INPUT voltage drops out and recovers. The POR delay allows the microprocessor’s crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the powerdown reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on V IN is typically 5 ms. (26 - 10% = 23.4 ms) (26 + 10% = 28.6 ms) a) (28.6 + 5% = 30.0 ms)b) b) (23.4 - 5% = 22.2 ms) min.: (30.0 - 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms) Timer Programming The on-chip oscillator needs an external resistor REXT connected between the R pin and VSS (see Fig. 10). It allows the user to adjust the power-on reset (POR) delay, watchdog time TWD and with this also the closed and open time windows as well as the watchdog reset pulse width (TWD/40). With R EXT = 110 kW, the typical values are: - Power-on reset delay: TPOR is 100 ms - Watchdog time: TWD is 100 ms - Closed window: TCW is 80 ms - Open window: TOW is 40 ms - Watchdog reset: TWDR is 2.5 ms Note the current consumption increases as the frequency increases. The ratio between TWD = 25.4 ms is 0.975. Then the relation over the production and the full temperature range is, TCL period = 0.975 x TWD 0.975 x R EXT or TCL period = , as typical value. 1.025 Typical TCL period of (24.0 + 26.7) / 2 = 25.4 ms = 26 ms and the (TCL period) a) While PRODUCTION value unknown for the customer when R EXT ¹ 110 kW. b) While operating TEMPERATURE range -40 °C ≤ TA ≤ +85 °C. 5. If you fixed a TCL period = 26 ms 26 x 1.025 Þ REXT = = 27.3 kW 0.975 If during your production the TWD time can be measured at TA = +25 °C and the mC can adjust the TCL period, then the TCL period range will be much larger for the full operating temperature. 6 V6155 Timer Clearing and RES Action The watchdog circuit monitors the activity of the processor. If the user’s software does not send a pulse to the TCL input within the programmed open window timeout period, a short watchdog RES pulse is generated which is equal to TWD/40 = 2.5 ms typically (see Fig. 7). With the open window constraint, new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution) it will cause the system to be reset. If the software is stuck in a loop which includes the routine to clear the watchdog, then a conventional watchdog will not reset even though the software is malfunctioning; the V6155 will generate a system reset because the watchdog is cleared too quickly. If no TCL pulse is applied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + TWDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section “Enable - EN Output”). The RES output must be pulled up to VDD even if the output is not used by the system (see Fig. 10). after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 5 ms, overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed. The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (i.e. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The V6155 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (i.e. the system has correctly restarted after a reset condition). Enable - EN Output Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 8. On power-up, when the voltage at VIN reaches VREF, the power-on reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on reset delay is completed. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR CAN-Bus Sleep Mode Detector If the microcontroller is in standby mode that means it does not have any pulses on the TCL input. After 3 reset pulse periods (TCW + TOW +T WDR ) on the RES output, the V6155 switches on an internal resistor of 1 MΩ , and it will have a reset pulse of typically 3 ms every 1 second on the RES output. When a TCL edge (rising or falling) appears on the TCL input or the power supply goes down and up, the V6155 switches to the R input. Typical Application VDD V6155 Supply voltage 100 nF R1 100 kΩ Address Decoder 100 kΩ R VIN TCL µP RES R2 Motor EN Controls VSS RES EN GND Fig. 10 7 V6155 VREF versus VDD at TA = − 40 ° C, + 25 ° C, + 85 ° C 2.0 1.8 1.6 1.4 1.2 VREF [V] VREF versus VDD at TA = -40 °C, +25 °C, +85 °C 1.290 TA = -40 ° C 1.285 TA = -40 ° C 1.280 TA = +25 ° C TA = +25 ° C VREF [V] 1.275 TA = +85 ° C 1.0 0.8 0.6 0.4 0.2 0.0 1.5 1.270 TA = +85 ° C 1.265 1.260 2.5 3.5 4.5 5.5 6.5 7.5 Fig. 11 1 2 3 4 5 6 7 8 Fig. 12 VDD [V] VDD [V] VREF versus Temperature at VDD = 3 V, 5 V and 8 V 1.50 1.45 VREF versus Temperature at VDD = 3 V, 5 V and 8 V 1.280 1.275 VDD = 5 V VDD = 3 V 1.40 1.35 1.30 VREF [V] 1.25 1.20 1.15 1.10 1.05 1.00 -50 -25 0 +25 +50 +75 +100 +125 TA [° C] Fig. 13 1.250 VDD = 8 V 1.255 VDD = 5 V and 3 V VREF [V] 1.270 1.265 1.260 VDD = 8 V 1.245 -50 -25 0 +25 +50 +75 +100 +125 TA [° C] Fig. 14 8 V6155 TWD versus Supply Voltage at TA ≤ + 85 ° C 100000 TWD versus V DD at TA = +125 ° C 10000 0 R = 10 MΩ 10000 R = 10 MΩ 1000 0 1000 TWD [ms] R = 1 MΩ TWD [ms] 1000 R = 1 MΩ 100 R = 100 kΩ 100 R = 100 kΩ R = 10 kΩ 10 3 4 5 VDD[V] 6 7 8 Fig. 15 10 R = 10 kΩ 4 5 6 7 8 Fig. 16 VOUTPUT[V] 3 TWD versus Temperature at VDD = 5 V 100000 TWD versus R at V DD = 5 V 10000 TA = +125 ° C R = 10 MΩ 10000 1000 1000 TWD [ms] TWD [ms] R = 1 MΩ 100 R = 100 kΩ 100 10 R = 10 kΩ 10 -40 -15 +10 +35 +60 +85 +110 Fig. 17 TA[° C] 1 1 TA ≤ +85 ° C 10 100 R [kΩ] 1000 10’000 Fig. 18 9 V6155 TWD versus R at V DD = 5 V 10’000 TA = +125 ° C TA ≤ +85 ° C 1000 100 TWD [ms] 10 1 1 10 100 R [kΩ] Fig. 19 1000 10’000 10 V6155 TWD Coefficient versus REXT at TA = + 25 ° C 1.10 1.08 1.06 1.04 1.02 TWD Coefficient 1.00 0.98 0.96 0.94 0.92 0.90 0.88 0.86 10 100 REXT [ kΩ ] 1000 Fig. 20 REXT Coefficient versus TWD at TA = + 25 ° C 1.16 1.14 1.12 1.10 1.08 REXT Coefficient 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 10 100 TWD [ms] 1000 Fig. 21 11 V6155 Ordering Information The V6155 is available in the following packages: Type Package V6155 8P DIP8 V6155 8S SO8 When ordering please specify complete part number. EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. © 2000 EM Microelectronic-Marin SA, 10/00, Rev. C/311 12 EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. (+41) 32 - 755 51 11, Fax (+41) 32 - 755 54 03