0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
10CL016YF484I7G

10CL016YF484I7G

  • 厂商:

    ENPIRION(英特尔)

  • 封装:

    BGA484

  • 描述:

    Cyclone® 10 LP Field Programmable Gate Array (FPGA) IC 340 516096 15408 484-BGA

  • 数据手册
  • 价格&库存
10CL016YF484I7G 数据手册
Intel® Cyclone® 10 LP Device Datasheet ID: 683251 Online Version Send Feedback C10LP51002 Version: 2022.10.31 Contents Contents Intel® Cyclone® 10 LP Device Datasheet.................................................................................................................................... 3 Operating Conditions........................................................................................................................................................... 3 Absolute Maximum Ratings......................................................................................................................................... 4 Maximum Allowed Overshoot or Undershoot Voltage....................................................................................................... 4 Recommended Operating Conditions.............................................................................................................................6 ESD Performance.......................................................................................................................................................8 DC Characteristics......................................................................................................................................................8 I/O Standard Specifications....................................................................................................................................... 14 Power Consumption........................................................................................................................................................... 20 Switching Characteristics....................................................................................................................................................21 Core Performance Specifications.................................................................................................................................21 Periphery Performance..............................................................................................................................................25 Configuration Specifications................................................................................................................................................ 34 JTAG Timing Parameters........................................................................................................................................... 35 Active Configuration Mode Specifications..................................................................................................................... 35 AS Configuration Timing............................................................................................................................................36 Passive Configuration Mode Specifications................................................................................................................... 36 PS Configuration Timing............................................................................................................................................37 FPP Configuration Timing.......................................................................................................................................... 38 I/O Timing....................................................................................................................................................................... 39 Glossary.......................................................................................................................................................................... 40 Document Revision History for the Intel Cyclone 10 LP Device Datasheet.................................................................................. 45 Intel® Cyclone® 10 LP Device Datasheet 2 Send Feedback 683251 | 2022.10.31 Send Feedback Intel® Cyclone® 10 LP Device Datasheet This document describes the electrical and switching characteristics for Intel® Cyclone® 10 LP devices as well as I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. Operating Conditions When Intel Cyclone 10 LP devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Intel Cyclone 10 LP devices, you must consider the operating requirements described in this document. Intel Cyclone 10 LP devices are offered in commercial, industrial, extended industrial and, automotive grades as follows: • –6 (fastest) and –8 speed grades for commercial devices • –7 and –8 speed grades for industrial devices • –7 speed grade for automotive devices Intel Cyclone 10 LP devices are offered in the following core voltages: • Lower core voltage option (1.0 V)—"Z": For –I8 speed grade • Standard core voltage option (1.2 V)—"Y": For –C6, –C8, –I7, and –A7 speed grades A prefix associated with the operating temperature range is attached to the speed grades: • Commercial with a "C" prefix: –C6, –C8 • Industrial with an "I" prefix: –I7, –I8 • Automotive with an "A" prefix: –A7 Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Related Information Intel Cyclone 10 LP Available Options, Intel Cyclone 10 LP Device Overview Provides more information about the supported speed grades for Intel Cyclone 10 LP devices. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Intel Cyclone 10 LP devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied at these conditions. Caution: Conditions beyond those listed in the following table cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time have adverse effects on the device. Table 1. Absolute Maximum Ratings for Intel Cyclone 10 LP Devices Supply voltage specifications apply to voltage readings taken at the device pins with respect to ground, not at the power supply. Symbol VCCINT Parameter Min Max Unit Core voltage –0.5 1.8 V VCCA Phase-locked loop (PLL) analog power supply –0.5 3.75 V VCCD_PLL PLL digital power supply –0.5 1.8 V VCCIO I/O banks power supply –0.5 3.75 V VI DC input voltage –0.5 4.2 V IOUT DC output current, per pin –25 40 mA TSTG Storage temperature –65 150 °C TJ Operating junction temperature –40 125 °C Maximum Allowed Overshoot or Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in the following table and undershoot to –2.0 V for a magnitude of currents less than 100 mA and for periods shorter than 20 ns. The following table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the lifetime of the device. The maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. Intel® Cyclone® 10 LP Device Datasheet 4 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Note: A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 65% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 65/10ths of a year. Table 2. Maximum Allowed Overshoot During Transitions over a 10-Year Time Frame for Intel Cyclone 10 LP Devices Symbol Parameter Vi AC Input Voltage Condition (V) Overshoot Duration as % of High Time Unit VI = 4.20 100 % VI = 4.25 98 % VI = 4.30 65 % VI = 4.35 43 % VI = 4.40 29 % VI = 4.45 20 % VI = 4.50 13 % VI = 4.55 9 % VI = 4.60 6 % In the following figure, the overshoot voltage is shown in red and is present on the input pin of the Intel Cyclone 10 LP device at over 4.3 V but below 4.4 V. For example, for an overshoot of 4.3 V, the percentage of high time for the overshoot can be as high as 65% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. For lower I/O toggle rates and situations in which the device is in an idle state, lifetimes are increased. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 5 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Figure 1. Intel Cyclone 10 LP Devices Overshoot Duration 4.4 V 4.3 V 3.3 V DT T Recommended Operating Conditions This section describes the functional operation limits for AC and DC parameters for Intel Cyclone 10 LP devices. Table 3. Recommended Operating Conditions for Intel Cyclone 10 LP Devices This table lists the steady-state voltage and current values expected from Intel Cyclone 10 LP devices. All supplies must be strictly monotonic without plateaus. VCCIO for all I/O banks must be powered up during device operation. All VCCA pins must be powered to 2.5 V (even when PLLs are not used) and must be powered up and powered down at the same time. Parameter Symbol VCCINT VCCIO (1) (1)(2) Supply voltage for internal logic Supply voltage for output buffers Condition Min Typ Max Unit 1.2-V operation 1.15 1.2 1.25 V 1.0-V operation 0.97 1.0 1.03 V 3.3-V operation 3.135 3.3 3.465 V continued... (1) VCC must rise monotonically. (2) VCCIO powers all input buffers. Intel® Cyclone® 10 LP Device Datasheet 6 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol VCCA (1) VCCD_PLL Parameter Supply (analog) voltage for PLL regulator (1) Supply (digital) voltage for PLL Condition Min Typ Max Unit 3.0-V operation 2.85 3 3.15 V 2.5-V operation 2.375 2.5 2.625 V 1.8-V operation 1.71 1.8 1.89 V 1.5-V operation 1.425 1.5 1.575 V 1.2-V operation 1.14 1.2 1.26 V — 2.375 2.5 2.625 V 1.2-V operation 1.15 1.2 1.25 V 1.0-V operation 0.97 1.0 1.03 V VI Input voltage — –0.5 — 3.6 V VO Output voltage — 0 — VCCIO V TJ Operating junction temperature For commercial use 0 — 85 °C For industrial use –40 — 100 °C –40 — 125 °C –40 — 125 °C 50 µs — 50 ms — 50 µs — 3 ms — — — 10 mA For extended temperature (3) For automotive use tRAMP Power supply ramp time Standard power-on reset (POR) Fast POR IDiode Magnitude of DC current across PCI*-clamp diode when enable (4) (5) — Related Information Extended Temperature Device Support (3) Refer to the Extended Temperature Device Support page for more details about the support. (4) The POR time for Standard POR ranges between 50 and 200 ms. Each individual power supply must reach the recommended operating range within 50 ms. (5) The POR time for fast POR ranges between 3 and 9 ms. Each individual power supply must reach the recommended operating range within 3 ms. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 7 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 ESD Performance The electrostatic discharge (ESD) voltages use the human body model (HBM) and charged device model (CDM) for Intel Cyclone 10 LP devices general purpose I/Os (GPIOs) and high-speed serial interface (HSSI) I/Os. Table 4. ESD for Intel Cyclone 10 LP Devices GPIOs and HSSI I/Os Symbol Parameter VESDHBM ESD voltage using the HBM (GPIOs) VESDCDM ESD using the CDM (GPIOs) Passing Voltage Unit ± 2000 V ± 500 V DC Characteristics Supply Current The device supply current requirement is the minimum current drawn from the power supply pins that can be used as a reference for power size planning. Use the Excel-based early power estimator (EPE) to get the supply current estimates for your design because these currents vary greatly with the resources used. Table 5. I/O Pin Leakage Current for Intel Cyclone 10 LP Devices This value is specified for normal device operation. The value varies during device power-up. This applies for all VCCIO settings (3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V). The 10 μA I/O leakage current limit is applicable when the internal clamping diode is off. A higher current can be observed when the diode is on. Symbol Parameter Condition Min Max Unit II Input pin leakage current VI = 0 V to VCCIOMAX –10 10 μA IOZ Tristated I/O pin leakage current VO = 0 V to VCCIOMAX –10 10 μA Bus Hold The bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Intel® Cyclone® 10 LP Device Datasheet 8 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Table 6. Bus Hold Parameter for Intel Cyclone 10 LP Devices Bus hold trip points are based on the calculated input voltages from the JEDEC standard. Parameter Condition VCCIO (V) 1.2 1.5 1.8 Unit 2.5 3.0 3.3 Min Max Min Max Min Max Min Max Min Max Min Max Bus hold low, sustaining current VIN > VIL (maximum) 8 — 12 — 30 — 50 — 70 — 70 — μA Bus hold high, sustaining current VIN < VIL (minimum) –8 — –12 — –30 — –50 — –70 — –70 — μA Bus hold low, overdrive current 0 V < VIN < VCCIO — 125 — 175 — 200 — 300 — 500 — 500 μA Bus hold high, overdrive current 0 V < VIN < VCCIO — –125 — –175 — –200 — –300 — –500 — –500 μA Bus hold trip point — 0.3 0.9 0.375 1.125 0.68 1.07 0.7 1.7 0.8 2 0.8 2 V OCT Specifications Table 7. Series OCT Without Calibration across Process, Temperature, and Voltage (PVT) Specifications for Intel Cyclone 10 LP Devices Description Series OCT without calibration Send Feedback VCCIO (V) Resistance Tolerance Unit Commercial Maximum Industrial, Extended industrial, and Automotive Maximum 3.0 ±30 ±40 % 2.5 ±30 ±40 % 1.8 ±40 ±50 % 1.5 ±50 ±50 % 1.2 ±50 ±50 % Intel® Cyclone® 10 LP Device Datasheet 9 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Table 8. Series OCT with Calibration at Device Power-Up Specifications for Intel Cyclone 10 LP Devices OCT calibration is automatically performed at device power-up for OCT-enabled I/Os. Description VCCIO (V) Series OCT with calibration at device power-up Table 9. Calibration Accuracy Unit Commercial Maximum Industrial, Extended industrial, and Automotive Maximum 3.0 ±10 ±10 % 2.5 ±10 ±10 % 1.8 ±10 ±10 % 1.5 ±10 ±10 % 1.2 ±10 ±10 % OCT Variation with Voltage and Temperature after Calibration at Device Power-Up for Intel Cyclone 10 LP Devices Use this table to determine the final OCT resistance considering the variations after calibration at device power-up. Nominal Voltage dR/dT (%/°C) dR/dV (%/mV) 3.0 0.262 –0.026 2.5 0.234 –0.039 1.8 0.219 –0.086 1.5 0.199 –0.136 1.2 0.161 –0.288 Final OCT Resistance Equation ΔRV = (V2 – V1) × 1000 × dR/dV (6) ΔRV is a variation of resistance with voltage. (7) V2 is final voltage. (8) V1 is the initial voltage. Intel® Cyclone® 10 LP Device Datasheet 10 (6) (7) (8) (9) Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 ΔRT = (T2 – T1) × dR/dT (10) (11) (12) (13) For ΔRx < 0; MFx = 1/ (|ΔRx|/100 + 1) For ΔRx > 0; MFx = ΔRx/100 + 1 MF = MFV × MFT (14) (15) (14) (15) (15) Rfinal = Rinitial × MF (15) (16) (17) Impedance Change Example Calculate the change of 50-Ω I/O impedance from 25°C at 3.0 V to 85°C at 3.15 V as follows: ΔRV = (3.15 – 3) × 1000 × –0.026 = –3.83 ΔRT = (85 – 25) × 0.262 = 15.72 Because ΔRV is negative, MFV = 1 / (3.83/100 + 1) = 0.963 Because ΔRT is positive, (9) dR/dV is the change percentage of resistance with voltage after calibration at device power-up. (10) ΔRT is a variation of resistance with temperature. (11) T2 is the final temperature. (12) T1 is the initial temperature. (13) dR/dT is the change percentage of resistance with temperature after calibration at device power-up. (14) Subscript (15) MF is multiplication factor. (16) Rfinal is final resistance. (17) Rinitial is initial resistance. x refers to both Send Feedback V and T. Intel® Cyclone® 10 LP Device Datasheet 11 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 MFT = 15.72/100 + 1 = 1.157 MF = 0.963 × 1.157 = 1.114 Rfinal = 50 × 1.114 = 55.71 Ω Pin Capacitance Table 10. Pin Capacitance for Intel Cyclone 10 LP Devices Symbol Parameter Typical – Quad Flat Pack (QFP) Typical – Ball-Grid Array (BGA) (18) Unit CIOTB Input capacitance on top and bottom I/O pins 7 6 pF CIOLR Input capacitance on right I/O pins 7 5 pF CLVDSLR Input capacitance on right I/O pins with dedicated LVDS output 8 7 pF CVREFLR (19) Input capacitance on right dual-purpose VREF pin when used as VREF or user I/O pin 21 21 pF CVREFTB (19) Input capacitance on top and bottom dual-purpose VREF pin when used as VREF or user I/O pin 23 pF CCLKTB Input capacitance on top and bottom dedicated clock input pins 7 6 pF CCLKLR Input capacitance on right dedicated clock input pins 6 5 pF 23 (20) (18) The pin capacitance applies to FBGA, UBGA, and MBGA packages. (19) When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and tCO because of higher pin capacitance. (20) CVREFTB for the 10CL025 device is 30 pF. Intel® Cyclone® 10 LP Device Datasheet 12 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Internal Weak Pull-Up and Weak Pull-Down Resistor Table 11. Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Cyclone 10 Devices All I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK pin. Symbol R_PU R_PD Parameter Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you enable the programmable pull-up resistor option Value of the I/O pin pull-down resistor before and during configuration Condition Min Typ Max Unit VCCIO = 3.3 V ± 5% (21) (22) 7 25 41 kΩ VCCIO = 3.0 V ± 5% (21) (22) 7 28 47 kΩ VCCIO = 2.5 V ± 5% (21) (22) 8 35 61 kΩ VCCIO = 1.8 V ± 5% (21) (22) 10 57 108 kΩ VCCIO = 1.5 V ± 5% (21) (22) 13 82 163 kΩ VCCIO = 1.2 V ± 5% (21) (22) 19 143 351 kΩ VCCIO = 3.3 V ± 5% (23) 6 19 30 kΩ VCCIO = 3.0 V ± 5% (23) 6 22 36 kΩ VCCIO = 2.5 V ± 5% (23) 6 25 43 kΩ VCCIO = 1.8 V ± 5% (23) 7 35 71 kΩ VCCIO = 1.5 V ± 5% (23) 8 50 112 kΩ (21) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. (22) R_PU = (VCCIO – VI)/IR_PU Minimum condition: –40°C; VCCIO = VCC + 5% , VI = VCC + 5% – 50 mV; Typical condition: 25°C; VCCIO = VCC, VI = 0 V; Maximum condition: 100°C; VCCIO = VCC – 5% , VI = 0 V; in which VI refers to the input voltage at the I/O pin. (23) R_PD = VI/IR_PD Minimum condition: –40°C; VCCIO = VCC + 5% , VI = 50 mV; Typical condition: 25°C; VCCIO = VCC, VI = VCC – 5% ; Maximum condition: 100°C; VCCIO = VCC – 5% , VI = VCC – 5% ; in which VI refers to the input voltage at the I/O pin. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 13 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Hot-Socketing Table 12. Hot-Socketing Specifications for Intel Cyclone 10 LP Devices During hot-socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF. Symbol Parameter Maximum IIOPIN(DC) DC current per I/O pin 300 μA IIOPIN(AC) AC current per I/O pin IXCVRTX(DC) DC current per transceiver TX pin 100 mA IXCVRRX(DC) DC current per transceiver RX pin 50 mA 8 mA (24) Schmitt Trigger Input Intel Cyclone 10 LP devices support Schmitt trigger input on the TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rate. Table 13. Hysteresis Specifications for Schmitt Trigger Input for Supported VCCIO Range in Intel Cyclone 10 LP Devices Symbol VSCHMITT Parameter Hysteresis for Schmitt trigger input Condition (V) Minimum Unit VCCIO = 3.3 200 mV VCCIO = 2.5 200 mV VCCIO = 1.8 140 mV VCCIO = 1.5 110 mV I/O Standard Specifications Tables in this section list the input voltage sensitivities (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Intel Cyclone 10 LP devices. (24) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. Intel® Cyclone® 10 LP Device Datasheet 14 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Single-Ended I/O Standard Specifications Table 14. Single-Ended I/O Standard Specifications for Intel Cyclone 10 LP Devices AC load, CL = 10 pF I/O Standard VCCIO (V) VIL (V) VIH (V) VOL (V) VOH (V) IOL (mA) IOH (mA) Min Typ Max Min Max Min Max Max Min 3.3-V LVTTL 3.135 3.3 3.465 — 0.8 1.7 3.6 0.45 2.4 4 –4 3.3-V LVCMOS 3.135 3.3 3.465 — 0.8 1.7 3.6 0.2 VCCIO – 0.2 2 –2 2.85 3.0 3.15 –0.3 0.8 1.7 VCCIO + 0.3 0.45 2.4 4 –4 3.0-V LVTTL 3.0-V LVCMOS (25) (25) 2.85 3.0 3.15 –0.3 0.8 1.7 VCCIO + 0.3 0.2 VCCIO – 0.2 0.1 –0.1 2.5 V 2.375 2.5 2.625 –0.3 0.7 1.7 VCCIO + 0.3 0.4 2.0 1 –1 1.8 V 1.71 1.8 1.89 –0.3 0.35 × VCCIO 0.65 × VCCIO 2.25 0.45 VCCIO – 0.45 2 –2 1.5 V 1.425 1.5 1.575 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2 –2 1.2 V 1.14 1.2 1.26 –0.3 0.35 x VCCIO 0.65 x VCCIO VCCIO + 0.3 0.25 x VCCIO 0.75 x VCCIO 2 –2 3.0-V PCI 2.85 3.0 3.15 — 0.3 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5 3.0-V PCI-X 2.85 3.0 3.15 — 0.35 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5 Related Information AN 447: Interfacing Intel Devices with 3.3/3.0/2.5 V LVTTL/LVCMOS I/O Systems Provides more information about interfacing Intel Cyclone 10 LP devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O standards. (25) To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 3.3-V LVTTL specification (4 mA), set the current strength settings to 4 mA or higher. Setting at lower current strength may not meet the IOL and IOH specifications in the handbook. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 15 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Table 15. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Intel Cyclone 10 LP Devices I/O Standard VCCIO (V) VREF (V) VTT (V) (26) Min Typ Max Min Typ Max Min Typ Max 2.375 2.5 2.625 1.19 1.25 1.31 VREF – 0.04 VREF VREF + 0.04 SSTL-18 Class I, II 1.7 1.8 1.9 0.833 0.9 0.969 VREF – 0.04 VREF VREF + 0.04 HSTL-18 Class I, II 1.71 1.8 1.89 0.85 0.9 0.95 0.85 0.9 0.95 HSTL-15 Class I, II 1.425 1.5 1.575 0.71 0.75 0.79 0.71 0.75 0.79 0.52 × VCCIO — 0.5 × VCCIO — SSTL-2 Class I, II HSTL-12 Class I, II 1.14 1.2 1.26 0.48 × VCCIO 0.5 × VCCIO (27) 0.47 × VCCIO 0.5 × VCCIO (28) (27) (28) (27) 0.53 × VCCIO (28) Single-Ended SSTL and HSTL I/O Standards Signal Specifications Table 16. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Intel Cyclone 10 LP Devices I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (mA) IOH (mA) Min Max Min Max Min Max Min Max Max Min SSTL-2 Class I — VREF – 0.18 VREF + 0.18 — — VREF – 0.35 VREF + 0.35 — VTT – 0.57 VTT + 0.57 8.1 –8.1 SSTL-2 Class II — VREF – 0.18 VREF + 0.18 — — VREF – 0.35 VREF + 0.35 — VTT – 0.76 VTT + 0.76 16.4 –16.4 SSTL-18 Class I — VREF – 0.125 VREF + 0.125 — — VREF – 0.25 VREF + 0.25 — VTT – 0.475 VTT + 0.475 6.7 –6.7 SSTL-18 Class II — VREF – 0.125 VREF + 0.125 — — VREF – 0.25 VREF + 0.25 — 0.28 VCCIO – 0.28 13.4 –13.4 continued... (26) VTT of the transmitting device must track VREF of the receiving device. (27) Value shown refers to DC input reference voltage, VREF(DC). (28) Value shown refers to AC input reference voltage, VREF(AC). Intel® Cyclone® 10 LP Device Datasheet 16 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V) VOL (V) VOH (V) IOL (mA) IOH (mA) Min Max Min Max Min Max Min Max Max Min HSTL-18 Class I — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO – 0.4 8 –8 HSTL-18 Class II — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO – 0.4 16 –16 HSTL-15 Class I — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO – 0.4 8 –8 HSTL-15 Class II — VREF – 0.1 VREF + 0.1 — — VREF – 0.2 VREF + 0.2 — 0.4 VCCIO – 0.4 16 –16 HSTL-12 Class I –0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 –0.24 VREF – 0.15 VREF + 0.15 VCCIO + 0.24 0.25 × VCCIO 0.75 × VCCIO 8 –8 HSTL-12 Class II –0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 –0.24 VREF – 0.15 VREF + 0.15 VCCIO + 0.24 0.25 × VCCIO 0.75 × VCCIO 14 –14 Related Information I/O and High Speed I/O in Intel Cyclone 10 LP Devices chapter, Intel Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook Provides more information about receiver input and transmitter output waveforms, and other differential I/O standards. Differential SSTL I/O Standard Specifications Table 17. Differential SSTL I/O Standard Specifications for Intel Cyclone 10 LP Devices Differential SSTL requires a VREF input. I/O Standard VCCIO (V) VSwing(DC) (V) VX(AC) (V) VSwing(AC) (V) VOX(AC) (V) Min Typ Max Min Max Min Typ Max Min Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.36 VCCIO VCCIO/2 – 0.2 — VCCIO/2 + 0.2 0.7 VCCIO VCCIO/2 – 0.125 — VCCIO/2 + 0.125 SSTL-18 Class I, II 1.7 1.8 1.90 0.25 VCCIO VCCIO/2 – 0.175 — VCCIO/2 + 0.175 0.5 VCCIO VCCIO/2 – 0.125 — VCCIO/2 + 0.125 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 17 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Differential HSTL I/O Standard Specifications Table 18. Differential HSTL I/O Standard Specifications for Intel Cyclone 10 LP Devices Differential HSTL requires a VREF input. I/O Standard VCCIO (V) VDIF(DC) (V) VX(AC) (V) VCM(DC) (V) VDIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSTL-18 Class I, II 1.71 1.8 1.89 0.2 — 0.85 — 0.95 0.85 — 0.95 0.4 — HSTL-15 Class I, II 1.425 1.5 1.575 0.2 — 0.71 — 0.79 0.71 — 0.79 0.4 — HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO 0.48 × VCCIO — 0.52 × VCCIO 0.48 × VCCIO — 0.52 × VCCIO 0.3 0.48 × VCCIO Differential I/O Standard Specifications Table 19. Differential I/O Standard Specifications for Intel Cyclone 10 LP Devices I/O Standard LVPECL (Row I/Os) (31) LVPECL (Column I/Os) (31) VCCIO (V) VID (mV) VIcM (V) (29) VOD (mV) (30) VOS (V) (30) Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.80 — — — — — — 0.55 ≤ 500 Mbps DMAX ≤ 700 Mbps 1.80 1.05 DMAX > 700 Mbps 1.55 0.05 DMAX≤ 500 Mbps 1.80 — — — — — — 0.55 500 Mbps ≤ DMAX ≤ 700 Mbps 1.80 2.375 2.5 2.625 100 — continued... (29) VIN range: 0 V ≤ VIN ≤ 1.85 V. (30) RL range: 90 ≤ RL ≤ 110 Ω. (31) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins. Intel® Cyclone® 10 LP Device Datasheet 18 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 I/O Standard VCCIO (V) Min LVDS (Row I/Os) LVDS (Column I/Os) 2.375 2.375 Typ 2.5 2.5 VID (mV) Max 2.625 2.625 Min 100 100 Max — — VIcM (V) (29) VOD (mV) Min Condition Max 1.05 DMAX > 700 Mbps 1.55 0.05 DMAX≤ 500 Mbps 1.80 0.55 500 Mbps ≤ DMAX ≤ 700 Mbps 1.80 1.05 DMAX > 700 Mbps 1.55 0.05 DMAX ≤ 500 Mbps 1.80 0.55 500 Mbps ≤ DMAX ≤ 700 Mbps 1.80 1.05 DMAX > 700 Mbps 1.55 (30) VOS (V) (30) Min Typ Max Min Typ Max 247 — 600 1.125 1.25 1.375 247 — 600 1.125 1.25 1.375 BLVDS (Row I/Os) 2.375 2.5 2.625 100 — — — — — — — — — — BLVDS (Column I/Os) (32) 2.375 2.5 2.625 100 — — — — — — — — — — mini-LVDS (Row I/Os) (33) 2.375 2.5 2.625 — — — — — 300 — 600 1.0 1.2 1.4 mini-LVDS (Column I/Os) 2.375 2.5 2.625 — — — — — 300 — 600 1.0 1.2 1.4 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5 (32) (33) RSDS (Row I/ Os) (33) continued... (29) (30) VIN range: 0 V ≤ VIN ≤ 1.85 V. RL range: 90 ≤ RL ≤ 110 Ω. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 19 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 I/O Standard VCCIO (V) VID (mV) VIcM (V) (29) VOD (mV) (30) VOS (V) (30) Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max RSDS (Column I/Os) (33) 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.5 PPDS (Row I/ Os) (33) 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4 PPDS (Column I/Os) (33) 2.375 2.5 2.625 — — — — — 100 200 600 0.5 1.2 1.4 Power Consumption Use the following methods to estimate power for a design: • the Excel-based EPE • the Intel Quartus® Prime power analyzer feature The interactive Excel-based EPE is used prior to designing the device to get a magnitude estimate of the device power. The Intel Quartus Prime power analyzer provides better quality estimates based on the specifics of the design after place-androute is complete. The power analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, combined with detailed circuit models, can yield very accurate power estimates. Related Information • Early Power Estimator User Guide Provides more information about the power estimation tools. • Intel Quartus Prime Standard Edition User Guide: Power Analysis and Optimization Provides more information about power estimation tools. (29) VIN range: 0 V ≤ VIN ≤ 1.85 V. (30) RL range: 90 ≤ RL ≤ 110 Ω. (32) There are no fixed VIN, VOD , and VOS specifications for BLVDS. They depend on the system topology. (33) The Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins. Intel® Cyclone® 10 LP Device Datasheet 20 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Switching Characteristics This section provides performance characteristics of Intel Cyclone 10 LP core and periphery blocks for commercial grade devices. Core Performance Specifications Clock Tree Specifications Table 20. Clock Tree Performance for Intel Cyclone 10 LP Devices Device Performance Unit C6 C8 I7 I8 A7 10CL006 500 402 437.5 362 402 MHz 10CL010 500 402 437.5 362 402 MHz 10CL016 500 402 437.5 362 402 MHz 10CL025 500 402 437.5 362 402 MHz 10CL040 500 402 437.5 362 402 MHz 10CL055 500 402 437.5 362 — MHz 10CL080 500 402 437.5 362 — MHz 10CL120 — 402 437.5 362 — MHz PLL Specifications PLL specifications are for Intel Cyclone 10 LP devices operating in the commercial junction temperature range (0°C to 85°C), the industrial junction temperature range (–40°C to 100°C), the extended industrial junction temperature range (–40°C to 125°C), and the automotive junction temperature range (–40°C to 125°C). Send Feedback Intel® Cyclone® 10 LP Device Datasheet 21 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Table 21. PLL Specifications for Intel Cyclone 10 LP Devices This table is applicable for general purpose PLLs and multipurpose PLLs. You must connect VCCD_PLL to VCCINT through the decoupling capacitor and ferrite bead. Symbol Min Typ Max Unit Input clock frequency (–C6, –C8, –I7, and –A7 speed grades) 5 — 472.5 MHz Input clock frequency (–I8 speed grade) 5 — 362 MHz PFD input frequency 5 — 325 MHz 600 — 1300 MHz Input clock duty cycle 40 — 60 % Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI FREF < 100 MHz — — ±750 ps PLL output frequency — — 472.5 MHz PLL output frequency (–C6 speed grade) — — 472.5 MHz PLL output frequency (–I7, –A7 speed grades) — — 450 MHz PLL output frequency (–C8 speed grade) — — 402.5 MHz PLL output frequency (–I8 speed grade) — — 362 MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tLOCK Time required to lock from end of device configuration — — 1 fIN Parameter (34) fINPFD fVCO (35) PLL internal VCO operating range fINDUTY tINJITTER_CCJ (36) fOUT_EXT (external clock output) (34) fOUT (to global clock) ms continued... (34) This parameter is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (35) The VCO frequency reported by the Intel Quartus Prime software in the PLL Summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (36) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less than 200 ps. Intel® Cyclone® 10 LP Device Datasheet 22 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Parameter Min Typ Max Unit Time required to lock dynamically (after switchover, reconfiguring any non-post-scale counters/delays or areset is deasserted) — — 1 ms Dedicated clock output period jitter FOUT ≥ 100 MHz — — 300 ps FOUT < 100 MHz — — 30 mUI Dedicated clock output cycle-to-cycle jitter FOUT ≥ 100 MHz — — 300 ps FOUT < 100 MHz — — 30 mUI Regular I/O period jitter FOUT ≥ 100 MHz — — 650 ps FOUT < 100 MHz — — 75 mUI Regular I/O cycle-to-cycle jitter FOUT ≥ 100 MHz — — 650 ps FOUT < 100 MHz — — 75 mUI tPLL_PSERR Accuracy of PLL phase shift — — ±50 ps tARESET Minimum pulse width on areset signal. 10 — — ns tCONFIGPLL Time required to reconfigure scan chains for PLLs — — SCANCLK tDLOCK tOUTJITTER_PERIOD_DEDCLK tOUTJITTER_CCJ_DEDCLK tOUTJITTER_PERIOD_IO tOUTJITTER_CCJ_IO (37) (37) (37) (37) 3.5 (38) cycles continued... (37) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied. (38) With 100-MHz scanclk frequency. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 23 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Parameter fSCANCLK tCASC_OUTJITTER_PERIOD_DEDCLK (39) (40) Min Typ Max Unit scanclk frequency — — 100 MHz Period jitter for dedicated clock output in cascaded PLLs (FOUT ≥ 100 MHz) — — 425 ps Period jitter for dedicated clock output in cascaded PLLs (FOUT ≥ 100 MHz) — — 42.5 mUI Embedded Multiplier Specifications Table 22. Embedded Multiplier Specifications for Intel Cyclone 10 LP Devices Mode Resources Used Performance Unit Number of Multipliers C6 I7, A7 C8 I8 9 × 9-bit multiplier 1 340 300 260 240 MHz 18 × 18-bit multiplier 1 287 250 200 185 MHz Memory Block Specifications Table 23. M9K Memory Block Performance Specifications for Intel Cyclone 10 LP Devices Memory M9K Block Mode Resources Used Performance LEs M9K Memory C6 I7, A7 C8 I8 47 1 315 274 238 200 MHz Single-port 256 × 36 0 1 315 274 238 200 MHz Simple dual-port 256 × 36 CLK 0 1 315 274 238 200 MHz True dual port 512 × 18 single CLK 0 1 315 274 238 200 MHz FIFO 256 × 36 (39) The cascaded PLLs specification is applicable only with the following conditions: • Upstream PLL—0.59 MHz ≥ Upstream PLL bandwidth < 1 MHz • Downstream PLL—Downstream PLL bandwidth > 2 MHz (40) PLL cascading is not supported for transceiver applications. Intel® Cyclone® 10 LP Device Datasheet 24 Unit Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Periphery Performance I/O performance supports several system interfaces, such as the high-speed I/O interface and the PCI/PCI-X bus interface. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency with a 10 pF load. Note: Actual achievable frequency depends on design- and system-specific factors. Perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specifications RSDS Transmitter Timing Specifications Table 24. RSDS Transmitter Timing Specifications for Intel Cyclone 10 LP Devices Applicable for true RSDS and emulated RSDS_E_3R transmitter. True RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the output pin of all I/O Banks. Symbol fHSCLK (input clock frequency) Device operation in Mbps Mode C6 I7 C8, A7 I8 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max ×10 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×8 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×7 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×4 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×2 5 — 180 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×1 5 — 360 5 — 311 5 — 311 5 — 311 MHz ×10 100 — 360 100 — 311 100 — 311 100 — 311 Mbps ×8 80 — 360 80 — 311 80 — 311 80 — 311 Mbps ×7 70 — 360 70 — 311 70 — 311 70 — 311 Mbps ×4 40 — 360 40 — 311 40 — 311 40 — 311 Mbps ×2 20 — 360 20 — 311 20 — 311 20 — 311 Mbps continued... Send Feedback Intel® Cyclone® 10 LP Device Datasheet 25 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Mode C6 I7 C8, A7 I8 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max ×1 10 — 360 10 — 311 10 — 311 10 — 311 Mbps tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 % Transmitter channel-tochannel skew (TCCS) — — — 200 — — 200 — — 200 — — 200 ps Output jitter (peak to peak) — — — 500 — — 500 — — 550 — — 600 ps tRISE 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps tFALL 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps — — — 1 — — 1 — — 1 — — 1 ms tLOCK (41) Emulated RSDS_E_1R Transmitter Timing Specifications Table 25. Emulated RSDS_E_1R Transmitter Timing Specifications for Intel Cyclone 10 LP Devices Emulated RSDS_E_1R transmitter is supported at the output pin of all I/O Banks. Symbol fHSCLK (input clock frequency) Modes C6 I7 C8, A7 I8 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max ×10 5 — 85 5 — 85 5 — 85 5 — 85 MHz ×8 5 — 85 5 — 85 5 — 85 5 — 85 MHz ×7 5 — 85 5 — 85 5 — 85 5 — 85 MHz ×4 5 — 85 5 — 85 5 — 85 5 — 85 MHz ×2 5 — 85 5 — 85 5 — 85 5 — 85 MHz ×1 5 — 170 5 — 170 5 — 170 5 — 170 MHz continued... (41) tLOCK is the time required for the PLL to lock from the end-of-device configuration. Intel® Cyclone® 10 LP Device Datasheet 26 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Modes C6 I7 C8, A7 I8 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max ×10 100 — 170 100 — 170 100 — 170 100 — 170 Mbps ×8 80 — 170 80 — 170 80 — 170 80 — 170 Mbps ×7 70 — 170 70 — 170 70 — 170 70 — 170 Mbps ×4 40 — 170 40 — 170 40 — 170 40 — 170 Mbps ×2 20 — 170 20 — 170 20 — 170 20 — 170 Mbps ×1 10 — 170 10 — 170 10 — 170 10 — 170 Mbps tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 % TCCS — — — 200 — — 200 — — 200 — — 200 ps Output jitter (peak to peak) — — — 500 — — 500 — — 550 — — 600 ps tRISE 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps tFALL 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps — — — 1 — — 1 — — 1 — — 1 ms Device operation in Mbps tLOCK (42) (42) tLOCK is the time required for the PLL to lock from the end-of-device configuration. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 27 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Mini-LVDS Transmitter Timing Specifications Table 26. Mini-LVDS Transmitter Timing Specifications for Intel Cyclone 10 LP Devices Applicable for true and emulated mini-LVDS transmitter. True mini-LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated mini-LVDS transmitter is supported at the output pin of all I/O banks. Symbol Modes C6 I7 C8, A7 I8 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max ×10 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×8 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×7 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×4 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×2 5 — 200 5 — 155.5 5 — 155.5 5 — 155.5 MHz ×1 5 — 400 5 — 311 5 — 311 5 — 311 MHz ×10 100 — 400 100 — 311 100 — 311 100 — 311 Mbps ×8 80 — 400 80 — 311 80 — 311 80 — 311 Mbps ×7 70 — 400 70 — 311 70 — 311 70 — 311 Mbps ×4 40 — 400 40 — 311 40 — 311 40 — 311 Mbps ×2 20 — 400 20 — 311 20 — 311 20 — 311 Mbps ×1 10 — 400 10 — 311 10 — 311 10 — 311 Mbps tDUTY — 45 — 55 45 — 55 45 — 55 45 — 55 % TCCS — — — 200 — — 200 — — 200 — — 200 ps Output jitter (peak to peak) — — — 500 — — 500 — — 550 — — 600 ps fHSCLK (input clock frequency) Device operation in Mbps continued... Intel® Cyclone® 10 LP Device Datasheet 28 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Modes C6 I7 C8, A7 I8 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max tRISE 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps tFALL 20 – 80%, CLOAD = 5 pF — 500 — — 500 — — 500 — — 500 — ps — — — 1 — — 1 — — 1 — — 1 ms tLOCK (43) True LVDS Transmitter Timing Specifications Table 27. True LVDS Transmitter Timing Specifications for Intel Cyclone 10 LP Devices True LVDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Symbol fHSCLK (input clock frequency) HSIODR Modes C6 I7 C8, A7 I8 Unit Min Max Min Max Min Max Min Max ×10 5 420 5 370 5 320 5 320 MHz ×8 5 420 5 370 5 320 5 320 MHz ×7 5 420 5 370 5 320 5 320 MHz ×4 5 420 5 370 5 320 5 320 MHz ×2 5 420 5 370 5 320 5 320 MHz ×1 5 420 5 402.5 5 402.5 5 362 MHz ×10 100 840 100 740 100 640 100 640 Mbps ×8 80 840 80 740 80 640 80 640 Mbps ×7 70 840 70 740 70 640 70 640 Mbps ×4 40 840 40 740 40 640 40 640 Mbps ×2 20 840 20 740 20 640 20 640 Mbps ×1 10 420 10 402.5 10 402.5 10 362 Mbps continued... (43) tLOCK is the time required for the PLL to lock from the end-of-device configuration. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 29 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Modes C6 I7 C8, A7 I8 Unit Min Max Min Max Min Max Min Max tDUTY — 45 55 45 55 45 55 45 55 % TCCS — — 200 — 200 — 200 — 200 ps Output jitter (peak to peak) — — 500 — 500 — 550 — 600 ps tLOCK (44) — — 1 — 1 — 1 — 1 ms Emulated LVDS Transmitter Timing Specifications Table 28. Emulated LVDS Transmitter Timing Specifications for Intel Cyclone 10 LP Devices Emulated LVDS transmitter is supported at the output pin of all I/O Banks. Symbol fHSCLK (input clock frequency) HSIODR Modes C6 I7 C8, A7 I8 Unit Min Max Min Max Min Max Min Max ×10 5 320 5 320 5 275 5 275 MHz ×8 5 320 5 320 5 275 5 275 MHz ×7 5 320 5 320 5 275 5 275 MHz ×4 5 320 5 320 5 275 5 275 MHz ×2 5 320 5 320 5 275 5 275 MHz ×1 5 402.5 5 402.5 5 402.5 5 362 MHz ×10 100 640 100 640 100 550 100 550 Mbps ×8 80 640 80 640 80 550 80 550 Mbps ×7 70 640 70 640 70 550 70 550 Mbps ×4 40 640 40 640 40 550 40 550 Mbps ×2 20 640 20 640 20 550 20 550 Mbps continued... (44) tLOCK is the time required for the PLL to lock from the end-of-device configuration. Intel® Cyclone® 10 LP Device Datasheet 30 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Modes C6 I7 C8, A7 I8 Unit Min Max Min Max Min Max Min Max ×1 10 402.5 10 402.5 10 402.5 10 362 Mbps tDUTY — 45 55 45 55 45 55 45 55 % TCCS — — 200 — 200 — 200 — 200 ps Output jitter (peak to peak) — — 500 — 500 — 550 — 600 ps tLOCK (45) — — 1 — 1 — 1 — 1 ms LVDS Receiver Timing Specifications Table 29. LVDS Receiver Timing Specifications for Intel Cyclone 10 LP Devices LVDS receiver is supported at all I/O Banks. Symbol fHSCLK (input clock frequency) HSIODR Modes C6 I7 C8, A7 I8 Unit Min Max Min Max Min Max Min Max ×10 10 437.5 10 370 10 320 10 320 MHz ×8 10 437.5 10 370 10 320 10 320 MHz ×7 10 437.5 10 370 10 320 10 320 MHz ×4 10 437.5 10 370 10 320 10 320 MHz ×2 10 437.5 10 370 10 320 10 320 MHz ×1 10 437.5 10 402.5 10 402.5 10 362 MHz ×10 100 875 100 740 100 640 100 640 Mbps ×8 80 875 80 740 80 640 80 640 Mbps ×7 70 875 70 740 70 640 70 640 Mbps ×4 40 875 40 740 40 640 40 640 Mbps continued... (45) tLOCK is the time required for the PLL to lock from the end-of-device configuration. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 31 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol SW Input jitter tolerance tLOCK (46) Modes C6 I7 C8, A7 I8 Unit Min Max Min Max Min Max Min Max ×2 20 875 20 740 20 640 20 640 Mbps ×1 10 437.5 10 402.5 10 402.5 10 362 Mbps — — 400 — 400 — 400 — 550 ps — — 500 — 500 — 550 — 600 ps — — 1 — 1 — 1 — 1 ms Duty Cycle Distortion Specifications Table 30. Worst-Case Duty Cycle Distortion on Intel Cyclone 10 LP Devices I/O Pins The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general purpose I/O pins. Intel Cyclone 10 LP devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current strength. Symbol C6 Output Duty Cycle I7 C8, I8, A7 Unit Min Max Min Max Min Max 45 55 45 55 45 55 % OCT Calibration Timing Specification Table 31. Timing Specification for Series OCT with Calibration at Device Power-Up for Intel Cyclone 10 LP Devices OCT calibration takes place after device configuration and before entering user mode. Description Symbol tOCTCAL (46) Duration of series OCT with calibration at device power-up Unit 20 µs tLOCK is the time required for the PLL to lock from the end-of-device configuration. Intel® Cyclone® 10 LP Device Datasheet 32 Maximum Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 IOE Programmable Delay The incremental values for the settings are generally linear. For the exact values for each setting, use the latest version of the Intel Quartus Prime software. The values in the table show the delay of programmable IOE delay chain with maximum offset settings after excluding the intrinsic delay (delay at minimum offset settings). The minimum and maximum offset timing numbers are in reference to setting 0 as available in the Intel Quartus Prime software. Table 32. IOE Programmable Delay on Column Pins for Intel Cyclone 10 LP 1.0 V Core Voltage Devices Parameter Paths Affected Number of Setting Min Offset Max Offset Unit Fast Corner Slow Corner I8 I8 Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.924 3.411 ns Input delay from pin to input register Pad to I/O input register 8 0 1.875 3.367 ns Delay from output register to output pin I/O output register to pad 2 0 0.631 1.124 ns Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.931 1.684 ns Table 33. IOE Programmable Delay on Row Pins for Intel Cyclone 10 LP 1.0 V Core Voltage Devices Parameter Paths Affected Number of Setting Min Offset Max Offset Unit Fast Corner Slow Corner I8 I8 Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.921 3.412 ns Input delay from pin to input register Pad to I/O input register 8 0 1.919 3.441 ns Delay from output register to output pin I/O output register to pad 2 0 0.623 1.168 ns Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.919 1.656 ns Send Feedback Intel® Cyclone® 10 LP Device Datasheet 33 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Table 34. IOE Programmable Delay on Column Pins for Intel Cyclone 10 LP 1.2 V Core Voltage Devices Parameter Paths Affected Number of Setting Min Offset Max Offset Fast Corner Unit Slow Corner C6 I7 A7 C6 C8 I7 A7 Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.314 1.211 1.211 2.177 2.433 2.388 2.508 ns Input delay from pin to input register Pad to I/O input register 8 0 1.307 1.203 1.203 2.19 2.540 2.430 2.545 ns Delay from output register to output pin I/O output register to pad 2 0 0.437 0.402 0.402 0.747 0.880 0.834 0.873 ns Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.693 0.665 0.665 1.200 1.532 1.393 1.441 ns Table 35. IOE Programmable Delay on Row Pins for Intel Cyclone 10 LP 1.2 V Core Voltage Devices Parameter Paths Affected Number of Setting Min Offset Max Offset Fast Corner Unit Slow Corner C6 I7 A7 C6 C8 I7 A7 Input delay from pin to internal cells Pad to I/O dataout to core 7 0 1.314 1.209 1.209 2.201 2.510 2.429 2.548 ns Input delay from pin to input register Pad to I/O input register 8 0 1.312 1.207 1.207 2.202 2.558 2.447 2.557 ns Delay from output register to output pin I/O output register to pad 2 0 0.458 0.419 0.419 0.783 0.924 0.875 0.915 ns Input delay from dual-purpose clock pin to fan-out destinations Pad to global clock network 12 0 0.686 0.657 0.657 1.185 1.506 1.376 1.422 ns Configuration Specifications This section provides configuration specifications and timing for the Intel Cyclone 10 LP devices. Intel® Cyclone® 10 LP Device Datasheet 34 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 JTAG Timing Parameters Table 36. JTAG Timing Parameters for Intel Cyclone 10 LP Devices Symbol Parameter Min Max Unit tJCP TCK clock period 40 — ns tJCH TCK clock high time 19 — ns tJCL TCK clock low time 19 — ns tJPSU_TDI JTAG port setup time for TDI 1 — ns tJPSU_TMS JTAG port setup time for TMS 3 — ns tJPH JTAG port hold time 10 — ns tJPCO JTAG port clock to output (47) — 15 ns JTAG port high impedance to valid output (47) — 15 ns tJPXZ JTAG port valid output to high impedance (47) — 15 ns tJSSU Capture register setup time 5 — ns tJSH Capture register hold time 10 — ns tJSCO Update register clock to output — 25 ns tJSZX Update register high impedance to valid output — 25 ns tJSXZ Update register valid output to high impedance — 25 ns tJPZX Active Configuration Mode Specifications Table 37. Active Configuration Mode Specifications for Intel Cyclone 10 LP Devices Programming Mode Active Serial (AS) (47) DCLK Range Typical DCLK Unit 20 to 40 33 MHz The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 35 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 AS Configuration Timing Table 38. AS Configuration Timing for Intel Cyclone 10 LP Devices Symbol Parameter Configuration Time Unit 10 ns tSU Setup time tDH Hold time 0 ns tCO Clock-to-output time 4 ns Related Information AS Configuration Timing Provides the AS configuration timing waveform. Passive Configuration Mode Specifications Table 39. Passive Configuration Mode Specifications for Intel Cyclone 10 LP Devices Programming Mode Passive Serial (PS) VCCINT Voltage Level (V) 1.0 (48) 1.2 Fast Passive Parallel (FPP) (49) DCLK fMAX Unit 66 MHz 133 MHz 1.0 (48) 66 MHz 1.2 (50) 100 MHz (48) VCCINT = 1.0 V is only supported for Intel Cyclone 10 LP 1.0 V core voltage devices. (49) FPP configuration mode supports all Intel Cyclone 10 LP devices (except for E144 package devices). (50) Intel Cyclone 10 LP 1.2 V core voltage devices support 133 MHz DCLK fMAX for 10CL006, 10CL010, 10CL016, 10CL025, and 10CL040 only. Intel® Cyclone® 10 LP Device Datasheet 36 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 PS Configuration Timing Table 40. PS Configuration Timing Parameters for Intel Cyclone 10 LP Devices Symbol Parameter Minimum 1.2 V Core Voltage Maximum 1.0 V Core Voltage 1.2 V Core Voltage Unit 1.0 V Core Voltage tCF2CD nCONFIG low to CONF_DONE low — 500 ns tCF2ST0 nCONFIG low to nSTATUS low — 500 ns tCFG nCONFIG low pulse width 500 — ns tSTATUS nSTATUS low pulse width 45 tCF2ST1 — nCONFIG high to nSTATUS high tCF2CK nCONFIG high to first rising edge on DCLK tST2CK nSTATUS high to first rising edge of DCLK tDH Data hold time after rising edge on DCLK tCD2UM CONF_DONE high to user mode tCD2CU 230 (51) 230 (51) µs 230 (52) µs — µs 2 — µs 0 — ns 300 650 µs CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with tCD2CU + (3,192 × CLKUSR period) — — tDSU Data setup time before rising edge on DCLK tCH DCLK high time (53) CLKUSR option on 5 8 — 3.2 6.4 — — ns continued... (51) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (52) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. (53) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 37 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Parameter Minimum Maximum Unit 1.2 V Core Voltage 1.0 V Core Voltage 1.2 V Core Voltage 1.0 V Core Voltage tCL DCLK low time 3.2 6.4 — — ns tCLK DCLK period 7.5 15 — — ns fMAX DCLK frequency — — 133 66 MHz Related Information PS Configuration Timing Provides the PS configuration timing waveform. FPP Configuration Timing Table 41. FPP Timing Parameters for Intel Cyclone 10 LP Devices Symbol Parameter Minimum 1.2 V Core Voltage 1.0 V Core Voltage Maximum 1.2 V Core Voltage Unit 1.0 V Core Voltage tCF2CD nCONFIG low to CONF_DONE low — 500 ns tCF2ST0 nCONFIG low to nSTATUS low — 500 ns tCFG nCONFIG low pulse width 500 — ns tSTATUS nSTATUS low pulse width 45 230 (54) µs tCF2ST1 nCONFIG high to nSTATUS high — 230 (55) µs tCF2CK nCONFIG high to first rising edge on DCLK tST2CK nSTATUS high to first rising edge of DCLK tDH Data hold time after rising edge on DCLK tCD2UM CONF_DONE high to user mode (56) 230 (54) — µs 2 — µs 0 — ns 300 650 µs continued... (54) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (55) This value is applicable if you do not delay configuration by externally holding the nSTATUS low. Intel® Cyclone® 10 LP Device Datasheet 38 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Symbol Parameter Minimum 1.2 V Core Voltage Maximum 1.0 V Core Voltage 1.2 V Core Voltage Unit 1.0 V Core Voltage tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with tCD2CU + (3,192 × CLKUSR period) — — tDSU Data setup time before rising edge on DCLK tCH CLKUSR option on 5 8 — — ns DCLK high time 3.2 6.4 — — ns tCL DCLK low time 3.2 6.4 — — ns tCLK DCLK period 7.5 15 — — ns fMAX DCLK frequency — — 133 66 MHz Related Information FPP Configuration Timing Provides the FPP configuration timing waveform. I/O Timing I/O timing data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the timing analysis. You may generate the I/O timing report manually using the Timing Analyzer or using the automated script. The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information AN 775: I/O Timing Information Generation Guidelines Provides the techniques to generate I/O timing information using the Intel Quartus Prime software. (56) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 39 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Glossary Terms • Receiver input skew margin (RSKM)—High-speed I/O block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2. • SW (Sampling Window)—High-speed I/O block: The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window. Clock Pins and Blocks • fHSCLK—High-speed I/O block: High-speed receiver/transmitter input and output clock frequency. • GCLK—Input pin directly to Global Clock network. • GCLK PLL—Input pin to Global Clock network through the PLL. • HSIODR—High-speed I/O block: Maximum/minimum LVDS data transfer rate (HSIODR = 1/TUI). • PLL Block—The following figure highlights the PLL specification parameters CLKOUT Pins Switchover fOUT _EXT CLK fIN Core Clock N fINPFD PFD CP LF VCO fVCO Counters C0..C4 fOUT GCLK Phase tap M Key Reconfigurable in User Mode • RL—Receiver differential input discrete resistor (external to Intel Cyclone 10 LP devices). Intel® Cyclone® 10 LP Device Datasheet 40 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Example Waveforms Input Waveforms for the SSTL Differential I/O Standard VIH VSWING VREF VIL JTAG Waveform TMS TDI tJCH tJCP tJPSU_TDI tJPSU_TMS t JCL tJPH TCK tJPZX TDO Signal to be Captured Signal to be Driven tJSSU tJSZX tJPXZ tJPCO tJSH tJSCO tJSXZ Receiver Waveform for LVDS and LVPECL Differential Standards Send Feedback Intel® Cyclone® 10 LP Device Datasheet 41 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 Single-Ended Waveform Positive Channel (p) = VIH Negative Channel (n) = VIL VCM Ground Differential Input Waveform + VTH 0V - VTH p-n Single-Ended Voltage-Referenced I/O Standard V CCIO V OH V IH (AC ) V REF V IH(DC ) V IL(DC ) V IL(AC ) V OL V SS Intel® Cyclone® 10 LP Device Datasheet 42 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Transmitter Output Waveform for the LVDS, Mini-LVDS, PPDS and RSDS Differential I/O Standards: Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VOS Ground Differential Waveform (Mathematical Function of Positive and Negative Channel) VOD 0V VOD p-n Delay Definitions • tC—High-speed receiver and transmitter input and output clock period. • Channel-to-channel-skew (TCCS)—High-speed I/O block: The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. • tcin—Delay from the clock pad to the I/O input register. • tCO—Delay from the clock pad to the I/O output. • tcout—Delay from the clock pad to the I/O output register. • tDUTY—High-speed I/O block: Duty cycle on high-speed transmitter output clock. • tFALL—Signal high-to-low transition time (80–20%). • tH—Input register hold time. Send Feedback Intel® Cyclone® 10 LP Device Datasheet 43 Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 • Timing Unit Interval (TUI)—High-speed I/O block: The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w). • tINJITTER—Period jitter on the PLL clock input. • tOUTJITTER_DEDCLK—Period jitter on the dedicated clock output driven by a PLL. • tOUTJITTER_IO—Period jitter on the general purpose I/O driven by a PLL. • tpllcin—Delay from the PLL inclk pad to the I/O input register. • tpllcout—Delay from the PLL inclk pad to the I/O output register. • tRISE—Signal low-to-high transition time (20–80%). • tSU—Input register setup time. Voltage Definitions • VCM(DC)—DC common mode input voltage. • VDIF(AC)—AC differential input voltage: The minimum AC input differential voltage required for switching. • VDIF(DC)—DC differential input voltage: The minimum DC input differential voltage required for switching. • VICM—Input common mode voltage: The common mode of the differential signal at the receiver. • VID—Input differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. • VIH—Voltage input high: The minimum positive voltage applied to the input that is accepted by the device as a logic high. • VIH(AC)—High-level AC input voltage. • VIH(DC)—High-level DC input voltage. • VIL—Voltage input low: The maximum positive voltage applied to the input that is accepted by the device as a logic low. • VIL (AC)—Low-level AC input voltage. • VIL (DC)—Low-level DC input voltage. • VIN—DC input voltage. • VOCM—Output common mode voltage: The common mode of the differential signal at the transmitter. • VOD—Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. VOD = VOH – VOL. • VOH—Voltage output high: The maximum positive voltage from an output that the device considers is accepted as the minimum positive high level. Intel® Cyclone® 10 LP Device Datasheet 44 Send Feedback Intel® Cyclone® 10 LP Device Datasheet 683251 | 2022.10.31 • VOL—Voltage output low: The maximum positive voltage from an output that the device considers is accepted as the maximum positive low level. • VOS—Output offset voltage: VOS = (VOH + VOL) / 2. • VOX (AC)—AC differential output cross point voltage: the voltage at which the differential output signals must cross. • VREF—Reference voltage for the SSTL and HSTL I/O standards. • VREF (AC)—AC input reference voltage for the SSTL and HSTL I/O standards. VREF(AC) = VREF(DC) + noise. The peak-to-peak AC noise on VREF must not exceed 2% of VREF(DC). • VREF (DC)—DC input reference voltage for the SSTL and HSTL I/O standards. • VSWING (AC)—AC differential input voltage: AC input differential voltage required for switching. For the SSTL differential I/O standard, refer to Input Waveforms. • VSWING (DC)—DC differential input voltage: DC input differential voltage required for switching. For the SSTL differential I/O standard, refer to Input Waveforms. • VTT—Termination voltage for the SSTL and HSTL I/O standards. • VX (AC)—AC differential input cross point voltage: The voltage at which the differential input signals must cross. Document Revision History for the Intel Cyclone 10 LP Device Datasheet Document Version Changes 2022.10.31 Added footnote to TJ for extended temperature in the Recommended Operating Conditions for Intel Cyclone 10 LP Devices table. 2018.05.07 • • • • 2017.05.08 Send Feedback Removed the specifications for the quad flat no leads (QFN) package in the Pin Capacitance for Intel Cyclone 10 LP Devices table. Added the following configuration specifications: — AS Configuration Timing — PS Configuration Timing — FPP Configuration Timing Updated the description in the IOE Programmable Delay section. Updated the I/O Timing section on the I/O timing information generation guidelines. Initial release. Intel® Cyclone® 10 LP Device Datasheet 45
10CL016YF484I7G 价格&库存

很抱歉,暂时无法提供与“10CL016YF484I7G”相匹配的价格&库存,您可以联系我们找货

免费人工找货