DataSheeT – enpirion® power solutions
EN6347QI 4A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EN6347QI is an Intel® Enpirion® Power System on
a Chip (PowerSoC) DC-DC converter. It integrates the
inductor, MOSFET switches, small-signal circuits and
compensation in an advanced 4mm x 7mm x 1.85mm
38-pin QFN package.
FEATURES
• Integrated Inductor, MOSFETs, Controller
• 1.5% VOUT Accuracy (Over Load and Temperature)
• Up to 4A Continuous Operating Current
• 3 MHz Operating Frequency with Ext Clock Sync
The EN6347QI is specifically designed to meet the
precise voltage and fast transient requirements of
present and future high-performance, low-power
processor, DSP, FPGA, memory boards and system
level applications in distributed power architectures.
The device’s advanced circuit techniques, high
switching frequency, and proprietary integrated
inductor technology deliver high-quality, ultra
compact, non-isolated DC-DC conversion.
• High Efficiency (Up to 95%)
Intel Enpirion Power Solutions significantly help in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of components required for the complete power
solution helps to enable an overall system cost
saving.
• RoHS Compliant, MSL Level 3, 260°C Reflow
All Enpirion products are RoHS compliant and leadfree manufacturing environment compatible.
• Frequency Synchronization to External Clock
• Input Voltage Range (2.5V to 6.6V)
• Programmable Light Load Mode
• Output Enable Pin and Power OK
• Programmable Soft-Start
• Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
APPLICATIONS
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Low Voltage, Distributed Power Architectures
• High Efficiency 12V Intermediate Bus
Architectures
• Blade Servers, RAID Storage, Industrial Automation,
Embedded Computing, Wireless Communications
• Beat Frequency/Noise Sensitive Applications
EN6347QI
PVIN
VOUT
ENABLE
22µF
1206
CSS
AVIN
PGND
VFB
100
90
RA
80
CA
47µF
1206
PGND
LLM/
SS
AGND SYNC
Efficiency vs. Output Current
VOUT
RB
EFFICIENCY (%)
VIN
70
60
50
40
30
20
10
0
0.01
CONDITIONS
VIN = 5V
75mm2
VOUT = 3.3V LLM
VOUT = 3.3V PWM
0.1
1
10
OUTPUT CURRENT (A)
Figure 1. Simplified Applications Circuit
Figure 2. Highest Efficiency in Smallest Solution Size
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ORDERING INFORMATION
Part Number
Package Markings
TJ Rating
Package Description
EN6347QI
EN6347
-40°C to +125°C
38-pin (4mm x 7mm x 1.85mm) QFN
EVB-EN6347QI
EN6347
QFN Evaluation Board
Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html
NC(SW)
NC(SW)
NC(SW)
NC(SW)
AVIN
AGND
VFB
SS
RLLM
POK
ENABLE
LLM / SYNC
37
36
35
34
33
32
31
30
29
28
27
26
KEEP OUT
NC(SW)
12
13
14
15
16
17
18
19
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
6
NC(SW)
VOUT
11
5
VOUT
VOUT
10
4
KEEP OUT
VOUT
NC
39
PGND
9
3
VOUT
NC
8
2
VOUT
NC(SW)
7
1
VOUT
NC(SW)
38
PIN FUNCTIONS
25
NC
24
NC
23
NC
22
NC
21
PVIN
20
PVIN
Figure 3. Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically connected
to the PCB. Refer to Figure 11 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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PIN DESCRIPTIONS
PIN
1,2, 12,
34-38
NAME
NC(SW)
TYPE
FUNCTION
-
NO CONNECT – These pins are internally connected to the common
switching node of the internal MOSFETs. They are not to be electrically
connected to any external signal, ground, or voltage. Failure to follow this
guideline may result in damage to the device.
3,4,
22-25
NC
-
NO CONNECT – These pins may be internally connected. Do not connect
to each other or to any other electrical signal. Failure to follow this
guideline may result in device damage.
5- 11
VOUT
Power
Regulated converter output. Connect to the load and place output filter
capacitor(s) between these pins and PGND pins. Refer to the Layout
Recommendation section.
13-18
PGND
Ground
Input/Output power ground. Connect to the ground electrode of the input
and output filter capacitors. See VOUT and PVIN pin descriptions for more
details.
19-21
PVIN
Power
Input power supply. Connect to input power supply. Decouple with input
capacitor to PGND pin. Refer to the Layout Recommendation section.
26
LLM/SYNC
Analog
Dual function pin providing LLM Enable and External Clock
Synchronization (see Application Section). At static Logic HIGH, device will
allow automatic engagement of light load mode. At static logic LOW, the
device is forced into PWM only. A clocked input to this pin will synchronize
the internal switching frequency to the external signal. If this pin is left
floating, it will pull to a static logic high, enabling LLM.
27
ENABLE
Analog
Input Enable. Applying logic high enables the output and initiates a softstart. Applying logic low discharges the output through a soft-shutdown.
28
POK
Digital
Power OK is an open drain transistor used for power system state
indication. POK is logic high when VOUT is within -10% of VOUT nominal.
29
RLLM
Analog
Programmable LLM engage resistor to AGND allows for adjustment of load
current at which Light-Load Mode engages. Can be left open for PWM only
operation.
30
SS
Analog
A soft-start capacitor is connected between this pin and AGND. The value
of the capacitor controls the soft-start interval. Refer to Soft-Start
Operation in the Functional Description section for more details.
31
VFB
Analog
External Feedback Input. The feedback loop is closed through this pin. A
voltage divider at VOUT is used to set the output voltage. The midpoint of
the divider is connected to VFB. A phase lead capacitor from this pin to
VOUT is also required to stabilize the loop.
32
AGND
Power
Ground for internal control circuits. Connect to the power ground plane
with a via right next to the pin.
33
AVIN
Power
Input power supply for the controller. Connect to input voltage at a quiet
point. Refer to the Layout Recommendation section.
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PIN
39
NAME
PGND
TYPE
Ground
FUNCTION
Power ground thermal pad. Not a perimeter pin. Connect thermal pad to
the system GND plane for heat-sinking purposes. Refer to the Layout
Recommendation section.
ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER
SYMBOL
MIN
MAX
UNITS
PVIN, AVIN, VOUT
-0.3
7.0
V
ENABLE, POK, LLM/SYNC, PG
-0.3
VIN+0.3
V
VFB, SS, RLLM, VDDB
-0.3
2.5
V
MIN
MAX
UNITS
+150
°C
+150
°C
+260
°C
MAX
UNITS
Absolute Maximum Thermal Ratings
PARAMETER
CONDITION
Maximum Operating Junction
Temperature
Storage Temperature Range
Reflow Peak Body Temperature
-65
(10 Sec) MSL3 JEDEC J-STD-020A
Absolute Maximum ESD Ratings
PARAMETER
CONDITION
MIN
HBM (Human Body Model)
±2000
V
CDM (Charged Device Model)
±500
V
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RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
VIN
2.5
6.6
Output Voltage Range
VOUT
0.75
Output Current Range
IOUT
Operating Ambient Temperature Range
TA
Operating Junction Temperature
TJ
Input Voltage Range
VIN – VDO
UNITS
V
V
(1)
4
A
-40
+85
°C
-40
+125
°C
THERMAL CHARACTERISTICS
PARAMETER
SYMBOL
TYPICAL
UNITS
TSD
160
°C
TSDHYS
35
°C
Thermal Resistance: Junction to Ambient (0 LFM) (2)
θJA
30
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
3
°C/W
Thermal Shutdown
Thermal Shutdown Hysteresis
(1) VDO (dropout voltage) is defined as (ILOAD x Droput Resistance). Please refer to Electrical Characteristics Table.
(2) Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for high
thermal conductivity boards.
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ELECTRICAL CHARACTERISTICS
NOTE: VIN = 6.6V, Minimum and Maximum values are over operating ambient temperature range unless
otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
2.5
MAX
UNITS
6.6
V
Operating Input Voltage
VIN
Under Voltage Lock-Out
– VIN Rising
VUVLOR
Voltage above which UVLO is
not asserted
2.3
V
Under Voltage Lock-Out
– VIN Falling
VUVLOF
Voltage below which UVLO is
asserted
2.075
V
Shut-Down Supply
Current
IS
ENABLE = 0V
100
µA
Operating Quiescent
Current
IQ
LLM/SYNC = High
650
µA
Feedback Pin Voltage (3)
VFB
VIN = 5V, ILOAD = 0, TA =
25°C
0.7425
0.75
0.7575
V
0.739
0.75
0.761
V
0.735
0.75
0.765
V
5
nA
0A ≤ ILOAD ≤ 4A
Feedback Pin Voltage
(Load, Temp.)
VFB
Feedback Pin Voltage
(Line, Load, Temp.)
VFB
Feedback pin Input
Leakage Current (4)
IFB
VFB pin input leakage current
-5
VOUT Rise Time Range (4)
tRISE
Measured from when VIN >
VUVLOR & ENABLE pin voltage
crosses its logic high
threshold to when VOUT
reaches its final value. CSS =
15 nF
0.9
1.2
1.5
ms
Soft Start Capacitance
Range
CSS_RANGE
10
47
68
nF
Starting Date Code: X501 or
greater
3.0V ≤ VIN ≤ 6.0V
0A ≤ ILOAD ≤ 4A
Drop-Out Voltage (4)
VDO
VINMIN - VOUT at full load
240
360
mV
Drop-Out Resistance (4)
RDO
Input to output resistance
60
90
mΩ
Continuous Output
Current
IOUT
Over Current Trip Level
IOCP
PMW mode
0
4
LLM mode
0.002
4
(5)
VIN = 5V, VOUT = 1.2V
5
A
A
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PARAMETER
SYMBOL
Disable Threshold
VDISABLE
Enable Threshold
VEN
ENABLE Lockout Time
TEST CONDITIONS
ENABLE pin logic low
ENABLE pin logic high
2.5V ≤ VIN ≤ 6.6V
MIN
MAX
UNITS
0
0.6
V
1.8
VIN
V
TENLOCKOU
T
TYP
3.2
ms
ENABLE Pin Input
Current (4)
IEN
ENABLE pin has ~180kΩ pull
down
40
µA
Switching Frequency
(Free Running)
FSW
Free running frequency of
oscillator
3
MHz
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range of SYNC clock
frequency
SYNC Input Threshold –
Low (LLM/SYNC PIN)
VSYNC_LO
SYNC Clock Logic Level
SYNC Input Threshold –
High (LLM/SYNC PIN) (6)
VSYNC_HI
SYNC Clock Logic Level
POK Lower Threshold
POKLT
Output voltage as a fraction
of expected output voltage
POK Low Voltage
VPOKL
With 4mA current sink into
POK
0.4
V
POK High Voltage
VPOKH
2.5V ≤ VIN ≤ 6.6V
VIN
V
POK Pin Leakage
Current (4)
IPOKH
POK is high
1
µA
1.8
LLM Logic Low
(LLM/SYNC PIN)
VLLM_LO
LLM Static Logic Level
LLM Logic High
(LLM/SYNC PIN)
VLLM_HI
LLM Static Logic Level
3.5
MHz
0.8
V
2.5
V
90
Minimum VIN-VOUT to ensure
proper LLM operation
LLM Engage Headroom
LLM/SYNC Pin Current
2.5
%
800
mV
0.3
1.5
LLM/SYNC Pin is 5.0V
12pF
6.6V
22pF
≤ 5.0V
15pF
≤5.0V
33pF
6.6V
12pF
6.6V
27pF
5.0V
15pF
5.0V
33pF
3.3V
22pF
3.3V
39pF
2.5V
27pF
2.5V
47pF
> 3.3V
15pF
6.6V
27pF
≤ 3.3V
27pF
5.0V
33pF
6.6V
15pF
≤3.3V
47pF
5.0V
18pF
6.6V
27pF
≤ 3.3V
27pF
5.0V
39pF
≤3.3V
47pF
2.5V
1.8V
1.5V
≤ 1.2V
Input Capacitor Selection
The EN6347QI requires at least a 22µF X5R/X7R ceramic input capacitor. Additional input capacitors may be
used in parallel to reduce input voltage spikes caused by parasitic line inductance. For applications where the
input of the EN6347QI is far from the input power source, be sure to use sufficient bulk capacitors to mitigate
the extra line inductance. Low-cost, low-ESR ceramic capacitors should be used as input capacitors for this
converter. The dielectric must be X5R/X7R rated. Y5V or equivalent dielectric formulations must not be used
as these lose too much capacitance with frequency, temperature and bias voltage. In some applications, lower
value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency
decoupling.
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Table 3. Recommended Input Capacitors
Description
MFG
P/N
Murata
22µF, 10V, X7R, 1206
GRM31CR71A226ME15
Taiyo Yuden
LMK316AB7226KL-TR
AVX
1206ZC226KAT2A
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Murata
GRM21BR61C226ME44L
Taiyo Yuden
EMK212BBJ226MG-T
22µF, 10V, X5R, 1206
22µF, 16V, X5R, 0805
Output Capacitor Selection
The EN6347QI requires at least one 22µF 0805 case size ceramic output capacitor. Additional output
capacitors may be used in parallel near the load (>4mΩ away) to improve transient response as well as lower
output ripple. In some cases modifications to the compensation or output filter capacitance may be required
to optimize device performance such as transient response, ripple, or hold-up time. The EN6347QI provides
the capability to modify the control loop response to allow for customization for such applications. Note that
in Type III Voltage Mode Control, the double pole of the output filter is around 1/2π�LO ∙ Cout , where Cout is the
equivalent capacitance of all the output capacitors including the minimum required output capacitors that
Altera recommended and the extra bulk capacitors customers added based on their design requirement. While
the compensation network was designed based on the capacitors that Altera recommended, increasing the
output capacitance will shift the double pole to the direction of lower frequency, which will lower the loop
bandwidth and phase margin. In most cases, this will not cause the instability due to adequate phase margin
already in the design. In order to maintain a higher bandwidth as well as adequate phase margin, a slight
modification of the external compensation is necessary. This can be easily implemented by increasing the
leading capacitor value, Ca. In addition the ESR of the output capacitors also helps since the ESR and output
capacitance forms a zero which also helps to boost the phase.
Table 4. CA and Minimum ESR for Output Capacitors Ranges
Total COUT Range
Recommended CA
Min ESR
100µF to 250µF
27pF
0
250µF to 450µF
33pF
0
450µF to 1000µF
47pF
>4mΩ
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Table 5. Recommended Output Capacitors
Description
47µF, 6.3V, X7R, 1210
47uF, 6.3V, X5R, 1206
22µF, 10V, X7R, 1206
22 µF, 10V, X5R, 1206
22 µF, 10V, X5R, 0805
10µF, 10V, X7R, 0805
MFG
Murata
P/N
GRM32ER70J476ME20
Taiyo Yuden
LMK325B7476KM-TR
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK316BJ476ML-T
Murata
GRM31CR71A226ME15
Taiyo Yuden
LMK316AB7226KL-TR
AVX
1206ZC226KAT2A
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Murata
GRM219R61A226MEA0D
Taiyo Yuden
LMK212BJ226MG-T
Murata
GRM21BR71A106KE51
Taiyo Yuden
LMK212AB7106MG-T
AVX
0805ZC106KAT2A
Low ESR ceramic capacitors are required with X5R/X7R rated dielectric formulation. Y5V or equivalent
dielectric formulations must not be used as these lose too much capacitance with frequency, temperature and
bias voltage.
Output ripple voltage is determined by the aggregate output capacitor impedance. Output impedance,
denoted as Z, is comprised of effective series resistance, ESR, and effective series inductance, ESL:
Z = ESR + ESL
Placing output capacitors in parallel reduces the impedance and will hence result in lower PWM ripple voltage.
In addition, higher output capacitance will improve overall regulation and ripple in light-load mode.
1
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
For best LLM performance, we recommend using just 2x47µF capacitors mentioned in the above table, and no
10µF capacitor.
The VOUT sense point should be just after the last output filter capacitor right next to the device. Additional
bulk output capacitance beyond the above recommendations can be used on the output node of the
EN6347QI as long as the bulk capacitors are far enough from the VOUT sense point such that they don’t interfere
with the control loop operation.
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Table 6. Typical PWM Ripple Voltages
Output Capacitor
Configuration
Typical Output Ripple (mVp-p) (as
measured on EN6347QI Evaluation Board)*
1 x 47 µF
25
47 µF + 10 µF
14
* Note: 20 MHz BW limit
Power-Up Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before AVIN.
AVIN. Tying all three pins together meets these requirements.
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THERMAL CONSIDERATIONS
Thermal considerations are important power supply design facts that cannot be avoided in the real world.
Whenever there are power losses in a system, the heat that is generated by the power dissipation needs to be
accounted for. The Enpirion PowerSoC helps alleviate some of those concerns.
The Enpirion EN6347QI DC-DC converter is packaged in a 4x7x1.85mm 38-pin QFN package. The QFN
package is constructed with copper lead frames that have exposed thermal pads. The exposed thermal pad
on the package should be soldered directly on to a copper ground pad on the printed circuit board (PCB) to
act as a heat sink. The recommended maximum junction temperature for continuous operation is 125°C.
Continuous operation above 125°C may reduce long-term reliability. The device has a thermal overload
protection circuit designed to turn off the device at an approximate junction temperature value of 160°C.
The following example and calculations illustrate the thermal performance of the EN6347QI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 4A
First calculate the output power.
POUT = 3.3V x 4A = 13.2W
Next, determine the input power based on the efficiency (η) shown in Figure 8.
100
PWM Efficiency vs. IOUT (VIN = 5.0V)
90
EFFICIENCY (%)
80
~92%
70
60
50
40
30
20
CONDITIONS
VIN = 5V
10
0
0
0.5
1
1.5
2
VOUT = 3.3V
2.5
3
3.5
4
OUTPUT CURRENT (A)
Figure 8. Efficiency vs. Output Current
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For VIN = 5V, VOUT = 3.3V at 4A, η ≈ 92%
η = POUT / PIN = 92% = 0.92
PIN = POUT / η
PIN ≈ 13.2W / 0.92 ≈ 14.35W
The power dissipation (PD) is the power loss in the system and can be calculated by subtracting the output
power from the input power.
PD = PIN – POUT
≈ 14.35W – 13.2W ≈ 1.148W
With the power dissipation known, the temperature rise in the device may be estimated based on the theta JA
value (θJA). The θJA parameter estimates how much the temperature will rise in the device for every watt of
power dissipation. The EN6347QI has a θJA value of 30 °C/W without airflow.
Determine the change in temperature (ΔT) based on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 1.148W x 30°C/W = 34.43°C ≈ 35°C
The junction temperature (TJ) of the device is approximately the ambient temperature (TA) plus the change in
temperature. We assume the initial ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 35°C ≈ 60°C
The maximum operating junction temperature (TJMAX) of the device is 125°C, so the device can operate at a
higher ambient temperature. The maximum ambient temperature (TAMAX) allowed can be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 35°C ≈ 90°C
The maximum ambient temperature (before de-rating) the device can reach is 90°C given the input and output
conditions. Note that the efficiency will be slightly lower at higher temperatures and this calculation is an
estimate.
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APPLICATION CIRCUITS
Figure 9. Engineering Schematic with Engineering Notes
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LAYOUT RECOMMENDATIONS
Figure 9 shows critical components and layer 1 traces of a typical EN6347QI layout with ENABLE tied to VIN in
PWM mode. Alternate ENABLE configurations and other small signal pins need to be connected and routed
according to specific customer application. Please see the Gerber files on the Altera website
http://www.intel.com/enpirion for exact dimensions and other layers. Please refer to this Figure while reading
the layout recommendations in this section.
Figure 10. Top PCB Layer Critical Components and Copper for Minimum Footprint (Top View)
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EN6347QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EN6347QI should be as close to each other as possible so
that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: Three PGND pins are dedicated to the input circuit, and three to the output circuit. The
slit in Figure 10 separating the input and output GND circuits helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors. Please see the Gerber files on the Altera website http://www.intel.com/enpirion.
Recommendation 4: The large thermal pad underneath the component must be connected to the system
ground plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias
must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm.
Do not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the
path for heat dissipation from the converter.
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Recommendation 5: Multiple small vias (the same size as the thermal vias discussed in recommendation 4
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. It is preferred to put these vias under the capacitors along the edge of the GND copper closest to the
+V copper. Please see Figure 10. These vias connect the input/output filter capacitors to the GND plane, and
help reduce parasitic inductances in the input and output current loops. If the vias cannot be placed under CIN
and COUT, then put them just outside the capacitors along the GND slit separating the two components. Do not
use thermal reliefs or spokes to connect these vias to the ground plane.
Recommendation 6: AVIN is the power supply for the internal small-signal control circuits. It should be
connected to the input voltage at a quiet point. In Figure 10 this connection is made at the input capacitor
close to the VIN connection.
Recommendation 7: The layer 1 metal under the device must not be more than shown in Figure 10. See the
section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to
run sensitive signal or control lines underneath the converter package on other layers.
Recommendation 8: The VOUT sense point should be just after the last output filter capacitor. Keep the sense
trace as short as possible in order to avoid noise coupling into the control loop.
Recommendation 9: Keep RA, CA, and RB close to the VFB pin (see Figures 7). The VFB pin is a high-impedance,
sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the
AGND pin instead of going through the GND plane.
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DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 11.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN6347QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 11 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package.
Figure 11. Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Figure 12. EN6347QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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PACKAGE DIMENSIONS
Figure 13. EN6347QI Package Dimensions
Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html
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REVISION HISTORY
Rev
Date
Change(s)
J
April, 2018
Changed datasheet into Intel format.
K
August, 2018 Correct some typos
L
May, 2019
Correct some typos
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.altera.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
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