ACEX 1K
®
Programmable Logic Device Family
May 2003, ver. 3.4
Features...
Data Sheet
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Table 1. ACEXTM 1K Device Features
Feature
EP1K10
EP1K30
EP1K50
EP1K100
Typical gates
10,000
30,000
50,000
100,000
Maximum system gates
56,000
119,000
199,000
257,000
576
1,728
2,880
4,992
3
6
10
12
12,288
24,576
40,960
49,152
136
171
249
333
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
Altera Corporation
DS-ACEX-3.4
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Development
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Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
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Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
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Dual-port capability with up to 16-bit width per embedded array
block (EAB)
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Logic array for general logic functions
High density
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10,000 to 100,000 typical gates (see Table 1)
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Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
Cost-efficient programmable architecture for high-volume
applications
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Cost-optimized process
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Low cost solution for high-performance communications
applications
System-level features
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MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
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Low power consumption
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Bidirectional I/O performance (setup time [tSU] and clock-tooutput delay [tCO]) up to 250 MHz
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Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Extended temperature range
ACEX 1K Programmable Logic Device Family Data Sheet
...and More
Features
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2
-1 speed grade devices are compliant with PCI Local Bus
Specification, Revision 2.2 for 5.0-V operation
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Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
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Operate with a 2.5-V internal supply voltage
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In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
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ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
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Built-in, low-skew clock distribution trees
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100% functional testing of all devices; test vectors or scan chains
are not required
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Pull-up on I/O pins before and during configuration
Flexible interconnect
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FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
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Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
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Tri-state emulation that implements internal tri-state buses
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Up to six global clock signals and four global clear signals
Powerful I/O pins
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Individual tri-state output enable control for each pin
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Open-drain option on each I/O pin
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Programmable output slew-rate control to reduce switching
noise
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Clamp to VCCIO user-selectable on a pin-by-pin basis
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Supports hot-socketing
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
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Software design support and automatic place-and-route provided by
Altera development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Flexible package options are available in 100 to 484 pins, including
the innovative FineLine BGATM packages (see Tables 2 and 3)
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
DesignWare components, Verilog HDL, VHDL, and other interfaces
to popular EDA tools from manufacturers such as Cadence,
Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity,
VeriBest, and Viewlogic
Table 2. ACEX 1K Package Options & I/O Pin Count
Device
100-Pin TQFP
EP1K10
66
Notes (1), (2)
144-Pin TQFP
208-Pin PQFP
256-Pin
FineLine BGA
484-Pin
FineLine BGA
92
120
136
136 (3)
EP1K30
102
147
171
171 (3)
EP1K50
102
147
186
249
147
186
333
EP1K100
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(1)
(2)
(3)
ACEX 1K device package types include thin quad flat pack (TQFP), plastic quad flat pack (PQFP), and FineLine
BGA packages.
Devices in the same package are pin-compatible, although some devices have more I/O pins than others. When
planning device migration, use the I/O pins that are common to all devices.
This option is supported with a 256-pin FineLine BGA package. By using SameFrameTM pin migration, all FineLine
BGA packages are pin-compatible. For example, a board can be designed to support 256-pin and 484-pin FineLine
BGA packages.
Table 3. ACEX 1K Package Sizes
Device
100-Pin TQFP
144-Pin TQFP
208-Pin PQFP
Pitch (mm)
0.50
0.50
0.50
1.0
1.0
Area (mm2)
256
484
936
289
529
16 × 16
22 × 22
30.6 × 30.6
17 × 17
23 × 23
Length × width
(mm × mm)
Altera Corporation
256-Pin
FineLine BGA
484-Pin
FineLine BGA
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Notes:
ACEX 1K Programmable Logic Device Family Data Sheet
General
Description
Altera® ACEX 1K devices provide a die-efficient, low-cost architecture by
combining look-up table (LUT) architecture with EABs. LUT-based logic
provides optimized performance and efficiency for data-path, register
intensive, mathematical, or digital signal processing (DSP) designs, while
EABs implement RAM, ROM, dual-port RAM, or first-in first-out (FIFO)
functions. These elements make ACEX 1K suitable for complex logic
functions and memory functions such as digital signal processing, wide
data-path manipulation, data transformation and microcontrollers, as
required in high-performance communications applications. Based on
reconfigurable CMOS SRAM elements, the ACEX 1K architecture
incorporates all features necessary to implement common gate array
megafunctions, along with a high pin count to enable an effective interface
with system components. The advanced process and the low voltage
requirement of the 2.5-V core allow ACEX 1K devices to meet the
requirements of low-cost, high-volume applications ranging from DSL
modems to low-cost switches.
The ability to reconfigure ACEX 1K devices enables complete testing prior
to shipment and allows the designer to focus on simulation and design
verification. ACEX 1K device reconfigurability eliminates inventory
management for gate array designs and test vector generation for fault
coverage.
Table 4 shows ACEX 1K device performance for some common designs.
All performance results were obtained with Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 4. ACEX 1K Device Performance
Application
Resources
Used
Performance
LEs
EABs
Speed Grade
Units
-1
-2
-3
16-bit loadable counter
16
0
285
232
185
MHz
16-bit accumulator
16
0
285
232
185
MHz
16-to-1 multiplexer (1)
10
0
3.5
4.5
6.6
ns
16-bit multiplier with 3-stage pipeline(2)
592
0
156
131
93
MHz
256 × 16 RAM read cycle speed (2)
0
1
278
196
143
MHz
256 × 16 RAM write cycle speed (2)
0
1
185
143
111
MHz
Notes:
(1)
(2)
4
This application uses combinatorial inputs and outputs.
This application uses registered inputs and outputs.
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Table 5 shows ACEX 1K device performance for more complex designs.
These designs are available as Altera MegaCoreTM functions.
Table 5. ACEX 1K Device Performance for Complex Designs
Application
16-bit, 8-tap parallel finite impulse response (FIR)
filter
8-bit, 512-point Fast Fourier transform (FFT)
function
a16450 universal asynchronous
receiver/transmitter (UART)
LEs
Used
Performance
Speed Grade
Units
-1
-2
-3
597
192
156
116
1,854
23.4
28.7
38.9
µs
113
92
68
MHz
36
28
20.5
MHz
342
MSPS
ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cables. After
an ACEX 1K device has been configured, it can be reconfigured in-circuit
by resetting the device and loading new data. Because reconfiguration
requires less than 40 ms, real-time changes can be made during system
operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it by writing to a virtual
memory location, simplifying device reconfiguration.
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Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and datatransformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K Programmable Logic Device Family Data Sheet
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For more information on the configuration of ACEX 1K devices, see the
following documents:
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Configuration Devices for ACEX, APEX, FLEX, & Mercury Devices Data
Sheet
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
BitBlaster Serial Download Cable Data Sheet
ACEX 1K devices are supported by Altera development systems, which
are integrated packages that offer schematic, text (including AHDL), and
waveform design entry, compilation and logic synthesis, full simulation
and worst-case timing analysis, and device configuration. The software
provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other
interfaces for additional design entry and simulation support from other
industry-standard PC- and UNIX workstation-based EDA tools.
The Altera software works easily with common gate array EDA tools for
synthesis and simulation. For example, the Altera software can generate
Verilog HDL files for simulation with tools such as Cadence Verilog-XL.
Additionally, the Altera software contains EDA libraries that use devicespecific features such as carry chains, which are used for fast counter and
arithmetic functions. For instance, the Synopsys Design Compiler library
supplied with the Altera development system includes DesignWare
functions that are optimized for the ACEX 1K device architecture.
The Altera development systems run on Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations.
f
Functional
Description
For more information, see the MAX+PLUS II Programmable Logic
Development System & Software Data Sheet and the Quartus Programmable
Logic Development System & Software Data Sheet.
Each ACEX 1K device contains an enhanced embedded array that
implements memory and specialized logic functions, and a logic array
that implements general logic.
The embedded array consists of a series of EABs. When implementing
memory functions, each EAB provides 4,096 bits, which can be used to
create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions.
When implementing logic, each EAB can contribute 100 to 600 gates
towards complex logic functions such as multipliers, microcontrollers,
state machines, and DSP functions. EABs can be used independently, or
multiple EABs can be combined to implement larger functions.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
The logic array consists of logic array blocks (LABs). Each LAB contains
eight LEs and a local interconnect. An LE consists of a 4-input LUT, a
programmable flipflop, and dedicated signal paths for carry and cascade
functions. The eight LEs can be used to create medium-sized blocks of
logic—such as 8-bit counters, address decoders, or state machines—or
combined across LABs to create larger logic blocks. Each LAB represents
about 96 usable logic gates.
Signal interconnections within ACEX 1K devices (as well as to and from
device pins) are provided by the FastTrack Interconnect routing structure,
which is a series of fast, continuous row and column channels that run the
entire length and width of the device.
Figure 1 shows a block diagram of the ACEX 1K device architecture. Each
group of LEs is combined into an LAB; groups of LABs are arranged into
rows and columns. Each row also contains a single EAB. The LABs and
EABs are interconnected by the FastTrack Interconnect routing structure.
IOEs are located at the end of each row and column of the FastTrack
Interconnect routing structure.
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Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect routing structure. Each IOE
contains a bidirectional I/O buffer and a flipflop that can be used as either
an output or input register to feed input, output, or bidirectional signals.
When used with a dedicated clock pin, these registers provide exceptional
performance. As inputs, they provide setup times as low as 1.1 ns and
hold times of 0 ns. As outputs, these registers provide clock-to-output
times as low as 2.5 ns. IOEs provide a variety of features, such as JTAG
BST support, slew-rate control, tri-state buffers, and open-drain outputs.
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 1. ACEX 1K Device Block Diagram
Embedded Array Block (EAB)
I/O Element
(IOE)
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Column
Interconnect
Logic Array
EAB
Logic Array
Block (LAB)
IOE
IOE
IOE
IOE
Logic Element (LE)
Row
Interconnect
EAB
Local Interconnect
Logic
Array
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Embedded Array
ACEX 1K devices provide six dedicated inputs that drive the flipflops’
control inputs and ensure the efficient distribution of high-speed, lowskew (less than 1.0 ns) control signals. These signals use dedicated routing
channels that provide shorter delays and lower skews than the FastTrack
Interconnect routing structure. Four of the dedicated inputs drive four
global signals. These four global signals can also be driven by internal
logic, providing an ideal solution for a clock divider or an internally
generated asynchronous clear signal that clears many registers in the
device.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Embedded Array Block
The EAB is a flexible block of RAM, with registers on the input and output
ports, that is used to implement common gate array megafunctions.
Because it is large and flexible, the EAB is suitable for functions such as
multipliers, vector scalars, and error correction circuits. These functions
can be combined in applications such as digital filters and
microcontrollers.
Logic functions are implemented by programming the EAB with a readonly pattern during configuration, thereby creating a large LUT. With
LUTs, combinatorial functions are implemented by looking up the results
rather than by computing them. This implementation of combinatorial
functions can be faster than using algorithms implemented in general
logic, a performance advantage that is further enhanced by the fast access
times of EABs. The large capacity of EABs enables designers to implement
complex functions in a single logic level without the routing delays
associated with linked LEs or field-programmable gate array (FPGA)
RAM blocks. For example, a single EAB can implement any function with
8 inputs and 16 outputs. Parameterized functions, such as LPM functions,
can take advantage of the EAB automatically.
The EAB can also be used for bidirectional, dual-port memory
applications where two ports read or write simultaneously. To implement
this type of dual-port memory, two EABs are used to support two
simultaneous reads or writes.
Alternatively, one clock and clock enable can be used to control the input
registers of the EAB, while a different clock and clock enable control the
output registers (see Figure 2).
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The ACEX 1K enhanced EAB supports dual-port RAM. The dual-port
structure is ideal for FIFO buffers with one or two clocks. The ACEX 1K
EAB can also support up to 16-bit-wide RAM blocks. The ACEX 1K EAB
can act in dual-port or single-port mode. When in dual-port mode,
separate clocks may be used for EAB read and write sections, allowing the
EAB to be written and read at different rates. It also has separate
synchronous clock enable signals for the EAB read and write sections,
which allow independent control of these sections.
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ACEX 1K Programmable Logic Device Family Data Sheet
Figure 2. ACEX 1K Device in Dual-Port RAM Mode
Note (1)
Dedicated Inputs &
Global Signals
Dedicated Clocks
Row Interconnect
2
RAM/ROM
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
4
data[ ]
D
Q
ENA
Data Out
4, 8, 16, 32
D
ENA
rdaddress[ ]
EAB Local
Interconnect (2)
4, 8
Read Address
D
Q
ENA
wraddress[ ]
Write Address
D
rden
Q
Q
4, 8, 16, 32
ENA
Read Enable
wren
D
Q
ENA
outclocken
Write Enable
inclocken
D
ENA
inclock
outclock
Q
Write
Pulse
Generator
Multiplexers allow read
address and read
enable registers to be
clocked by inclock or
outclock signals.
Column Interconnect
Notes:
(1)
(2)
All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset.
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
The EAB can use Altera megafunctions to implement dual-port RAM
applications where both ports can read or write, as shown in Figure 3. The
ACEX 1K EAB can also be used in a single-port mode (see Figure 4).
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 3. ACEX 1K EAB in Dual-Port RAM Mode
Port A
Port B
address_a[]
address_b[]
data_a[]
data_b[]
we_a
we_b
clkena_a
clkena_b
Clock A
Clock B
Figure 4. ACEX 1K Device in Single-Port RAM Mode
Dedicated Inputs
& Global Signals
Dedicated
Clocks
Chip-Wide
Reset
Row Interconnect
13
4
D
Q
8, 4, 2, 1
EAB Local
Interconnect (1)
4, 8, 16, 32
RAM/ROM
256 × 16
512 × 8
Data In
1,024 × 4
2,048 × 2
Data Out
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2
D
Q
4, 8
Address
D
Q
8, 9, 10, 11
4, 8, 16, 32
Write Enable
D
Q
Column Interconnect
Note:
(1)
EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
Altera Corporation
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ACEX 1K Programmable Logic Device Family Data Sheet
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB’s self-timed RAM must only meet the setup
and hold time specifications of the global clock.
When used as RAM, each EAB can be configured in any of the following
sizes: 256 × 16; 512 × 8; 1,024 × 4; or 2,048 × 2. Figure 5 shows the ACEX 1K
EAB memory configurations.
Figure 5. ACEX 1K EAB Memory Configurations
256 × 16
512 × 8
1,024 × 4
2,048 × 2
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 × 16 RAM blocks can be combined to form a 256 × 32
block, and two 512 × 8 RAM blocks can be combined to form a
512 × 16 block. Figure 6 shows examples of multiple EAB combination.
Figure 6. Examples of Combining ACEX 1K EABs
256 × 32
512 × 16
256 × 16
512 × 8
256 × 16
512 × 8
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera software automatically combines EABs
to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive
write-enable, read-enable, and clock-enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write-enable, read-enable, clear, clock, and clock-enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outputs (see Figures 2 and 4). The column interconnect, which is adjacent
to the EAB, has twice as many channels as other columns in the device.
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the ACEX 1K architecture, facilitating
efficient routing with optimum device utilization and high performance.
Figure 7 shows the ACEX 1K LAB.
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Logic Array Block
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ACEX 1K Programmable Logic Device Family Data Sheet
Figure 7. ACEX 1K LAB
Dedicated Inputs &
Global Signals
(1)
Row Interconnect
6
LAB Local
Interconnect (2)
16
6
See Figure 13
for details.
4
LAB Control
Signals
4
Carry-In &
Cascade-In
2
4
LE1
4
LE2
4
LE3
4
LE4
4
LE5
4
LE6
4
LE7
4
LE8
8
2
8
24
Column-to-Row
Interconnect
Column
Interconnect
8
16
Carry-Out &
Cascade-Out
Notes:
(1)
(2)
EP1K10, EP1K30, and EP1K50 devices have 22 inputs to the LAB local interconnect channel from the row; EP1K100
devices have 26.
EP1K10, EP1K30, and EP1K50 devices have 30 LAB local interconnect channels; EP1K100 devices have 34.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LEs
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
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The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-input LUT, which is a function generator that can quickly compute any
function of four variables. In addition, each LE contains a programmable
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interconnect
routing structure. Figure 8 shows the ACEX 1K LE.
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 8. ACEX 1K Logic Element
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry-In
Cascade-In
Carry
Chain
Cascade
Chain
Register Bypass
D
PRN
Q
Programmable
Register
To FastTrack
Interconnect
ENA
CLRN
To LAB Local
Interconnect
labctrl1
labctrl2
Clear/
Preset
Logic
Chip-Wide
Reset
Clock
Select
labctrl3
labctrl4
Carry-Out
Cascade-Out
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock, clear, and preset control signals on the flipflop can
be driven by global signals, general-purpose I/O pins, or any internal
logic. For combinatorial functions, the flipflop is bypassed and the LUT’s
output drives the LE’s output.
The LE has two outputs that drive the interconnect: one drives the local
interconnect, and the other drives either the row or column FastTrack
Interconnect routing structure. The two outputs can be controlled
independently. For example, the LUT can drive one output while the
register drives the other output. This feature, called register packing, can
improve LE utilization because the register and the LUT can be used for
unrelated functions.
The ACEX 1K architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. The carry chain supports highspeed counters and adders, and the cascade chain implements wide-input
functions with minimum delay. Carry and cascade chains connect all LEs
in a LAB and all LABs in the same row. Intensive use of carry and cascade
chains can reduce routing flexibility. Therefore, the use of these chains
should be limited to speed-critical portions of a design.
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Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Carry Chain
The carry chain provides a very fast (as low as 0.2 ns) carry-forward
function between LEs. The carry-in signal from a lower-order bit drives
forward into the higher-order bit via the carry chain, and feeds into both
the LUT and the next portion of the carry chain. This feature allows the
ACEX 1K architecture to efficiently implement high-speed counters,
adders, and comparators of arbitrary width. Carry chain logic can be
created automatically by the compiler during design processing, or
manually by the designer during design entry. Parameterized functions,
such as LPM and DesignWare functions, automatically take advantage of
carry chains.
Figure 9 shows how an n-bit full adder can be implemented in n + 1 LEs
with the carry chain. One portion of the LUT generates the sum of two bits
using the input signals and the carry-in signal; the sum is routed to the
output of the LE. The register can be bypassed for simple adders or used
for an accumulator function. Another portion of the LUT and the carry
chain logic generates the carry-out signal, which is routed directly to the
carry-in signal of the next-higher-order bit. The final carry-out signal is
routed to an LE, where it can be used as a general-purpose signal.
Altera Corporation
17
13
Development
Tools
Carry chains longer than eight LEs are automatically implemented by
linking LABs together. For enhanced fitting, a long carry chain skips
alternate LABs in a row. A carry chain longer than one LAB skips either
from even-numbered LAB to even-numbered LAB, or from oddnumbered LAB to odd-numbered LAB. For example, the last LE of the
first LAB in a row carries to the first LE of the third LAB in the row. The
carry chain does not cross the EAB at the middle of the row. For instance,
in the EP1K50 device, the carry chain stops at the eighteenth LAB, and a
new carry chain begins at the nineteenth LAB.
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 9. ACEX 1K Carry Chain Operation (n-Bit Full Adder)
Carry-In
a1
b1
LUT
s1
Register
Carry Chain
LE1
a2
b2
LUT
s2
Register
Carry Chain
LE2
an
bn
LUT
sn
Register
Carry Chain
LEn
LUT
Register
Carry-Out
Carry Chain
LEn + 1
18
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Cascade Chain
With the cascade chain, the ACEX 1K architecture can implement
functions that have a very wide fan-in. Adjacent LUTs can be used to
compute portions of the function in parallel; the cascade chain serially
connects the intermediate values. The cascade chain can use a logical AND
or logical OR (via De Morgan’s inversion) to connect the outputs of
adjacent LEs. With a delay as low as 0.6 ns per LE, each additional LE
provides four more inputs to the effective width of a function. Cascade
chain logic can be created automatically by the compiler during design
processing, or manually by the designer during design entry.
Cascade chains longer than eight bits are implemented automatically by
linking several LABs together. For easier routing, a long cascade chain
skips every other LAB in a row. A cascade chain longer than one LAB
skips either from even-numbered LAB to even-numbered LAB, or from
odd-numbered LAB to odd-numbered LAB (e.g., the last LE of the first
LAB in a row cascades to the first LE of the third LAB). The cascade chain
does not cross the center of the row (e.g., in the EP1K50 device, the cascade
chain stops at the eighteenth LAB, and a new one begins at the nineteenth
LAB). This break is due to the EAB’s placement in the middle of the row.
13
Figure 10 shows how the cascade function can connect adjacent LEs to
form functions with a wide fan-in. These examples show functions of 4n
variables implemented with n LEs. The LE delay is 1.3 ns; the cascade
chain delay is 0.6 ns. With the cascade chain, decoding a 16-bit address
requires 3.1 ns.
Development
Tools
Figure 10. ACEX 1K Cascade Chain Operation
AND Cascade Chain
d[3..0]
OR Cascade Chain
d[3..0]
LUT
LUT
LE1
d[7..4]
LE1
d[7..4]
LUT
LUT
LE2
d[(4n – 1)..(4n – 4)]
d[(4n – 1)..(4n – 4)]
LUT
LEn
Altera Corporation
LE2
LUT
LEn
19
ACEX 1K Programmable Logic Device Family Data Sheet
LE Operating Modes
The ACEX 1K LE can operate in the following four modes:
■
■
■
■
Normal mode
Arithmetic mode
Up/down counter mode
Clearable counter mode
Each of these modes uses LE resources differently. In each mode, seven
available inputs to the LE—the four data inputs from the LAB local
interconnect, the feedback from the programmable register, and the
carry-in and cascade-in from the previous LE—are directed to different
destinations to implement the desired logic function. Three inputs to the
LE provide clock, clear, and preset control for the register. The Altera
software, in conjunction with parameterized functions such as LPM and
DesignWare functions, automatically chooses the appropriate mode for
common functions such as counters, adders, and multipliers. If required,
the designer can also create special-purpose functions that use a specific
LE operating mode for optimal performance.
The architecture provides a synchronous clock enable to the register in all
four modes. The Altera software can set DATA1 to enable the register
synchronously, providing easy implementation of fully synchronous
designs.
Figure 11 shows the ACEX 1K LE operating modes.
20
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 11. ACEX 1K LE Operating Modes
Normal Mode
Cascade-In
Carry-In
LE-Out to FastTrack
Interconnect
data1
data2
4-Input
LUT
data3
D
PRN
Q
LE-Out to Local
Interconnect
ENA
CLRN
data4
Cascade-Out
Arithmetic Mode
Carry-In
Cascade-In
LE-Out
data1
data2
D
3-Input
LUT
PRN
Q
13
ENA
CLRN
Development
Tools
3-Input
LUT
Cascade-Out
Carry-Out
Up/Down Counter Mode
Cascade-In
Carry-In
data1 (ena)
data2 (u/d)
3-Input
LUT
1
D
PRN
Q
LE-Out
0
data3 (data)
ENA
CLRN
3-Input
LUT
data4 (nload)
Carry-Out
Cascade-Out
Clearable Counter Mode
Carry-In
data1 (ena)
data2 (nclr)
3-Input
LUT
D
1
PRN
Q
LE-Out
0
data3 (data)
ENA
CLRN
3-Input
LUT
data4 (nload)
Altera Corporation
Carry-Out
Cascade-Out
21
ACEX 1K Programmable Logic Device Family Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a 4-input LUT. The compiler automatically selects the carryin or the DATA3 signal as one of the inputs to the LUT. The LUT output
can be combined with the cascade-in signal to form a cascade chain
through the cascade-out signal. Either the register or the LUT can be used
to drive both the local interconnect and the FastTrack Interconnect routing
structure at the same time.
The LUT and the register in the LE can be used independently (register
packing). To support register packing, the LE has two outputs; one drives
the local interconnect, and the other drives the FastTrack Interconnect
routing structure. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a 3-input function can be computed in the LUT, and a
fourth independent signal can be registered. Alternatively, a 4-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers two 3-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a 3-input function; the other generates a carry output. As shown
in Figure 11, the first LUT uses the carry-in signal and two data inputs
from the LAB local interconnect to generate a combinatorial or registered
output. For example, in an adder, this output is the sum of three signals:
a, b, and carry-in. The second LUT uses the same three signals to generate
a carry-out signal, thereby creating a carry chain. The arithmetic mode
also supports simultaneous use of the cascade chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Two 3-input LUTs are used; one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals without using the LUT resources.
22
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Clearable Counter Mode
The clearable counter mode is similar to the up/down counter mode, but
it supports a synchronous clear instead of the up/down control. The clear
function is substituted for the cascade-in signal in the up/down counter
mode. Two 3-input LUTs are used; one generates the counter data, and the
other generates the fast carry bit. Synchronous loading is provided by a
2-to-1 multiplexer. The output of this multiplexer is AND ed with a
synchronous clear signal.
Internal Tri-State Emulation
Internal tri-state emulation provides internal tri-states without the
limitations of a physical tri-state bus. In a physical tri-state bus, the
tri-state buffers’ output enable (OE) signals select which signal drives the
bus. However, if multiple OE signals are active, contending signals can be
driven onto the bus. Conversely, if no OE signals are active, the bus will
float. Internal tri-state emulation resolves contending tri-state buffers to a
low value and floating buses to a high value, thereby eliminating these
problems. The Altera software automatically implements tri-state bus
functionality with a multiplexer.
Logic for the programmable register’s clear and preset functions is
controlled by the DATA3, LABCTRL1, and LABCTRL2 inputs to the LE. The
clear and preset control structure of the LE asynchronously loads signals
into a register. Either LABCTRL1 or LABCTRL2 can control the
asynchronous clear. Alternatively, the register can be set up so that
LABCTRL1 implements an asynchronous load. The data to be loaded is
driven to DATA3; when LABCTRL1 is asserted, DATA3 is loaded into the
register.
During compilation, the compiler automatically selects the best control
signal implementation. Because the clear and preset functions are activelow, the Compiler automatically assigns a logic high to an unused clear or
preset.
The clear and preset logic is implemented in one of the following six
modes chosen during design entry:
■
■
■
■
■
■
Altera Corporation
Asynchronous clear
Asynchronous preset
Asynchronous clear and preset
Asynchronous load with clear
Asynchronous load with preset
Asynchronous load without clear or preset
23
Development
Tools
Clear & Preset Logic Control
13
ACEX 1K Programmable Logic Device Family Data Sheet
In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset. Figure 12 shows examples
of how to setup the preset and clear inputs for the desired functionality.
Figure 12. ACEX 1K LE Clear & Preset Modes
Asynchronous Clear
Asynchronous Preset
Asynchronous Preset & Clear
labctrl1
VCC
PRN
D
Q
Chip-Wide Reset
labctrl1 or
labctrl2
D
D
labctrl1 or
labctrl2
Chip-Wide Reset
PRN
Q
PRN
Q
CLRN
CLRN
labctrl2
Chip-Wide Reset
CLRN
VCC
Asynchronous Load without Clear or Preset
Asynchronous Load with Clear
NOT
NOT
labctrl1
(Asynchronous
Load)
labctrl1
(Asynchronous
Load)
data3
(Data)
D
NOT
PRN
Q
data3
(Data)
D
CLRN
CLRN
labctrl2
(Clear)
Chip-Wide Reset
PRN
Q
NOT
Chip-Wide Reset
Asynchronous Load with Preset
NOT
labctrl1
(Asynchronous
Load)
labctrl2
(Preset)
D
PRN
Q
data3
(Data)
CLRN
NOT
Chip-Wide Reset
24
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Asynchronous Clear
The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this
mode, the preset signal is tied to VCC to deactivate it.
Asynchronous Preset
An asynchronous preset is implemented as an asynchronous load, or with
an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1
asynchronously loads a one into the register. Alternatively, the Altera
software can provide preset control by using the clear and inverting the
register’s input and output. Inversion control is available for the inputs to
both LEs and IOEs. Therefore, if a register is preset by only one of the two
LABCTRL signals, the DATA3 input is not needed and can be used for one
of the LE operating modes.
Asynchronous Preset & Clear
When implementing asynchronous clear and preset, LABCTRL1 controls
the preset, and LABCTRL2 controls the clear. DATA3 is tied to VCC, so that
asserting LABCTRL1 asynchronously loads a one into the register,
effectively presetting the register. Asserting LABCTRL2 clears the register.
When implementing an asynchronous load in conjunction with the clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear. LABCTRL2 implements the clear by
controlling the register clear; LABCTRL2 does not have to feed the preset
circuits.
Asynchronous Load with Preset
When implementing an asynchronous load in conjunction with preset, the
Altera software provides preset control by using the clear and inverting
the input and output of the register. Asserting LABCTRL2 presets the
register, while asserting LABCTRL1 loads the register. The Altera software
inverts the signal that drives DATA3 to account for the inversion of the
register’s output.
Asynchronous Load without Preset or Clear
When implementing an asynchronous load without preset or clear,
LABCTRL1 implements the asynchronous load of DATA3 by controlling
the register preset and clear.
Altera Corporation
25
Development
Tools
Asynchronous Load with Clear
13
ACEX 1K Programmable Logic Device Family Data Sheet
FastTrack Interconnect Routing Structure
In the ACEX 1K architecture, connections between LEs, EABs, and device
I/O pins are provided by the FastTrack Interconnect routing structure,
which is a series of continuous horizontal and vertical routing channels
that traverse the device. This global routing structure provides
predictable performance, even in complex designs. In contrast, the
segmented routing in FPGAs requires switch matrices to connect a
variable number of routing paths, increasing the delays between logic
resources and reducing performance.
The FastTrack Interconnect routing structure consists of row and column
interconnect channels that span the entire device. Each row of LABs is
served by a dedicated row interconnect. The row interconnect can drive
I/O pins and feed other LABs in the row. The column interconnect routes
signals between rows and can drive I/O pins.
Row channels drive into the LAB or EAB local interconnect. The row
signal is buffered at every LAB or EAB to reduce the effect of fan-out on
delay. A row channel can be driven by an LE or by one of three column
channels. These four signals feed dual 4-to-1 multiplexers that connect to
two specific row channels. These multiplexers, which are connected to
each LE, allow column channels to drive row channels even when all eight
LEs in a LAB drive the row interconnect.
Each column of LABs or EABs is served by a dedicated column
interconnect. The column interconnect that serves the EABs has twice as
many channels as other column interconnects. The column interconnect
can then drive I/O pins or another row’s interconnect to route the signals
to other LABs or EABs in the device. A signal from the column
interconnect, which can be either the output of a LE or an input from an
I/O pin, must be routed to the row interconnect before it can enter a LAB
or EAB. Each row channel that is driven by an IOE or EAB can drive one
specific column channel.
Access to row and column channels can be switched between LEs in
adjacent pairs of LABs. For example, a LE in one LAB can drive the row
and column channels normally driven by a particular LE in the adjacent
LAB in the same row, and vice versa. This flexibility enables routing
resources to be used more efficiently. Figure 13 shows the ACEX 1K LAB.
26
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 13. ACEX 1K LAB Connections to Row & Column Interconnect
Column
Channels
To Other
Columns
Row Channels
At each intersection,
six row channels can
drive column channels.
13
From Adjacent LAB
To Adjacent LAB
LE 1
Each LE can switch
interconnect access
with an LE in the
adjacent LAB.
LE 2
LE 8
To LAB Local
Interconnect
Altera Corporation
To Other Rows
27
Development
Tools
Each LE can drive two
row channels.
ACEX 1K Programmable Logic Device Family Data Sheet
For improved routing, the row interconnect consists of a combination of
full-length and half-length channels. The full-length channels connect to
all LABs in a row; the half-length channels connect to the LABs in half of
the row. The EAB can be driven by the half-length channels in the left half
of the row and by the full-length channels. The EAB drives out to the fulllength channels. In addition to providing a predictable, row-wide
interconnect, this architecture provides increased routing resources. Two
neighboring LABs can be connected using a half-row channel, thereby
saving the other half of the channel for the other half of the row.
Table 6 summarizes the FastTrack Interconnect routing structure
resources available in each ACEX 1K device.
Table 6. ACEX 1K FastTrack Interconnect Resources
Device
Rows
Channels per
Row
Columns
Channels per
Column
EP1K10
3
144
24
24
EP1K30
6
216
36
24
EP1K50
10
216
36
24
EP1K100
12
312
52
24
In addition to general-purpose I/O pins, ACEX 1K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output-enable and clock-enable control signals. These signals
are available as control signals for all LABs and IOEs in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Figure 14 shows the interconnection of adjacent LABs and EABs, with
row, column, and local interconnects, as well as the associated cascade
and carry chains. Each LAB is labeled according to its location: a letter
represents the row and a number represents the column. For example,
LAB B3 is in row B, column 3.
28
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 14. ACEX 1K Interconnect Resources
See Figure 17
for details.
I/O Element (IOE)
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
Row
Interconnect
LAB
A1
LAB
A2
See Figure 16
for details.
LAB
A3
Column
Interconnect
To LAB A5
To LAB A4
IOE
IOE
IOE
IOE
LAB
B2
Development
Tools
LAB
B1
13
Cascade &
Carry Chains
LAB
B3
To LAB B5
To LAB B4
IOE
IOE
IOE
IOE
IOE
IOE
I/O Element
An IOE contains a bidirectional I/O buffer and a register that can be used
either as an input register for external data that requires a fast setup time
or as an output register for data that requires fast clock-to-output
performance. In some cases, using an LE register for an input register will
result in a faster setup time than using an IOE register. IOEs can be used
as input, output, or bidirectional pins. The compiler uses the
programmable inversion option to invert signals from the row and
column interconnect automatically where appropriate. For bidirectional
registered I/O implementation, the output register should be in the IOE
and the data input and output enable registers should be LE registers
placed adjacent to the bidirectional pin. Figure 15 shows the bidirectional
I/O registers.
Altera Corporation
29
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 15. ACEX 1K Bidirectional I/O Registers
Row and Column
Interconnect
2 Dedicated
Clock Inputs
4 Dedicated
Inputs
Peripheral
Control Bus
2
4
OE Register
12
D
Q
ENA
CLRN
VCC
Chip-Wide
Reset
VCC
Chip-Wide
Output Enable
OE[7..0]
Programmable Delay
VCC
Output Register
D
Q
CLK[1..0]
ENA
CLRN
CLK[3..2]
VCC
Open-Drain
Output
Slew-Rate
Control
ENA[5..0]
VCC
CLRN[1..0]
Chip-Wide
Reset
Input Register
D
Q
VCC
ENA
CLRN
Chip-Wide
Reset
30
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
On all ACEX 1K devices, the input path from the I/O pad to the FastTrack
Interconnect has a programmable delay element that can be used to
guarantee a zero hold time. Depending on the placement of the IOE
relative to what it is driving, the designer may choose to turn on the
programmable delay to ensure a zero hold time or turn it off to minimize
setup time. This feature is used to reduce setup time for complex pin-toregister paths (e.g., PCI designs).
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices and provides up to 12 peripheral control signals that
can be allocated as follows:
■
■
■
■
Up to eight output enable signals
Up to six clock enable signals
Up to two clock signals
Up to two clear signals
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE uses the inverted clock, all IOEs must use the inverted
clock, and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on an LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive all IOEs. For the true and complement of a clock to be used to drive
IOEs, drive it into both global clock pins. One global clock pin will supply
the true, and the other will supply the complement.
When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.
Altera Corporation
31
13
Development
Tools
If more than six clock-enable or eight output-enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chipwide reset signal resets all IOE registers, overriding any other control
signals.
ACEX 1K Programmable Logic Device Family Data Sheet
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7 lists the sources for each peripheral control signal and shows how
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals. Table 7 also shows the rows that can drive
global signals.
Table 7. Peripheral Bus Sources for ACEX Devices
EP1K10
EP1K30
EP1K50
EP1K100
OE0
Peripheral Control Signal
Row A
Row A
Row A
Row A
OE1
Row A
Row B
Row B
Row C
OE2
Row B
Row C
Row D
Row E
OE3
Row B
Row D
Row F
Row L
OE4
Row C
Row E
Row H
Row I
OE5
Row C
Row F
Row J
Row K
CLKENA0/CLK0/GLOBAL0
Row A
Row A
Row A
Row F
CLKENA1/OE6/GLOBAL1
Row A
Row B
Row C
Row D
CLKENA2/CLR0
Row B
Row C
Row E
Row B
CLKENA3/OE7/GLOBAL2
Row B
Row D
Row G
Row H
CLKENA4/CLR1
Row C
Row E
Row I
Row J
CLKENA5/CLK1/GLOBAL3
Row C
Row F
Row J
Row G
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-high pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
32
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see Figure 16).
Figure 16. ACEX 1K Row-to-IOE Connections
Note (1)
IOE1
m
Row FastTrack
Interconnect
n
n
n
IOE8
m
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Development
Tools
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive two
row channels.
Note:
(1)
The values for m and n are shown in Table 8.
Table 8 lists the ACEX 1K row-to-IOE interconnect resources.
Table 8. ACEX 1K Row-to-IOE Interconnect Resources
Device
Altera Corporation
Channels per Row (n)
Row Channels per Pin (m)
EP1K10
144
18
EP1K30
216
27
EP1K50
216
27
EP1K100
312
39
33
ACEX 1K Programmable Logic Device Family Data Sheet
Column-to-IOE Connections
When an IOE is used as an input, it can drive up to two separate column
channels. When an IOE is used as an output, the signal is driven by a
multiplexer that selects a signal from the column channels. Two IOEs
connect to each side of the column channels. Each IOE can be driven by
column channels via a multiplexer. The set of column channels is different
for each IOE (see Figure 17).
Figure 17. ACEX 1K Column-to-IOE Connections
Note (1)
Each IOE is driven by
a m-to-1 multiplexer
Column
Interconnect
m
IOE1
m
IOE1
n
n
n
Each IOE can drive two
column channels.
Note:
(1)
The values for m and n are shown in Table 9.
Table 9 lists the ACEX 1K column-to-IOE interconnect resources.
Table 9. ACEX 1K Column-to-IOE Interconnect Resources
Device
34
Channels per Column (n)
Column Channels per Pin (m)
EP1K10
24
16
EP1K30
24
16
EP1K50
24
16
EP1K100
24
16
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
SameFrame
Pin-Outs
ACEX 1K devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ballcount packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EP1K10 device in a 256-pin
FineLine BGA package to an EP1K100 device in a 484-pin FineLine BGA
package.
The Altera software provides support to design PCBs with SameFrame
pin-out devices. Devices can be defined for present and future use. The
Altera software generates pin-outs describing how to lay out a board that
takes advantage of this migration. Figure 18 shows an example of
SameFrame pin-out.
Figure 18. SameFrame Pin-Out Example
13
Development
Tools
Printed Circuit Board
Designed for 484-Pin FineLine BGA Package
256-Pin
FineLine
BGA
256-Pin FineLine BGA Package
(Reduced I/O Count or
Logic Requirements)
484-Pin
FineLine
BGA
484-Pin FineLine BGA Package
(Increased I/O Count or
Logic Requirements)
Table 10 shows the ACEX 1K device/package combinations that support
SameFrame pin-outs for ACEX 1K devices. All FineLine BGA packages
support SameFrame pin-outs, providing the flexibility to migrate not only
from device to device within the same package, but also from one package
to another. The I/O count will vary from device to device.
Altera Corporation
35
ACEX 1K Programmable Logic Device Family Data Sheet
f
For more information, search for “SameFrame” in MAX+PLUS II Help.
Table 10. ACEX 1K SameFrame Pin-Out Support
Device
256-Pin
FineLine
BGA
484-Pin
FineLine
BGA
EP1K10
v
(1)
EP1K30
v
(1)
EP1K50
v
v
EP1K100
v
v
Note:
(1)
ClockLock &
ClockBoost
Features
This option is supported with a 256-pin FineLine BGA package and SameFrame
migration.
To support high-speed designs, -1 and -2 speed grade ACEX 1K devices
offer ClockLock and ClockBoost circuitry containing a phase-locked loop
(PLL) that is used to increase design speed and reduce resource usage. The
ClockLock circuitry uses a synchronizing PLL that reduces the clock delay
and skew within a device. This reduction minimizes clock-to-output and
setup times while maintaining zero hold times. The ClockBoost circuitry,
which provides a clock multiplier, allows the designer to enhance device
area efficiency by sharing resources within the device. The ClockBoost
feature allows the designer to distribute a low-speed clock and multiply
that clock on-device. Combined, the ClockLock and ClockBoost features
provide significant improvements in system performance and
bandwidth.
The ClockLock and ClockBoost features in ACEX 1K devices are enabled
through the Altera software. External devices are not required to use these
features. The output of the ClockLock and ClockBoost circuits is not
available at any of the device pins.
The ClockLock and ClockBoost circuitry lock onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
36
Altera Corporation
ACEX 1K Programmable Logic Device Family Data Sheet
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the Altera
software, the GCLK1 pin can feed both the ClockLock and ClockBoost
circuitry in the ACEX 1K device. However, when both circuits are used,
the other clock pin cannot be used.
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the ClockLock and ClockBoost circuitry will lock onto the
clock during configuration. The circuit will be ready for use immediately
after configuration. Figure 19 shows the incoming and generated clock
specifications.
Figure 19. Specifications for the Incoming & Generated Clocks
t INDUTY
Development
Tools
t CLK1
13
Note (1)
t I + t CLKDEV
Input
Clock
tR
tF
tO
t I + t INCLKSTB
t OUTDUTY
ClockLock
Generated
Clock
tO
t O + t JITTER t O t JITTER
Note:
(1)
The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock
period.
Altera Corporation
37
ACEX 1K Programmable Logic Device Family Data Sheet
Tables 11 and 12 summarize the ClockLock and ClockBoost parameters
for -1 and -2 speed-grade devices, respectively.
Table 11. ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices
Max
Unit
tR
Symbol
Input rise time
Parameter
Condition
Min
Typ
5
ns
tF
Input fall time
5
ns
tINDUTY
Input duty cycle
40
60
%
fCLK1
Input clock frequency (ClockBoost clock
multiplication factor equals 1)
25
180
MHz
fCLK2
Input clock frequency (ClockBoost clock
multiplication factor equals 2)
16
90
MHz
fCLKDEV
Input deviation from user specification in the
Altera software (1)
25,000
(2)
PPM
100
ps
10
µs
tINCLKSTB