EP3SE80F780C3N

Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Version: Document Date: 10.0 2.2 © March 2011 Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. SIII5V1-2.2 Contents Chapter Revision Dates Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxv Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxv Chapter I. Device Core Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Stratix III Device Family Overview Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Architecture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Logic Array Blocks and Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 TriMatrix Embedded Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 DSP Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Clock Networks and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 I/O Banks and I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 High-Speed Differential I/O Interfaces with DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Hot Socketing and Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 IEEE 1149.1 (JTAG) Boundary-Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 Design Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 SEU Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Programmable Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Signal Integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Reference and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . © March 2011 Altera Corporation 2-1 2-1 2-3 2-4 Stratix III Device Handbook, Volume 1 iv Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 ALM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Extended LUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Carry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 Shared Arithmetic Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 LUT-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 ALM Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 LAB Power Management Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Chapter 3. MultiTrack Interconnect in Stratix III Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Row Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Column Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Memory Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 DSP Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 I/O Block Connections to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 TriMatrix Memory Block Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Parity Bit Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Byte-Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Packed Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Address Clock Enable Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Mixed Width Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Asynchronous Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 Error Correction Code Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Single Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Simple Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Shift-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Input/Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Read/Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation v Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting TriMatrix Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conflict Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read During Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Same-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed-Port Read-During-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Conditions and Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming File Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4-20 4-20 4-21 4-21 4-22 4-23 4-24 4-24 4-24 4-25 Chapter 5. DSP Blocks in Stratix III Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 DSP Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Simplified DSP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Operational Modes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 DSP Block Resource Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Input Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Multiplier and First-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Pipeline Register Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Second-Stage Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Round and Saturation Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Second Adder and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Operational Mode Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Independent Multiplier Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 9-, 12-, and 18-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 36-Bit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Double Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Two-Multiplier Adder Sum Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 18 × 18 Complex Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Four-Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 High Precision Multiplier Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 Multiply Accumulate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 FIR Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 FFT Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 Chapter 6. Clock Networks and PLLs in Stratix III Devices © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 vi Clock Networks in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Regional Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Periphery Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Clocking Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Clock Network Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Clock Output Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Clock Source Control for PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 PLLs in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Stratix III PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 PLL Clock I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Stratix III PLL Software Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Source Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Source-Synchronous Mode for LVDS Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 No-Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 Zero-Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 External Feedback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Clock Multiplication and Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 Post-Scale Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Programmable Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 PLL Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 pfdena . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 areset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 Automatic Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Manual Clock Switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 Programmable Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 Phase-Shift Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41 PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42 PLL Reconfiguration Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 Post-Scale Counters (C0 to C9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 Scan Chain Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 Charge Pump and Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Bypassing PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 PLL Cascading and Clock Network Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Spread-Spectrum Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Chapter II. I/O Interfaces Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1 Chapter 7. Stratix III Device I/O Features Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation vii Stratix III I/O Standards Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 I/O Standards and Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Stratix III I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Stratix III I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 3.3-V I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 High-Speed Differential I/O with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Programmable Current Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 Programmable Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 Programmable Differential Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 OCT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 On-Chip Series Termination without Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20 On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-21 Expanded On-Chip Series Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22 Left Shift Series Termination Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 On-Chip Parallel Termination with Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 Dynamic OCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 LVDS Input On-Chip Termination (RD ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 OCT Calibration Block Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 Sharing an OCT Calibration Block in Multiple I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 OCT Calibration Block Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 Power-Up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 OCT Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 Serial Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 Example of Using Multiple OCT Calibration Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-31 RS Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 Termination Schemes for I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 Single-Ended I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-32 Differential I/O Standards Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-36 Differential LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 Mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-39 I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Single-Ended I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 I/O Banks Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 Mixing Voltage-Referenced and Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . 7-41 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 Chapter 8. External Memory Interfaces in Stratix III Devices © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 viii Memory Interfaces Pin Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 Data and Data-Strobe/Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 Using R UP /RDN Pins in a DQS/DQ Group Used for Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . 8-5 Combining ×16/×18 DQS/DQ groups for ×36 QDR II+/QDR II SRAM Interface . . . . . . . . . . . . . 8-15 Rules to Combine Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Optional Parity, DM, BWSn, NWSn, ECC and QVLD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Address and Control/Command Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Memory Clock Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Stratix III External Memory Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 DQS Phase-Shift Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 DLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 Phase Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 DQS Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 DQS Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 Update Enable Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 DQS Postamble Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 Leveling Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 Dynamic OCT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 IOE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 I/O Configuration Block and DQS Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41 IOE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42 OCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 Programmable IOE Delay Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 Programmable Output Buffer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 Programmable Slew Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 Programmable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45 Chapter 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 LVDS Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 Differential Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 Differential Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Receiver Data Realignment Circuit (Bit Slip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Dynamic Phase Aligner (DPA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Soft-CDR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Programmable Pre-Emphasis and Programmable V OD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Differential I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Left/Right PLLs (PLL_Lx/ PLL_Rx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Receiver Skew Margin for Non-DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation ix Differential Pin Placement Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for DPA-Enabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPA-Enabled Channels and Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPA-Enabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Corner and Center Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Both Center Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Guidelines for DPA-Disabled Differential Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPA-Disabled Channels and Single-Ended I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPA-Disabled Channel Driving Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Corner and Center Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Both Center Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9-19 9-19 9-19 9-19 9-21 9-23 9-23 9-23 9-23 9-26 9-27 Chapter III. Hot Socketing, Configuration, Remote Upgrades, and Testing Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1 Chapter 10. Hot Socketing and Power-On Reset in Stratix III Devices Stratix III Hot-Socketing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stratix III Devices Can Be Driven Before Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins Remain Tri-Stated During Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insertion or Removal of a Stratix III Device from a Powered-Up System . . . . . . . . . . . . . . . . . . . . . Hot-Socketing Feature Implementation in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10-1 10-2 10-2 10-2 10-4 10-5 10-7 Chapter 11. Configuring Stratix III Devices Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 Design Security Using Configuration Bitstream Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Power-On Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 VCCPGM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 VCCPD Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 Fast Passive Parallel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 FPP Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 FPP Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 FPP Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Fast Active Serial Configuration (Serial Configuration Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-17 Estimating Active Serial Configuration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Programming Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 Passive Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 PS Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 PS Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 x Chapter 12. Remote System Upgrades with Stratix III Devices Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 Enabling Remote Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Configuration Image Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 Remote System Upgrade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-11 Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 ALTREMOTE_UPDATE Megafunction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices IEEE Std. 1149.1 BST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 IEEE Std. 1149.1 Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 Boundary-Scan Cells of a Stratix III Device I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 IEEE Std. 1149.1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 SAMPLE/PRELOAD Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 EXTEST Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 BYPASS Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 IDCODE Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 USERCODE Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 CLAMP Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 HIGHZ Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 I/O Voltage Support in JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 IEEE Std. 1149.1 BST Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 IEEE Std. 1149.1 BST Circuitry (Disabling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 IEEE Std. 1149.1 BST Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Boundary-Scan Description Language (BSDL) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-20 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 Chapter IV. Design Security and Single Event Upset (SEU) Mitigation Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-1 Chapter 14. Design Security in Stratix III Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stratix III Security Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security Against Copying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security Against Reverse Engineering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security Against Tampering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AES Decryption Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flexible Security Key Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stratix III Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security Modes Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stratix III Device Handbook, Volume 1 © March 2011 14-1 14-1 14-1 14-2 14-2 14-2 14-2 14-3 14-4 14-4 14-4 14-4 14-5 14-5 Altera Corporation xi Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 Chapter 15. SEU Mitigation in Stratix III Devices Error Detection Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 Configuration Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 User Mode Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 Automated Single Event Upset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Error Detection Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 CRC_ERROR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 Error Detection Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 Error Detection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 Recovering From CRC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Chapter V. Power and Thermal Management Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-1 Chapter 16. Programmable Power and Temperature-Sensing Diodes in Stratix III Devices Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stratix III Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selectable Core Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Power Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relationship Between Selectable Core Voltage and Programmable Power Technology . . . . . . . . . Stratix III External Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Sensing Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16-1 16-1 16-2 16-3 16-3 16-5 16-6 16-6 16-7 Chapter VI. Packaging Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VI-1 Chapter 17. Stratix III Device Packaging Information Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xii Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation Chapter Revision Dates The chapters in this book were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Stratix III Device Family Overview Revised: March 2010 Part Number: SIII51001-1.8 Chapter 2 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Revised: February 2009 Part Number: SIII51002-1.5 Chapter 3 MultiTrack Interconnect in Stratix III Devices Revised: October 2008 Part Number: SIII51003-1.2 Chapter 4 TriMatrix Embedded Memory Blocks in Stratix III Devices Revised: May 2009 Part Number: SIII51004-1.8 Chapter 5 DSP Blocks in Stratix III Devices Revised: March 2010 Part Number: SIII51005-1.7 Chapter 6 Clock Networks and PLLs in Stratix III Devices Revised: July 2010 Part Number: SIII51006-2.0 Chapter 7 Stratix III Device I/O Features Revised: July 2010 Part Number: SIII51007-1.9 Chapter 8 External Memory Interfaces in Stratix III Devices Revised: March 2010 Part Number: SIII51008-1.9 Chapter 9 High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Revised: July 2010 Part Number: SIII51009-1.9 Chapter 10 Hot Socketing and Power-On Reset in Stratix III Devices Revised: March 2010 Part Number: SIII51010-1.7 Chapter 11 Configuring Stratix III Devices Revised: March 2011 Part Number: SIII51011-2.0 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xiv Chapter 12 Remote System Upgrades with Stratix III Devices Revised: March 2010 Part Number: SIII51012-1.5 Chapter 13 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Revised: July 2010 Part Number: SIII51013-1.9 Chapter 14 Design Security in Stratix III Devices Revised: May 2009 Part Number: SIII51014-1.5 Chapter 15 SEU Mitigation in Stratix III Devices Revised: March 2010 Part Number: SIII51015-1.7 Chapter 16 Programmable Power and Temperature-Sensing Diodes in Stratix III Devices Revised: February 2009 Part Number: SIII51016-1.5 Chapter 17 Stratix III Device Packaging Information Revised: March 2010 Part Number: SIII51017-1.7 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation List of Figures xv List of Figures Figure 1–1: Stratix III Device Packaging Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Figure 2–1: Stratix III LAB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Figure 2–2: Stratix III LAB and MLAB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 2–3: Direct Link Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2–4: LAB-Wide Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 Figure 2–5: High-Level Block Diagram of the Stratix III ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Figure 2–6: Stratix III ALM Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Figure 2–7: ALM in Normal Mode (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Figure 2–8: 4 × 2 Crossbar Switch Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Figure 2–9: Input Function in Normal Mode (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Figure 2–10: Template for Supported Seven-Input Functions in Extended LUT Mode . . . . . . . . . . . . . . 2-11 Figure 2–11: ALM in Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 Figure 2–12: Conditional Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 Figure 2–13: ALM in Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 Figure 2–14: Example of a 3-Bit Add Utilizing Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 Figure 2–15: LUT Register from Two Combinational Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 Figure 2–16: ALM in LUT-Register Mode with 3-Register Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 Figure 2–17: Register Chain within an LAB (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 Figure 2–18: Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects . . . . . . . . . . . . . 2-20 Figure 3–1: R4 Interconnect Connections (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Figure 3–2: Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects . . . . . . . . . . . . . . . 3-3 Figure 3–3: C4 Interconnect Connections (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Figure 3–4: MLAB RAM Block LAB Row Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Figure 3–5: M9K RAM Block LAB Row Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Figure 3–6: M144K Row Unit Interface to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Figure 3–7: High-Level View, DSP Block Interface to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Figure 3–8: Detailed View, DSP Block Interface to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Figure 3–9: Row I/O Block Connection to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 Figure 3–10: Column I/O Block Connection to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Figure 4–1: Stratix III Byte-Enable Functional Waveform for M9K and M144K . . . . . . . . . . . . . . . . . . . . . 4-4 Figure 4–2: Stratix III Byte-Enable Functional Waveform for MLABs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Figure 4–3: Stratix III Address Clock Enable Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Figure 4–4: Stratix III Address Clock Enable during Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Figure 4–5: Stratix III Address Clock Enable during Write Cycle Waveform for M9K and M144K . . . . . 4-7 Figure 4–6: Stratix III Address Clock Enable during Write Cycle Waveform for MLABs . . . . . . . . . . . . . 4-8 Figure 4–7: Output Latch Asynchronous Clear Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Figure 4–8: ECC Block Diagram of the M144K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 Figure 4–9: Single-Port Memory (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Figure 4–10: Timing Waveform for Read-Write Operations (Single-Port Mode) for M9K and M144K . 4-12 Figure 4–11: Timing Waveform for Read-Write Operations (Single-Port Mode) for MLABs . . . . . . . . . 4-12 Figure 4–12: Stratix III Simple Dual-Port Memory (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Figure 4–13: Stratix III Simple Dual-Port Timing Waveforms for M9K and M144K . . . . . . . . . . . . . . . . . 4-14 Figure 4–14: Stratix III Simple Dual-Port Timing Waveforms for MLABs . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 Figure 4–15: Stratix III True Dual-Port Memory (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Figure 4–16: Stratix III True Dual-Port Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Figure 4–17: Stratix III Shift-Register Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Figure 4–18: Stratix III Read-During-Write Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xvi List of Figures Figure 4–19: Same Port Read-During-Write: New Data Mode (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Figure 4–20: Same Port Read-During-Write: Old Data Mode (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22 Figure 4–21: Mixed Port Read During Write: Old Data Mode (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 Figure 5–1: Overview of DSP Block Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Figure 5–2: Basic Two-Multiplier Adder Building Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 Figure 5–3: Four-Multiplier Adder and Accumulation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 Figure 5–4: Output Cascading Feature for FIR Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Figure 5–5: Stratix III Full DSP Block Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 Figure 5–6: Half-DSP Block Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Figure 5–7: Input Register of Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Figure 5–8: 18-Bit Independent Multiplier Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Figure 5–9: 12-Bit Independent Multiplier Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 Figure 5–10: 9-Bit Independent Multiplier Mode for Half-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 Figure 5–11: 36-Bit Independent Multiplier Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 Figure 5–12: Double Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 Figure 5–13: Unsigned 54 × 54 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 Figure 5–14: Two-Multiplier Adder Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 Figure 5–15: Loopback Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 Figure 5–16: Complex Multiplier Using Two-Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 Figure 5–17: Four-Multiplier Adder Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 Figure 5–18: Four-Multiplier Adder Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 Figure 5–19: Multiply Accumulate Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 Figure 5–20: Shift Operation Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 Figure 5–21: Round and Saturation Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 Figure 5–22: FIR Filter Using Tap-Delay Line Input and Tree Summation of Final Result . . . . . . . . . . . 5-37 Figure 5–23: FIR Filter using Tap-Delay Line Input and Chained Cascade Summation of Final Result 5-38 Figure 5–24: Semi-Parallel FIR Structure Using Chained Cascaded Summation . . . . . . . . . . . . . . . . . . . . 5-40 Figure 5–25: Radix-4 Butterfly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 Figure 6–1: Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Figure 6–2: Regional Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) . . . . . . . . . . . . . . . . . . 6-3 Figure 6–3: Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) . . . . . . . 6-3 Figure 6–4: Regional Clock Networks (EP3SL200, EP3SE260, and EP3SL340 Devices) (Note 1) . . . . . . . 6-4 Figure 6–5: Periphery Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) . . . . . . . . . . . . . . . . . 6-4 Figure 6–6: Periphery Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) . . . . . . 6-5 Figure 6–7: Periphery Clock Networks (EP3SL200 Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Figure 6–8: Periphery Clock Networks (EP3SE260 Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Figure 6–9: Periphery Clock Networks (EP3SL340 Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Figure 6–10: Stratix III Dual-Regional Clock Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Figure 6–11: Clock Input Multiplexer Logic for L2, L3, T1, T2, B1, B2, R2, and R3 PLLs . . . . . . . . . . . . . 6-14 Figure 6–12: Clock Input Multiplexer Logic for L1, L4, R1, and R4 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 Figure 6–13: Stratix III Global Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Figure 6–14: Regional Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 Figure 6–15: Stratix III External PLL Output Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 Figure 6–16: clkena Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Figure 6–17: clkena Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 Figure 6–18: Stratix III PLL Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20 Figure 6–19: Stratix III PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 Figure 6–20: External Clock Outputs for Top/Bottom PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Figure 6–21: External Clock Outputs for Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Figure 6–22: Stratix III PLL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation List of Figures xvii Figure 6–23: Phase Relationship Between Clock and Data in Source-Synchronous Mode . . . . . . . . . . . . 6-27 Figure 6–24: Phase Relationship Between Clock and Data LVDS Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 Figure 6–25: Phase Relationship Between PLL Clocks in No Compensation Mode . . . . . . . . . . . . . . . . . 6-28 Figure 6–26: Phase Relationship Between PLL Clocks in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Figure 6–27: Zero-Delay Buffer Mode in Stratix III PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 Figure 6–28: Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . 6-30 Figure 6–29: External Feedback Mode in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 Figure 6–30: Phase Relationship Between PLL Clocks in External-Feedback Mode . . . . . . . . . . . . . . . . . 6-31 Figure 6–31: Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 Figure 6–32: Automatic Clock Switchover Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 Figure 6–33: Automatic Switchover Upon Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35 Figure 6–34: Clock Switchover Using the clkswitch (Manual) Control (Note 1) . . . . . . . . . . . . . . . . . . . 6-36 Figure 6–35: Manual Clock Switchover Circuitry in Stratix III PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 Figure 6–36: VCO Switchover Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 Figure 6–37: Open- and Closed-Loop Response Bode Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39 Figure 6–38: Loop Filter Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40 Figure 6–39: Delay Insertion Using VCO Phase Output and Counter Delay Time . . . . . . . . . . . . . . . . . . 6-42 Figure 6–40: PLL Reconfiguration Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 Figure 6–41: PLL Reconfiguration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 Figure 6–42: Scan-Chain Order of PLL Components for Top/Bottom PLLs (Note 1) . . . . . . . . . . . . . . . 6-47 Figure 6–43: Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix III PLLs . . . . . . . . . . . . 6-47 Figure 6–44: Dynamic Phase Shifting Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 Figure 7–1: I/O Banks for Stratix III Devices (Note 1), (2), (3), (4), (5), (6), (7), (8), (9) . . . . . . . . . . . . . . . . 7-6 Figure 7–2: Number of I/Os in Each Bank in EP3SL50, EP3SL70, and EP3SE50 Devices in 484-Pin FineLine BGA Package (Note 1), (2), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 Figure 7–3: Number of I/Os in Each Bank in the 780-pin FineLine BGA Package (Note 1), (2), (3), (4) . 7-9 Figure 7–4: Number of I/Os in Each Bank in the 1152-pin FineLine BGA Package (Note 1), (2), (3), (4) . . . 7-10 Figure 7–5: Number of I/Os in Each Bank in EP2SL200, EP3SE260, and EP3SL340 Devices in the 1517-Pin FineLine BGA Package (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 Figure 7–6: Number of I/Os in Each Bank in EP3SL340 Devices in the 1760-pin FineLine BGA Package (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 Figure 7–7: IOE Structure for Stratix III Devices (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 Figure 7–8: On-Chip Series Termination without Calibration for Stratix III Devices . . . . . . . . . . . . . . . . 7-21 Figure 7–9: On-Chip Series Termination with Calibration for Stratix III Devices . . . . . . . . . . . . . . . . . . . 7-21 Figure 7–10: On-Chip Parallel Termination with Calibration for Stratix III Devices . . . . . . . . . . . . . . . . . 7-24 Figure 7–11: Dynamic Parallel OCT in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25 Figure 7–12: Differential Input On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 Figure 7–13: OCT Calibration Block (CB) Location in EP3SL50, EP3SL70, and EP3SE50 Devices (Note 1) . 7-27 Figure 7–14: OCT Calibration Block (CB) Location in EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28 Figure 7–15: OCT Calibration Block (CB) Location in EP3SL200, EP3SE260 and EP3SL340 (Note 1) . . 7-28 Figure 7–16: Example of Sharing Multiple I/O Banks with One OCT Calibration Block (Note 1) . . . . 7-29 Figure 7–17: Signals Used for User Mode Calibration (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30 Figure 7–18: OCT User-Mode Signal Timing Waveform for One OCT Block . . . . . . . . . . . . . . . . . . . . . . 7-31 Figure 7–19: OCT User-Mode Signal Timing Waveform for Two OCT Blocks . . . . . . . . . . . . . . . . . . . . . 7-32 Figure 7–20: SSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 Figure 7–21: HSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 Figure 7–22: Differential SSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . 7-35 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xviii List of Figures Figure 7–23: Differential HSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . 7-35 Figure 7–24: LVDS I/O Standard Termination for Stratix III Devices (Note 1) . . . . . . . . . . . . . . . . . . . . . 7-36 Figure 7–25: LVPECL AC Coupled Termination (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 Figure 7–26: LVPECL DC Coupled Termination (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37 Figure 7–27: RSDS I/O Standard Termination for Stratix III Devices (Note 1), (2) . . . . . . . . . . . . . . . . . . 7-38 Figure 7–28: Mini-LVDS I/O Standard Termination for Stratix III Devices (Note 1), (2) . . . . . . . . . . . . 7-39 Figure 8–1: Package Bottom View for Stratix III Devices (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 Figure 8–2: External Memory Interface Data Path Overview (Note 1), (2), (3) . . . . . . . . . . . . . . . . . . . . . . 8-3 Figure 8–3: Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, and EP3SL70 Devices in the 484-pin FineLine BGA Package (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 Figure 8–4: Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, EP3SL70, EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, and EP3SE260 Devices in the 780-pin FineLine BGA Package (Note 1) . 8-9 Figure 8–5: Number of DQS/DQ Groups in EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, EP3SE260, and EP3SL340 Devices in the 1152-pin FineLine BGA Package (Note 1) . . . . . . . . . . . . . . . . 8-10 Figure 8–6: Number of DQS/DQ Groups per Bank in EP3SL200, EP3SE260 and EP3SL340 Devices in the 1517-pin FineLine BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 Figure 8–7: DQS/DQ Bus Mode Support per Bank in EP3SL340 Devices in the 1760-pin FineLine BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 Figure 8–8: DQS Pins in Stratix III I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14 Figure 8–9: Memory Clock Generation Block Diagram (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Figure 8–10: DQS and CQn Pins and DQS Phase-Shift Circuitry (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Figure 8–11: Stratix III DLL and I/O Bank Locations (Package Bottom View) . . . . . . . . . . . . . . . . . . . . . 8-22 Figure 8–12: Simplified Diagram of the DQS Phase Shift Circuitry (Note 1) . . . . . . . . . . . . . . . . . . . . . 8-26 Figure 8–13: Stratix III DQS Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 Figure 8–14: Example of a DQS Update Enable Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 Figure 8–15: Avoiding a Glitch on a Non-Consecutive Read Burst Waveform . . . . . . . . . . . . . . . . . . . . . 8-31 Figure 8–16: DDR3 SDRAM Unbuffered Module Clock Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 Figure 8–17: Stratix III Write Leveling Delay Chains and Multiplexers (Note 1) . . . . . . . . . . . . . . . . . . . 8-32 Figure 8–18: Stratix III Read Leveling Delay Chains and Multiplexers (Note 1) . . . . . . . . . . . . . . . . . . . 8-33 Figure 8–19: Stratix III Dynamic OCT Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 Figure 8–20: Stratix III IOE Input Registers (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35 Figure 8–21: Stratix III IOE Output and Output-Enable Path Registers (Note 1) . . . . . . . . . . . . . . . . . . . 8-38 Figure 8–22: Delay Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 Figure 8–23: Delay Chains in an I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 Figure 8–24: Delay Chains in the DQS Input Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 Figure 8–25: I/O Configuration Block and DQS Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41 Figure 9–1: I/O Banks in Stratix III Devices (Note 1), (2), (3), (4), (5), (6) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 Figure 9–2: Transmitter Block Diagram for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Figure 9–3: Transmitter in Clock Output Mode for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 Figure 9–4: Serializer Bypass for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 Figure 9–5: Receiver Block Diagram for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Figure 9–6: Deserializer Bypass for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 Figure 9–7: Data Realignment Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Figure 9–8: DPA Clock Phase-to-Serial Data Timing Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 Figure 9–9: Soft-CDR Data and Clock Path for a Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Figure 9–10: Programmable VOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 Figure 9–11: On-Chip Differential I/O Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Figure 9–12: PLL Block Diagram for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 Figure 9–13: LVDS/DPA Clocks with Center PLLs for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation List of Figures xix Figure 9–14: LVDS/DPA Clocks with Center and Corner PLLs for Stratix III Devices . . . . . . . . . . . . . . 9-14 Figure 9–15: Bit Orientation in Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Figure 9–16: Bit-Order and Word Boundary for One Differential Channel (Note 1) . . . . . . . . . . . . . . . . 9-16 Figure 9–17: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA . . . . . . . . . . . 9-18 Figure 9–18: Corner and Center Left/Right PLLs Driving DPA-Enabled Differential I/Os in the Same Bank 9-20 Figure 9–19: Center Left/Right PLLs Driving DPA-Enabled Differential I/Os . . . . . . . . . . . . . . . . . . . . . 9-21 Figure 9–20: Invalid Placement of DPA-Enabled Differential I/Os Driven by Both Center Left/Right PLLs 9-22 Figure 9–21: Corner and Center Left/Right PLLs Driving DPA-Disabled Differential I/Os in the Same Bank 9-24 Figure 9–22: Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven by the Corner and Center Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 Figure 9–23: Both Center Left/Right PLLs Driving Cross-Bank DPA-Disabled Channels Simultaneously . 9-26 Figure 10–1: Hot-Socketing Circuitry for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 Figure 10–2: Transistor Level Diagram of a Stratix III Device I/O Buffers . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 Figure 10–3: Simplified POR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Figure 11–1: Enabling Compression for Stratix III Bitstreams in Compiler Settings . . . . . . . . . . . . . . . . . 11-5 Figure 11–2: Compressed and Uncompressed Configuration Data in the Same Configuration File . . . 11-6 Figure 11–3: Single Device FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Figure 11–4: Multi-Device FPP Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 Figure 11–5: Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 Figure 11–6: FPP Configuration Timing Waveform (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 Figure 11–7: FPP Configuration Timing Waveform with Decompression or Design Security Feature Enabled (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 Figure 11–8: Single Device Fast AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 Figure 11–9: Multi-Device Fast AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21 Figure 11–10: Multi-Device Fast AS Configuration When the Devices Receive the Same Data Using a Single SOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 Figure 11–11: Fast AS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 Figure 11–12: In-System Programming of Serial Configuration Devices . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 Figure 11–13: Single Device PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Figure 11–14: Multi-Device PS Configuration Using an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 Figure 11–15: Multiple-Device PS Configuration When Both Devices Receive the Same Data . . . . . . . 11-31 Figure 11–16: PS Configuration Timing Waveform (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Figure 11–17: PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 Figure 11–18: Multi-Device PS Configuration using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 Figure 11–19: JTAG Configuration of a Single Device Using a Download Cable . . . . . . . . . . . . . . . . . . 11-39 Figure 11–20: JTAG Configuration of Multiple Devices Using a Download Cable . . . . . . . . . . . . . . . . . 11-41 Figure 11–21: JTAG Configuration of a Single Device Using a Microprocessor . . . . . . . . . . . . . . . . . . . . 11-42 Figure 12–1: Functional Diagram of Stratix III Remote System Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 Figure 12–2: Remote System Upgrade Block Diagram for Stratix III Fast AS Configuration Scheme . . 12-2 Figure 12–3: Enabling Remote Update for Stratix III Devices in Compiler Settings . . . . . . . . . . . . . . . . . 12-4 Figure 12–4: Transitions Between Configurations in Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . 12-6 Figure 12–5: Remote System Upgrade Circuit Data Path (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Figure 12–6: Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Figure 12–7: Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Figure 12–8: Interface Signals Between the ALTREMOTE_UPDATE Megafunction and the Nios II Proces- © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xx List of Figures sor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13 Figure 13–1: IEEE Std. 1149.1 Boundary-Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 Figure 13–2: IEEE Std. 1149.1 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 Figure 13–3: Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 Figure 13–4: Stratix III Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry . . . . . . . . . . . . . . . . . 13-5 Figure 13–5: IEEE Std. 1149.1 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 Figure 13–6: IEEE Std. 1149.1 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 Figure 13–7: Selecting the Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 Figure 13–8: IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 Figure 13–9: SAMPLE/PRELOAD Shift Data Register Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 Figure 13–10: IEEE Std. 1149.1 BST EXTEST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 Figure 13–11: EXTEST Shift Data Register Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 Figure 13–12: BYPASS Shift Data Register Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 Figure 13–13: JTAG Chain of Mixed Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 Figure 14–1: Design Security (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Figure 14–2: Stratix III Security Modes - Sequence and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 Figure 15–1: Error Detection Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Figure 15–2: Enabling the Error Detection CRC Feature in the Quartus II Software . . . . . . . . . . . . . . . . 15-11 Figure 16–1: Stratix III Power Management Example (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 Figure 16–2: TEMPDIODEP and TEMPDIODEN External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 16-6 Figure 16–3: TSD Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation List of Tables xxi List of Tables Table 1–1: FPGA Family Features for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Table 1–2: Package Options and I/O Pin Counts (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Table 1–3: FineLine BGA Package Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Table 1–4: Hybrid FineLine BGA Package Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1–5: Speed Grades for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Table 1–6: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 Table 2–1: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Table 3–1: Stratix III Device Routing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Table 3–2: Number of LABs reachable using C4 and R4 interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 Table 3–3: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 Table 4–1: Summary of TriMatrix Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Table 4–2: TriMatrix Memory Capacity and Distribution in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . 4-3 Table 4–3: Truth Table for ECC Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 Table 4–4: Stratix III Port Width Configurations for MLABs, M9K Blocks, and M144K Blocks (Single-Port Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 Table 4–5: Stratix III M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) . . . . . . . . . . . 4-13 Table 4–6: Stratix III M144K Block Mixed-Width Configurations (Simple Dual-Port Mode) . . . . . . . . . 4-13 Table 4–7: Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) . . . . . . . . . . . . . . 4-15 Table 4–8: Stratix III M144K Block Mixed-Width Configurations (True Dual-Port Mode) . . . . . . . . . . . 4-16 Table 4–9: Stratix III TriMatrix Memory Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Table 4–10: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 Table 5–1: Number of DSP Blocks in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Table 5–2: Stratix III DSP Block Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Table 5–3: Input Register Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Table 5–4: Multiplier Sign Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Table 5–5: Examples of Shift Operations (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Table 5–6: Example of Round-To-Nearest-Even Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 Table 5–7: Comparison of Round-to-Nearest-Integer and Round-to-Nearest-Even . . . . . . . . . . . . . . . . . 5-32 Table 5–8: Examples of Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 Table 5–10: DSP Block Dynamic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 Table 5–10: Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 Table 6–1: Clock Resources in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 Table 6–2: Clock Input Pin Connectivity to Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Table 6–3: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 1) . . . . . . . . . . . . . . . . . 6-9 Table 6–4: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2) . . . . . . . . . . . . . . . . . 6-9 Table 6–5: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 3) . . . . . . . . . . . . . . . . 6-10 Table 6–6: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 4) . . . . . . . . . . . . . . . . 6-11 Table 6–7: Stratix III Device PLLs and PLL Clock Pin Drivers (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 Table 6–8: PLL Connectivity to GCLKs on Stratix III Devices (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 Table 6–9: Regional Clock Outputs From PLLs on Stratix III Devices (Note 1) . . . . . . . . . . . . . . . . . . . . 6-13 Table 6–10: Stratix III Device PLL Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 Table 6–11: Stratix III PLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 Table 6–12: PLL Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Table 6–13: PLL Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Table 6–14: Clock Feedback Mode Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Table 6–15: Real-Time PLL Reconfiguration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 Table 6–16: Top/Bottom PLL Reprogramming Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xxii List of Tables Table 6–17: charge_pump_current Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Table 6–18: loop_filter_r Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Table 6–19: loop_filter_c Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48 Table 6–20: PLL Counter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 Table 6–21: Dynamic Phase-Shifting Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 Table 6–22: Phase Counter Select Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50 Table 6–23: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Table 7–1: I/O Standard Applications for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Table 7–2: I/O Standards and Voltage Levels for Stratix III Devices (Note 1), (3) . . . . . . . . . . . . . . . . . . . 7-3 Table 7–3: Bank Migration Path with Increasing Device Size (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 Table 7–4: Memory Interface Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Table 7–5: Programmable Current Strength (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Table 7–6: Default Programmable Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Table 7–7: MultiVolt I/O Support for Stratix III Devices (Note 1), (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19 Table 7–8: Selectable I/O Standards with On-Chip Series Termination With or Without Calibration . 7-22 Table 7–9: Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration Range 7-23 Table 7–10: Selectable I/O Standards that Support On-Chip Parallel Termination with Calibration . . 7-24 Table 7–11: On-Chip Differential Termination in Quartus II Software Assignment Editor . . . . . . . . . . . 7-26 Table 7–12: OCT Calibration Block Ports for User Control and Description . . . . . . . . . . . . . . . . . . . . . . . 7-30 Table 7–13: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 Table 8–1: DQS and DQ Bus Mode Pins for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 Table 8–2: Number of DQS/DQ Groups in Stratix III Devices per Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 Table 8–3: DQ/DQS Group in Stratix III Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 Table 8–4: I/O Sub-Bank Combinations for Stratix III Devices that do not have ×36 Groups to form two ×36 Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Table 8–5: DLL Location and Supported I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 Table 8–6: DLL Reference Clock Input for EP3SE50, EP3SL50, and EP3SL70 Devices . . . . . . . . . . . . . . . 8-23 Table 8–8: DLL Reference Clock Input for EP3SE80, EP3SE110, EP3SL110, and EP3SL150 Devices in the 1152-pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 Table 8–7: DLL Reference Clock Input for EP3SE80, EP3SE110, and EP3SL150 Devices in the 780-pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 Table 8–9: DLL Reference Clock Input for EP3SL200, EP3SE260 and EP3SL340 Devices (Note 1), (2) . 8-25 Table 8–10: Stratix III DLL Frequency Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 Table 8–11: I/O Configuration Block Bit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41 Table 8–12: DQS Configuration Block Bit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42 Table 8–13: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45 Table 9–1: LVDS Channels Supported in Stratix III Device Side I/O Banks (Note 1), (2), (3) . . . . . . . . . 9-3 Table 9–2: LVDS Channels (Emulated) Supported in Stratix III Device Column I/O Banks (Note 1), (2) . . 9-4 Table 9–3: Differential Bit Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 Table 9–4: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 Table 10–1: Power Supplies Ramp-Up Time (tRAMP) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Table 10–2: Power Supplies Monitored by the POR Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 Table 10–3: Power Supplies That Are Not Monitored by the POR Circuitry . . . . . . . . . . . . . . . . . . . . . . . 10-6 Table 10–4: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 Table 11–1: Stratix III Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Table 11–2: Stratix III Uncompressed Raw Binary File (.rbf) Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 Table 11–3: Stratix III Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 Table 11–4: Stratix III MSEL Pin Settings for FPP Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation List of Tables xxiii Table 11–5: FPP Timing Parameters for Stratix III Devices (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 Table 11–6: FPP Timing Parameters for Stratix III Devices with Decompression or Design Security Feature Enabled (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 Table 11–7: Stratix III MSEL Pin Settings for AS Configuration Schemes (Note 1) . . . . . . . . . . . . . . . . 11-17 Table 11–8: Fast AS Timing Parameters for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 Table 11–9: Stratix III MSEL Pin Settings for PS Configuration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 Table 11–10: PS Timing Parameters for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 Table 11–11: Dedicated JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 Table 11–12: Dedicated Configuration Pin Connections During JTAG Configuration . . . . . . . . . . . . . . 11-40 Table 11–13: Stratix III Configuration Pin Summary (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 Table 11–14: Dedicated Configuration Pins on the Stratix III Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 Table 11–15: Optional Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 Table 11–16: Dedicated JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 Table 11–17: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51 Table 12–1: Stratix III Remote System Upgrade Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 Table 12–2: Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 Table 12–3: Remote System Upgrade Control Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Table 12–4: Remote System Upgrade Status Register Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Table 12–5: Control Register Contents After an Error or Reconfiguration Trigger Condition . . . . . . . . 12-11 Table 12–6: 10-MHz Internal Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 Table 12–7: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 Table 13–1: IEEE Std. 1149.1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 Table 13–2: Stratix III Boundary-Scan Register Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 Table 13–3: Stratix III Device Boundary Scan Cell Descriptions (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 Table 13–4: Stratix III JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 Table 13–5: 32-Bit Stratix III Device IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 Table 13–6: Supported TDO/TDI Voltage Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 Table 13–7: Disabling IEEE Std. 1149.1 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 Table 13–8: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 Table 14–1: Security Keys Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 Table 14–2: Key Retention Time of Coin-Cell Type Batteries used for Volatile Key Storage . . . . . . . . . . 14-3 Table 14–3: Security Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Table 14–4: Allowed Configuration Modes for Various Security Modes (Note 1) . . . . . . . . . . . . . . . . . . 14-6 Table 14–5: Design Security Configuration Schemes Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 Table 14–6: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 Table 15–1: EDERROR_INJECT JTAG Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 Table 15–2: Fault Injection Register and Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 Table 15–3: CRC_ERROR Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 Table 15–4: Error Detection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 Table 15–5: Minimum and Maximum Error Detection Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 Table 15–6: Minimum Update Interval for Error Message Register (Note 1) . . . . . . . . . . . . . . . . . . . . 15-10 Table 15–7: CRC Calculation Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 Table 15–8: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 Table 16–1: Stratix III Programmable Power Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 Table 16–2: Stratix III Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 Table 16–3: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 Table 17–1: FineLine and Hybrid FineLine BGA Packages for Stratix III Devices . . . . . . . . . . . . . . . . . . . 17-1 Table 17–2: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xxiv Stratix III Device Handbook, Volume 1 List of Tables © March 2011 Altera Corporation Additional Information This handbook provides comprehensive information about the Altera® Stratix ® III family of devices. How to Contact Altera For the most up-to-date information about Altera products, see the following table. Contact (Note 1) Contact Method Address Technical support Website www.altera.com/support Technical training Website www.altera.com/training Email custrain@altera.com Product literature Website www.altera.com/literature Non-technical support (General) Email nacomp@altera.com (Software Licensing) Email authorization@altera.com Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Meaning Bold Type with Initial Capital Letters Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. bold type External timing parameters, directory names, project names, disk drive names, file names, file name extensions, and software utility names are shown in bold type. Examples: fMAX , \qdesigns directory, d: drive, chiptrip.gdf file. Italic Type with Initial Capital Letters Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA , n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: , .pof file. Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. “Subheading Title” References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.” © March 2011 Altera Corporation Stratix III Device Handbook, Volume 1 xxvi Typographic Conventions Visual Cue Courier type Meaning Signal and port names are shown in lowercase Courier type. Examples: data1 , tdi , input. Active-low signals are denoted by suffix n , e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN ), as well as logic function names (e.g., TRI ) are shown in Courier. 1., 2., 3., and a., b., c., etc. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. ■ ■ Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. c A caution calls attention to a condition or possible situation that can damage or destroy the product or the user’s work. w A warning calls attention to a condition or possible situation that can cause injury to the user. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation Section I. Device Core This section provides a complete overview of all features relating to the Stratix® III device family, which is the most architecturally advanced, high performance, low power FPGA in the market place. This section includes the following chapters: ■ Chapter 1, Stratix III Device Family Overview ■ Chapter 2, Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices ■ Chapter 3, MultiTrack Interconnect in Stratix III Devices ■ Chapter 4, TriMatrix Embedded Memory Blocks in Stratix III Devices ■ Chapter 5, DSP Blocks in Stratix III Devices ■ Chapter 6, Clock Networks and PLLs in Stratix III Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © July 2010 Altera Corporation Stratix III Device Handbook, Volume 1 I–2 Stratix III Device Handbook, Volume 1 Section I: Device Core Revision History © July 2010 Altera Corporation 1. Stratix III Device Family Overview SIII51001-1.8 The Stratix ® III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace. Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’s lowest power, high-performance FPGAs. Specifically designed for ease of use and rapid system integration, the Stratix III FPGA family offers two variants optimized to meet different application needs: ■ The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. ■ The Stratix III E family is memory- and multiplier-rich for data-centric applications. Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high-speed I/O. Package and die enhancements with dynamic on-chip termination, output delay, and current strength control provide best-in-class signal integrity. Based on a 1.1-V, 65-nm all-layer copper SRAM process, the Stratix III family is a programmable alternative to custom ASICs and programmable processors for high-performance logic, digital signal processing (DSP), and embedded designs. Stratix III devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, Stratix III devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells. Features Summary Stratix III devices offer the following features: © March 2010 ■ 48,000 to 338,000 equivalent logic elements (LEs) (refer to Table 1–1) ■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers ■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters ■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity ■ Programmable Power Technology, which minimizes power while maximizing device performance Altera Corporation Stratix III Device Handbook, Volume 1 1–2 Chapter 1: Stratix III Device Family Overview Features Summary ■ Selectable Core Voltage, available in low-voltage devices (L ordering code suffix), enables selection of lowest power or highest performance operation ■ Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device ■ Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting ■ Memory interface support with dedicated DQS logic on all I/O banks ■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks ■ Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide range of industry I/O standards ■ Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O banks ■ High-speed differential I/O support with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance ■ Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI ■ The only high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to protect designs ■ Robust on-chip hot socketing and power sequencing support ■ Integrated cyclical redundancy check (CRC) for configuration memory error detection with critical error determination for high availability systems support ■ Built-in error correction coding (ECC) circuitry to detect and correct data errors in M144K TriMatrix memory blocks ■ Nios® II embedded processor support ■ Support for multiple intellectual property megafunctions from Altera ® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Features Summary 1–3 Table 1–1 lists the Stratix III FPGA family features. Table 1–1. FPGA Family Features for Stratix III Devices Device/ Feature Stratix III Logic Family Stratix III Enhanced Family M144K Blocks Total MLAB Embedded Blocks RAM Kbits MLAB RAM Kbits (1) 18×18-bit Total Multipliers RAM Kbits(2) (FIR Mode) PLLs (3) ALMs LEs M9K Blocks EP3SL50 19K 47.5K 108 6 950 1,836 297 2,133 216 4 EP3SL70 27K 67.5K 150 6 1,350 2,214 422 2,636 288 4 EP3SL110 43K 107.5K 275 12 2,150 4,203 672 4,875 288 8 EP3SL150 57K 142.5K 355 16 2,850 5,499 891 6,390 384 8 EP3SL200 80K 200K 468 36 4,000 9,396 1,250 10,646 576 12 EP3SL340 135K 337.5K 1,040 48 6,750 16,272 2,109 18,381 576 12 EP3SE50 19K 47.5K 400 12 950 5,328 297 5,625 384 4 EP3SE80 32K 80K 495 12 1,600 6,183 500 6,683 672 8 EP3SE110 43K 107.5K 639 16 2,150 8,055 672 8,727 896 8 EP3SE260 102K 255K 864 48 5,100 14,688 1,594 16,282 768 12 Notes to Table 1–1: (1) MLAB ROM mode supports twice the number of MLAB RAM Kbits. (2) For total ROM Kbits, use this equation to calculate: Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024] (3) The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the Clock Networks and PLLs in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook for the availability of the PLLs for each device. The Stratix III logic family (L) offers balanced logic, memory, and multipliers to address a wide range of applications, while the enhanced family (E) offers more memory and multipliers per logic and is ideal for wireless, medical imaging, and military applications. Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer to Table 1–2 and Table 1–3). © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 1–4 Chapter 1: Stratix III Device Family Overview Features Summary Table 1–2 lists the Stratix III FPGA package options and I/O pin counts. Table 1–2. Package Options and I/O Pin Counts (Note 1) 484-Pin FineLine BGA (2) 780-Pin FineLine BGA (2) 1152-Pin FineLine BGA (2) 1517-Pin FineLine BGA (3) 1760-Pin FineLine BGA (3) EP3SL50 296 488 — — — EP3SL70 296 488 — — — EP3SL110 — 488 744 — — EP3SL150 — 488 744 — — EP3SL200 — 488 (5) 744 976 — Device EP3SL340 — — 744 (4) 976 1,120 EP3SE50 296 488 — — — EP3SE80 — 488 744 — — EP3SE110 — 488 744 — — EP3SE260 — 488 (5) 744 976 — Notes to Table 1–2: (1) The arrows indicate vertical migration. (2) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) that can be used for data inputs. (3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, and PLL_R1_CLKn) that can be used for data inputs. (4) The EP3SL340 FPGA is offered only in the H1152 package, but not offered in the F1152 package. (5) The EP3SE260 and EP3SL200 FPGAs are offered only in the H780 package, but not offered in the F780 package. All Stratix III devices support vertical migration within the same package (for example, you can migrate between the EP3SL50 and EP3SL70 devices in the 780-pin FineLine BGA package). Vertical migration allows you to migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. To ensure that a board layout supports migratable densities within one package offering, enable the applicable vertical migration path within the Quartus® II software. On the Assignments menu, point to Device and click Migration Devices. You can migrate from the L family to the E family without increasing the number of LEs available. This minimizes the cost of vertical migration. Table 1–3 lists the Stratix III FineLine BGA (FBGA) package sizes. Table 1–3. FineLine BGA Package Sizes Dimension 484 Pin 780 Pin 1152 Pin 1517 Pin 1760 Pin Pitch (mm) 1.00 1.00 1.00 1.00 1.00 Area (mm2) 529 841 1,225 1,600 1,849 23/23 29/29 35/35 40/40 43/43 Length/Width (mm/ mm) Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Features Summary 1–5 Table 1–4 lists the Stratix III Hybrid FineLine BGA (HBGA) package sizes. Table 1–4. Hybrid FineLine BGA Package Sizes Dimension 780 Pin 1152 Pin Pitch (mm) 1.00 1.00 Area (mm ) 1,089 1,600 Length/Width (mm/ mm) 33/33 40/40 2 Stratix III devices are available in up to three speed grades: –2, –3, and –4, with –2 being the fastest. Stratix III devices are offered in both commercial and industrial temperature range ratings with leaded and lead-free packages. Selectable Core Voltage is available in specially marked low-voltage devices (L ordering code suffix). Table 1–5 lists the Stratix III device speed grades. Table 1–5. Speed Grades for Stratix III Devices (Part 1 of 2) Device EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 © March 2010 Temperature Grade 484 -Pin FineLine BGA 780-Pin FineLine BGA 780-Pin Hybrid FineLine BGA 1152-Pin FineLine BGA 1152-Pin Hybrid FineLine BGA 1517-Pin FineLine BGA 1760-Pin FineLine BGA Commercial –2, –3, –4, –4L –2, –3,–4, –4L — — — — — Industrial –3, –4, –4L –3, –4, –4L — — — — — Commercial –2, –3, –4, –4L –2, –3, –4, –4L — — — — — Industrial –3, –4, –4L –3, –4, –4L — — — — — Commercial — –2, –3, –4, –4L — –2, –3, –4, –4L — — — Industrial — –3, –4, –4L — –3, –4, –4L — — — Commercial — –2,–3, –4, –4L — –2, –3, –4, –4L — — — Industrial — –3, –4, –4L — –3, –4, –4L — — — Commercial — — –2,–3, –4, –4L –2,–3, –4, –4L — –2,–3, –4, –4L — Industrial (1) — — –3, –4, –4L –3, –4, –4L — –3, –4, –4L — Commercial — — — — –2, –3, –4 –2, –3, –4 –2, –3, –4 Industrial (1) — — — — –3, –4, –4L –3, –4, –4L –3, –4, –4L Commercial –2, –3, –4, –4L –2, –3, –4, –4L — — — — — Industrial –3, –4, –4L –3, –4, –4L — — — — — Commercial — –2, –3, –4, –4L — –2, –3, –4, –4L — — — Industrial — –3, –4, –4L — –3, –4, –4L — — — Commercial — –2,–3, –4, –4L — –2, –3, –4, –4L — — — Industrial — –3, –4, –4L — –3, –4, –4L — — — Altera Corporation Stratix III Device Handbook, Volume 1 1–6 Chapter 1: Stratix III Device Family Overview Architecture Features Table 1–5. Speed Grades for Stratix III Devices (Part 2 of 2) Device EP3SE260 484 -Pin FineLine BGA 780-Pin FineLine BGA 780-Pin Hybrid FineLine BGA 1152-Pin FineLine BGA 1152-Pin Hybrid FineLine BGA 1517-Pin FineLine BGA 1760-Pin FineLine BGA Commercial — — –2, –3, –4, –4L –2,– 3, –4, –4L — –2, –3, –4, –4L — Industrial (1) — — –3, –4, –4L –3, –4, –4L — –3, –4,–4L — Temperature Grade Note to Table 1–5: (1) For EP3SL340, EP3SL200, and EP3SE260 devices, the industrial junction temperature range for –4L is 0–100°C, regardless of supply voltage. Architecture Features The following section describes the various features of the Stratix III family FPGAs. Logic Array Blocks and Adaptive Logic Modules The Logic Array Block (LAB) is composed of basic building blocks known as Adaptive Logic Modules (ALMs) that can be configured to implement logic, arithmetic, and register functions. Each LAB consists of ten ALMs, carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. ALMs are part of a unique, innovative logic structure that delivers faster performance, minimizes area, and reduces power consumption. ALMs expand the traditional 4-input look-up table architecture to 7 inputs, increasing performance by reducing LEs, logic levels, and associated routing. In addition, ALMs maximize DSP performance with dedicated functionality to efficiently implement adder trees and other complex arithmetic functions. The Quartus II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. The Stratix III LAB has a new derivative called Memory LAB (or MLAB), which adds SRAM memory capability to the LAB. MLAB is a superset of the LAB and includes all LAB features. MLABs support a maximum of 320 bits of simple dual-port Static Random Access Memory (SRAM). Each ALM in an MLAB can be configured as a 16×2 block, resulting in a configuration of 16×20 simple dual port SRAM block. MLAB and LAB blocks always co-exist as pairs in all Stratix III families, allowing up to 50% of the logic (LABs) to be traded for memory (MLABs). f For more information about LABs and ALMs, refer to the Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices chapter. f For more information about MLAB modes, features and design considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Architecture Features 1–7 MultiTrack Interconnect In the Stratix III architecture, connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDrive technology. The MultiTrack interconnect consists of continuous, performance-optimized row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. The MultiTrack interconnect provides 1-hop connection to 34 adjacent LABs, 2-hop connections to 96 adjacent LABs and 3-hop connections to 160 adjacent LABs. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the reoptimization cycles that typically follow design changes and additions. The Quartus II Compiler also automatically places critical design paths on faster interconnects to improve design performance. f For more information, refer to the MultiTrack Interconnect in Stratix III Devices chapter. TriMatrix Embedded Memory Blocks TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes the following blocks: ■ 320-bit MLAB blocks optimized to implement filter delay lines, small FIFO buffers, and shift registers ■ 9-Kbit M9K blocks that can be used for general purpose memory applications ■ 144-Kbit M144K blocks that are ideal for processor code storage, packet and video frame buffering Each embedded memory block can be independently configured to be a single- or dual-port RAM, ROM, or shift register via the Quartus II MegaWizardTM Plug-In Manager. Multiple blocks of the same type can also be stitched together to produce larger memories with minimal timing penalty. TriMatrix memory provides up to 16,272 Kbits of embedded SRAM at up to 600 MHz operation. f For more information about TriMatrix memory blocks, modes, features, and design considerations, refer to the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter. DSP Blocks Stratix III devices have dedicated high-performance digital signal processing (DSP) blocks optimized for DSP applications requiring high data throughput. Stratix III devices provide you with the ability to implement various high-performance DSP functions easily. Complex systems such as WiMAX, 3GPP WCDMA, CDMA2000, voice over Internet Protocol (VoIP), H.264 video compression, and high-definition television (HDTV) require high-performance DSP blocks to process data. These system designs typically use DSP blocks to implement finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 1–8 Chapter 1: Stratix III Device Family Overview Architecture Features Stratix III devices have up to 112 DSP blocks. The architectural highlights of the Stratix III DSP block are the following: ■ High-performance, power optimized, fully pipelined multiplication operations ■ Native support for 9-bit, 12-bit, 18-bit, and 36-bit word lengths ■ Native support for 18-bit complex multiplications ■ Efficient support for floating point arithmetic formats (24-bit for Single Precision and 53-bit for Double Precision) ■ Signed and unsigned input support ■ Built-in addition, subtraction, and accumulation units to efficiently combine multiplication results ■ Cascading 18-bit input bus to form tap-delay lines ■ Cascading 44-bit output bus to propagate output results from one block to the next block ■ Rich and flexible arithmetic rounding and saturation units ■ Efficient barrel shifter support ■ Loopback capability to support adaptive filtering DSP block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on user configuration. This option saves ALM routing resources and increases performance, because all connections and blocks are inside the DSP block. Additionally, the DSP Block input registers can efficiently implement shift registers for FIR filter applications, and the Stratix III DSP blocks support rounding and saturation. The Quartus II software includes megafunctions that control the mode of operation of the DSP blocks based on user parameter settings. f For more information, refer to the DSP Blocks in Stratix III Devices chapter. Clock Networks and PLLs Stratix III devices provide dedicated Global Clock Networks (GCLKs), Regional Clock Networks (RCLKs), and Periphery Clock Networks (PCLKs). These clocks are organized into a hierarchical clock structure that provides up to 104 unique clock domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16 GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant. Stratix III devices deliver abundant PLL resources with up to 12 PLLs per device and up to 10 outputs per PLL. Every output can be independently programmed, creating a unique, customizable clock frequency. Inherent jitter filtration and fine granularity control over multiply, divide ratios, and dynamic phase-shift reconfiguration provide the high-performance precision required in today’s high-speed applications. Stratix III PLLs are feature rich, supporting advanced capabilities such as clock switchover, reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs can be used for general-purpose clock management supporting multiplication, phase shifting, and programmable duty cycle. Stratix III PLLs also support external feedback mode, spread-spectrum input clock tracking, and post-scale counter cascading. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Architecture Features f 1–9 For more information, refer to the Clock Networks and PLLs in Stratix III Devices chapter. I/O Banks and I/O Structure Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32, 36, 40, or 48 I/Os. This modular bank structure improves pin efficiency and eases device migration. The I/O banks contain circuitry to support external memory interfaces at speeds up to 533 MHz and high-speed differential I/O interfaces meeting up to 1.6 Gbps performance. It also supports high-speed differential inputs and outputs running at speeds up to 800 MHz. Stratix III devices support a wide range of industry I/O standards, including single-ended, voltage referenced single-ended, and differential I/O standards. The Stratix III I/O supports programmable bus hold, programmable pull-up resistor, programmable slew rate, programmable drive strength, programmable output delay control, and open-drain output. Stratix III devices also support on-chip series (RS) and on-chip parallel (RT) termination with auto calibration for single-ended I/O standards and on-chip differential termination (RD) for LVDS I/O standards on Left/Right I/O banks. Dynamic OCT is also supported on bi-directional I/O pins in all I/O banks. f For more information, refer to the Stratix III Device I/O Features chapter. External Memory Interfaces The Stratix III I/O structure has been completely redesigned to provide flexibility and enable high-performance support for existing and emerging external memory standards such as DDR, DDR2, DDR3, QDR II, QDR II+, and RLDRAM II at frequencies of up to 533 MHz. Packed with features such as dynamic on-chip termination, trace mismatch compensation, read/write leveling, half-rate registers, and 4-to 36-bit programmable DQ group widths, Stratix III I/Os supply the built-in functionality required for rapid and robust implementation of external memory interfaces. Double data-rate support is found on all sides of the Stratix III device. Stratix III devices provide an efficient architecture to quickly and easily fit wide external memory interfaces exactly where you want them. A self-calibrating soft IP core (ALTMEMPHY), optimized to take advantage of the Stratix III device I/O, along with the Quartus II timing analysis tool (TimeQuest), provide the total solution for the highest reliable frequency of operation across process voltage and temperature. f For more information about external memory interfaces, refer to the External Memory Interfaces in Stratix III Devices chapter. High-Speed Differential I/O Interfaces with DPA Stratix III devices contain dedicated circuitry for supporting differential standards at speeds up to 1.6 Gbps. The high-speed differential I/O circuitry supports the following high-speed I/O interconnect standards and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 1–10 Chapter 1: Stratix III Device Family Overview Architecture Features 4×, 6×, 7×, 8×, and 10× SERDES modes when using the dedicated DPA circuitry. DPA minimizes bit errors, simplifies PCB layout and timing management for high-speed data transfer, and eliminates channel-to-channel and channel-to-clock skew in high-speed data transmission systems. Soft CDR can also be implemented, enabling low-cost 1.6-Gbps clock embedded serial links. Stratix III devices have the following dedicated circuitry for high-speed differential I/O support: f ■ Differential I/O buffer ■ Transmitter serializer ■ Receiver deserializer ■ Data realignment ■ Dynamic phase aligner (DPA) ■ Soft CDR functionality ■ Synchronizer (FIFO buffer) ■ PLLs For more information, refer to the High Speed Differential I/O Interfaces with DPA in Stratix III Devices chapter. Hot Socketing and Power-On Reset Stratix III devices are hot-socketing compliant. Hot socketing is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. Robust on-chip hot-socketing and power-sequencing support ensures proper device operation independent of the power-up sequence. You can insert or remove a Stratix III board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot-socketing feature makes it easier to use Stratix III devices on PCBs that also contain a mixture of 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V devices. With the Stratix III hot socketing feature, you do not need to ensure a specific power-up sequence for each device on the board. f For more information, refer to the Hot Socketing and Power-On Reset in Stratix III Devices chapter. Configuration Stratix III devices are configured using one of the following four configuration schemes: ■ Fast passive parallel (FPP) ■ Fast active serial (AS) ■ Passive serial (PS) ■ Joint Test Action Group (JTAG) All configuration schemes use either an external controller (for example, a MAX® II device or microprocessor), a configuration device, or a download cable. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Architecture Features 1–11 Stratix III devices support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to Stratix III devices. During configuration, the Stratix III device decompresses the bitstream in real time and programs its SRAM cells. Stratix III devices support decompression in the FPP when using a MAX II device/microprocessor plus flash, fast AS, and PS configuration schemes. The Stratix III decompression feature is not available in the FPP when using the enhanced configuration device and JTAG configuration schemes. f For more information, refer to the Configuring Stratix III Devices chapter. Remote System Upgrades Stratix III devices feature remote system upgrade capability, allowing error-free deployment of system upgrades from a remote location securely and reliably. Soft logic (either the Nios embedded processor or user logic) implemented in a Stratix III device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, and can recover from an error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry is unique to Stratix series FPGAs and helps to avoid system downtime. f For more information, refer to the Remote System Upgrades with Stratix III Devices chapter. IEEE 1149.1 (JTAG) Boundary-Scan Testing Stratix III devices support the JTAG IEEE Std. 1149.1 specification. The Boundary-Scan Test (BST) architecture offers the capability to test pin connections without using physical test probes and capture functional data while a device is operating normally. Boundary-scan cells in the Stratix III device can force signals onto pins or capture data from pin or logic array signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results. In addition to BST, you can use the IEEE Std. 1149.1 controller for Stratix III device in-circuit reconfiguration (ICR). f For more information, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices chapter. Design Security Stratix III devices are high-density, high-performance FPGAs with support for 256-bit volatile and non-volatile security keys to protect designs against copying, reverse engineering, and tampering. Stratix III devices have the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm, an industry standard encryption algorithm that is FIPS-197 certified and requires a 256-bit security key. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 1–12 Chapter 1: Stratix III Device Family Overview Architecture Features The design security feature is available when configuring Stratix III FPGAs using the fast passive parallel (FPP) configuration mode with an external host (such as a MAX II device or microprocessor), or when using fast active serial (AS) or passive serial (PS) configuration schemes. f For more information about the design security feature, refer to the Design Security in Stratix III Devices chapter. SEU Mitigation Stratix III devices have built-in error detection circuitry to detect data corruption due to soft errors in the configuration random-access memory (CRAM) cells. This feature allows all CRAM contents to be read and verified continuously during user mode operation to match a configuration-computed CRC value. The enhanced CRC circuit and frame-based configuration architecture allows detection and location of multiple, single, and adjacent bit errors which, in conjunction with a soft circuit supplied as a reference design, allows don’t-care soft errors in the CRAM to be ignored during device operation. This provides a steep decrease in the effective soft error rate, increasing system reliability. On-chip memory block SEU mitigation is also offered using the ninth bit and a configurable megafunction in the Quartus II software for MLAB and M9K blocks while the M144K memory blocks have built-in error correction code (ECC) circuitry. f For more information about the dedicated error detection circuitry, refer to the SEU Mitigation in Stratix III Devices chapter. Programmable Power Stratix III delivers Programmable Power, the only FPGA with user programmable power options balancing today’s power and performance requirements. Stratix III devices utilize the most advanced power-saving techniques, including a variety of process, circuit, and architecture optimizations and innovations. In addition, user controllable power reduction techniques provide an optimal balance of performance and power reduction specific for each design configured into the Stratix III FPGA. The Quartus II software (starting from version 6.1) automatically optimizes designs to meet the performance goals while simultaneously leveraging the programmable power-saving options available in the Stratix III FPGA without the need for any changes to the design flow. f For more information about Programmable Power in Stratix III devices, refer to the following documents: ■ Programmable Power and Temperature Sensing Diode in Stratix III Devices chapter ■ AN 437: Power Optimization in Stratix III FPGAs ■ Stratix III Programmable Power White Paper Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Reference and Ordering Information 1–13 Signal Integrity Stratix III devices simplify the challenge of signal integrity through a number of chip, package, and board level enhancements to enable efficient high-speed data transfer into and out of the device. These enhancements include: ■ 8:1:1 user I/O/Gnd/VCC ratio to reduce the loop inductance in the package ■ Dedicated power supply for each I/O bank, limit of I/Os is 24 to 48 I/Os per bank, to help limit simultaneous switching noise ■ Programmable slew-rate support with up to four settings to match desired I/O standard, control noise, and overshoot ■ Programmable output-current drive strength support with up to six settings to match desired I/O standard performance ■ Programmable output-delay support to control rise/fall times and adjust duty cycle, compensate for skew, and reduce simultaneous switching outputs (SSO) noise ■ Dynamic OCT with auto calibration support for series and parallel OCT and differential OCT support for LVDS I/O standard on the left/right banks f For more information about SI support in the Quartus II software, refer to the Quartus II Handbook. f For more information about how to use the various configuration, PLL, external memory interfaces, I/O, high-speed differential I/O, power, and JTAG pins, refer to the Stratix III Device Family Pin Connection Guidelines. Reference and Ordering Information The following section describes Stratix III device software support and ordering information. Software Support Stratix III devices are supported by the Altera Quartus II design software, version 6.1 and later, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap® II logic analyzer, and device configuration. f For more information about the Quartus II software features, refer to the Quartus II Handbook. The Quartus II software supports a variety of operating systems. The specific operating system for the Quartus II software can be obtained from the Quartus II Readme.txt file or the Operating System Support section of the Altera website. It also supports seamless integration with industry-leading EDA tools through the NativeLink ® interface. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 1–14 Chapter 1: Stratix III Device Family Overview Chapter Revision History Ordering Information Figure 1–1 shows the ordering codes for Stratix III devices. f For more information about a specific package, refer to the Stratix III Device Package Information chapter. Figure 1–1. Stratix III Device Packaging Ordering Information EP3SL 150 F 1152 C 2 ES Family Signature Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices L: Low-voltage devices EP3SL: Stratix III Logic EP3SE: Stratix III DSP/Memory Device Type Speed Grade 50 70 80 110 150 200 260 340 2, 3, or 4, with 2 being the fastest Operating Temperature C: Commercial temperature (t J = 0 C to 85 C) I : Industrial temperature (t J = - 40 C to 100 C) Package Type Pin Count Number of pins for a particular package: 484 780 1152 1517 1760 F: FineLine BGA (FBGA) H: Hybrid FineLine BGA (HBGA) Chapter Revision History Table 1–6 lists the revision history for this chapter. Table 1–6. Chapter Revision History (Part 1 of 2) Date Version Changes Made Updated for the Quartus II software version 9.1 SP2 release: March 2010 1.8 ■ Updated Table 1–2. ■ Updated “I/O Banks and I/O Structure” section. May 2009 1.7 Updated “Software” and “Signal Integrity” sections. February 2009 October 2008 1.6 1.5 Stratix III Device Handbook, Volume 1 ■ Updated “Features” section. ■ Updated Table 1–1. ■ Removed “Referenced Documents” section. ■ Updated “Features” section. ■ Updated Table 1–1 and Table 1–5. ■ Updated New Document Format. © March 2010 Altera Corporation Chapter 1: Stratix III Device Family Overview Chapter Revision History 1–15 Table 1–6. Chapter Revision History (Part 2 of 2) Date Version May 2008 1.4 November 2007 October 2007 1.3 1.2 Changes Made ■ Updated “Introduction”. ■ Updated Table 1–1. ■ Updated Table 1–2. ■ Added Table 1–5. ■ Updated “Reference and Ordering Information”. ■ Updated package type information in Figure 1–1. ■ Updated Table 1–1. ■ Updated Table 1–2. ■ Minor typo fixes. ■ Added Table 1–4. ■ Added section “Referenced Documents”. ■ Added live links for references. May 2007 1.1 Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in Table 1–1. November 2006 1.0 Initial Release. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 1–16 Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview Chapter Revision History © March 2010 Altera Corporation 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices SIII51002-1.5 Introduction This chapter describes the features of the logic array block (LAB) in the Stratix® III core fabric. The logic array block is composed of basic building blocks known as adaptive logic modules (ALMs) that can be configured to implement logic functions, arithmetic functions, and register functions. Logic Array Blocks Each LAB consists of ten ALMs, carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. The direct link interconnect allows a LAB to drive into the local interconnect of its left and right neighbors. Register chain connections transfer the output of the ALM register to the adjacent ALM register in an LAB. The Quartus® II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Figure 2–1 shows the Stratix III LAB structure and the LAB interconnects. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–2 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Logic Array Blocks Figure 2–1. Stratix III LAB Structure C4 C12 Row Interconnects of Variable Speed & Length R20 R4 ALMs Direct link interconnect from adjacent block Direct link interconnect from adjacent block Direct link interconnect to adjacent block Direct link interconnect to adjacent block Local Interconnect LAB MLAB Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows Column Interconnects of Variable Speed & Length The LAB of Stratix III has a new derivative called Memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB as shown in Figure 2–2. The MLAB supports a maximum of 320-bits of simple dual-port static random access memory (SRAM). You can configure each ALM in an MLAB as a 16 × 2 block, resulting in a configuration of 16 × 20 simple dual port SRAM block. MLAB and LAB blocks always co-exist as pairs in all Stratix III families. MLAB is a superset of the LAB and includes all LAB features. Figure 2–2 shows an overview of LAB and MLAB topology. f The MLAB is described in detail in the TriMatrix Embedded Memory Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Logic Array Blocks 2–3 Figure 2–2. Stratix III LAB and MLAB Structure LUT-based-16 x 2 Simple dual port SRAM (1) ALM LUT-based-16 x 2 Simple dual port SRAM (1) LUT-based-16 x 2 Simple dual port SRAM (1) LUT-based-16 x 2 Simple dual port SRAM (1) LUT-based-16 x 2 Simple dual port SRAM (1) ALM LAB Control Block (1) ALM LUT-based-16 x 2 Simple dual port SRAM (1) LUT-based-16 x 2 Simple dual port SRAM (1) LUT-based-16 x 2 Simple dual port SRAM (1) LUT-based-16 x 2 Simple dual port SRAM (1) MLAB ALM ALM LAB Control Block LUT-based-16 x 2 Simple dual port SRAM ALM ALM ALM ALM ALM LAB Note to Figure 2–2: (1) You can use MLAB ALM as a regular LAB ALM or configure it as a dual-port SRAM, as shown. LAB Interconnects The LAB local interconnect can drive ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs/MLABs, M9K RAM blocks, M144K blocks, or DSP blocks from the left and right can also drive a LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 30 ALMs through fast local and direct link interconnects. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–4 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Logic Array Blocks Figure 2–3shows the direct link connection. Figure 2–3. Direct Link Connection Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output ALMs ALMs Direct link interconnect to right Direct link interconnect to left Local Interconnect MLAB LAB LAB Control Signals Each LAB contains dedicated logic for driving control signals to its ALMs. The control signals include three clocks, three clock enables, two asynchronous clears, a synchronous clear, and synchronous load control signals. This gives a maximum of 10 control signals at a time. Although you generally use synchronous load and clear signals when implementing counters, you can also use them with other functions. Each LAB has two unique clock sources and three clock enable signals, as shown in Figure 2–4. The LAB control block can generate up to three clocks using the two clock sources and three clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any ALM in a particular LAB using the labclk1 signal also uses labclkena1 signal. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2–4shows the LAB control signal generation circuit. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules 2–5 Figure 2–4. LAB-Wide Control Signals There are two unique clock signals per LAB. 6 Dedicated Row LAB Clocks 6 6 Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk0 labclk1 labclkena0 or asyncload or labpreset labclk2 labclkena1 labclkena2 labclr1 syncload labclr0 synclr Adaptive Logic Modules The basic building block of logic in the Stratix III architecture, the adaptive logic module (ALM), provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs to the two combinational ALUTs, one ALM can implement various combinations of two functions. This adaptability allows an ALM to be completely backwardcompatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions. In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, an ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure 2–5 shows a high-level block diagram of the Stratix III ALM while Figure 2–6 shows a detailed view of all the connections in an ALM. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–6 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Figure 2–5. High-Level Block Diagram of the Stratix III ALM shared_arith_in carry_in Combinational/Memory ALUT0 reg_chain_in labclk To general or local routing dataf0 datae0 6-Input LUT adder0 D Q dataa To general or local routing reg0 datab datac datad datae1 adder1 D Q 6-Input LUT To general or local routing reg1 dataf1 To general or local routing Combinational/Memory ALUT1 reg_chain_out shared_arith_out Stratix III Device Handbook, Volume 1 carry_out © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules 2–7 sclr carry_out shared_arith_out dataf1 datae1 3-INPUT LUT 3-INPUT LUT + 3-INPUT LUT 3-INPUT LUT 4-INPUT LUT datad datac dataa datab datae0 dataf0 4-INPUT LUT shared_arith_in + carry_in VCC GND clk[2:0] syncload aclr[1:0] reg_chain_in D D CLR CLR Q reg_chain_out row, column direct link routing row, column direct link routing local interconnect row, column direct link routing row, column direct link routing Q local interconnect Figure 2–6. Stratix III ALM Details One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, and synchronous load/clear inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of an ALM. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–8 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers (refer to Figure 2–6). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output. ALM Operating Modes The Stratix III ALM can operate in one of the following modes: ■ Normal ■ Extended LUT Mode ■ Arithmetic ■ Shared Arithmetic ■ LUT-Register Each mode uses ALM resources differently. In each mode, eleven available inputs to an ALM—the eight data inputs from the LAB local interconnect, carry-in from the previous ALM or LAB, the shared arithmetic chain connection from the previous ALM or LAB, and the register chain connection—are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all ALM modes. 1 Refer to “LAB Control Signals” on page 2–4 for more information on the LAB-wide control signals. The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. Normal Mode The normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The normal mode allows two functions to be implemented in one Stratix III ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs. Figure 2–7 shows the supported LUT combinations in normal mode. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Figure 2–7. ALM in Normal Mode dataf0 datae0 datac dataa 4-Input LUT datab datad datae1 dataf1 4-Input LUT dataf0 datae0 datac dataa datab 5-Input LUT datad datae1 dataf1 3-Input LUT dataf0 datae0 datac dataa datab 5-Input LUT 4-Input LUT datad datae1 dataf1 2–9 (Note 1) combout0 dataf0 datae0 datac dataa datab 5-Input LUT combout0 5-Input LUT combout1 dataf0 datae0 dataa datab datac datad 6-Input LUT combout0 dataf0 datae0 dataa datab datac datad 6-Input LUT combout0 6-Input LUT combout1 combout1 datad datae1 dataf1 combout0 combout1 combout0 combout1 datae1 dataf1 Note to Figure 2–7: (1) Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2. The normal mode provides complete backward compatibility with four-input LUT architectures. For the packing of 2 five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–10 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules In the case of implementing 2 six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4 × 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one ALM, as shown in Figure 2–8. The shared inputs are dataa, datab, datac, and datad, while the unique select lines are datae0 and dataf0 for function0, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture. Figure 2–8. 4 × 2 Crossbar Switch Example 4 × 2 Crossbar Switch sel0[1..0] inputa inputb out0 inputc inputd Implementation in 1 ALM dataf0 datae0 dataa datab datac datad Six-Input LUT (Function0) combout0 Six-Input LUT (Function1) combout1 out1 sel1[1..0] datae1 dataf1 In a sparsely used device, functions that could be placed into one ALM may be implemented in separate ALMs by the Quartus II software in order to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically utilizes the full potential of the Stratix III ALM. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments. Any six-input function can be implemented utilizing inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are utilized, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (refer to Figure 2–9). If datae1 and dataf1 are utilized, the output drives to register1 and/or bypasses register1 and drives to the interconnect using the bottom set of output drivers. The Quartus II Compiler automatically selects the inputs to the LUT. ALMs in normal mode support register packing. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Figure 2–9. Input Function in Normal Mode 2–11 (Note 1) To general or local routing dataf0 datae0 dataa datab datac datad 6-Input LUT D Q To general or local routing reg0 datae1 dataf1 (2) D Q To general or local routing reg1 labclk These inputs are available for register packing. Notes to Figure 2–9: (1) If datae1 and dataf1 are used as inputs to the six-input function, then datae0 and dataf0 are available for register packing. (2) The dataf1 input is available for register packing only if the six-input function is un-registered. Extended LUT Mode Use the extended LUT mode to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. Figure 2–10 shows the template of supported seven-input functions utilizing extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the template shown in Figure 2–10 occur naturally in designs. These functions often appear in designs as "if-else" statements in Verilog HDL or VHDL code. Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode datae0 datac dataa datab datad dataf0 5-Input LUT To general or local routing combout0 D 5-Input LUT Q To general or local routing reg0 datae1 dataf1 (1) This input is available for register packing. Note to Figure 2–10: (1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available. Arithmetic Mode The arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. The ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of 2 four-input functions. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–12 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules The four LUTs share the dataa and datab inputs. As shown in Figure 2–11, the carry-in signal feeds to adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs. Figure 2–11. ALM in Arithmetic Mode carry_in datae0 adder0 4-Input LUT To general or local routing D dataf0 datac datab dataa To general or local routing reg0 4-Input LUT adder1 4-Input LUT datad datae1 Q To general or local routing D 4-Input LUT Q To general or local routing reg1 dataf1 carry_out While operating in arithmetic mode, the ALM can support simultaneous use of the adder's carry output along with combinational logic outputs. In this operation, the adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–12. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules 2–13 Figure 2–12. Conditional Operation Example Adder output is not used. ALM 1 X[0] Comb & Adder Logic Y[0] X[0] D R[0] To general or local routing R[1] To general or local routing R[2] To general or local routing Q reg0 syncdata syncload X[1] Comb & Adder Logic Y[1] X[1] D Q reg1 syncload Carry Chain ALM 2 X[2] Y[2] Comb & Adder Logic X[2] D Q reg0 syncload Comb & Adder Logic carry_out To local routing & then to LAB-wide syncload The equation for this example is: R = (X < Y) ? Y : X To implement this function, the adder is used to subtract Y from X. If X is less than Y, the carry_out signal is 1. The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data Y drives the syncdata inputs to the registers. If X is greater than or equal to Y, the syncload signal is de-asserted and X drives the data port of the registers. The arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, and synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down, and add/subtract control signals. These control signals are good candidates for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. These signals can also be individually disabled or enabled per register. The Quartus II software automatically places any registers that are not used by the counter into other LABs. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–14 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. The two-bit carry select feature in Stratix III devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the sixth ALM in an LAB. The final carry-out signal is routed to a ALM, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 20 (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix™ memory and DSP blocks. A carry chain can continue as far as a full column. To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only utilize either the top half or the bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB within the column. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. In every alternate LAB column, the top half can be bypassed; in the other MLAB columns, the bottom half can be bypassed. 1 For more information on carry chain interconnect, refer to “ALM Interconnects” on page 2–20. Shared Arithmetic Mode In shared arithmetic mode, the ALM can implement a three-input add within an ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in the LAB) via a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Figure 2–13 shows the ALM using this feature. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules 2–15 Figure 2–13. ALM in Shared Arithmetic Mode shared_arith_in carry_in labclk 4-Input LUT To general or local routing D datae0 datac datab dataa datad datae1 Q To general or local routing reg0 4-Input LUT 4-Input LUT To general or local routing D 4-Input LUT Q To general or local routing reg1 carry_out shared_arith_out You can find adder trees in many different applications. For example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data that was transmitted utilizing spread spectrum technology. An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure 2–14. The partial sum (S[3..0]) and the partial carry (C[3..0]) is obtained using the LUTs, while the result (R[3..0]) is computed using the dedicated adders. © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–16 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Figure 2–14. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode shared_arith_in = '0' carry_in = '0' ALM Implementation ALM 1 3-Input LUT 3-Bit Add Example S0 R0 X3 X2 X1 X0 1st stage add is implemented Y3 Y2 Y1 Y0 in LUTs. + in s. 3-Input LUT C0 X1 Y1 Z1 3-Input LUT S1 3-Input LUT C1 3-Input LUT S2 Z3 Z2 Z1 Z0 S3 S2 S1 S0 2nd stage add is implemented X0 Y0 Z0 + C3 C2 C1 C0 R1 R4 R3 R2 R1 R0 Binary Add Decimal Equivalents 1110 0100 +1101 0111 +1100 14 4 + 13 7 + 2 x 12 ALM 2 R2 X2 Y2 Z2 3-Input LUT C2 X3 Y3 Z3 3-Input LUT S3 R3 31 11111 3-Input LUT C3 R4 Shared Arithmetic Chain The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a three-input add. This significantly reduces the resources necessary to implement large adder trees or correlator functions. The shared arithmetic chains can begin in either the first or sixth ALM in an LAB. The Quartus II Compiler creates shared arithmetic chains longer than 20 (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long shared arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to the carry chains, the top and bottom half of shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules 1 2–17 Refer to “ALM Interconnects” on page 2–20 for more information on shared arithmetic chain interconnect. LUT-Register Mode LUT-Register mode allows third register capability within an ALM. Two internal feedback loops allow combinational ALUT1 to implement the master latch and combinational ALUT0 to implement the slave latch needed for the third register. The LUT register shares its clock, clock enable, and asynchronous clear sources with the top dedicated register. Figure 2–15 shows the register constructed using two combinational blocks within the ALM. Figure 2–16 shows the ALM in LUT-Register mode. Figure 2–15. LUT Register from Two Combinational Blocks sumout clk aclr LUT regout 4-input LUT combout sumout datain(datac) 5-input LUT combout sclr © February 2009 Altera Corporation Stratix III Device Handbook, Volume 1 2–18 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Figure 2–16. ALM in LUT-Register Mode with 3-Register Capability clk [2:0] aclr [1:0] reg_chain_in datain DC1 lelocal 0 aclr aclr sclr regout datain latchout sdata leout 0 a regout leout 0 b E0 F1 lelocal 1 aclr datain E1 sdata F0 leout 1 a regout leout 1 b reg_chain_out Register Chain In addition to the general routing outputs, the ALMs in an LAB have register chain outputs. The register chain routing allows registers in the same LAB to be cascaded together. The register chain interconnect allows a LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between ALMs while saving local interconnect resources (refer to Figure 2–17). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules Figure 2–17. Register Chain within an LAB 2–19 (Note 1) From previous ALM within the LAB reg_chain_in labclk To general or local routing adder0 D Q To general or local routing reg0 Combinational Logic adder1 D Q To general or local routing reg1 To general or local routing To general or local routing adder0 D Q To general or local routing reg0 Combinational Logic adder1 D Q To general or local routing reg1 To general or local routing reg_chain_out To next ALM within the LAB Note to Figure 2–17: (1) You can use the combinational or adder logic to implement an unrelated, un-registered function. 1 © February 2009 For more information on register chain interconnect, refer to “ALM Interconnects” on page 2–20. Altera Corporation Stratix III Device Handbook, Volume 1 2–20 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Adaptive Logic Modules ALM Interconnects There are three dedicated paths between ALMs: Register Cascade, Carry-chain, and Shared Arithmetic chain. Stratix III devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance.Figure 2–18 shows the shared arithmetic chain, carry chain, and register chain interconnects. Figure 2–18. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects Local interconnect routing among ALMs in the LAB Carry chain & shared arithmetic chain routing to adjacent ALM ALM 1 Register chain routing to adjacent ALM's register input ALM 2 Local interconnect ALM 3 ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 ALM 9 ALM 10 f For information about routing between LABs, refer to the MultiTrack Interconnect in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Clear and Preset Logic Control LAB-wide signals control the logic for the register's clear signal. The ALM directly supports an asynchronous clear function. You can achieve the register preset through the Quartus II software’s NOT-gate push-back logic option. Each LAB supports up to two clears. Stratix III devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals. Stratix III Device Handbook, Volume 1 © February 2009 Altera Corporation Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Conclusion 2–21 LAB Power Management Techniques The following techniques are used to manage static and dynamic power consumption within the LAB: ■ Stratix III low-voltage devices (L ordering code suffix) offer selectable core voltage to reduce both DC and AC power. ■ To save AC power, Quartus II forces all adder inputs low when ALM adders are not in use. ■ Stratix III LABs operate in high-performance mode or low-power mode. The Quartus II software automatically chooses the appropriate mode for an LAB based on the design to optimize speed vs. leakage trade-offs. ■ Clocks represent a significant portion of dynamic power consumption due to their high switching activity and long paths. The LAB clock that distributes a clock signal to registers within a LAB is a significant contributor to overall clock power consumption. Each LAB's clock and clock enable signal are linked. For example, a combinational ALUT or register in a particular LAB using the labclk1 signal also uses the labclkena1 signal. To disable LAB-wide clock power consumption without disabling the entire clock tree, use the LAB-wide clock enable to gate the LAB-wide clock. The Quartus II software automatically promotes register-level clock enable signals to the LAB-level. All registers within an LAB that share a common clock and clock enable are controlled by a shared gated clock. To take advantage of these clock enables, use a clock enable construct in your HDL code for the registered logic. f Refer to the Power Optimization chapter in section 3 of the Quartus II Handbook for details on implementation. f For detailed information about Stratix III programmable power capabilities, refer to the Programmable Power and Temperature Sensing Diode in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Conclusion Logic array block and adaptive logic modules are the basic building blocks of the Stratix III device. You can use these to configure logic functions, arithmetic functions, and register functions. The ALM provides advanced features with efficient logic utilization and is completely backward-compatible. Chapter Revision History Table 2–1shows the revision history for this document. Table 2–1. Chapter Revision History(Sheet 1 of 2) Date and Revision February 2009, version 1.5 October 2008, version 1.4 © February 2009 Changes Made Removed “Referenced Documents” section. ■ Updated “LAB Control Signals”, and “Carry Chain” Sections. ■ Updated New Document Format. Altera Corporation Summary of Changes — — Stratix III Device Handbook, Volume 1 2–22 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Chapter Revision History Table 2–1. Chapter Revision History(Sheet 2 of 2) Date and Revision May 2008, version 1.3 Changes Made Updated Figure 2–2 and Figure 2–6. October 2007, version 1.2 ■ Added section “Referenced Documents”. ■ Added live links for references. May 2007, version 1.1 ■ Minor formatting changes. ■ Updated Figure 2–6 to include a missing connection. November 2006, version 1.0 Summary of Changes — Minor changes. Minor changes. Initial Release. Stratix III Device Handbook, Volume 1 — © February 2009 Altera Corporation 3. MultiTrack Interconnect in Stratix III Devices SIII51003-1.2 Introduction Stratix ® III devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures, digital signal processing (DSP) blocks, and input/output elements (IOE). These blocks communicate with themselves and to one another through a fabric of routing wires. This chapter provides details on the Stratix III core routing structure. It also describes how Stratix III block types interface to this fabric. In the Stratix III architecture, connections between adaptive logic modules (ALMs), TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDrive technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus® II Compiler automatically routes critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Row Interconnects Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory blocks in the same row. These row interconnect resources include: ■ Direct link interconnects between LABs and adjacent blocks ■ R4 interconnects traversing four blocks to the right or left ■ R20 row interconnects for high-speed access across the length of the device The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors. This capability provides fast communication between adjacent LABs and blocks without using row interconnect resources. The direct link interconnect is the fastest way to communicate between two adjacent blocks. The R4 interconnects span a combination of four LABs, memory logic array blocks (MLAB), DSP blocks, M9K blocks, and M144K blocks. Use these resources for fast row connections in a four-LAB region. Figure 3–1 shows R4 interconnect connections from a LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–2 Chapter 3: MultiTrack Interconnect in Stratix III Devices Column Interconnects interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they drive. R4 interconnects can also drive C4 and C12 (column interconnects) for connections from one row to another. Additionally, R4 interconnects can drive R20 interconnects. Figure 3–1. R4 Interconnect Connections (Note 1), (2) Adjacent LAB can Drive onto Another LAB's R4 Interconnect C4 and C12 Column Interconnects (1) R4 Interconnect Driving Right R4 Interconnect Driving Left LAB Neighbor MLAB LAB Neighbor Notes to Figure 3–1 (1) C4 and C12 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. R20 row interconnects span 20 LABs and provide the fastest resource for row connections between distant LABs, TriMatrix memory, DSP blocks, and row IOEs. R20 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R20 interconnects can drive R20, R4, C12, and C4 interconnects. Column Interconnects The column interconnect operates similarly to the row interconnect. It vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect. These column interconnect resources include: ■ Shared arithmetic chain interconnects in a LAB and from LAB to LAB ■ Carry chain interconnects in a LAB and from LAB to LAB ■ Register chain interconnects in a LAB ■ C4 interconnects traversing a distance of four blocks in the same device column ■ C12 column interconnects for high-speed vertical routing through the device Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation Chapter 3: MultiTrack Interconnect in Stratix III Devices Column Interconnects 3–3 Stratix III devices include an enhanced interconnect structure in LABs for routing-shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 3–2 shows the shared arithmetic chain, carry chain, and register chain interconnects. Figure 3–2. Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects Local Interconnect Routing Among ALMs in the LAB Carry Chain & Shared Arithmetic Chain Routing to Adjacent ALM ALM 1 Register Chain Routing to Adjacent ALM's Register Input ALM 2 Local Interconnect ALM 3 ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 ALM 9 ALM10 The C4 interconnects span four adjacent interfaces in the same device column. C4 interconnects also pass by M144K and DSP blocks. A single M144K block utilizes eight adjacent interfaces in the same column. A DSP block utilizes four adjacent interfaces in the same column. Figure 3–3 shows the C4 interconnect connections from a LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–4 Chapter 3: MultiTrack Interconnect in Stratix III Devices Column Interconnects Figure 3–3. C4 Interconnect Connections (Note 1) C4 Interconnects Drives Local and R4 Interconnects up to Four Rows C4 Interconnects Driving Up LAB R4 Interconnects Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect C4 Interconnects Driving Down Note to Figure 3–3: (1) Each C4 interconnect can drive either up or down four rows. Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation Chapter 3: MultiTrack Interconnect in Stratix III Devices Column Interconnects 3–5 C12 column interconnects span a length of 12 LABs and provide the fastest resource for column connections between distant LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C12 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array through interconnects similar to LAB-to-LAB interfaces. Each block (for example, TriMatrix memory blocks and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. Table 3–1 shows the Stratix III device's routing scheme. Table 3–1. Stratix III Device Routing Scheme C12 Inter-connect — — — — — — v — — — — — — Carry chain — — — — — — — — — v — — — — — — Register chain — — — — — — — — — v — — — — — — Local interconnect — — — — — — — — — v v v v v v v Direct link interconnect — — — v — — — — — — — — — — — — R4 interconnect — — — v — v v v v — — — — — — — R20 interconnect — — — v — v v v v — — — — — — — C4 interconnect — — — v — v — v — — — — — — — — C12 interconnect — — — v — v v v v — — — — — — — DSP Blocks Carry Chain Row IOE C4 Inter-connect — Column IOE R20 Inter-connect — MLAB RAM Block M9K RAM Block M144K Block R4 Inter-connect — Source ALM Direct Link Inter-connect Shared arithmetic chain Shared Arithmetic Chain Local Inter-connect Register Chain Destination ALM v v v v v v — v — — — — — — — — MLAB RAM block — — — v v v — v — — — — — — — — M9K RAM block — — — — v v — v — — — — — — — — M144K block — — — — v v — v — — — — — — — — DSP blocks — — — — v v — v — — — — — — — — Column IOE — — — — — — — v v — — — — — — — Row IOE — — — — v v v v — — — — — — — — Notes to Table 3–1: (1) Except column IOE local interconnects. (2) Row IOE local interconnects. (3) Column IOE local interconnects. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–6 Chapter 3: MultiTrack Interconnect in Stratix III Devices Memory Block Interface The R4 and C4 interconnects provide superior and flexible routing capabilities. Stratix III has a three-sided routing architecture which allows the interconnect wires from each LAB to reach the adjacent LABs to its right and left. A given LAB can drive 32 other LABs using one R4 or C4 interconnect, in one hop. This routing scheme improves efficiency and flexibility by placing all the critical LABs within one hop of the routing interconnects. Table 3–2 shows how many LABs are reachable within one, two, or three hops using the R4 and C4 interconnects. Table 3–2. Number of LABs reachable using C4 and R4 interconnects Hops Number of LABs 1 34 2 96 3 160 Memory Block Interface TriMatrix memory consists of three types of RAM blocks: MLAB, M9K, and M144K. This section provides a brief overview of how the different memory blocks interface to the routing structure. The RAM blocks in Stratix III devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The MLAB RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The MLAB RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. Each MLAB RAM block has up to 20 direct link input connections from the left adjacent LAB and another 20 from the right adjacent LAB. MLAB RAM outputs can also connect to left and right LABs through a direct link interconnect. The MLAB RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 3–4 shows the MLAB RAM block to LAB row interface. Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation Chapter 3: MultiTrack Interconnect in Stratix III Devices Memory Block Interface 3–7 Figure 3–4. MLAB RAM Block LAB Row Interface C4 Interconnects Direct link interconnect to adjacent LAB R4 Interconnects 20 Direct link interconnect to adjacent LAB dataout Direct link interconnect from adjacent LAB 20 Direct link interconnect from adjacent LAB MLAB clocks datain MLAB Local Interconnect Region control signals address LAB Row Clocks The M9K RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M9K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 20 direct link input connections to the M9K RAM Block are possible from the left adjacent LABs and another 20 possible from the right adjacent LAB. M9K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 3–5 shows the M9K RAM block to logic array interface. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–8 Chapter 3: MultiTrack Interconnect in Stratix III Devices Memory Block Interface Figure 3–5. M9K RAM Block LAB Row Interface C4 Interconnects Direct link interconnect to adjacent LAB R4 Interconnects Direct link interconnect to adjacent LAB 20 36 dataout M9K Direct link interconnect from adjacent LAB 20 20 datain control signals Direct link interconnect from adjacent LAB byte enable clocks address M9K Local Interconnect LAB Row Clocks The M144K blocks use eight interfaces in the same device column. The M144K block local interconnects are driven by R4, C4, and direct link interconnects from adjacent LABs on either the right or left side of the MRAM block. Up to 20 direct link input connections to the M144K block are possible from the left adjacent LABs and another 20 possible from the right adjacent LAB. M144K block outputs can also connect to the LABs on the block’s left and right sides through direct link interconnect. Figure 3–6 shows the interface between the M144K RAM block and the logic array. Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation Chapter 3: MultiTrack Interconnect in Stratix III Devices DSP Block Interface 3–9 Figure 3–6. M144K Row Unit Interface to Interconnect R4 Interconnects C4 Interconnects C4 Interconnects M144K Block LAB LAB Up to 5 dataout_a[ ] Up to 10 20 20 Up to 14 Direct Link Interconnects Row Interface Block M144K Block to LAB Row Interface Block Interconnect Region datain_a[ ] addressa[ ] addressstall rden/wren byteena[ ] clocken_a clock_a aclr Direct Link Interconnects Up to 16 Row Interface Block M144K Block to LAB Row Interface Block Interconnect Region DSP Block Interface Stratix III device DSP block input registers can generate a shift register that cascades down in the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. You can cascade registers within multiple DSP blocks for 9-bit or 18-bit finite impulse response (FIR) filters larger than four taps, with additional adder stages implemented in ALMs. If the DSP block is configured as 36-bit blocks, the adder, subtractor, or accumulator stages are implemented in ALMs. Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks. The DSP block is divided into four block units that interface with four LAB rows on the left and right. You can consider each block unit as two 18-bit multipliers followed by an adder with 72 inputs and 36 outputs. A local interconnect region is associated with each DSP block. Like a LAB, this interconnect region can be fed with 20 direct link interconnects from the LAB to the left or right of the DSP block in the same row. R4 and C4 routing resources can access the DSP block's local interconnect region. These outputs work similarly to LAB outputs. Eighteen outputs from the DSP block can drive to the left LAB through direct link interconnects and eighteen can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing. Figure 3–7 and Figure 3–8 show the DSP block interfaces to LAB rows. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–10 Chapter 3: MultiTrack Interconnect in Stratix III Devices DSP Block Interface Figure 3–7. High-Level View, DSP Block Interface to Interconnect DSP Block R4, C4 & Direct Link Interconnects OA[17..0] OB[17..0] R4, C4 & Direct Link Interconnects A1[35..0] B1[35..0] OC[17..0] OD[17..0] A2[35..0] B2[35..0] OE[17..0] OF[17..0] A3[35..0] B3[35..0] OG[17..0] OH[17..0] A4[35..0] B4[35..0] Stratix III Device Handbook, Volume 1 © October 2008 Altera Corporation Chapter 3: MultiTrack Interconnect in Stratix III Devices I/O Block Connections to Interconnect 3–11 Figure 3–8. Detailed View, DSP Block Interface to Interconnect Direct Link Interconnect from Adjacent LAB C4 Interconnects R4 Interconnects Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB 36 DSP Block Row Structure 36 LAB LAB 18 20 20 12 Control 72 A[35..0] B[35..0] OA[17..0] OB[17..0] 36 Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 72 Inputs per Row 36 Outputs per Row I/O Block Connections to Interconnect The IOEs are located in I/O blocks around the periphery of the Stratix III device. There are up to four IOEs per row I/O block and four IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 3–9 shows how a row I/O block connects to the logic array. Figure 3–10 shows how a column I/O block connects to the logic array. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–12 Chapter 3: MultiTrack Interconnect in Stratix III Devices I/O Block Connections to Interconnect Figure 3–9. Row I/O Block Connection to Interconnect R20 Interconnects R4 Interconnects C4 Interconnects I/O Block Local Interconnect 64 Data & Control Signals from Logic Array 64 LAB Horizontal I/O Block io_dataina[3..0] io_datainb[3..0] Direct Link Interconnect to Adjacent LAB LAB Local Interconnect Stratix III Device Handbook, Volume 1 Direct Link Interconnect from Adjacent LAB Horizontal I/O Block Contains up to Four IOEs © October 2008 Altera Corporation Chapter 3: MultiTrack Interconnect in Stratix III Devices Conclusion 3–13 Figure 3–10. Column I/O Block Connection to Interconnect 52 Data & Control Signals from Logic Array Vertical I/O Block Contains up to Four IOEs Vertical I/O Block 52 IO_dataina[3:0] IO_datainb[3:0] io_clk[7..0] I/O Block Local Interconnect R4 Interconnects LAB LAB Local Interconnects MLAB LAB C12 Interconnects C4 Interconnects Conclusion Stratix III devices consist of an array of logic blocks such as LABs, TriMatrix memory, DSP blocks, and IOEs. These blocks communicate with themselves and one another through the MultiTrack interconnect structures. The Quartus II compiler automatically routes critical design paths on faster interconnects to improve design performance and optimize the device resources. © October 2008 Altera Corporation Stratix III Device Handbook, Volume 1 3–14 Chapter 3: MultiTrack Interconnect in Stratix III Devices Chapter Revision History Chapter Revision History Table 3–3 shows the revision history for this document. Table 3–3. Chapter Revision History Date and Revision October 2008, version 1.2 October 2007, version 1.1 November 2006, version 1.0 Changes Made Summary of Changes Updated New Document Format. ■ Minor formatting changes. ■ Added section “Chapter Revision History”. ■ Added live links for references. — Minor formatting changes. Initial Release. Stratix III Device Handbook, Volume 1 — © October 2008 Altera Corporation 4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.8 Introduction TriMatrix embedded memory blocks provide three different sizes of embedded SRAM to efficiently address the needs of Stratix® III FPGA designs. TriMatrix memory includes 640- (in ROM mode only) or 320-bit memory logic array blocks (MLABs), 9-Kbit M9K blocks, and 144-Kbit M144K blocks. The MLABs have been optimized to implement filter delay lines, small first-in first-out (FIFO) buffers, and shift registers. You can use the M9K blocks for general purpose memory applications, and the M144K blocks are ideal for processor code storage, packet buffering, and video frame buffering. You can independently configure each embedded memory block to be a single- or dual-port RAM, FIFO, ROM, or shift register via the Quartus® II MegaWizardTM Plug-In Manager. You can stitch together multiple blocks of the same type to produce larger memories with minimal timing penalty. TriMatrix memory provides up to 20,491 Kbits of embedded SRAM at up to 600 MHz operation. This chapter describes TriMatrix memory blocks, modes, features, and design considerations. Overview Table 4–1 summarizes the features supported by the three sizes of TriMatrix memory. Table 4–1. Summary of TriMatrix Memory Features (Part 1 of 2) Feature MLABs M9K Blocks M144K Blocks 600 MHz 580 MHz 580 MHz 640 (in ROM mode) or 320 (in other modes) 9,216 147,456 Configurations (depth × width) 16 × 8 8K×1 16 K × 8 16 × 9 4K×2 16 K × 9 (1) 16 × 10 2K×4 8 K × 16 16 × 16 1K×8 8 K × 18 16 × 18 1K×9 4 K × 32 16 × 20 512 × 16 4 K × 36 512 × 18 2 K × 64 256 × 32 2 K × 72 Maximum performance Total memory bits (including parity bits) 256 × 36 v Parity bits © May 2009 Altera Corporation v v Stratix III Device Handbook, Volume 1 4–2 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Table 4–1. Summary of TriMatrix Memory Features (Part 2 of 2) Feature MLABs M9K Blocks M144K Blocks Byte-enable v v v Packed mode — v v Address clock enable v v v Single-port memory v v v Simple dual-port memory v v v True dual-port memory — v v Embedded shift register v v v ROM v v v FIFO buffer v v v Simple dual-port mixed width support — v v True dual-port mixed width support — v v Memory initialization file (.mif) v v v Mixed-clock mode v v v Power-up condition Outputs cleared if registered, otherwise reads memory contents Outputs cleared Outputs cleared Output registers Output registers Output registers — v v Write/Read operation triggering Write: Falling clock edges Write and Read: Rising clock edges Write and Read: Rising clock edges Same-port read-during-write Outputs set to don’t care Outputs set to old or new data Outputs set to old or new data Mixed-port read-during-write Outputs set to old data or don’t care Outputs set to old data or don’t care Outputs set to old data or don’t care Soft IP support via Quartus II software Soft IP support via Quartus II software Built-in support in ×64 wide SDP mode or soft IP support via Quartus II software Register clears Asynchronous clear on output latch ECC Support Read: Rising clock edges Notes to Table 4–1: (1) In ROM mode, MLABs support the (depth × width) configurations of 64×8, 64×9, 64×10, 32×16, 32×18, or 32× 20. (2) MLABs support byte-enable via emulation. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–3 Table 4–2 shows the capacity and distribution of the TriMatrix memory blocks for each Stratix III family member Table 4–2. TriMatrix Memory Capacity and Distribution in Stratix III Devices MLABs M9K Blocks M144K Blocks Total Dedicated RAM Bits (dedicated memory blocks only) Total RAM Bits (including MLABs) (1) EP3SL50 950 108 6 1,836 Kb 2,133 Kb EP3SL70 1,350 150 6 2,214 Kb 2,636 Kb EP3SL110 2,150 275 12 4,203 Kb 4,875 Kb EP3SL150 2,850 355 16 5,499 Kb 6,390 Kb EP3SL200 4,000 468 36 9,396 Kb 10,646 Kb EP3SL340 6,750 1,040 48 16,272 Kb 18,381 Kb EP3SE50 950 400 12 5,328 Kb 5,625 Kb EP3SE80 1,600 495 12 6,183 Kb 6,683 Kb EP3SE110 2,150 639 16 8,055 Kb 8,727 Kb EP3SE260 5,100 864 48 14,688 Kb 16,282 Kb Device Note to Table 4–2: (1) For total ROM Kbits, use this equation to calculate: Total ROM Kbits = Total Embedded RAM Kbits + [(number of MLAB blocks × 640)/1024] TriMatrix Memory Block Types While the M9K and M144K memory blocks are dedicated resources, the MLABs are dual-purpose blocks. They can be configured as regular logic array blocks (LABs) or as memory logic array blocks (MLABs). Ten adaptive logic modules (ALMs) make up one MLAB. Each ALM in an MLAB can be configured as a 16 × 2 block, resulting in a 16 × 20 simple dual-port SRAM block in a single MLAB. In ROM mode, each ALM in an MLAB can be configured as either a 64 × 1 or a 32 × 2 block, resulting in a 64 × 10 or 32 × 20 ROM block in a single MLAB. 1 All the ALMs share the same address bits. Therefore, you cannot combine multiple memories with different address bits and implement them in a single MLAB. 1 When you are using an MLAB as memory, you will not be able to use the unused ALMs in the MLAB even if you do not use the full capacity of an MLAB. Parity Bit Support All TriMatrix memory blocks have built-in parity-bit support. The ninth bit associated with each byte can store a parity bit or serve as an additional data bit. No parity function is actually performed on the ninth bit. Byte-Enable Support All TriMatrix memory blocks support byte-enables that mask the input data so that only specific bytes of data are written. The unwritten bytes retain the previous written value. The write enable (wren) signals, along with the byte-enable (byteena) signals, control the RAM blocks’ write operations. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–4 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 1 MLABs support byte-enable via emulation. There will be increased logic utilization when the byte-enables are emulated. The default value for the byte-enable signals is high (enabled), in which case writing is controlled only by the write enable signals. The byte-enable registers have no clear port. When using parity bits on the M9K and M144K blocks, the byte-enable controls all nine bits (eight bits of data plus one parity bit). When using parity bits on the MLAB, the byte-enable controls all 10 bits in the widest mode. Byte-enables operate in a one-hot fashion, with the LSB of the byteena signal corresponding to the least significant byte of the data bus. For example, if you are using a RAM block in ×18 mode, with byteena = 01, data[8..0] is enabled and data[17..9] is disabled. Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte-enables are active high. 1 You cannot use the byte-enable feature when using the ECC feature on M144K blocks. Figure 4–1 shows how the write enable (wren) and byte-enable (byteena) signals control the operations of the M9K and M144K. When a byte-enable bit is de-asserted during a write cycle, the corresponding data byte output can appear as either a “don’t care” value or the current data at that location. The output value for the masked byte is controllable via the Quartus II software. When a byte-enable bit is asserted during a write cycle, the corresponding data byte output also depends on the setting chosen in the Quartus II software. Figure 4–1. Stratix III Byte-Enable Functional Waveform for M9K and M144K inclock wren address data byteena contents at a0 a0 an a1 a2 a0 a1 ABCD XXXX 10 XX XXXX 01 11 FFFF XX ABFF FFFF contents at a1 a2 FFCD FFFF contents at a2 ABCD don't care: q (asynch) doutn ABXX XXCD ABCD ABFF FFCD ABCD current data: q (asynch) doutn ABFF FFCD ABCD ABFF FFCD ABCD Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–5 Figure 4–2 shows how the write enable (wren) and byte-enable (byteena) signals control the operations of the MLABs. The write operation in MLABs is triggered by failing clock edges. Figure 4–2. Stratix III Byte-Enable Functional Waveform for MLABs inclock wren address data byteena contents at a0 an a1 a2 a0 a1 ABCD XXXX 10 XX 01 11 XX ABFF FFFF FFCD FFFF contents at a2 doutn a2 XXXX FFFF contents at a1 current data: q (asynch) a0 FFFF ABCD ABFF FFFF FFCD FFFF ABCD ABFF FFCD FFCD Packed Mode Support Stratix III M9K and M144K blocks support packed mode. The packed mode feature packs two independent single-port RAMs into one memory block. The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block into true dual-port mode and using the MSB of the address to distinguish between the two logical RAMs. The size of each independent single-port RAM must not exceed half of the target block size. Address Clock Enable Support All Stratix III memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signals is low (disabled). © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–6 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Figure 4–3 shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall. Figure 4–3. Stratix III Address Clock Enable Block Diagram address[0] 1 0 address[N] 1 0 address[0] register address[0] address[N] register address[N] addressstall clock Figure 4–4 shows the address clock enable waveform during the read cycle. Figure 4–4. Stratix III Address Clock Enable during Read Cycle Waveform inclock rdaddress a0 a1 a2 a3 a4 a5 a6 rden addressstall latched address (inside memory) an q (synch) doutn-1 q (asynch) Stratix III Device Handbook, Volume 1 doutn doutn dout0 a4 a1 a0 dout0 dout4 dout1 dout1 a5 dout4 dout5 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–7 Figure 4–5 shows the address clock enable waveform during the write cycle for M9K and M144K. Figure 4–5. Stratix III Address Clock Enable during Write Cycle Waveform for M9K and M144K inclock wraddress a0 a1 a2 a3 a4 a5 a6 00 01 02 03 04 05 06 data wren addressstall latched address (inside memory) contents at a0 contents at a1 a1 a0 XX 01 02 XX contents at a3 XX contents at a5 Altera Corporation a4 a5 00 XX contents at a2 contents at a4 © May 2009 an 03 04 XX XX 05 Stratix III Device Handbook, Volume 1 4–8 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Figure 4–6 shows the address clock enable waveform during the write cycle for MLABs. Figure 4–6. Stratix III Address Clock Enable during Write Cycle Waveform for MLABs inclock wraddress data a0 a1 a2 a3 a4 a5 a6 00 01 02 03 04 05 06 wren addressstall latched address (inside memory) contents at a0 contents at a1 a1 a0 an a4 00 XX XX 01 02 contents at a2 XX contents at a3 XX contents at a4 contents at a5 a5 03 04 XX XX 05 Mixed Width Support M9K and M144K memory blocks inherently support mixed data widths. MLABs can support mixed data widths through emulation via the Quartus II software. When using simple dual-port or true dual-port mixed width support allows you to read and write different data widths to a memory block. Refer to “Memory Modes” on page 4–10 for details on the different widths supported per memory mode. 1 You cannot use the ECC on M144 memory blocks when using the mixed width support. 1 MLABs do not support mixed-width FIFO mode. Asynchronous Clear Stratix III M9K and M144K memory blocks support asynchronous clears on the output latches and output registers. MLABs supports asynchronous clear on the output registers only as the output is not latched. Therefore, if your M9K and M144K are not using the output registers, you can still clear the RAM outputs via the output latch asynchronous clear. The functional waveform in Figure 4–7 shows this functionality. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–9 Figure 4–7. Output Latch Asynchronous Clear Waveform outclk aclr aclr at latch q You can selectively enable asynchronous clears per logical memory via the Quartus II RAM MegaWizard Plug-In Manager. f For more information, refer to the RAM Megafunction User Guide. Error Correction Code Support Stratix III M144K blocks have built-in support for error correction code (ECC) when in ×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in the memory array. The M144K blocks have a single-error-correction double-error-detection (SECDED) implementation. SECDED can detect and fix a single-bit error in a 64-bit word or detect two-bit errors in a 64-bit word. It cannot detect three or more errors. The M144K ECC status is communicated via a three-bit status flag eccstatus[2..0]. The status flag can be either registered or unregistered. When registered, it uses the same clock and asynchronous clear signals as the output registers. When not registered, it cannot be asynchronously cleared. Table 4–3 shows the truth table for the ECC status flags. Table 4–3. Truth Table for ECC Status Flags Status © May 2009 eccstatus[2] eccstatus[1] eccstatus[0] No error 0 0 0 Single error and fixed 0 1 1 Double error and no fix 1 0 1 Illegal 0 0 1 Illegal 0 1 0 Illegal 1 0 0 Illegal 1 1 X 1 You cannot use the byte-enable feature when ECC is engaged. 1 Read during write “old data” mode is not supported when ECC is engaged. Altera Corporation Stratix III Device Handbook, Volume 1 4–10 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Figure 4–8 shows a block diagram of the ECC block of the M144K. Figure 4–8. ECC Block Diagram of the M144K 8 64 64 SECDED Encoder Data Input 8 72 RAM Array 72 64 SECDED Encoder Comparator 8 64 8 8 64 Error Locator 64 Error Correction Block Flag Generator 3 Status Flags 64 Data Output Memory Modes Stratix III TriMatrix memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K and M144K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations. Depending on which TriMatrix memory block you target, the following modes may be used: 1 ■ Single-port ■ Simple dual-port ■ True dual-port ■ Shift-register ■ ROM ■ FIFO When using the memory blocks in ROM, single-port, simple dual-port, or true dual-port mode, you can corrupt the memory contents if you violate the setup or hold-time on any of the memory block input registers. This applies to both read and write operations. Single Port RAM All TriMatrix memory blocks support single-port mode. Single-port mode allows you to do either one read or one write operation at a time. Simultaneous reads and writes are not supported in single-port mode. Figure 4–9 shows the single-port RAM configuration. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–11 Figure 4–9. Single-Port Memory (Note 1) data[ ] address[ ] wren byteena[] addressstall inclock clockena rden aclr q[] outclock Note to Figure 4–9: (1) You can implement two single-port memory blocks in a single M9K or M144K block. See “Packed Mode Support” on page 4–5 for more details. During a write operation, behavior of the RAM outputs is configurable. If you use the read-enable signal and perform a write operation with the read enable deactivated, the RAM outputs retain the values they held during the most recent active read enable. If you activate read enable during a write operation, or if you are not using the read-enable signal at all, the RAM outputs either show the new data being written, the old data at that address, or a don’t care value. To choose the desired behavior, set the read-during-write behavior to either new data, old data, or don’t care in the RAM MegaWizard Plug-In Manager in the Quartus II software. See “Read During Write” on page 4–21 for more details on this behavior. Table 4–4 shows the possible port width configurations for TriMatrix memory blocks in single-port mode. Table 4–4. Stratix III Port Width Configurations for MLABs, M9K Blocks, and M144K Blocks (Single-Port Mode) Port Width Port Width Configurations MLABs (1) M9K Blocks M144K Blocks 16 × 8 8K×1 16 K × 8 16 × 9 4K×2 16 K × 9 16 × 10 2K×4 8 K × 16 16 × 16 1K×8 8 K × 18 16 × 18 1K×9 4 K × 32 16 × 20 512 × 16 4 K × 36 512 × 18 2 K × 64 256 × 32 2 K × 72 256 × 36 Note to Table 4–4: (1) Configurations of 64 × 8, 64 × 9, 64 × 10, 32 × 16, 32 × 18, and 32 × 20 are supported by stitching multiple MLAB blocks. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–12 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Figure 4–10 shows the timing waveforms for read and write operations in single-port mode with unregistered outputs for M9K and M144K. In M9K and M144K registering the RAM’s outputs would simply delay the q output by one clock cycle. Figure 4–10. Timing Waveform for Read-Write Operations (Single-Port Mode) for M9K and M144K clk_a wrena rdena address_a data_a q_a (asynch) a0 A a1 B C A a0(old data) D B E F D a1(old data) E Figure 4–11 shows the timing waveforms for read and write operations in single-port mode with unregistered outputs for MLABs. For MLABs, the read operation is triggered by the rising clock edges whereas the write operation is triggered by the falling clock edges. Figure 4–11. Timing Waveform for Read-Write Operations (Single-Port Mode) for MLABs clk_a wrena rdena address_a data_a q_a (asynch) a0 A a0 (old data) B A a1 C B D C a1 (old data) E D F E Simple Dual-Port Mode All TriMatrix memory blocks support simple dual-port mode. Simple dual-port mode allows you to perform one-read and one-write operation to different locations at the same time. Figure 4–12 shows the simple dual-port configuration. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–13 Figure 4–12. Stratix III Simple Dual-Port Memory (Note 1) data[ ] wraddress[ ] wren byteena[] wr_addressstall wrclock wrclocken aclr rdaddress[ ] rden q[ ] rd_addressstall rdclock rdclocken ecc_status Note to Figure 4–12: (1) Simple dual-port RAM supports input/output clock mode in addition to the read/write clock mode shown. Simple dual-port mode supports different read and write data widths (mixed width support). Table 4–5 shows the mixed width configurations for the M9K blocks in simple dual-port mode. MLABs do not have native support for mixed width operation. The Quartus II software can implement mixed width memories in MLABs by using more than one MLAB. Table 4–5. Stratix III M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port 8K×1 4K×2 2K×4 1K×8 512×16 256×32 1K×9 512×18 256×36 8K×1 v v v v v v — — — 4K×2 v v v v v v — — — 2K×4 v v v v v v — — — 1K×8 v v v v v v — — — 512×16 v v v v v v — — — 256×32 v v v v v v — — — 1K×9 — — — — — — v v v 512×18 — — — — — — v v v 256×36 — — — — — — v v v Table 4–6 shows the mixed width configurations for the M144K blocks in simple dual-port mode. Table 4–6. Stratix III M144K Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port 16K×8 8K×16 4K×32 2K×64 16K×9 8K×18 4K×36 2K×72 16K×8 v v v v — — — — 8K×16 v v v v — — — — 4K×32 v v v v — — — — 2K×64 v v v v — — — — 16K×9 — — — — v v v v 8K×18 — — — — v v v v 4K×36 — — — — v v v v 2K×72 — — — — v v v v © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–14 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview In simple dual-port mode, M9K and M144K blocks support separate write-enable and read-enable signals. You can save power by keeping the read-enable signal low (inactive) when not reading. Read-during-write operations to the same address can either output a don’t care value or old data. To choose the desired behavior, set the read-during-write behavior to either don’t care or old data in the RAM MegaWizard Plug-In Manager in the Quartus II software. See “Read During Write” on page 4–21 for more details about this behavior. MLABs only support a write-enable signal. Read-during-write behavior for the MLABs can be either don’t care, new data, or old data. The available choices depend on the configuration of the MLAB. Figure 4–13 shows the timing waveforms for read and write operations in simple dual-port mode with unregistered outputs in M9K and M144K. Registering the RAM’s outputs would simply delay the q output by one clock cycle in M9k and M144K. Figure 4–13. Stratix III Simple Dual-Port Timing Waveforms for M9K and M144K wrclock wren wraddress an-1 data din-1 a0 an a1 a2 a3 din a4 a5 din4 din5 a6 din6 rdclock rden rdaddress q (asynch) bn b1 b0 doutn-1 b2 b3 dout0 doutn Figure 4–14 shows the timing waveforms for read and write operations in simple dual-port mode with unregistered outputs in MLABs. In MLABs, the write operation is triggered by the falling clock edges. Figure 4–14. Stratix III Simple Dual-Port Timing Waveforms for MLABs wrclock wren wraddress an-1 data din-1 a0 an a1 a2 din a3 a4 a5 din4 din5 a6 din6 rdclock rden rdaddress q (asynch) bn doutn-1 Stratix III Device Handbook, Volume 1 b0 doutn b1 b2 b3 dout0 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–15 True Dual-Port Mode Stratix III M9K and M144K blocks support true dual-port mode. Sometimes called bi-directional dual-port, this mode allows you to perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 4–15 shows the true dual-port RAM configuration. Figure 4–15. Stratix III True Dual-Port Memory (Note 1) data_a[ ] address_a[ ] wren_a byteena_a[] addressstall_a clock_a rden_a aclr_a q_a[] data_b[ ] address_b[] wren_b byteena_b[] addressstall_b clock_b rden_b aclr_b q_b[] Note to Figure 4–15: (1) True dual-port memory supports input/output clock mode in addition to the independent clock mode shown. The widest bit configuration of the M9K and M144K blocks in true dual-port mode is as follows: ■ 512 × 16-bit (×18-bit with parity) (M9K) ■ 4K × 32-bit (×36-bit with parity) (M144K) Wider configurations are unavailable because the number of output drivers is equivalent to the maximum bit width of the respective memory block. Because true dual-port RAM has outputs on two ports, its maximum width equals half of the total number of output drivers. Table 4–7 lists the possible M9K block mixed-port width configurations in true dual-port mode. Table 4–7. Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) Write Port Read Port 8K×1 4K×2 2K×4 1K×8 512×16 1K×9 512×18 8K×1 v v v v v — — 4K×2 v v v v v — — 2K×4 v v v v v — — 1K×8 v v v v v — — 512×16 v v v v v — — 1K×9 — — — — — v v 512×18 — — — — — v v © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–16 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Table 4–8 lists the possible M144K block mixed-port width configurations in true dual-port mode. Table 4–8. Stratix III M144K Block Mixed-Width Configurations (True Dual-Port Mode) Write Port Read Port 16K×8 8K×16 4K×32 16K×9 8K×18 4K×36 16K×8 v v v — — — 8K×16 v v v — — — 4K×32 v v v — — — 16K×9 — — — v v v 8K×18 — — — v v v 4K×36 — — — v v v In true dual-port mode, M9K and M144K blocks support separate write-enable and read-enable signals. You can save power by keeping the read-enable signal low (inactive) when not reading. Read-during-write operations to the same address can either output new data at that location or old data. To choose the desired behavior, set the read-during-write behavior to either new data or old data in the RAM MegaWizard Plug-In Manager in the Quartus II software. See “Read During Write” on page 4–21 for more details about this behavior. In true dual-port mode you can access any memory location at any time from either port. When accessing the same memory location from both ports, you must avoid possible write conflicts. A write conflict happens when you attempt to write to the same address location from both ports at the same time. This results in unknown data being stored to that address location. No conflict resolution circuitry is built into the Stratix III TriMatrix memory blocks. You must handle address conflicts external to the RAM block. Figure 4–16 shows the true dual-port timing waveforms for the write operation at port A and read operation at port B with the Read-During-Write behavior set to new data. Registering the RAM’s outputs would simply delay the q outputs by one clock cycle. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview 4–17 Figure 4–16. Stratix III True Dual-Port Timing Waveform clk_a wren_a address_a an-1 an data_a din-1 din q_a (asynch) din-1 a0 din a1 dout0 a2 dout1 a3 dout2 a4 a5 a6 din4 din5 din6 dout3 din4 din5 clk_b wren_b address_b q_b (asynch) bn doutn-1 b0 b1 b2 b3 doutn dout0 dout1 dout2 Shift-Register Mode All Stratix III memory blocks support shift register mode. Embedded memory block configurations can implement shift registers for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flipflops that quickly exhaust many logic cells for large shift registers. A more efficient alternative is to use embedded memory as a shift-register block, which saves logic cell and routing resources. The size of a shift register (w × m × n) is determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–18 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview Figure 4–17 shows the TriMatrix memory block in shift-register mode. Figure 4–17. Stratix III Shift-Register Memory Configuration w × m × n Shift Register m-Bit Shift Register W W m-Bit Shift Register W W n Number of Taps m-Bit Shift Register W W m-Bit Shift Register W W ROM Mode All Stratix III TriMatrix memory blocks support ROM mode. A .mif file initializes the ROM content of these blocks. The address lines of the ROM are registered on M9K and M144K blocks, but can be unregistered on MLABs. The outputs can be registered or unregistered. Output registers can be asynchronously cleared. The ROM read operation is identical to the read operation in the single-port RAM configuration. FIFO Mode All TriMatrix memory blocks support FIFO mode. MLABs are ideal for designs with many small, shallow FIFO buffers. To implement FIFO buffers in your design, use the Quartus II software FIFO MegaWizard Plug-In Manager. Both single and dual-clock (asynchronous) FIFOs are supported. f 1 For more information about implementing FIFO buffers, refer to the Single- and Dual-Clock FIFO Megafunctions User Guide. MLABs do not support mixed-width FIFO mode. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Clocking Modes 4–19 Clocking Modes Stratix III TriMatrix memory blocks support the following clocking modes: ■ Independent ■ Input/output ■ Read/write ■ Single clock 1 Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations. 1 Altera recommends using a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block performance. Use Quartus II to report timing for this and other memory block clocking schemes. f For more information refer to the Stratix III Device Family Errata Sheet. Table 4–9 shows the clocking mode versus memory mode support matrix. Table 4–9. Stratix III TriMatrix Memory Clock Modes True Dual-Port Mode Simple Dual-Port Mode Single-Port Mode ROM Mode FIFO Mode Independent v — — v — Input/output v v v v — Read/write — v — — v Single clock v v v v v Clocking Mode Independent Clock Mode Stratix III TriMatrix memory blocks can implement independent clock mode for true dual-port memories. In this mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port also supports independent clock enables for port A and port B registers. Asynchronous clears are supported only for output latches and output registers on both ports. Input/Output Clock Mode Stratix III TriMatrix memory blocks can implement input/output clock mode for true and simple dual-port memories. In this mode, an input clock controls all registers related to the data input to the memory block, including data, address, byte-enables, read enables, and write enables. An output clock controls the data output registers. Asynchronous clears are available on output latches and output registers only. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–20 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Design Considerations Read/Write Clock Mode Stratix III TriMatrix memory blocks can implement read/write clock mode for simple dual-port memories. In this mode, a write clock controls the data-input, write-address, and write-enable registers. Similarly, a read clock control the data-output, read-address, and read-enable registers. The memory blocks support independent clock enables for both the read and write clocks. Asynchronous clears are available on data output latches and registers only. When using read/write mode, if you perform a simultaneous read/write to the same address location, the output read data will be unknown. If you require the output data to be a known value in this case, use either single-clock mode or input/output clock mode and choose the appropriate read-during-write behavior in the Megawizard. Single Clock Mode Stratix III TriMatrix memory blocks can implement single-clock mode for true dual-port, simple dual-port, and single-port memories. In this mode, a single clock, together with a clock enable, is used to control all registers of the memory block. Asynchronous clears are available on output latches and output registers only. Design Considerations This section describes guidelines for designing with TriMatrix memory blocks. Selecting TriMatrix Memory Blocks The Quartus II software automatically partitions user-defined memory into embedded memory blocks by taking into account both speed and size constraints placed on your design. For example, the Quartus II software may spread out a memory across multiple memory blocks when resources are available to increase the performance of the design. You can manually assign the memory to a specific block size via the RAM MegaWizard Plug-In Manager. MLABs can implement single-port SRAM through emulation via the Quartus II software. Emulation results in minimal additional logic resources being used. Because of the dual-purpose architecture of the MLAB, it only has data input registers and output registers in the block. MLABs gain input address registers and additional optional data output registers from adjacent ALMs by using register packing. f For more information about register packing, refer to the Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. Conflict Resolution When using the memory blocks in true dual-port mode, it is possible to attempt two write operations to the same memory location (address). Since no conflict resolution circuitry is built into the memory blocks, this results in unknown data being written to that location. Therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Design Considerations 4–21 Read During Write You can customize the read-during-write behavior of the Stratix III TriMatrix memory blocks to suit your design needs. Two types of read-during-write operations are available: same port and mixed port. Figure 4–18 shows the difference between the two types. Figure 4–18. Stratix III Read-During-Write Data Flow Port A data in Port B data in Mixed-port data flow Same-port data flow Port A data out Port B data out Same-Port Read-During-Write Mode This mode applies to either a single-port RAM or the same port of a true dual-port RAM. In same-port read-during-write mode, three output choices are available: new data mode (or flow-through), old data mode, or don’t care mode. In new data mode, the new data is available on the rising edge of the same clock cycle on which it was written. In old data mode, the RAM outputs reflect the old data at that address before the write operation proceeds. In don’t care mode, the RAM outputs don’t care values for a read-during-write operation. If you are not using the new data mode or old data mode, you should select the don’t care mode. Using the don’t care mode increases the flexibility in the type of memory block used, provided you do not assign block type when instantiating a memory block. You may also get potential performance gain by selecting the don’t care mode. © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–22 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Design Considerations Figure 4–19 shows the sample functional waveforms of same-port read-during-write behavior with new data. Figure 4–19. Same Port Read-During-Write: New Data Mode (Note 1) clk_a 0A address 0B rdena wrena bytenna data_a 01 10 00 A123 B456 C789 XX23 q_a (asyn) B4XX 11 XXXX DDDD EEEE DDDD EEEE FFFF FFFF Note to Figure 4–19: (1) “X” can be a don’t care value or current data at that location, depending on the setting chosen in the Quartus II software. Figure 4–20 shows the sample functional waveforms of same-port read-during-write behavior with old data mode. Figure 4–20. Same Port Read-During-Write: Old Data Mode (Note 1) clk_a A0 address A1 rdena wrena bytenna data_a q_a (asyn) 01 10 00 A123 B456 C789 A0 (old data) DoldDold23 11 B423 DDDD EEEE A1(old data) DDDD FFFF EEEE Note to Figure 4–20: (1) Dold is the old data bit at address A0, A0 (old data) is the old data at address A0, and A1 (old data) is the old data at address A1. Mixed-Port Read-During-Write Mode This mode applies to a RAM in simple or true dual-port mode which has one port reading and the other port writing to the same address location with the same clock. In this mode you also have two output choices: old data or don’t care. In old data mode, a read-during-write operation to different ports causes the RAM outputs to reflect the old data at that address location. In don’t care mode, the same operation results in a “don’t care” or “unknown” value on the RAM outputs. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Design Considerations 1 4–23 For more details about how to implement the desired behavior, read-during-write behavior is controlled via the RAM MegaWizard Plug-In Manager refer to the RAM Megafunction User Guide. You should select don’t care mode if you do not use old data mode. This increases the flexibility in the type of memory block used, if you do not assign block type when instantiating a memory block. You may also get potential performance gain by selecting don’t care mode. Figure 4–21 shows a sample functional waveform of mixed-port read-during-write behavior for the old data mode. In don’t care mode, the old data shown in the figure is simply replaced with “don’t cares”. Figure 4–21. Mixed Port Read During Write: Old Data Mode (Note 1) clk_a&b wrena A0 address_a A1 data_a AAAA BBBB CCCC bytenna 11 01 10 DDDD EEEE FFFF 11 rdenb A0 address_b q_b_(asyn) A0 (old data) AAAA A1 AABB A1(old data) DDDD EEEE Note to Figure 4–21: (1) A0 (old data) is the old data at address A0 and A1 (old data) is the old data at address A1. Mixed-port read-during-write using two different clocks in simple-dual port RAM with old data output is supported via emulation. The Quartus II software takes two memory blocks to implement the widest width mode. Power-Up Conditions and Memory Initialization M9K and M144K memory block outputs power up to zero (cleared), regardless of whether the output registers are used or bypassed. MLABs power up to zero if output registers are used and power up reading the memory contents if output registers are not used. However, the actual RAM cells power up to an unknown state. Therefore, after power-up, if an address is read before being written, the output from the read operation is undefined because the contents are not initialized. All memory blocks support initialization via .mif file. You can create .mif files in the Quartus II software and specify their use with the RAM MegaWizard Plug-In Manager when instantiating a memory in your design. Even if a memory is pre-initialized (for example, by a .mif file), it still powers up with its outputs cleared. f © May 2009 For more information about .mif files, refer to the RAM Megafunction User Guide and the Quartus II Handbook. Altera Corporation Stratix III Device Handbook, Volume 1 4–24 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Conclusion Power Management Stratix III memory block clock-enables allow you to control clocking of each memory block to reduce AC power consumption. Use the read-enable signal to ensure that read operations only occur when you need them to. If your design does not require read-during-write, you can reduce your power consumption by de-asserting the read-enable signal during write operations, or any period when no memory operations occur. The Quartus II software automatically places any unused memory blocks in low power mode to reduce static power. Programming File Compatibility Beginning with version 8.1, the Quartus II software supports the logic option STRATIXIII_MRAM_COMPATIBILITY. When this option is set to on, the Quartus II software will generate programming files compatible with both affected and fixed silicons (for write speed decrease in M144K blocks). The default setting for this option is on. f For the list of devices that is affected by the write speed decrease for M144K blocks refer to the Stratix III Device Family Errata Sheet. To set the STRATIXIII_MRAM_COMPATIBILITY variable, enter the following line in the Quartus Settings File: set_global_assignment –name STRATIXIII_MRAM_COMPATIBILITY ON When targeting fixed silicon devices, set the STRATIXIII_MRAM_COMPATIBILITY variable to OFF. When the STRATIXIII_MRAM_COMPATIBILITY option is set to OFF, you will be able to achieve the higher FMAX that is published for M144K blocks in fixed silicons and the programming files will only be compatible with fixed silicons. These programming files will not configure other silicon revisions. The nSTATUS pin will drive out low and configuration will fail. Conclusion The Stratix III TriMatrix embedded memory structure provides three different on-chip RAM block sizes to address your design needs. All memory blocks are fully customizable and can be cascaded to implement wider or deeper memories with minimal speed penalty. You can independently configure each embedded memory block to be a single- or dual-port RAM, FIFO, ROM, or shift register via the Quartus II MegaWizard Plug-In Manager software. Stratix III Device Handbook, Volume 1 © May 2009 Altera Corporation Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Chapter Revision History 4–25 Chapter Revision History Table 4–10 shows the revision history for this chapter. Table 4–10. Chapter Revision History Date and Revision May 2009, version 1.8 February 2009, version 1.7 November 2008, Version 1.6 October 2008, version 1.5 May 2008, version 1.4 November 2007, version 1.3 October 2007, version 1.2 Changes Made Summary of Changes ■ Updated Table 4–1. ■ Updated “Read/Write Clock Mode” and “Simple Dual-Port Mode” sections. ■ Updated Figure 4–2, Figure 4–4, and Figure 4–5. ■ Removed “Referenced Documents” section. ■ Updated “Byte-Enable Support”, “Address Clock Enable Support”, “Asynchronous Clear”, “Single Port RAM”, and “Simple Dual-Port Mode” sections. ■ Updated Figure 4–1, Figure 4–5, Figure 4–8, Figure 4–10, and Figure 4–15. ■ Added Figure 4–2, Figure 4–6, Figure 4–11, Figure 4–14, and Figure 4–16. ■ Updated Table 4–1. ■ Updated “Asynchronous Clear” and “Clocking Modes” section. ■ Added “Programming File Compatibility” section. ■ Updated New Document Format. ■ Updated “Introduction” section. ■ Updated “TriMatrix Memory Block Types” section. ■ Updated “Byte-Enable Support” section. ■ Updated “Mixed Width Support” section. ■ Updated “Same-Port Read-During-Write Mode” section. ■ Updated Figure 4–16, Figure 4–17, and Figure 4–18. ■ Updated “Mixed-Port Read-During-Write Mode” section. ■ Updated Table 4–1, Table 4–2, and Table 4–4. Updated Table 4–2. ■ Updated Table 4–1. ■ Added section “Referenced Documents”. ■ Added live links for references. — — — — — — — May 2007, version 1.1 Updated Table 4–2, Table 4–9. — November 2006, version 1.0 Initial Release. — © May 2009 Altera Corporation Stratix III Device Handbook, Volume 1 4–26 Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Chapter Revision History © May 2009 Altera Corporation 5. DSP Blocks in Stratix III Devices SIII51005-1.7 Introduction The Stratix ® III family of devices have dedicated high-performance digital signal processing (DSP) blocks optimized for DSP applications. These DSP blocks of the Altera® Stratix device family are the third generation of hardwired, fixed function silicon blocks dedicated to maximizing signal processing capability, ease of use, and lowest silicon cost. Many complex systems such as WiMAX, 3GPP WCDMA, high-performance computing (HPC), voice over Internet protocol (VoIP), H.264 video compression, medical imaging, and HDTV use sophisticated digital signal processing techniques, and this typically requires a large number of mathematical computations. Stratix III devices are ideally suited as the DSP blocks consist of a combination of dedicated elements that perform multiplication, addition, subtraction, accumulation, summation, and dynamic shift operations. Along with the high-performance Stratix III soft logic fabric and TriMatrix™ memory structures, you can configure these blocks to build sophisticated fixed-point and floating-point arithmetic functions. These can be manipulated easily to implement common larger computationally intensive subsystems such as finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. DSP Block Overview Each Stratix III device has two to seven columns of DSP blocks that implement multiplication, multiply-add, multiply-accumulate (MAC), and dynamic shift functions efficiently. The logical functionality of the Stratix III DSP block is a superset of the previous generation of the DSP block found in Stratix and Stratix II devices. Architectural highlights of the Stratix III DSP block include: © March 2010 ■ High-performance, power-optimized, fully registered and pipelined multiplication operations ■ Natively supported 9-bit, 12-bit, 18-bit, and 36-bit wordlengths ■ Natively supported 18-bit complex multiplications ■ Efficiently supported floating-point arithmetic formats (24-bit for single precision and 53-bit for double precision) ■ Signed and unsigned input support ■ Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently ■ Cascading 18-bit input bus to form tap-delay line for filtering applications ■ Cascading 44-bit output bus to propagate output results from one block to the next block without external logic support ■ Rich and flexible arithmetic rounding and saturation units Altera Corporation Stratix III Device Handbook, Volume 1 5–2 Chapter 5: DSP Blocks in Stratix III Devices DSP Block Overview ■ Efficient barrel shifter support ■ Loopback capability to support adaptive filtering Table 5–1 lists the number of DSP blocks for the Stratix III device family. Table 5–1. Number of DSP Blocks in Stratix III Devices Independent Input and Output Multiplication Operators Family Device DSP Blocks 9×9 12 × 12 Multipliers Multipliers Stratix III Logic Stratix III Enhanced 18 × 18 18 × 18 36 × 36 Multipliers Complex Multipliers Four Multiplier Adder Mode High Precision Multiplier Adder Mode 18 × 18 18 × 36 EP3SL50 27 216 162 108 54 54 216 108 EP3SL70 36 288 216 144 72 72 288 144 EP3SL110 36 288 216 144 72 72 288 144 EP3SL150 48 384 288 192 96 96 384 192 EP3SL200 72 576 432 288 144 144 576 288 EP3SE260 96 768 576 384 192 192 768 384 EP3SL340 72 576 432 288 144 144 576 288 EP3SE50 48 384 288 192 96 96 384 192 EP3SE80 84 672 504 336 168 168 672 336 EP3SE110 112 896 672 448 224 224 896 448 EP3SE260 (1) 96 768 576 384 192 192 768 384 Note to Table 5–1: (1) The EP3SE260 device is rich in LE, memory, and multiplier resources. Hence, it aligns with both logic (L) and enhanced (E) variants. Table 5–1 lists that the largest Stratix III DSP centric device (EP3SE110) provides up to 896 18 × 18 multiplier functionality in the 36 × 36, complex 18 × 18, and summation modes. Each DSP block occupies four LAB blocks in height and can be divided further into two half-blocks that share some common clock signals, but are for all common purposes identical in functionality. The layout of each block is shown in Figure 5–1. 1 The Stratix III DSP block input data lines of 288-bits are double that of Stratix and Stratix II, but the number of output data lines remains at 144 bits. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation 5–3 Figure 5–1. Overview of DSP Block Signals 34 Control 144 Input Data Half-DSP Block 72 Output Data 72 Output Data 288 144 Half-DSP Block Full DSP Block Simplified DSP Operation In Stratix and Stratix II devices, the fundamental building block consists of an 18-bit × 18-bit multiplier that can also function as two 9-bit × 9-bit multipliers. For Stratix III, the fundamental building block is a pair of 18-bit × 18-bit multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in Equation 5–1 and Figure 5–2. Note that for all signed numbers, input and output data is represented in 2’s complement format only. Equation 5–1. Multiplier Equation P[36..0] = A0[17..0] × B0 [17..0] ± A1 [17..0] × B1[17..0] Figure 5–2. Basic Two-Multiplier Adder Building Block A0[17..0] B0[17..0] +/− © March 2010 A1[17..0] D Q B1[17..0] D Q Altera Corporation P[36..0] Stratix III Device Handbook, Volume 1 5–4 Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation The structure shown in Figure 5–2 is very useful for building more complex structures, such as complex multipliers and 36 × 36 multipliers, as described in later sections. Each Stratix III DSP block contains four Two-Multiplier Adder units (two Two-Multiplier Adder units per half-block). Therefore, there are eight 18 × 18 multiplier functionalities per DSP block. Following the Two-Multiplier Adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the following alternative functions per Half-Block: Equation 5–2. Four-Multiplier Adder Equation Z[37..0] = P0[36..0] + P1[36..0] Equation 5–3. Four-Multiplier Adder Equation (44-Bit Accumulation) Wn[43..0] = W n-1[43..0] ± Zn [37..0] In these equations, n denotes sample time, and P[36..0] are the results from the Two-Multiplier Adder units. Equation 5–2 provides a sum of four 18-bit × 18-bit multiplication operations (Four-Multiplier Adder), and Equation 5–3 provides a four 18-bit × 18-bit multiplication operation but with maximum of a 44-bit accumulation capability by feeding the output of the unit back to itself. This is shown in Figure 5–3. You can bypass all register stages depending on which mode you select. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation 5–5 Output Register Bank Adder/ Accumulator 44 Result + 144 Input Register Bank Input Data Pipeline Register Bank + Figure 5–3. Four-Multiplier Adder and Accumulation Capability Half-DSP Block To support commonly found FIR-like structures efficiently, a major addition to the DSP block in Stratix III is the ability to propagate the result of one Half-Block to the next Half-Block completely within the DSP block without additional soft logic overhead. This is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous Half-Block with the 44-bit result of the current block. The 44-bit result is fed either to the next Half-Block or out of the DSP block through the output register stage. This is shown in Figure 5–4. Detailed examples are described in later sections. The combination of a fast, low-latency Four-Multiplier Adder unit and the “chained cascade” capability of the output-chaining adder provide an optimal FIR and vector multiplication capability. To support single-channel type FIR filters efficiently, you can configure one of the multiplier input’s registers to form a tap delay line input, saving resources and providing higher system performance. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–6 Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation Figure 5–4. Output Cascading Feature for FIR Structures From Previous Half-Block DSP Output Register Bank Round/Saturate Adder/ Accumulator + 44 Result + 144 Input Register Bank Input Data Pipeline Register Bank + 44 Half DSP Block 44 To Next Half-Block DSP Also shown in Figure 5–4 is the optional Rounding and Saturation Unit (RSU). This unit provides a rich set of commonly found arithmetic round and saturation functions used in signal processing. In addition to the independent multipliers and sum modes, you can use the DSP blocks to perform shift operations. The DSP block can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. A top-level view of the Stratix III DSP block is shown in Figure 5–5. A more detailed diagram is shown in Figure 5–6. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation 5–7 Figure 5–5. Stratix III Full DSP Block Summary From Previous Half-Block DSP 44 Output Multiplexer Round/Saturate Output Register Bank Round/Saturate Output Register Bank + Output Multiplexer + Adder/Accumulator 144 Pipeline Register Bank Input Data Input Register Bank + Result Top Half-DSP Block 44 + Adder/Accumulator 144 Pipeline Register Bank Input Data Input Register Bank + + Result Bottom Half-DSP Block To Next Half-Block DSP © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–8 Chapter 5: DSP Blocks in Stratix III Devices Operational Modes Overview Operational Modes Overview Each Stratix III DSP block can be used in one of five basic operational modes. Table 5–2 lists the five basic operational modes and the number of multipliers that can be implemented within a single DSP block, depending on the mode. Table 5–2. Stratix III DSP Block Operation Modes Multiplier in Width # of Mults # per Block Signed or Unsigned RND, SAT In Shift Register Chainout Adder 1st Stage Add/Sub 2nd Stage Add/Acc 9-bits 1 8 Both No No No — — 12-bits 1 6 Both No No No — — 18-bits 1 4 Both Yes Yes No — — 36-bits 1 2 Both No No No — — Double 1 2 Both No No No — — Two-Multiplier Adder(1) 18-bits 2 4 Signed (4) Yes No No Both — Four-Multiplier Adder 18-bits 4 2 Both Yes Yes Yes Both Add Only High Precision Multiplier Adder 18 × 36-bits 2 2 Both No No No — Add Only Multiply Accumulate 18-bits 4 2 Both Yes Yes Yes Both Both Shift (2) 36-bits (3) 1 2 Both No No — — — Mode Independent Multiplier Notes to Table 5–2: (1) This mode also supports the loopback mode. In loopback mode, the number of loopback multipliers per DSP block is two and the remaining multipliers can be used in regular Two-Multiplier Adder mode. (2) The dynamic shift mode supports arithmetic shift left, arithmetic shift right, logical shift left, logical shift right, and rotation operation. (3) The dynamic shift mode operates on a 32-bit input vector but the multiplier width is configured as 36-bits. (4) Unsigned value is also supported but you must make sure that the result can be contained within 36-bits. The DSP block consists of two identical halves (top-half and bottom-half). Each half has four 18 × 18 multipliers. The Quartus® II software includes megafunctions used to control the mode of operation of the multipliers. After making the appropriate parameter settings using the megafunction’s MegaWizardTM Plug-In Manager, the Quartus II software automatically configures the DSP block. Stratix III DSP blocks can operate in different modes simultaneously. Each half-block is fully independent except for the sharing of the four clock, ena, and aclr signals. For example, you can break down a single DSP block to operate a 9 × 9 multiplier in one Half-Block and an 18 × 18 two-multiplier adder in the other Half-Block. This increases DSP block resource efficiency and allows you to implement more multipliers within a Stratix III device. The Quartus II software automatically places multipliers that can share the same DSP block resources within the same block. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions 5–9 DSP Block Resource Descriptions The DSP block consists of the following elements: ■ Input register bank ■ Four Two-Multiplier Adders ■ Pipeline register bank ■ Two second-stage adders ■ Four round and saturation logic units ■ Second adder register and output register bank A detailed overall architecture of the top half of the DSP block is shown in Figure 5–6. Figure 5–6. Half-DSP Block Architecture clock[3..0] ena[3..0] alcr[3..0] chainin[ ] (1) signa signb output_round output_saturate rotate shift_right zero_loopback accum_sload zero_chainout chainout_round chainout_saturate overflow (2) chainout_sat_overflow (3) scanina[ ] dataa_3[ ] Multiplexer Shift/Rotate Output Register Bank Second Round/Saturate (4) Chainout Adder Second Adder Register Bank First Round/Saturate datab_2[ ] Second Stage Adder/Accumulator dataa_2[ ] Pipeline Register Bank datab_1[ ] Input Register Bank datab_0[ ] dataa_1[ ] First Stage Adder loopback First Stage Adder dataa_0[ ] result[ ] datab_3[ ] Half-DSP Block scanouta chainout Notes to Figure 5–6: (1) (2) (3) (4) chainin[] can only come from the chainout port of the previous DSP blocks and not from general routing. Block output for accumulator overflow and saturate overflow. Block output for saturation overflow of chainout. When the chainout adder is not in use, the second adder register banks are known as output register banks. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–10 Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions Input Registers All of the DSP block registers are triggered by the positive edge of the clock signal and are cleared upon power up. Each multiplier operand can feed an input register or directly to the multiplier, bypassing the input registers. (This is configured at compile time.) The following DSP block signals control the input registers within the DSP block: ■ clock[3..0] ■ ena[3..0] ■ aclr[3..0] Every DSP block has nine 18-bit data input register banks per half DSP block. Every half DSP block has the option to use the eight data register banks as inputs to the four multipliers. The special ninth register bank is a delay register required by modes that use both the cascade and chainout features of the DSP block and is for balancing the latency requirements when using the chained cascade feature. A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) could be driven from general routing or from the cascade chain, as shown in Figure 5–7. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions 5–11 Figure 5–7. Input Register of Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb scanina[17..0] dataa_0[17..0] loopback datab_0[17..0] +/− dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] +/− dataa_3[17..0] datab_3[17..0] Delay Register You must select whether the A-input comes from general routing or from the cascade chain at compile time. In cascade mode, the dedicated shift outputs from one multiplier block directly feeds input registers of the adjacent multiplier below it (within the same half DSP block) or the first multiplier in the next half DSP block, to form an 8-tap shift register chain per DSP Block. The DSP block can increase the length of the shift register chain by cascading to the lower DSP blocks. The dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular FPGA routing resources. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–12 Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions Shift registers are useful in DSP functions such as FIR filters. When implementing 18 × 18 or smaller width multipliers, you do not need external logic to create the shift register chain because the input shift registers are internal to the DSP block. This implementation significantly reduces the logical element (LE) resources required, avoids routing congestion, and results in predictable timing. The first multiplier in every half DSP block (top- and bottom-half) in Stratix III devices has a multiplexer for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown in Figure 5–6. In loopback mode, the most significant 18-bit registered outputs are connected as feedback to the multiplier input of the first top multiplier in each half DSP block. Loopback modes are used by recursive filters where the previous output is needed to compute the current output. The loopback mode is described in detail in “Two-Multiplier Adder Sum Mode” on page 5–21. Table 5–3 lists the input register modes for the DSP block. Table 5–3. Input Register Modes Register Input Mode (1) 9×9 12 × 12 18 × 18 36 × 36 Double Parallel input v v v v v Shift register input (2) — — v — — Loopback input (3) — — v — — Notes to Table 5–3: (1) The multiplier operand input wordlengths are statically configured at compile time. (2) Available only on the A-operand. (3) Only one loopback input is allowed per Half-Block. See Figure 5–15 for details. Multiplier and First-Stage Adder The multiplier stage natively supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers. Other wordlengths are padded up to the nearest appropriate native wordlength; for example, 16 × 16 would be padded up to use 18 × 18. Refer to “Independent Multiplier Modes” on page 5–15 for more details. Depending on the data width of the multiplier, a single DSP block can perform many multiplications in parallel. Each multiplier operand can be a unique signed or unsigned number. Two dynamic signals, signa and signb, control the representation of each operand, respectively. A logic 1 value on the signa/signb signal indicates that data A/data B is a signed number; a logic 0 value indicates an unsigned number. Table 5–4 lists the sign of the multiplication result for the various operand sign representations. The result of the multiplication is signed if any one of the operands is a signed value. Table 5–4. Multiplier Sign Representation Data A (signa Value) Data B (signb Value) Result Unsigned (logic 0) Unsigned (logic 0) Unsigned Unsigned (logic 0) Signed (logic 1) Signed Signed (logic 1) Unsigned (logic 0) Signed Signed (logic 1) Signed (logic 1) Signed Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions 5–13 Each Half Block has its own signa and signb signal. Therefore, all of the data A inputs feeding the same DSP Half Block must have the same sign representation. Similarly, all of the data B inputs feeding the same DSP Half Block must have the same sign representation. The multiplier offers full precision regardless of the sign representation in all operational modes except for full precision 18 x 18 loopback and Two-Multiplier Adder modes. Refer to “Two-Multiplier Adder Sum Mode” on page 5–21 for details. 1 When the signa and signb signals are unused, the Quartus II software sets the multiplier to perform unsigned multiplication by default. The outputs of the multipliers are the only outputs that can feed into the first-stage adder, as shown in Figure 5–6. There are four first-stage adders in a DSP block (two adders per half DSP block). The first-stage adder block has the ability to perform addition and subtraction. The control signal for addition or subtraction is static and has to be configured upon compile time. The first-stage adders are used by the sum modes to compute the sum of two multipliers, 18 × 18-complex multipliers, and to perform the first stage of a 36 × 36 multiply and shift operation. Depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, round and saturation unit, or the output registers. Pipeline Register Stage The output from the first-stage adder can either feed or bypass the pipeline registers, as shown in Figure 5–6. Pipeline registers increase the DSP block’s maximum performance (at the expense of extra cycles of latency), especially when using the subsequent DSP block stages. Pipeline registers split up the long signal path between the input-registers/multiplier/first-stage adder and the second-stage adder/round-and-saturation/output-registers, creating two shorter paths. Second-Stage Adder There are four individual 44-bit second-stage adders per DSP block (2 adders per half DSP block). You can configure the second-stage adders as follows: © March 2010 ■ The final stage of a 36-bit multiplier ■ A sum of four (18 × 18) ■ An accumulator (44-bits maximum) ■ A chained output summation (44-bits maximum) 1 The chained-output adder can be used at the same time as a second-level adder in chained output summation mode. 1 The output of the second-stage adder has the option to go into the round and saturation logic unit or the output register. 1 You cannot use the second-stage adder independently from the multiplier and first-stage adder. Altera Corporation Stratix III Device Handbook, Volume 1 5–14 Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions Round and Saturation Stage The round and saturation logic units are located at the output of the 44-bit second-stage adder (round logic unit followed by the saturation logic unit). There are two round and saturation logic units per half DSP block. The input to the round and saturation logic unit can come from one of the following stages: ■ Output of the multiplier (independent multiply mode in 18 × 18) ■ Output of the first-stage adder (Two-Multiplier Adder) ■ Output of the pipeline registers ■ Output of the second-stage adder (Four-Multiplier Adder, Multiply-Accumulate Mode in 18 × 18) These stages are discussed in detail in “Operational Mode Descriptions” on page 5–15. The round and saturation logic unit is controlled by the dynamic round and saturate signals, respectively. A logic 1 value on the round, saturate, or both enables the round, saturate, or both logic units. 1 You can use the round and saturation logic units together or independently. Second Adder and Output Registers The second adder register and output register banks are two banks of 44-bit registers that can also be combined to form larger 72-bit banks to support 36 × 36 output results. The outputs of the different stages in the Stratix III devices are routed to the output registers through an output selection unit. Depending on the operational mode of the DSP block, the output selection unit selects whether the outputs of the DSP blocks comes from the outputs of the multiplier block, first-stage adder, pipeline registers, second-stage adder, or the round and saturation logic unit. The output selection unit is set automatically by the software, based on the DSP block operational mode you specified, and has the option to either drive or bypass the output registers. The exception is when the block is used in shift mode, in which case the user dynamically controls the output-select multiplexer directly. When the DSP block is configured in “chained cascaded” output mode, both of the second-stage adders are used. The first one is used for performing Four-Multiplier Adder and the second is used for the chainout adder. The outputs of the Four-Multiplier Adder are routed to the second-stage adder registers before it enters the chainout adder. The output of the chainout adder goes to the regular output register bank. Depending on the configuration, the chainout results can be routed to the input of the next half-block’s chainout adder input or to the general fabric (functioning as regular output registers). Refer to “Operational Mode Descriptions” on page 5–15 for details. Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–15 The second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. The following DSP block signals control the output registers within the DSP block: ■ clock[3..0] ■ ena[3..0] ■ aclr[3..0] Operational Mode Descriptions The various modes of operation are discussed below. Independent Multiplier Modes In independent input and output multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers. 9-, 12-, and 18-Bit Multiplier You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A single DSP block can support up to eight individual 9 × 9 multipliers, six 12 × 12 multipliers, or up to four individual 18 × 18 multipliers. For operand widths up to 9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a 12 × 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an 18 × 18 multiplier is implemented. This is done by the Quartus II software by zero-padding the LSBs. Figure 5–8, Figure 5–9, and Figure 5–10 show the DSP block in the independent multiplier operation mode. Figure 5–8. 18-Bit Independent Multiplier Mode for Half-DSP Block signa clock[3..0] signb overflow 18 datab_1[17..0] Pipeline Register Bank 18 dataa_1[17..0] Input Register Bank 18 datab_0[17..0] 36 result_0[ ] Output Register Bank 18 dataa_0[17..0] Round/Saturate output_round output_saturate Round/Saturate ena[3..0] aclr[3..0] 36 result_1[ ] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–16 Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions Figure 5–9. 12-Bit Independent Multiplier Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb 12 dataa_0[11..0] 24 result_0[ ] 12 Output Register Bank 12 datab_1[11..0] Pipeline Register Bank 12 dataa_1[11..0] Input Register Bank datab_0[11..0] 24 result_1[ ] 12 dataa_2[11..0] 24 result_2[ ] 12 datab_2[11..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–17 Figure 5–10. 9-Bit Independent Multiplier Mode for Half-Block clock[3..0] ena[3..0] aclr[3..0] signa signb 9 dataa_0[8..0] 18 result_0[ ] 9 datab_0[8..0] 9 dataa_1[8..0] Output Register Bank 9 dataa_2[8..0] Pipeline Register Bank 9 datab_1[8..0] Input Register Bank 18 result_1[ ] 18 result_2[ ] 9 datab_2[8..0] 9 dataa_3[8..0] 18 result_3[ ] 9 datab_3[8..0] Half-DSP Block The multiplier operands can accept signed integers, unsigned integers, or a combination of both. You can change the signa and signb signals dynamically and can be registered in the DSP block. Additionally, the multiplier inputs and result can be registered independently. You can use the pipeline registers within the DSP block to pipeline the multiplier result, increasing the performance of the DSP block. 1 © March 2010 The round and saturation logic unit is supported for the 18-bit independent multiplier mode only. Altera Corporation Stratix III Device Handbook, Volume 1 5–18 Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 36-Bit Multiplier You can efficiently construct a 36 × 36 multiplier using four 18 × 18 multipliers. This simplification fits conveniently into one half-DSP block, and is implemented in the DSP block automatically by selecting the 36 × 36 mode. Stratix III devices can have up to two 36-bit multipliers per DSP block (one 36-bit multiplier per half DSP block). The 36-bit multiplier is also under the independent multiplier mode but uses the entire half DSP block, including the dedicated hardware logic after the pipeline registers to implement the 36 × 36 bit multiplication operation. This is shown in Figure 5–11. The 36-bit multiplier is useful for applications requiring more than 18-bit precision; for example, for the mantissa multiplication portion of single precision and extended single precision floating-point arithmetic applications. Figure 5–11. 36-Bit Independent Multiplier Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb dataa_0[35..18] datab_0[35..18] datab_0[17..0] + Output Register Bank dataa_0[35..18] Input Register Bank datab_0[35..18] Pipeline Register Bank + dataa_0[17..0] 72 result[ ] + dataa_0[17..0] datab_0[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–19 Double Multiplier The Stratix III DSP block can be configured to efficiently support an unsigned 54 × 54 bit multiplier that is required to compute the mantissa portion of an IEEE double precision floating point multiplication. A 54 × 54 bit multiplier can be built using basic 18 × 18 multipliers, shifters, and adders. In order to efficiently utilize the Stratix III DSP block's built in shifters and adders, a special Double mode (partial 54 × 54 multiplier) is available that is a slight modification to the basic 36 × 36 Multiplier mode. This is shown in Figure 5–12 and Figure 5–13. Figure 5–12. Double Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb dataa_0[35..18] datab_0[35..18] datab_0[17..0] + Output Register Bank dataa_0[35..18] Input Register Bank datab_0[35..18] Pipeline Register Bank + dataa_0[17..0] 72 result[ ] + dataa_0[17..0] datab_0[17..0] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–20 Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions Figure 5–13. Unsigned 54 × 54 Multiplier clock[3..0] ena[3..0] aclr[3..0] "0" "0" dataa[53..36] signa signb Two Multiplier Adder Mode + 36 datab[53..36] dataa[35..18] Double Mode 55 datab[35..18] dataa[53..36] datab[17..0] dataa[35..18] Final Adder (implemented with ALUT logic) datab[53..36] dataa[53..36] Shifters and Adders datab[53..36] dataa[17..0] 108 result[ ] 36 x 36 Mode datab[35..18] dataa[35..18] Shifters and Adders datab[35..18] dataa[17..0] 72 datab[17..0] dataa[17..0] datab[17..0] Unsigned 54 X 54 Multiplier Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–21 Two-Multiplier Adder Sum Mode In the two-multiplier adder configuration, the DSP block can implement four 18-bit Two-Multiplier Adders (2 Two-Multiplier Adders per half DSP block). You can configure the adders to take the sum or difference of two multiplier outputs. Summation or subtraction has to be selected at compile time. The Two-Multiplier Adder function is useful for applications such as FFTs, complex FIR, and IIR filters. Figure 5–14 shows the DSP block configured in the two-multiplier adder mode. The loopback mode is the other sub-feature of the two-multiplier adder mode. Figure 5–15 shows the DSP block configured in the loopback mode. This mode takes the 36-bit summation result of the two multipliers and feeds back the most significant 18-bits to the input. The lower 18-bits are discarded. You have the option to disable or zero-out the loopback data by using the dynamic zero_loopback signal. A logic 1 value on the zero_loopback signal selects the zeroed data or disables the looped back data, while a logic 0 selects the looped back data. 1 The option to use the loopback mode or the general two-multiplier adder mode must be selected at compile time. For the Two-Multiplier Adder mode, if all the inputs are full 18-bit and unsigned, the result will require 37 bits. As the output data width in Two-Multiplier Adder mode is limited to 36 bits, this 37-bit output requirement is not allowed. Any other combination that does not violate the 36-bit maximum result is permitted; for example, two 16 × 16 signed Two-Multiplier Adders is valid. The two-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–22 Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions Figure 5–14. Two-Multiplier Adder Mode for Half-DSP Block signa clock[3..0] ena[3..0] aclr[3..0] signb output_round output_saturate overflow + datab_2[17..0] + dataa_3[17..0] result_0[ ] Output Register Bank dataa_2[17..0] Input Register Bank datab_1[17..0] Pipeline Register Bank dataa_1[17..0] Round/Saturate datab_0[17..0] Round/Saturate dataa_0[17..0] result_1[ ] datab_3[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–23 Figure 5–15. Loopback Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_saturate zero_loopback overflow Output Register Bank dataa_1[17..0] + Round/Saturate datab_0[17..0] Pipeline Register Bank loopback Input Register Bank dataa_0[17..0] result[ ] datab_1[17..0] Half-DSP Block © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–24 Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 18 × 18 Complex Multiply You can configure the DSP block when used in Two-Multiplier Adder mode to implement complex multipliers using the two-multiplier adder mode. A single half DSP block can implement one 18-bit complex multiplier. A complex multiplication can be written as shown in Equation 5–4. Equation 5–4. Complex Multiplication Equation (a + jb) × (c + jd) = ((a × c) – (b × d)) + j((a × d) + (b × c)) To implement this complex multiplication within the DSP block, the real part ((a × c) – (b × d)) is implemented using two multipliers feeding one subtractor block while the imaginary part ((a × d) + (b × c)) is implemented using another two multipliers feeding an adder block. Figure 5–16 shows an 18-bit complex multiplication. This mode automatically assumes all inputs are using signed numbers. Figure 5–16. Complex Multiplier Using Two-Multiplier Adder Mode clock[3..0] ena[3..0] aclr[3..0] signa signb A B − 36 (A x C) − (B x D) (Real Part) 36 (A x D) − (B x C) (Imaginary Part) + Output Register Bank Input Register Bank D Pipeline Register Bank C Half-DSP Block Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–25 Four-Multiplier Adder In the four-multiplier adder configuration shown in Figure 5–17, the DSP block can implement two four-multiplier adders (one four-multiplier adder per half DSP block). These modes are useful for implementing one-dimensional and two-dimensional filtering applications. The four-multiplier adder is performed in two addition stages. The outputs of two of the four multipliers are initially summed in the two first-stage adder blocks. The results of these two adder blocks are then summed in the second-stage adder block to produce the final four-multiplier adder result, as shown by Equation 5–2 and Equation 5–3. Figure 5–17. Four-Multiplier Adder Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] signa signb output_round output_saturate overflow dataa_0[ ] datab_0[ ] + dataa_2[ ] + Output Register Bank datab_1[ ] Round/Saturate Input Register Bank Pipeline Register Bank dataa_1[ ] result[ ] datab_2[ ] + dataa_3[ ] datab_3[ ] Half-DSP Block The four-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © March 2010 Altera Corporation Stratix III Device Handbook, Volume 1 5–26 Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions High Precision Multiplier Adder In the high precision multiplier adder configuration shown in Figure 5–18, the DSP block can implement two two-multiplier adders, with multiplier precision of 18 × 36 (one two-multiplier adder per DSP half block). This mode is useful in filtering or FFT applications where a data path greater than 18 bits is required, yet 18 bits is sufficient for the coefficient precision. This can occur in cases where that data has a high dynamic range. If the coefficients are fixed, as in FFT and most filter applications, the precision of 18 bits will provide a dynamic range over 100 dB if the largest coefficient is normalized to the maximum 18-bit representation. In these situations, the data path can be up to 36 bits, allowing ample headroom to bit growth, or gain changes in the signal source without loss of precision. This mode is also extremely useful in single precision block floating point applications. The high precision multiplier adder is preformed in two stages. The 18 × 36 multiply is decomposed into two 18 × 18 multipliers. The multiplier with the LSB of the data source is performed unsigned, while the multiplier with the MSB of the data source can be signed or signed. The latter multiplier has its result left shifted by 18 bits prior to the first adder stage, creating an effective 18 × 36 multiplier. The results of these two adder blocks are then summed in the second stage adder block to produce the final result. Equation 5–5. High Precision Multiplier Adder Equation Z[54..0] = P0[53..0] + P1 [53..0] where P0 = A[17..0] ´ B[35..0] and P1 = C[17..0] ´ D[35..0] Stratix III Device Handbook, Volume 1 © March 2010 Altera Corporation Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 5–27 Figure 5–18. Four-Multiplier Adder Mode for Half-DSP Block signa signb clock[3..0] ena[3..0] aclr[3..0] overflow dataA[17..0] dataB[17..0] Output Register Bank dataC[17..0]