NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 3: Proper Measurement of Switch Node – OUT
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Minimize loop
EFFICIENT POWER CONVERSION
EPC
Ground probe
against TP3
THERMAL CONSIDERATIONS
Do not let probe tip touch
back of low-side die!
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9006 Development Board
PWM Input
–
(For Efficiency
Measurement)
PWM
Input
VDD
Gate Drive
Regulator
OUT
VIN
Gate Drive
Supply
–
VIN V
LM5113
Gate
Driver
Half-Bridge with Bypass
Switch Node
+
IIN
VIN Supply
+
< 70 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
7 V – 12 V
6,
100
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Logic and
Dead-time
Adjust
External Circuit
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Quick Start Procedure
EPC
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
100
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
For shutdown, please follow steps in reverse.
Do not use probe ground lead
6,
www.epc-co.com
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Development Board / Demonstration Board Notification
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
www.epc-co.com
The EPC9006 development board is a 100 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge configuration using
Table 1
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
1.
2.
3.
4.
5.
6.
7.
8.
9.
Place probe in large via at OUT
Contact us:
DESCRIPTION
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Performance Summary (TA = 25°C)
SYMBOL
VDD
PARAMETER
Gate Drive Input Supply Range
VIN
CONDITIONS
MIN
7
MAX
12
UNITS
V
Bus Input Voltage Range
70*
V
VOUT
Switch Node Output Voltage
100
V
IOUT
Switch Node Output Current
5*
A
VPWM
PWM Logic Input Voltage Threshold
Input ‘High’
3.5
6
V
0
30
100#
1.5
Minimum ‘High’ State Input Pulse Width
Minimum ‘Low’ State Input Pulse Width
Input ‘Low’
VPWM rise and fall time < 10ns
VPWM rise and fall time < 10ns
V
ns
ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 3: Proper Measurement of Switch Node – OUT
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Minimize loop
EFFICIENT POWER CONVERSION
EPC
Ground probe
against TP3
THERMAL CONSIDERATIONS
Do not let probe tip touch
back of low-side die!
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9006 Development Board
PWM Input
–
(For Efficiency
Measurement)
PWM
Input
VDD
Gate Drive
Regulator
OUT
VIN
Gate Drive
Supply
–
VIN V
LM5113
Gate
Driver
Half-Bridge with Bypass
Switch Node
+
IIN
VIN Supply
+
< 70 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
7 V – 12 V
6,
100
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Logic and
Dead-time
Adjust
External Circuit
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Quick Start Procedure
EPC
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
100
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
For shutdown, please follow steps in reverse.
Do not use probe ground lead
6,
www.epc-co.com
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Development Board / Demonstration Board Notification
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
www.epc-co.com
The EPC9006 development board is a 100 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge configuration using
Table 1
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
1.
2.
3.
4.
5.
6.
7.
8.
9.
Place probe in large via at OUT
Contact us:
DESCRIPTION
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Performance Summary (TA = 25°C)
SYMBOL
VDD
PARAMETER
Gate Drive Input Supply Range
VIN
CONDITIONS
MIN
7
MAX
12
UNITS
V
Bus Input Voltage Range
70*
V
VOUT
Switch Node Output Voltage
100
V
IOUT
Switch Node Output Current
5*
A
VPWM
PWM Logic Input Voltage Threshold
Input ‘High’
3.5
6
V
0
30
100#
1.5
Minimum ‘High’ State Input Pulse Width
Minimum ‘Low’ State Input Pulse Width
Input ‘Low’
VPWM rise and fall time < 10ns
VPWM rise and fall time < 10ns
V
ns
ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Figure 3: Proper Measurement of Switch Node – OUT
EFFICIENT POWER CONVERSION
EPC
Place probe in large via at OUT
Do not use probe ground lead
6,
100
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9006 Development Board
EPC
PWM Input
–
(For Efficiency
Measurement)
PWM
Input
VDD
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
OUT
VIN
Gate Drive
Supply
Half-Bridge with Bypass
External Circuit
–
VIN V
Switch Node
+
IIN
VIN Supply
+
< 70 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
6,
7 V – 12 V
100
DESCRIPTION
Development Board EPC9006
Quick Start Guide
Contact us:
www.epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
For shutdown, please follow steps in reverse.
Minimize loop
Ground probe
against TP3
THERMAL CONSIDERATIONS
Do not let probe tip touch
back of low-side die!
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
www.epc-co.com
The EPC9006 development board is a 100 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
100 V Half-Bridge with Gate Drive, Using EPC2007
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge configuration using
Table 1
PARAMETER
Gate Drive Input Supply Range
SYMBOL
VDD
I
OUT
OUT
V
PWM
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Performance Summary (TA = 25°C)
Bus Input Voltage Range
VIN
V
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Quick Start Procedure
MIN
7
CONDITIONS
MAX
12
70*
Switch Node Output Voltage
100
Switch Node Output Current
5*
PWM Logic Input Voltage Threshold
Minimum ‘High’ State Input Pulse Width
Minimum ‘Low’ State Input Pulse Width
Input ‘High’
Input ‘Low’
VPWM rise and fall time < 10ns
VPWM rise and fall time < 10ns
3.5
6
0
30
100#
1.5
UNITS
V
V
V
A
V
V
ns
ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Figure 3: Proper Measurement of Switch Node – OUT
EFFICIENT POWER CONVERSION
EPC
Place probe in large via at OUT
Do not use probe ground lead
6,
100
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9006 Development Board
EPC
PWM Input
–
(For Efficiency
Measurement)
PWM
Input
VDD
Logic and
Dead-time
Adjust
Gate Drive
Regulator
LM5113
Gate
Driver
OUT
VIN
Gate Drive
Supply
Half-Bridge with Bypass
External Circuit
–
VIN V
Switch Node
+
IIN
VIN Supply
+
< 70 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
6,
7 V – 12 V
100
DESCRIPTION
Development Board EPC9006
Quick Start Guide
Contact us:
www.epc-co.com
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
For shutdown, please follow steps in reverse.
Minimize loop
Ground probe
against TP3
THERMAL CONSIDERATIONS
Do not let probe tip touch
back of low-side die!
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
www.epc-co.com
The EPC9006 development board is a 100 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
100 V Half-Bridge with Gate Drive, Using EPC2007
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge configuration using
Table 1
PARAMETER
Gate Drive Input Supply Range
SYMBOL
VDD
I
OUT
OUT
V
PWM
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Performance Summary (TA = 25°C)
Bus Input Voltage Range
VIN
V
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
Development Board / Demonstration Board Notification
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
Quick Start Procedure
MIN
7
CONDITIONS
MAX
12
70*
Switch Node Output Voltage
100
Switch Node Output Current
5*
PWM Logic Input Voltage Threshold
Minimum ‘High’ State Input Pulse Width
Minimum ‘Low’ State Input Pulse Width
Input ‘High’
Input ‘Low’
VPWM rise and fall time < 10ns
VPWM rise and fall time < 10ns
3.5
6
0
30
100#
1.5
UNITS
V
V
V
A
V
V
ns
ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
Table 2 : Bill of Material
Item
Qty
Reference
1
4
C4, C10, C11, C13
2
2
C6, C7
3
1
C12
4
2
C16, C17
5
2
D1, D2
6
4
J1, J2, J9, TP3 (See Note 1)
7
1
J3, J4, J5, J6, J7, J8
8
2
Q1, Q2
9
1
R1
10
2
R2, R15
11
1
R4
12
1
R5
13
2
R11, R12
14
2
TP1, TP2
15
1
TP3
16
1
U1
17
1
U2
18
1
U3
19
1
U4
20
0
R13, R14
21
0
C15, C19
22
0
D5, D6
23
0
P1, P2
Note 1: 36 pin Header to be cut as follows:
J1: cut 2 pins used
J2 & J9: cut 4 pins used
TP3: cut 1 pin used
1
2
Part Description
Manufacturer / Part #
Capacitor, 1uF, 10%, 25V, X5R
Capacitor, 100pF, 5%, 50V, NP0
Capacitor, 0.1uF, 10%, 25V, X5R
Capacitor, 2.2uF, 10%, 100V, X5R
Schottky Diode, 30V
Connector
Connector
eGaN® FET
Resistor, 10.0K, 5%, 1/8W
Resistor, 0 Ohm, 1/10W
Resistor, 22 Ohm, 1%, 1/8W
Resistor, 47 Ohm, 1%, 1/8W
Resistor, 0 Ohm, 1/8W
Test Point
Connector
I.C., Logic
I.C., Gate driver
I.C., Regulator
I.C., Logic
Optional Resistor
Optional Capacitor
Optional Diode
Optional Potentiometer
Murata, GRM188R61E105KA12D
TDK, C1608C0G1H101J
TDK, C1608X5R1E104K
Taiyo Yuden, HMK325B7225K
Diodes Inc., SDM03U40-7
FCI, 68001-236HLF
FCI, 68602-224HLF
EPC, EPC2007
Stackpole, RMCF0603FT10K0
Panasonic, ERJ-3GEY0R00V
Stackpole, RMCF0603FT22R0
Stackpole, RMCF0603FT47R0
Stackpole, RMCF0603ZT0R00
Keystone Elect, 5015
1 pin of Tyco, 4-103185-0
Fairchild, NC7SZ00L6X
Texas Instruments, LM5113
Microchip, MCP1703T-5002E/MC
Fairchild, NC7SZ08L6X
4
3
5
6
A
A
7 - 12 Vdc
U3
8
C10
7
1uF, 25V
6
OUT
NC
NC
NC
NC
NC
GND
VCC
1
C11
2
3
C4
4
1uF, 25V
1uF, 25V
9
5
IN
GND
J1
1
2
CON2
TP2
Keystone 5015
1
GND
Y
5
0.1uF,
25V
4
C12
LOH
J4
CON4
4
3
2
1
HB
VDD
SW OUT
Opt.
D5
C6
C15
33
R12
Q2
1 Ohm
EPC2007
R13
Opt.
C19
Optional
C16
C17
4.7uF,
50V
4.7uF, 50V
C
TP3
1
CON1
J7
CON4
1
2
3
4
C7
D6
Opt.
Opt.
100p
SDM03U40
R5
Optional
U2
LM5113
GND
22
D2
R15
Zero
HOH
C13
SDM03U40
R4
2
J3
CON4
1uF, 25V
D1
Y
NC7SZ08L6X
P2
Optional
2
LOL
P1
Optional
1
2
3
4
VDD
GND
R14
J6
CON4
EPC2007
U4
B
PWM2
Q1
R11 1 Ohm
VSS
R2
Zero
A
C
B
70V Max
HS
3
NC7SZ00L6X
CON2
1
2
3
4
5
1
B
VCC
6
J5
CON4
4
3
2
1
2
VDD
HOL
R1
10k
U1
A
LI
J2
1
2
CON2
J9
1
2
HI
B
PWM1
MCP1703
100p
1
4
3
2
1
GND
TP1
Keystone 5015
J8
CON4
D
D
100 V Half-Bridge with Gate Drive, using EPC2007
Rev. 2.0
1
2
3
4
5
6
Table 2 : Bill of Material
Item
Qty
Reference
1
4
C4, C10, C11, C13
2
2
C6, C7
3
1
C12
4
2
C16, C17
5
2
D1, D2
6
4
J1, J2, J9, TP3 (See Note 1)
7
1
J3, J4, J5, J6, J7, J8
8
2
Q1, Q2
9
1
R1
10
2
R2, R15
11
1
R4
12
1
R5
13
2
R11, R12
14
2
TP1, TP2
15
1
TP3
16
1
U1
17
1
U2
18
1
U3
19
1
U4
20
0
R13, R14
21
0
C15, C19
22
0
D5, D6
23
0
P1, P2
Note 1: 36 pin Header to be cut as follows:
J1: cut 2 pins used
J2 & J9: cut 4 pins used
TP3: cut 1 pin used
1
2
Part Description
Manufacturer / Part #
Capacitor, 1uF, 10%, 25V, X5R
Capacitor, 100pF, 5%, 50V, NP0
Capacitor, 0.1uF, 10%, 25V, X5R
Capacitor, 2.2uF, 10%, 100V, X5R
Schottky Diode, 30V
Connector
Connector
eGaN® FET
Resistor, 10.0K, 5%, 1/8W
Resistor, 0 Ohm, 1/10W
Resistor, 22 Ohm, 1%, 1/8W
Resistor, 47 Ohm, 1%, 1/8W
Resistor, 0 Ohm, 1/8W
Test Point
Connector
I.C., Logic
I.C., Gate driver
I.C., Regulator
I.C., Logic
Optional Resistor
Optional Capacitor
Optional Diode
Optional Potentiometer
Murata, GRM188R61E105KA12D
TDK, C1608C0G1H101J
TDK, C1608X5R1E104K
Taiyo Yuden, HMK325B7225K
Diodes Inc., SDM03U40-7
FCI, 68001-236HLF
FCI, 68602-224HLF
EPC, EPC2007
Stackpole, RMCF0603FT10K0
Panasonic, ERJ-3GEY0R00V
Stackpole, RMCF0603FT22R0
Stackpole, RMCF0603FT47R0
Stackpole, RMCF0603ZT0R00
Keystone Elect, 5015
1 pin of Tyco, 4-103185-0
Fairchild, NC7SZ00L6X
Texas Instruments, LM5113
Microchip, MCP1703T-5002E/MC
Fairchild, NC7SZ08L6X
4
3
5
6
A
A
7 - 12 Vdc
U3
8
C10
7
1uF, 25V
6
OUT
NC
NC
NC
NC
NC
GND
VCC
1
C11
2
3
C4
4
1uF, 25V
1uF, 25V
9
5
IN
GND
J1
1
2
CON2
TP2
Keystone 5015
1
GND
Y
5
0.1uF,
25V
4
C12
LOH
J4
CON4
4
3
2
1
HB
VDD
SW OUT
Opt.
D5
C6
C15
33
R12
Q2
1 Ohm
EPC2007
R13
Opt.
C19
Optional
C16
C17
4.7uF,
50V
4.7uF, 50V
C
TP3
1
CON1
J7
CON4
1
2
3
4
C7
D6
Opt.
Opt.
100p
SDM03U40
R5
Optional
U2
LM5113
GND
22
D2
R15
Zero
HOH
C13
SDM03U40
R4
2
J3
CON4
1uF, 25V
D1
Y
NC7SZ08L6X
P2
Optional
2
LOL
P1
Optional
1
2
3
4
VDD
GND
R14
J6
CON4
EPC2007
U4
B
PWM2
Q1
R11 1 Ohm
VSS
R2
Zero
A
C
B
70V Max
HS
3
NC7SZ00L6X
CON2
1
2
3
4
5
1
B
VCC
6
J5
CON4
4
3
2
1
2
VDD
HOL
R1
10k
U1
A
LI
J2
1
2
CON2
J9
1
2
HI
B
PWM1
MCP1703
100p
1
4
3
2
1
GND
TP1
Keystone 5015
J8
CON4
D
D
100 V Half-Bridge with Gate Drive, using EPC2007
Rev. 2.0
1
2
3
4
5
6
NOTE. The EPC9006 development board does not have any current or thermal protection on board.
Figure 4: Typical Waveforms for VIN = 48 V to 5 V/5 A (1000kHz) Buck converter
CH1: VPWM Input voltage – CH2: (IOUT) Switch node current – CH4: (VOUT) Switch node voltage
Figure 3: Proper Measurement of Switch Node – OUT
The EPC9006 development board showcases the EPC2007 eGaN FET. Although the electrical performance surpasses that for traditional Si devices,
their relatively smaller size does magnify the thermal management requirements. The EPC9006 is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rating of these
devices, but care must be taken to not exceed the absolute maximum die temperature of 125°C.
Minimize loop
EFFICIENT POWER CONVERSION
EPC
Ground probe
against TP3
THERMAL CONSIDERATIONS
Do not let probe tip touch
back of low-side die!
NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the
oscilloscope probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See
Figure 3 for proper scope probe technique. Do not let the probe tip touch the low-side die.
Figure 2: Proper Connection and Measurement Setup
EFFICIENT POWER CONVERSION
Figure 1: Block Diagram of EPC9006 Development Board
PWM Input
–
(For Efficiency
Measurement)
PWM
Input
VDD
Gate Drive
Regulator
OUT
VIN
Gate Drive
Supply
–
VIN V
LM5113
Gate
Driver
Half-Bridge with Bypass
Switch Node
+
IIN
VIN Supply
+
< 70 V
A
+
Gate Drive Supply
(Note Polarity)
VDD Supply
–
7 V – 12 V
6,
100
Peter Cheng
FAE Support, Asia
Mobile: +886.938.009.706
peter.cheng@epc-co.com
Logic and
Dead-time
Adjust
External Circuit
Stephen Tsang
Sales, Asia
Mobile: +852.9408.8351
stephen.tsang@epc-co.com
Quick Start Procedure
EPC
Bhasy Nair
Global FAE Support
Office: +1.972.805.8585
Mobile: +1.469.879.2424
bhasy.nair@epc-co.com
Development board EPC9006 is easy to set up to evaluate the performance of the EPC2007 eGaN FET. Refer to Figure 2 for proper connect
and measurement setup and follow the procedure below:
100
Renee Yawger
WW Marketing
Office: +1.908.475.5702
Mobile: +1.908.619.9678
renee.yawger@epc-co.com
With power off, connect the input power supply bus to +VIN (J5,J6) and ground / return to –VIN (J7,J8).
With power off, connect the switch node of the half bridge OUT (J3,J4) to your circuit as required.
With power off, connect the gate drive input to +VDD (J1, Pin-1) and ground return to –VDD (J1, Pin-2).
With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins.
Turn on the gate drive supply – make sure the supply is between 7 V and 12 V range.
Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage of 100 V on VOUT).
Turn on the controller / PWM input source and probe switching node to see switching operation.
Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior,
efficiency and other parameters.
For shutdown, please follow steps in reverse.
Do not use probe ground lead
6,
www.epc-co.com
Development Board EPC9006
Quick Start Guide
100 V Half-Bridge with Gate Drive, Using EPC2007
Development Board / Demonstration Board Notification
The EPC9006 board is intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not
designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations.
As board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are
not RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant.
No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications
assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
EPC reserves the right at any time, without notice, to change said circuitry and specifications.
www.epc-co.com
The EPC9006 development board is a 100 V maximum device voltage, 5 A maximum output current, half bridge with onboard gate
drives, featuring the EPC2007 enhancement mode (eGaN®) field
effect transistor (FET). The purpose of this development board is
to simplify the evaluation process of the EPC2007 eGaN FET by
including all the critical components on a single board that can be
easily connected into any existing converter.
The EPC9006 development board is 2” x 1.5” and contains not
only two EPC2007 eGaN FET in a half bridge configuration using
Table 1
EPC Products are distributed exclusively through Digi-Key.
www.digikey.com
1.
2.
3.
4.
5.
6.
7.
8.
9.
Place probe in large via at OUT
Contact us:
DESCRIPTION
National LM5113 gate driver, supply and bypass capacitors. The
board contains all critical components and layout for optimal
switching performance. There are also various probe points to facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2007s eGaN FET please refer to
the datasheet available from EPC at www.epc-co.com. The datasheet should be read in conjunction with this quick start guide.
Performance Summary (TA = 25°C)
SYMBOL
VDD
PARAMETER
Gate Drive Input Supply Range
VIN
CONDITIONS
MIN
7
MAX
12
UNITS
V
Bus Input Voltage Range
70*
V
VOUT
Switch Node Output Voltage
100
V
IOUT
Switch Node Output Current
5*
A
VPWM
PWM Logic Input Voltage Threshold
Input ‘High’
3.5
6
V
0
30
100#
1.5
Minimum ‘High’ State Input Pulse Width
Minimum ‘Low’ State Input Pulse Width
Input ‘Low’
VPWM rise and fall time < 10ns
VPWM rise and fall time < 10ns
V
ns
ns
*Assumes inductive load, maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus voltage and thermals.
# Limited by time needed to ‘refresh’ high side bootstrap supply voltage.
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