F25L04UA-100PG

ESMT Flash FEATURES Single supply voltage 2.7~3.6V Speed - Read max frequency : 33MHz - Fast Read max frequency : 50MHz; 75MHz; 100MHz Low power consumption - Active current :40mA - Standby current : 25 μ A Reliability - 100,000 program/erase cycles typically - 10 years Data Retention Program - Byte program time 8 μ s(typical) Erase - Chip erase time 11s(typical) F25L04UA 3V Only 4 Mbit Serial Flash Memory - Sector erase time 0.7s(typical) Auto Address Increment (AAI) Programming - Decrease total chip programming time over Byte-Program operations SPI Serial Interface - SPI Compatible : Mode 0 and Mode3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) Package avalible - 8-pin SOIC 150-mil ORDERING INFORMATION Part No. F25L04UA -50PG F25L04UA -75PG Speed 50MHz 75MHz Package 8 lead SOIC 8 lead SOIC COMMENTS Pb-free Pb-free Pb-free F25L04UA -100PG 100MHz 8 lead SOIC GENERAL DESCRIPTION The F25L04UA is a 4Megabit, 3V only CMOS Serial Flash memory device. ESMT’s memory devices reliably store memory data even after 100,000 program and erase cycles. The F25L04UA features a sector erase architecture. The device memory array is divided into one 8K bytes, two 4K bytes, one 16K bytes, one 32K bytes, and seven 64K bytes. Sectors can be erased individually without affecting the data in other sectors. Whole chip erase capabilities provide the flexibility to revise the data in the device. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 1/25 ESMT PIN CONFIGURATIONS 8-PIN SOIC F25L04UA 0 CE 1 8 VDD SO 2 3 7 6 HOLD SCK WP VSS 4 5 SI PIN Description Symbol SCK SI Pin Name Serial Clock Serial Data Input Functions To provide the timming for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK. To transfer data serially out of the device. Data is shifted out on the falling edge of SCK. To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporaiily stop serial communication with SPI flash memory without resetting the device. To provide power. SO CE WP Serial Data Output Chip Enable Write Protect HOLD VDD VSS Hold Power Supply Ground Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 2/25 ESMT SECTOR STRUCTURE F25L04UA Table1 : F25L04UA Sector Address Table Symbol 11 10 9 8 7 6 5 4 3 2 1 0 Sector Size (Kbytes) 8KB 4KB 4KB 16KB 32KB 64KB 64KB 64KB 64KB 64KB 64KB 64KB Address range 7E000H – 7FFFFH 7D000H – 7DFFFH 7C000H – 7CFFFH 78000H – 7BFFFH 70000H – 77FFFH 60000H – 6FFFFH 50000H – 5FFFFH 40000H – 4FFFFH 30000H – 3FFFFH 20000H – 2FFFFH 10000H – 1FFFFH 00000H – 0FFFFH Sector Address A18 1 1 1 1 1 1 1 1 0 0 0 0 A17 1 1 1 1 1 1 0 0 1 1 0 0 A16 1 1 1 1 1 0 1 0 1 0 1 0 A15 1 1 1 1 0 X X X X X X X A14 1 1 1 0 X X X X X X X X A13 1 0 0 X X X X X X X X X A12 X 1 0 X X X X X X X X X Table2 : F25L04UA Block Protection Table Protection Level 0 1(1/8 memory array) 2(1/4 memory array) 3(all memory array) BP1 0 0 1 1 BP0 0 1 0 1 Protected Memory Area None 70000H –7FFFFH 60000H –7FFFFH 00000H –7FFFFH Block Protection (BP1, BP0) The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table2 to be software protected against any memory Write (Program or Erase) operations. The Write-Status-Register (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP is high or the Block-Protection-Look (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are both 0. After power-up, BP1 and BP0 are set to1. Block Protection Lock-Down (BPL) WP pin driven low (VIL), enables the Block-Protection -Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 3/25 ESMT FUNTIONAL BLOCK DIAGRAM F25L04UA Address Buffers and Latches X-Decoder SuperFlash Memory Y-Decoder Control Logic I/O Butters and Data Latches Serial Interface CE SCK SI SO WP HOLD Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 4/25 ESMT Hold Operation HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal’s rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not F25L04UA coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 3 for Hold Condition waveform. Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 17 for Hold timing. S CK HO L D A ctive Ho ld A ctive Ho ld A ctive Figure 3 : HOLD CONDITION WAVEFORM Write Protection F25L04UA provides software Write protection. The Write Protect pin ( WP ) enables or disables the lockdown function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. See Table 2 for Block-Protection description. TABLE3: CONDITIONS TO EXECUTE WRITE-STATUS- REGISTER (WRSR) INSTRUCTION WP BPL 1 0 X Execute WRSR Instruction Not Allowed Allowed Allowed L L Write Protect Pin ( WP ) The Write Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined by the value of the BPL bit (see Table 3). When WP is high, the lock-down function of the BPL bit is disabled. H Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 5/25 ESMT Status Register The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation, F25L04UA the status register may be read only to determine the completion of an operation in progress. Table 4 describes the function of each bit in the software status register. TABLE 4: SOFTWARE STATUS REGISTER Bit 0 1 2 3 4:5 6 7 Name BUSY WEL BP0 BP1 RES AAI BPL Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 2) Indicate current level of block write protection (See Table 2) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Byte-Program mode 1 = BP1, BP0 are read-only bits 0 = BP1, BP0 are read/writable Default at Power-up 0 0 1 1 0 0 0 Read/Write R R R/W R/W N/A R R/W Note1 : Only BP0,BP1 and BPL are writable Note2 : All register bits are volatility Note3 : All area are protected at power-on (BP1=1,BP0=1) Busy The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. Write Enable Latch (WEL) The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions: Power-up Write-Disable (WRDI) instruction completion Byte-Program instruction completion Auto Address Increment (AAI) programming reached its highest memory address • Sector-Erase instruction completion • Block-Erase instruction completion • Chip-Erase instruction completion • • • • Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 6/25 ESMT Instructions Instructions are used to Read, Write (Erase and Program), and configure the F25L04UA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of F25L04UA SCK starting with the most significant bit. CE must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read-ID and Read-Status-Register instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first. TABLE 5: DEVICE OPERATION INSTRUCTIONS Cycle Type/ Operation1,2 Read High-Speed-Read Sector-Erase4,5 Chip-Erase5 5 Byte-Program Auto Address Increment word programming (AAI)6 Read-Status-Register (RDSR) Enable-Write-Status-Register 8 (EWSR) Write-Status-Register (WRSR)8 Write-Enable (WREN) 11 Write-Disable (WRDI) Jedec-Read-ID (JEDEC-ID) 10 1. 2. 3. 4. 5. 6. 7. 8. Max Freq MHz 33 Bus Cycle4 1 SIN 03H 0BH 20H 60H 02H AFH 05H 50H 01H 06H 04H 9FH SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 2 SIN A23-A16 A23-A16 A23-A16 A23-A16 A23-A16 X Data X SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DOUT Hi-Z 8CH 3 SIN A15-A8 A15-A8 A15-A8 A15-A8 A15-A8 X SOUT Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note7 8CH 4 SIN A7-A0 A7-A0 A7-A0 A7-A0 A7-A0 -. X SOUT SIN Hi-Z X Hi-Z X Hi-Z Hi-Z DIN Hi-Z Note7 8CH DIN 5 SOUT DOUT X Hi-Z Hi-Z Note7 SIN X 6 SOUT DOUT 50 and 75 and 100 Operation: SIN = Serial In, SOUT = Serial Out X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary) One bus cycle is eight clock periods. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH Prior to any Byte-Program, AAI-Program, Sector-Erase ,or Chip-Erase operation, the Write-Enable (WREN) instruction must be executed. To continue programming to the next sequential address location, enter the 8-bit command, AFH, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective. 9. The Jedec-Read-ID is continuous with on going clock cycles until terminated by a low to high transition on CE . 10. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 8CH as top memory type; third byte 8CH as memory capacity. 11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 7/25 ESMT Read (33 MHz) The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning F25L04UA (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address location 7FFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE must remain active low for the duration of the Read cycle. See Figure 4 for the Read sequence. CE MODE3 SCK MODE1 12345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 70 SI MSB 03 ADD. MSB ADD. ADD. SO HIGH IMPENANCE MSB N DOUT N+1 DOUT N+2 DOUT N+3 DOUT N+4 D OUT Figure 4 : READ SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 8/25 ESMT Fast-Read (50 MHz ; 75 MHz; 100 MHz) The High-Speed-Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE must remain active low for the duration of the High-Speed-Read cycle. See Figure 5 for the High-Speed-Read sequence. Following a dummy byte (8 clocks input dummy cycle), the High-Speed-Read instruction outputs the data starting from the specified address location. The data output stream is continuous F25L04UA through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 4 Mbit density, once the data from address location 07FFFFH has been read, the next output will be from address location 000000H. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80 SI MSB 0B ADD. MSB HIGH IMPENANCE ADD. ADD. X N DOUT MSB N+1 DOUT N+2 DOUT N+3 DOUT N+4 DOUT SO Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH) Figure 5 : HIGH-SPEED-READ SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 9/25 ESMT Byte-Program The Byte-Program instruction programs the bits in the selected byte to the desired data. The selected byte must be in the erased state (FFH) when initiating a Program operation. A Byte-Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Byte-Program instruction. The Byte-Program F25L04UA instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, the data is input in order from MSB (bit 7) to LSB (bit 0). CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TBP for the completion of the internal self-timed Byte-Program operation. See Figure 6 for the Byte-Program sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 SI MSB 02 ADD. MSB HIGH IMPENANCE ADD. ADD. DIN MSB LSB SO Figure 6 : BYTE-PROGRAM SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 10/25 ESMT Auto Address Increment (AAI) Program The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. Prior to any write operation, the Write-Enable (WREN) instruction must be executed. The AAI program instruction is initiated by executing an 8-bit command, AFH, followed by address bits [A23-A0]. Following the addresses, the data is input sequentially from MSB (bit 7) to LSB (bit 0). CE must be driven high before the AAI program instruction is executed. The user must poll the F25L04UA BUSY bit in the software status register or wait TBP for the completion of each internal self-timed Byte-Program cycle. Once the device completes programming byte, the next sequential address may be program, enter the 8-bit command, AFH, followed by the data to be programmed. When the last desired byte had been programmed, execute the Write-Disable (WRDI) instruction, 04H, to terminate AAI. After execution of the WRDI command, the user must poll the Status register to ensure the device completes programming. See Figure 7 for AAI programming sequence. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0). TBP CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 333435 36 373839 0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 T BP 01 SI AF A[23,16] A[15,8] A[7,0] Data Byte 1 AF Data Byte 2 TBP CE 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 SCK 01234567 0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15 SI AF Last Data Byte 04 Write Disable (WRDI) Instruction to terminate AAI Operation 05 Read Status Register(RDSR) Instruction to verify end of AAI Operation DOUT SO Figure 7 : AUTO ADDRESS INCREMENT (AAI) PROGRAM SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 11/25 ESMT Sector-Erase The Sector-Erase instruction clears all bits in the selected sector to FFH. A Sector-Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector-Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23-A0]. Address bits F25L04UA [AMS-A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TSE for the completion of the internal self-timed Sector-Erase cycle. See Figure 8 for the Sector-Erase sequence. CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 SI MSB 02 A DD. MSB HIGH IMPENANCE ADD. A DD. D IN SO FIGURE 8 : SECTOR-ERASE SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 12/25 ESMT Chip-Erase The Chip-Erase instruction clears all bits in the device to FFH. A Chip-Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write-Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip-Erase instruction is initiated by executing an 8-bit command, F25L04UA 60H. CE must be driven high before the instruction is executed. The user may poll the Busy bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure 9 for the Chip-Erase sequence. CE MODE3 SCK MODE0 01234567 SI MSB 60 SO HIGH IMPENANCE FIGURE 9 : CHIP-ERASE SEQUENCE Read-Status-Register (RDSR) The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. Read-Status-Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE See Figure 10 for the RDSR instruction sequence. CE MODE3 SCK MODE1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SI MSB HIGH IMPENANCE 05 SO Bit7 MSB Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Status Register Out Figure10 : READ-STATUS-REGISTER (RDSR) SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 13/25 ESMT Write-Enable (WREN) The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE must be driven high before the WREN instruction is executed. F25L04UA CE MODE3 SCK MODE0 01234567 SI MSB 06 SO HIGH IMPENANCE FIGURE 11 : WRITE ENABLE (WREN) SEQUENCE Write-Disable (WRDI) The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed. CE MODE3 SCK MODE0 01234567 SI MSB 04 SO HIGH IMPENANCE Figure 12 : WRITE DISABLE (WRDI) SEQUENCE Enable-Write-Status-Register (EWSR) The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR) instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 14/25 ESMT Write-Status-Register (WRSR) The Write-Status-Register instruction works in conjunction with the Enable-Write-Status-Register (EWSR) instruction to write new values to the BP1, BP0, and BPL bits of the status register. The Write-Status-Register instruction must be executed immediately after the execution of the Enable-Write-Status -Register instruction (very next instruction bus cycle). This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like SDP (software data protection) command structure which prevents any accidental alteration of the status register values. The Write-Status-Register instruction will be ignored when WP is low and BPL bit is set to “1”. When the WP is low, the BPL bit can only be set from “0” to “1” to lockdown the status register, but cannot be reset from “1” to “0”. F25L04UA When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, and BP1 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the BP0, BP1, and BPL bit in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to “1” to lock down the status register as well as altering the BP0 and BP1 bit at the same time. See Table 3 for a summary description of WP and BPL functions. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. See Figure 13 for EWSR and WRSR instruction sequences. CE MODE3 SCK MODE0 STATUS REGISTER IN 76543210 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 SI MSB 50 MSB HIGH IMPENANCE 01 SO Figure 13 : ENABLE-WRITE-STATUS-REGISTER (EWSR) AMD WRITE-STATUS-REGISTER (WRSR) SEQUENCE Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 15/25 ESMT Jedec-Read-ID (JEDEC-ID) F25L04UA The Jedec-Read-ID instruction is for reading the Manufacturer ID of 1-byte and followed by Device ID of 2-byte. The ESMT Manufacturer ID is 8CH.,the memory type ID is 8CH as the first-byte device ID, the memory capacity ID is 8CH as the second-byte device ID. The instruction sequence is shown in Fig14. The Jedec-Read-ID instruction is terminated by a low to high transition on CE at any time during data output. Figure 14 : Jedec-Read-ID (JEDEC-ID) CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1920 2122 23 24 2526 27 282930 31 32 33 34 SI 9F SO HIGH IMPENANCE MSB 8C MSB 8C 8C Jedec-Read-ID DATA Manufacture’s ID Device ID Memory Type Byte1 8CH Byte2 8CH Memory Capacity Byte3 8CH Elite Semiconductor Memory Technology Inc. Publication Date: Jan. 2009 Revision: 1.2 16/25 ESMT ELECTRICAL SPECIFICATIONS F25L04UA Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (