M12L16161A-6T

M12L16161A 512K x 16Bit x 2Banks Synchronous DRAM FEATURES z z z z z z z z z GENERAL DESCRIPTION JEDEC standard 3.3V power supply The M12L16161A is 16,777,216 bits synchroLVTTL compatible with multiplexed address nous high data rate Dynamic RAM organized as Dual banks operation 2 x 524,288 words by 16 bits, fabricated with MRS cycle with address key programs high performance CMOS technology. Synchro- CAS Latency (2 & 3 ) nous design allows precise cycle control with the - Burst Length (1, 2, 4, 8 & full page) use of system clock I/O transactions are possible - Burst Type (Sequential & Interleave) on every clock cycle. Range of operating freAll inputs are sampled at the positive going edge quencies, programmable burst length and programmable latencies allow the same device to be of the system clock Burst Read Single-bit Write operation useful for a variety of high bandwidth, high performance memory system applications. DQM for masking Auto & self refresh 32ms refresh period (2K cycle) ORDERING INFORMATION Part NO. M12L16161A-4.3T M12L16161A-5T M12L16161A-5.5T M12L16161A-6T M12L16161A-7T M12L16161A-8T MAX Freq. 233MHz 200MHz 183MHz 166MHz 143MHz 125MHz Interface Package LVTTL 50 TSOP(II) PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP(II) (400mil x 825mil) (0.8 mm PIN PITCH) Elite Semiconductor Memory Technology Inc. P.1 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A FUNCTIONAL BLOCK DIAGRAM I/O Control Bank Select Data Input Register LWE LDQM Row Buffer Refresh Counter Row Decoder Output Buffer 512K x 16 512K x 16 Sense AMP Address Register LRAS CLK CKE DQi CLK ADD LCBR Col. Buffer LRAS Column Decoder Latency & Burst Length Programming Register LCKE LCBR LWE LCAS LWCBR LDQM Timing Register CS RAS CAS WE L(U)DQM PIN FUNCTION DESCRIPTION Pin CLK CS CKE A0 ~ A10/AP BA Name System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. RAS CAS Column Address Strobe WE L(U)DQM DQ0 ~ 15 VDD/VSS Write Enable Data Input / Output Mask Data Input / Output Power Supply/Ground Elite Semiconductor Memory Technology Inc. P.2 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A VDDQ/VSSQ N.C/RFU Data Output Power/Ground No Connection/ Reserved for Future Use Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN,VOUT VDD,VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ + 150 1 50 Unit V V °C W MA Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA=0 to 70 °C ) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Note : Symbol VDD,VDDQ VIH VIL VOH VOL IIL IOL Min 3.0 2.0 -0.3 2.4 -5 -5 Typ 3.3 3.0 0 Max 3.6 VDD+0.3 0.8 0.4 5 5 Unit V V V V V uA uA Note 1 2 IOH =-2mA IOL = 2mA 3 4 1.VIH (max) = 4.6V AC for pulse width ≤ 10ns acceptable. 2.VIL (min) = -1.5V AC for pulse width ≤ 10ns acceptable. 3.Any input 0V ≤ VIN ≤ VDD+ 0.3V, all other pins are not under test = 0V. 4.Dout is disabled, 0V ≤ VOUT ≤ VDD. CAPACITANCE (VDD = 3.3V, TA = 25 °C , f = 1MHz) Pin CLOCK RAS , CAS , WE , CS , CKE, LDQM, UDQM ADDRESS DQ0 ~DQ15 Symbol CCLK CIN CADD COUT Min 2.5 2.5 2.5 4.0 Max 4.0 5.0 5.0 6.5 Unit pF pF pF pF Elite Semiconductor Memory Technology Inc. P.3 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70 °C VIH(min)/VIL(max)=2.0V/0.8V) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non powerdown mode Symbol ICC1 ICC2P ICC2PS ICC2N Test Condition CAS Version Latency -4.3 -5 -5.5 -6 -7 -8 Unit Note 1 Burst Length = 1 tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA CKE ≤ VIL(max), tCC =15ns CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns Input signals are changed one time during 30ns CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable CKE ≤ VIL(max), tCC =15ns CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns Input signals are changed one time during 30ns CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞ Input signals are stable IOL= 0Ma, Page Burst All Band Activated, tCCD = tCCD (min) 3 2 250 230 210 190 160 140 mA 2 2 30 2 10 10 40 10 mA mA mA mA mA mA ICC2NS Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current Self Refresh Current ICC3P ICC3PS ICC3N ICC3NS ICC4 270 250 230 210 180 160 mA 270 250 230 210 180 160 270 250 230 210 180 160 mA 1 mA 1 ICC5 ICC6 tRC ≥ tRC(min) CKE ≤ 0.2V 2 Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min). 2.Refresh period is 32ms. Addresses are changed only one time during tCC(min). Elite Semiconductor Memory Technology Inc. P.4 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V,TA= 0 to 70 °C ) Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3. 3V Vtt =1.4V 1200 è 50 Output VOH(DC ) = 2.4V, I OH = -2mA VOL(DC) = 0.4V, IOL = 2mA Output Value 2.4 / 0.4 1.4 tr / tf = 1 / 1 1.4 See Fig.2 Unit V V ns V è Z0=50 è 30 pF 870 è 30 pF (Fig.1) DC Output Load circ ui t ( Fig.2) AC Output Load C ircui t OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Symbol -4.3 8.6 12.9 12.9 34.4 47.3 -5 10 15 15 40 55 Version -5.5 -6 11 12 16 16 40 100 60 1 1 1 1 1 1 60 63 68 16 18 42 -7 14 16 20 42 -8 16 20 20 48 Unit ns ns ns ns us ns CLK CLK CLK CLK ea 1 2 2 2 3 4 Note 1 1 1 1 Last data in to new col. Address delay Last data in to row precharge Last data in to burst stop Col. Address to col. Address delay Number of valid output data CAS latency=3 CAS latency=2 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 4. Minimum delay is required to complete write. 4. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks. Elite Semiconductor Memory Technology Inc. P.5 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CLK cycle time CLK to valid output delay CAS Latency =3 CAS Latency =2 CAS Latency =3 CAS Latency =2 Symbol -4.3 -5 -5.5 -6 -7 -8 Unit Note Min Max Min Max Min Max Min Max Min Max Min Max 4.3 6 2 1.7 1.7 1.7 1 1 4 5 1000 4 5 5 7 2 2 2 2 1 1 4.5 5 1000 4.5 5 5.5 7.5 2.5 2 2 2 1 1 5 6 1000 5 6 6 8 2.5 2 2 2 1 1 5.5 6 1000 5.5 6 7 8.6 2.5 2.5 2.5 2 1 1 6 6 1000 6 6 8 10 2.5 3 3 2.5 1 1 6 7 1000 ns 6 7 ns ns ns ns ns ns ns ns 1 1 2 3 3 3 3 2 tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS Latency =3 CAS latency =2 *All AC parameters are measured from half to half. Note: 1.Parameters depend on programmed CAS latency. 2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter. 3.Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter. Elite Semiconductor Memory Technology Inc. P.6 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A FREQUENCY vs. AC PARAMENTER RELATIONAHIP TABLE M12L16161A-4.3T Frequency 233MHz(4.3ns) 200MHz(5.0ns) 183MHz(5.5ns) 166MHz(6.0ns) 143MHz(7.0ns) CAS Latency 3 3 3 3 2 tRC 47.3ns 11 10 10 9 7 tRAS 34.3ns 8 7 7 6 5 tRP 12.9ns 3 3 3 3 2 tRRD 8.6ns 2 2 2 2 2 tRCD 12.9ns 3 3 3 3 2 tCCD 4.3ns 1 1 1 1 1 (Unit: number of clock) tCDL 4.3ns 1 1 1 1 1 tRDL 4.3ns 1 1 1 1 1 M12L16161A-5T Frequency 200MHz(5.0ns) 183MHz(5.5ns) 166MHz(6.0ns) 143MHz(7.0ns) 125MHz(8.0ns) 111MHz(9.0ns) CAS Latency 3 3 3 2 2 2 tRC 55ns 11 10 10 9 7 7 tRAS 40ns 8 8 7 6 5 5 tRP 15ns 3 3 3 3 2 2 tRRD 10ns 2 2 2 2 2 2 tRCD 15ns 3 3 3 3 2 2 (Unit: number of clock) tCCD 5ns 1 1 1 1 1 1 tCDL 5ns 1 1 1 1 1 1 tRDL 5ns 1 1 1 1 1 1 M12L16161A-5.5T Frequency 183MHz(5.5ns) 166MHz(6.0ns) 143MHz(7.0ns) 125MHz(8.0ns) 111MHz(9.0ns) CAS Latency 3 3 2 2 2 tRC 60ns 11 10 9 8 7 tRAS 40ns 8 7 6 5 5 tRP 16ns 3 3 3 2 2 tRRD 11ns 2 2 2 2 2 tRCD 16ns 3 3 3 2 2 (Unit: number of clock) tCCD 5.5ns 1 1 1 1 1 tCDL 5.5ns 1 1 1 1 1 tRDL 5.5ns 1 1 1 1 1 M12L16161A-6T Frequency 166MHz(6.0ns) 143MHz(7.0ns) 125MHz(8.0ns) 111MHz(9.0ns) 100MHz(10.0ns) CAS Latency 3 3 2 2 2 tRC 60ns 10 9 9 7 7 tRAS 42ns 7 6 6 5 5 tRP 18ns 3 3 3 2 2 tRRD 12ns 2 2 2 2 2 tRCD 16ns 3 3 2 2 2 (Unit: number of clock) tCCD 6ns 1 1 1 1 1 tCDL 6ns 1 1 1 1 1 tRDL 6ns 1 1 1 1 1 M12L16161A-7T Frequency 143MHz(7.0ns) 125MHz(8.0ns) 111MHz(9.0ns) 100MHz(10.0ns) 83MHz(12.0ns) CAS Latency 3 3 2 2 2 tRC 62ns 9 9 8 7 6 tRAS 42ns 6 6 5 5 4 tRP 20ns 3 3 3 2 2 tRRD 14ns 2 2 2 2 2 tRCD 16ns 3 2 2 2 2 (Unit: number of clock) tCCD 7ns 1 1 1 1 1 tCDL 7ns 1 1 1 1 1 tRDL 7ns 1 1 1 1 1 M12L16161A-8T Frequency 125MHz(8.0ns) 111MHz(9.0ns) 100MHz(10.0ns) 83MHz(12.0ns) 75MHz(13.0ns) CAS Latency 3 3 2 2 2 tRC 68ns 9 9 7 6 6 tRAS 48ns 6 6 5 4 4 tRP 20ns 3 3 2 2 2 tRRD 16ns 2 2 2 2 2 tRCD 20ns 3 3 2 2 2 (Unit: number of clock) tCCD 8ns 1 1 1 1 1 tCDL 8ns 1 1 1 1 1 tRDL 8ns 1 1 1 1 1 Elite Semiconductor Memory Technology Inc. P.7 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Mode Register 11 0 11 x 11 11 x 11 0 10 0 10 x 10 10 x 10 0 9 0 9 1 9 9 x 9 0 8 0 8 0 8 1 8 1 8 0 7 1 7 0 7 0 7 1 7 0 6 5 4 3 2 2 1 1 BL 1 2 v 2 1 v 1 BL 0 JEDEC Standard Test Set (refresh counter test) 6 5 43 LTMODE WT 6 6 v 6 5 4 3 0 Burst Read and Single Write (for Write Through Cache) 0 Use in future 5 43 v v v 5 43 LTMODE WT 0 v 0 Vender Specific Mode Register Set Bit2-0 000 001 010 011 100 101 110 111 0 1 v =Valid x =Don’t care WT=0 1 2 4 8 R R R Full page Sequential Interleave WT=1 1 2 4 8 R R R R 2 Burst length Wrap type Bits6-4 000 001 010 011 100 101 110 111 Latency mode CAS Latency R R 2 3 R R R R Remark R : Reserved Mode Register Write Timing C LOC K CKE CS RA S C AS WE A 0-A 11 M od e R e g is t e r W r it e Elite Semiconductor Memory Technology Inc. P.8 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Burst Length and Sequence (Burst of Two) Starting Address (column address A0 binary) 0 1 Sequential Addressing Sequence (decimal) 0, 1 1, 0 Interleave Addressing Sequence (decimal) 0, 1 1, 0 (Burst of Four) Starting Address (column address A1-A0, binary) 00 01 10 11 Sequential Addressing Sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Addressing Sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 (Burst of Eight) Starting Address (column address A2-A0, binary) 000 001 010 011 100 101 110 111 Sequential Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice. POWER UP SEQUENCE 1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs. 2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3.Issue precharge commands for all banks of the devices. 4.Issue 2 or more auto-refresh commands. 5.Issue mode register set command to initialize the mode register. Cf.)Sequence of 4 & 5 is regardless of the order. Elite Semiconductor Memory Technology Inc. P.9 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A SIMPLIFIED TRUTH TABLE COMMAND Mode Register Set Auto Refresh Entry Self Refresh Exit CKEn-1 CKEn CS H X L H H L L L L H H H X L H H H H H L H L H H H X X X X L H L H L L L L H L X H L H L H L RAS L L H X L H H H L X V X X H X V X X H CAS L L H X H L L H H X V X X H X V X H WE L H H X H H L L L X V X X H X V X H DQM BA A10/AP A9~A0 Note X OP CODE 1,2 3 X X 3 3 X X 3 X V Row Address Column 4 L X V Address (A0~A7) 4,5 H Column L 4 X V Address H (A0~A7) 4,5 X X 6 V L 4 X X X H 4 X X X X X V X X X 7 X Register Refresh Bank Active & Row Addr. Auto Precharge Disable Read & Column Address Auto Precharge Enable Auto Precharge Disable Write & Column Auto Precharge Enable Address Burst Stop Bank Selection Precharge Both Banks Clock Suspend or Active Power Down Precharge Power Down Mode Entry Exit Entry Exit DQM No Operation Command X (V= Valid, X= Don’t Care, H= Logic High , L = Logic Low) Note:1 OP Code: Operation Code A0~ A10/AP, BA: Program keys.(@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by “Auto”. Auto / self refresh can be issued only at both banks precharge state. 4. BA: Bank select address. If “Low”: at read, write, row active and precharge, bank A is selected. If “High”: at read, write, row active and precharge, bank B is selected. If A10/AP is “High” at row precharge, BA ignored and both banks are selected. 5.During burst read or write with auto precharge, new read/write command can not be issued. Another bank read /write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6.Burst stop command is valid at every burst length. 7.DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Elite Semiconductor Memory Technology Inc. P .10 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1 tC H 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC H IG H CKE * Note 1 tRAS tR C tSH tRP tSS CS tRC D tSH RAS tS S CAS tSS tS H ADDR Ra tSS * Note 2 * Note 2,3 tCCD tSH tS S Ca Cb tSH * Note 2,3 * N ote2, 3 * Note 4 * Note2 Cc Rb BA BS BS BS BS BS BS A10 /A P Ra * N ote 3 * Not e 3 * Not e 3 * Note 4 Rb tRAC tSAC DQ Qa tSLZ WE tS S tSS DQM tS H tOH Db tSS tS H tSH Qc Row A ct ive Rea d Write Rea d Precharg e Row A c tiv e :Don't Care Elite Semiconductor Memory Technology Inc. P .11 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A *Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. BA 0 1 Active & Read/Write Bank A Bank B 3.Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA Operation 0 Disable auto precharge, leave bank A active at end of burst. 0 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 1 Enable auto precharge, precharge bank B at end of burst. 4.A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA 0 0 0 1 1 X precharge Bank A Bank B Both Banks Elite Semiconductor Memory Technology Inc. P .12 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Power Up Sequence 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE H igh l evel i s neces sary CS tRP RAS tRC tRC CAS ADD R Key RAa BA Key A10/AP Key RAa High- Z DQ WE DQM H ig h l evel i s nec es s ar y Precharge All Ba nks Auto Refresh Auto Refresh Mo d e Reg i s ter S et (A -Bank) Row A ct ive : D on't care Elite Semiconductor Memory Technology Inc. P .13 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Read & Write Cycle at Same Bank @Burst Length = 4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 C KE H IG H tR C CS * N o te 1 tR CD RA S * N o te 2 C AS AD D R Ra Ca 0 Rb Cb0 BA A1 0 /A P Ra Rb t OH CL=2 QC C L=3 R AC * N o te 3 tR A C * N o te 3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tSAC Qa0 tOH Qa1 Qa2 tS H Z Qa3 * N o te 4 tR DL Db0 Db1 Db2 Db3 t t S AC tSHZ *N o t e 4 tR DL WE DQ M Ro w Ac ti v e ( A - B a nk ) R ea d ( A -B a n k ) Pr e c h a r g e ( A -B a n k ) Ro w Ac t ive ( A -B a n k ) Wri te ( A -B a n k ) Pr ec ha rg e ( A -B a n k ) : D o n 't c a r e *Note: 1.Minimum row cycle times is required to complete internal DRAM operation. 2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clock. 3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC 4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst) Burst can’t end in Full Page Mode. Elite Semiconductor Memory Technology Inc. P .14 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Page Read & Write Cycle at Same Bank @ Burst Length=4 0 CLOCK CK E CS HIGH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRCD RAS *Note2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra t RD L CL=2 DQ Qa0 Qa1 Qb1 Qb2 Dc0 Dc1 Dd0 Dd2 Qa0 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 CL=3 tC DL WE * Note 3 *Note1 DQM Row Active (A-Bank) Read (A-Bank) Read ( A-Bank) Wri te ( A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. P .15 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Page Read Cycle at Different Bank @ Burst Length=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE *Note 1 HIGH CS RAS *Note 2 CAS ADDR RAa CAa RB b CBb CAc CBd CAe BA A10/AP RAa RBb CL=2 DQ CL=3 QAa 0 QAa 1 QAa2 QAa3 QBb 0 QBb1 QBb 2 QBb3 QAc0 QAc1 QBd 0 QBd1 QAe0 QAe1 QAa0 QAa1 QAa2 QAa3 QBb0 QBb 1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Ban k) Rea d (B-Bank) Rea d (A-Ba nk) Rea d ( B-Bank) Rea d ( A-Ba nk ) Prech arge (A-Ba nk) : D on't care *Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege. 2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. P .16 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Page Write Cycle at Different Bank @Burst Length = 4 0 CL O CK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CK E HIGH CS RAS CAS * Note2 ADD R RAa C Aa R Bb C Bb CAc C Bd BA A10/AP RAa R Bb DQ DAa0 DAa1 DAa2 DAa3 D Bb0 DBb1 D Bb2 D Bb3 DAc 0 DAc1 DBd0 DBd1 tCDL WE tRD L *Note 1 DQM Row Active ( A-Bank) Row Active ( B-Ba nk) W rite ( A-Bank) W rite (B-B ank) W rite ( A-Bank) Wri te ( B-Bank) Prec harge (B oth B anks ) : D o n 't c a r e *Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. P .17 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Read & Write Cycle at Different Bank @ Burst Length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE HIGH CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc BA A10/AP RAa RBb RBb RAc *Note1 tCDL CL=2 DQ CL=3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 QAc0 QAc1 QAc2 WE DQM Row Active (A-Bank) Read (A-Bank) Row Active (B-Bank) Precharge (A-Bank) W rite (B-Bank) Row Active (A-Bank) Read (A-Bank) :D on't Care *Note: 1.tCDL should be met to complete write. Elite Semiconductor Memory Technology Inc. P .18 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Read & Write Cycle with auto Precharge @ Burst Length =4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE H IG H CS RAS CAS ADDR Ra Rb Ca Cb BA A1 0 /A P Ra Rb CL=2 DQ C L=3 Qa 0 Qa 1 Qa 2 Qa 3 D b0 Db1 Db2 D b3 Qa 0 Qa 1 Qa2 Qa3 Db0 D b1 D b2 D b3 WE DQM Row Active ( A - Ba nk ) Rea d wi th Auto P recha rge ( A - Ban k ) Row Active ( B - Bank ) CL= 2 Auto Precha rge Start P oin t ( A - Ba nk) CL= 3 Auto Precharge Start Point ( A - Bank ) Write with Auto Prec harge (B-Bank) Auto Precha rge Sta rt Point (B-Bank) :Don't Care *Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start (In the case of Burst Length=1 & 2 and BRSW mode) Elite Semiconductor Memory Technology Inc. P .19 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE CS RAS CAS ADDR Ra Ca Cb Cc BA A10/AP Ra DQ Qa 0 Qa 1 Qa 2 Qa 3 Qb 0 Qb 1 Dc0 Dc 2 tSHZ WE tSHZ *Note1 DQM Row Ac t iv e Read Clock S u s p en s i o n Read W rite DQM Read DQM Writ e Clock S u s p en s i o n Writ e DQ M :Don't Care *Note:1.DQM is needed to prevent bus contention. Elite Semiconductor Memory Technology Inc. P .20 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK CKE HIGH CS RAS CAS ADDR RAa CAa CAb BA A1 0/ AP RAa *Note2 1 1 Q A b 0 Q A b 1 QA b 2 QA b 3 QA b 4 Q A b 5 CL=2 DQ CL=3 QAa0 QAa1QA a2 QAa3QAa4 2 QA a0 QAa1 QAa2 QAa3 QAa4 2 Q A b 0 Q A b 1 QA b 2 Q A b 3 Q A b 4 Q A b 5 WE *Note1 DQM Row Active (A-Bank) Read (A-Bank) B ur s t St op R ead (A-Bank) Pre charg e (A-Bank) :Don't Care *Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue. 2.About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycle”. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. P .21 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page 0 CL OC K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CKE HIGH CS RAS CA S ADDR RA a CAa CAb BA A1 0 /A P RA a tBDL *Not e 2 t RDL DAb0 DAb1 DAb2 DAb3 DA b4 D Ab5 DQ DA a0 DAa1 DAa2 DA a3 DA a4 WE DQM Row A cti ve ( A- Bank ) W rite ( A- Ban k ) Burs t Stop W rit e (A - Ban k ) Prec harge ( A - B an k ) :D on' t C ar e *Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue. 2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. Input data after Row precharge cycle will be masked internally. 3.Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. P .22 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Burst Read Single bit Write Cycle @Burst Length=2 0 CLOCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 *Note 1 CKE H IG H CS RAS *No te 2 CAS ADDR RAa CAa RBb CAb RAc CBc CAd BA A10 /A P RAa RBb RAc C L =2 DQ CL =3 DA a0 QA b 0 Q A b 1 DBc0 Q A d 0 QA d 1 DAa0 QAb 0 QAb 1 DBc0 QA d 0 Q A d 1 WE DQM Row Active (A-Bank) Row Active (B-Ba nk ) W ri te (A -B a nk ) Rea d wi th Auto Prech arge (A-Bank ) Row Active ( A -Ba nk ) Rea d (A -Ba nk ) Prec ha rg e ( A -Ba nk ) W ri te w ith Auto Precharge (B-Bank) :Don't Care *Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set). At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length. 2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge command will be issued after two clock cycles. Elite Semiconductor Memory Technology Inc. P .23 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 0 CLOCK *No te 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tSS CKE *Note1 tSS * No te3 tSS CS RAS CAS ADD R Ra Ca BA A10/A P Ra tSHZ DQ Qa 0 Qa 1 Qa 2 WE DQM P rec ha rge Power -D ow n En t r y Row Active Read Active Power-down Exit Prec harge P recha rge Power-Down Exit Active Power-down Entry : Don't care *Note :1.Both banks should be in idle state prior to entering precharge power down mode. 2.CKE should be set high at least 1CLK+tss prior to Row active command. 3.Can not violate minimum refresh specification. (32ms) Elite Semiconductor Memory Technology Inc. P .24 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Self Refresh Entry & Exit Cycle 0 CLOCK *No te 2 * No te 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRCmin *No te 6 * No te 1 CKE *Note3 tS S CS *No te 5 RAS *Note7 CA S ADDR BA A10 /A P DQ Hi -Z Hi - Z WE DQM Sel f Refres h Entry Sel f R efresh Exi t Au to R efresh : Don't care *Note: TO ENTER SELF REFRESH MODE 1. CS , RAS & CAS with CKE should be low at the same clock cycle. 2.After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE. 3.The device remains in self refresh mode as long as CKE stays “Low”. cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4.System clock restart and be stable before returning CKE high. 5. CS Starts from high. 6.Minimum tRC is required after CKE going high to complete self refresh exit. 7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc. P .25 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A Mode Register Set Cycle 0 CLOCK 1 2 3 4 5 6 Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 CKE HIG H HIGH CS *Note2 RA S *Note1 CA S *Note3 ADD R Key Ra tRFC DQ Hi-Z Hi- Z WE DQM MR S New Comma n d Auto Ref resh New Comma n d :Don't Care *Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register. 2.Minimum 2 clock cycles should be met before new RAS activation. 3.Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. P .26 Publication Date : Jan. 2000 Revision : 1.3u M12L16161A PACKAGE DIMENSIONS 50-LEAD TSOP(II) SDRAM(400mil) D 50 26 -HA A2 DETAIL A O 2 (4X) E1 E R2 0.21 REF R1 O1.5 0.665 REF B -C1 8.78 25 -C- A1 O 3 (4X) GAGE .25 -Ce SEATING PLANE b 2.91 (ZD) 0.10 C O PLANE O1 B L DETAIL A L1 b WITH PLATING BASE METAL b1 c1 c SECTION B-B Symbol A A1 A2 b b1 c c1 D ZD E E1 L L1 R1 R2 Min 0.05 0.95 0.30 0.30 0.12 0.10 20.82 11.56 10.03 0.40 ð ð² ð³ ð´ 0.12 0.12 0 0 10 10 Dimension in mm Nom 0.10 1.00 0.35 0.127 20.95 0.875 REF 11.76 10.16 0.50 0.80 REF 0.80 BSC 15 15 Max 1.20 0.15 1.05 0.45 0.40 0.21 0.16 21.08 11.96 10.29 0.60 Min 0.002 0.037 0.012 0.012 0.005 0.004 0.820 0.455 0.394 0.016 0.25 8 20 20 0.005 0.005 0 0 10 10 Dimension in inch Nom 0.004 0.039 0.014 0.005 0.825 0.034 REF 0.463 0.400 0.020 0.031 REF 0.031 BSC 15 15 Max 0.047 0.006 0.041 0.018 0.016 0.008 0.006 0.830 0.471 0.405 0.024 0.010 8 20 20 Elite Semiconductor Memory Technology Inc. P .27 Publication Date : Jan. 2000 Revision : 1.3u