AD484M1644VTA-15

Ascend Semiconductor Corporation 64Mb SDRAM ASCEND ASCEND Semiconductor Semiconductor 64M SDRAM 64M SDRAM Data sheet Data sheet Tel: (03)5635888 / Fax: (03)5635188/ http://www.ascendsemi.com.tw Preliminary 1 Ascend Semiconductor Corporation Ordering Information 64Mb SDRAM AD 48 4M 16 4 4 V T A – 7 L I Ascend Semiconductor Operating Range I : Industrial -40℃ ~ 85℃ Non : Commercial 0℃ ~ 70℃ S : Special 0℃ ~ 85℃ EDO FPM DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : 40 41 42 43 46 48 Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1 K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Power Non : Standard L : Low power Min Cycle Time ( Max Freq.) -55 : 5.5ns ( 183MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) -15 : 15ns (66MHz,CL1 applicable) Revision A : 1st B : 2nd C : 3rd D :4th Interface V: 3.3V R: 2.5V Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) Preliminary 2 Ascend Semiconductor Corporation 64Mb( 4Banks ) Synchronous DRAM AD484M1644VTA ( 4Mx16 ) Description 64Mb SDRAM The AD484M1644VTA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 1,048,756 words x 4 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock . The 64Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL . Features • Fully synchronous to positive clock edge • Single 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Industrial temperature available • Programmable Burst Length ( BL ) - 1,2,4,8 or full page • Programmable CAS Latency ( CL ) -1, 2 or 3 • Data Mask ( DQM ) for Read/Write masking • Programmable wrap sequential - Sequential ( BL = 1/2/4/8/full page ) - Interleave ( BL = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the positive rising edge of the system clock. • Auto refresh and self refresh • 4,096 refresh cycles / 64ms Ordering Information Part number AD484M1644VTA-55 Max Freg. 183MHz Package 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII Operation Range Commercial Range : 0℃ ~ 70℃ Power Standard Note AD484M1644VTA-6 167MHz Commercial Range : 0℃ ~ 70℃ Standard AD484M1644VTA-7 143MHz Commercial Range : 0℃ ~ 70℃ Standard AD484M1644VTA-15 66MHz Commercial Range : 0℃ ~ 70℃ Standard CL1 AD484M1644VTA-7L 143MHz Commercial Range : 0℃ ~ 70℃ Low power AD484M1644VTA-8L 125MHz Commercial Range : 0℃ ~ 70℃ Low power AD484M1644VTA-10L 100MHz Commercial Range : 0℃ ~ 70℃ Low power * Ascend Semiconductor reserves the right to change products or specification without notice. Preliminary 3 Ascend Semiconductor Corporation Ordering Information Part number AD484M1644VTA-7I 64Mb SDRAM Max Freg. 143MHz Package 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII 54pins, TSOPII Operation Range Industrial Range : -40℃ ~ 85℃ Power Standard Note AD484M1644VTA-8I 125MHz Industrial Range : -40℃ ~ 85℃ Standard AD484M1644VTA-10I 100MHz Industrial Range : -40℃ ~ 85℃ Standard AD484M1644VTA-7LI 143MHz Industrial Range : -40℃ ~ 85℃ Low power AD484M1644VTA-8LI 125MHz Industrial Range : -40℃ ~ 85℃ Low power AD484M1644VTA-10LI 100MHz Industrial Range : -40℃ ~ 85℃ Low power * Ascend Semiconductor reserves the right to change products or specification without notice. Pin Assignment ( Top View ) VDD 1 DQ0 2 VDDQ 3 DQ1 4 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13 VDD 14 LDQM 15 /WE 16 /CAS 17 /RAS 18 /CS 19 BA0 20 BA1 21 A10/AP 22 A0 23 A1 24 A2 25 A3 26 VDD 27 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS Preliminary 54pin TSOP-II (400milx875mil) (0.8mm Pin pitch) 4 Ascend Semiconductor Corporation Pin Descriptions ( Simplified ) 64Mb SDRAM Pin CLK /CS CKE Name System Clock Chip select Clock Enable Pin Function Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA(CA0 to CA7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. A0 ~ A11 Address BA0, BA1 Bank Address /RAS Row address strobe /CAS Column address strobe /WE Write Enable LDQM/ UDQM Data input/output Mask DQM controls I/O buffers. DQ0 ~ 15 Data input/output DQ pins have the same function as I/O pins on a conventional DRAM. VDD /VSS VDDQ/VSSQ NC Power supply/Ground Power supply/Ground No connection VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. This pin is recommended to be left No Connection on the device. Preliminary 5 Ascend Semiconductor Corporation 64Mb SDRAM Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 Auto/Self Refresh Counter DQM Row Add. Buffer Row Decoder Address Register Memory Array S/A & I/O gating Col. Decoder Col. Add. Buffer Write DQM Control Data In DQi Data Out Read DQM Control Mode Register Set Col. Add. Counter Burst Counter DQM /WE DQM Timing Register CLK /CLK CKE /CS /RAS /CAS Preliminary 6 Ascend Semiconductor Corporation Simplified State Diagram 64Mb SDRAM Self Refresh LF SE LF SE it Ex Mode Register Set MRS IDLE REF CBR Refresh CK E ACT CK E↓ Power Down Write Row Active h wit ad Re CKE↓ CKE BS T Re ad Read Active Power Down WRITE Suspend CKE↓ CKE Wr ite wit h Read WRITE READ Write CKE↓ CKE READ Suspend CKE PR E WRITEA Suspend CKE↓ WRITEA E PR READA CKE↓ CKE READA Suspend POWER ON Precharge Precharge Manual Input Automatic Sequence Preliminary 7 Ascend Semiconductor Corporation Address Input for Mode Register Set 64Mb SDRAM BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Operation Mode CAS Latency Burst Length Burst Length Sequential Interleave A2 1 1 0 2 2 0 4 4 0 8 8 0 Reserved Reserved 1 Reserved Reserved 1 Reserved Reserved 1 Full Page Reserved 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Type Sequential Interleave A3 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 BA1 0 0 BA0 0 0 A11 0 0 A10 0 0 A9 0 1 A8 0 0 A7 0 0 Operation Mode Normal Burst read with Single-bit Write Preliminary 8 Ascend Semiconductor Corporation Burst Type ( A3 ) 64Mb SDRAM Burst Length 2 4 8 Full Page * A2 A1 A0 XX0 XX1 X00 X01 X10 X11 000 001 010 011 100 101 110 111 nnn Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+ 1 Cn+ 2 … ... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 - * Page length is a function of I/O organization and column addressing x32 (CA0 ~ CA7) : Full page = 256 bits Preliminary 9 Ascend Semiconductor Corporation Truth Table 1. Command Truth Table ( AD484M1644VTA ) Command Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set 64Mb SDRAM Symbol DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL MRS CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X /CS H L L L L L L L L L L /RAS /CAS X H H H H H L L L L L X H H L L L H H H H L /WE X H L H H L H H L L L BA0, A11, A10 BA1 A9~A0 X X X V V V V V V X L X X X L H L H V L H L X X X V V V V V X X V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. DQM Truth Table Command Data write / output enable Data mask / output disable Upper byte write enable / output enable Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set Symbol ENB MASK BSTH READ READA WRIT WRITA ACT PRE PALL MRS CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X /CS H L L L L L L L L L L Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Command Activating Any Clock suspend Idle Idle Self refresh Idle Power down Command Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit Symbol CKE n-1 H L L H H L L H L n L L H H L H H L H /CS X X X L L L H X X /RAS /CAS X X X L L H X X X X X X L L H X X X /WE Addr. X X X H H H X X X X X X X X X X X X REF SELF Remark H = High level, L = Low level, X = High or Low level (Don't care) Preliminary 10 Ascend Semiconductor Corporation 64Mb SDRAM 4. Operative Command Table Current state /CS /R H L L L L L L L H L L L L L L L H L L L L L L L L H L L L L L L L L X H H H L L L L X H H H L L L L X H H H L L L L L X H H H L L L L L /C /W X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L Addr. X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Nop or power down Nop or power down ILLEGAL ILLEGAL Row activating Nop Refresh or self refresh Mode register accessing Nop Nop Begin read : Determine AP Begin write : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read : Determine AP Terminate burst, start write : Determine AP ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end → Write recovering Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read : Determine AP 7, 8 Terminate burst, new write : Determine AP 7 ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Notes 2 2 3 3 Idle 4 Row active 5 5 3 6 4 Read 7 7, 8 3 4 Write 7,8 7 3 9 Remark H = High level, L = Low level, X = High or Low level (Don't care) Preliminary 11 Ascend Semiconductor Corporation 64Mb SDRAM Current state /CS /R H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /C /W X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Addr. X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Continue burst to end → Precharging Continue burst to end → Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst to end → Write recovering with auto precharge Continue burst to end → Write recovering with auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter idle after tRCD Nop → Enter idle after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes Read with AP 3 3 3 3 Write with AP 3 3 3 3 Precharging 3 3 3 Row activating 3 3 3,10 3 Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Preliminary 12 Ascend Semiconductor Corporation 64Mb SDRAM Current state /CS /R H L L L L L L L L H L L L L L L L L H L L L L H L L L L X H H H H L L L L X H H H H L L L L X H H L L X H H H L /C /W X H H L L H H L L X H H L L H H L L X H L H L X H H L X X H L H L H L H L X H L H L H L H L X X X X X X H L X X Addr. X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X X Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/ BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS Action Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL Notes Write recovering 8 3 3 Write recovering with AP 3,8 3 3 Refreshing Mode Register Accessing Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; → Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recov ery requirements. 9. Must mask preceding data which don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. Preliminary 13 Ascend Semiconductor Corporation 64Mb SDRAM 5. Command Truth Table for CKE Current state CKE n X H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L n-1 H L L Self refresh L L L H H H H Self refresh recovery H H H H H Power down L L H H H H H Both banks H idle H H H H L H Row active L H Any state H other than listed above L L /CS /R X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X /C /W X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X X Addr. X X X X X X X X X X X X X X X X X Action INVALID, CLK (n – 1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) would exit power down Exit power down → Idle Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Refer t o operations in Operative Command Table Power down Refer to operations in Operative Command Table Power down Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend Notes X Op-Code X Op-Code X X X X X X 1 1 1 2 Remark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. Preliminary 14 Ascend Semiconductor Corporation Operating Range Range Commercial Industrial Special 64Mb SDRAM Vcc 3 V ~ 3.6V 3 V ~ 3.6V 3 V ~ 3.6V Ambient Temperature 0 C to +70 C ° ° -40 C to +85 C ° ° 0 C to +85 C ° ° Absolute Maximum Ratings Symbol VIN, VOUT VDD , V DDQ TSTG PD IOS Item Input, Output Voltage Power Supply Voltage Storage Temperature Power Dissipation Short Circuit Current Rating -0.3 ~ 4.6 -0.3 ~ 4.6 -55 ~ 150 1 50 Units V V C W mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( All Operating Range ) Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input logic high voltage Input logic low voltage Min. 3.0 3.0 2.0 -0.3 Typical 3.3 3.3 Max. 3.6 3.6 VDD+0.3 0.8 Units V V V V Note : 1. All voltage referred to VSS. 2. VIH (max) = 5.6V for pulse width ≤ 3ns 3. VIL (min) = -2.0V for pulse width ≤ 3ns Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25 C ) Symbol CCLK CI CO Parameter Clock capacitance Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML,DQMU Input/Output capacitance Min. 2.5 2.5 4.0 Max. 4.0 5.0 6.5 Units pF pF pF Preliminary 15 Ascend Semiconductor Corporation Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, All Operating Range) 64Mb SDRAM Parameter Symbol Test condition MAX -5.5 -6 ---7 ---8 --10 -15 -75 --- Units Notes Operating current ICC1 Burst length = 1, tRC ≥ tRC (min), IOL = 0 mA, One bank active CKE ≤ VIL (max.), tCk = 15 ns CKE ≤ VIL (max.), tCk = ∞ CL=1 CL=2 CL=3 Standard Low power --- 100 95 mA 1 Precharge standby current in power down mode ICC2P ICC2PS ICC2N Standard Low power 135 120 110 100 95 1000 500 1000 500 35 uA uA uA uA mA Precharge standby current in non-power down mode CKE ≥ VIH (min.), tCK = 15 ns, /CS ≥ VIH (min.)Input signals are changed one time during 30ns CKE ≥ VIH(min.), tCK = ∞ Input signals are stable ICC2NS ICC3P ICC3PS ICC3N 25 8 8 50 mA mA mA mA Active standby current in power down mode CKE ≤ VIL(max), tCK = 15ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIH(min), tCK = 15ns, / CS ≥ VIH(min) Input signals are changed one time during 30ns CKE ≥ VIH(min), tCK = ∞ Input signals are stable CL=1 Active standby current in non-power down mode (4 bank activated) ICC3NS 40 --------80 --- mA Operating current (Burst mode) Refresh current Self Refresh current ICC4 tCCD = 2CLKs , I OL = 0 mA tRC ≥ t RC(min.) CKE ≤ 0.2V CL=2 CL=3 110 100 mA 2 150 140 130 120 110 ICC5 ICC6 160 150 145 140 130 85 Standard Low power mA 3 4 5 1 500 mA uA Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard power version. 5. Low power version. Preliminary 16 Ascend Semiconductor Corporation 64Mb SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Test condition Min. Max. Unit Input leakage current IIL 0 ≤ VI ≤ VDDQ, VDDQ=VDD All other pins not under test=0 V 0 ≤ VO ≤ VDDQ, DOUT is disabled Io = -4mA Io = +4mA -0.5 +0.5 uA Output leakage current High level output voltage Low level output voltage IOL VOH VOL -0.5 2.4 +0.5 uA V 0.4 V AC Operating Test Conditions ( VDD = 3.3V +/- 0.3 V, All Operating Range ) Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level 1.4V / 1.4V See diagram as below 2.4V / 0.4V 2ns 1.4V Vtt = 1.4V 50Ω Output Z = 50Ω 50pF Preliminary 17 Ascend Semiconductor Corporation Operating AC Characteristics ( V DD = 3.3V +/- 0.3 V, All Operating Range ) Parameter CL = 3 CL = 2 Access time from CLK CLK high level width CLK low level width Data-out hold time CL = 3 CL = 2 Data-out to high impedance time Data-out to low impedance time Input hold time Input setup time ACTIVE to ACTIVE command period ACTIVE to PRECHARGE command period PRECHARGE to ACTIVE command period ACTIVE to READ/WRITE delay time ACTIVE(one) to ACTIVE(another) command READ/WRITE command to READ/WRITE command Data-in to PRECHARGE command Data-in to BURST stop command Data-out to high impedance from PRECHARGE command Refresh time(4,096 cycle) CL = 3 CL = 2 tREF CL = 3 CL = 2 tLZ tIH tIS tRC tRAS tRP tRCD tRRD tCCD tDPL tBDL tROH 1 1 1.5 60 42 100k 18 18 10 1 2 1 3 2 64 tHZ CL = 3 CL = 2 tCH tCL tOH 2.0 2.0 2.0 _ 4.5 _ 1 1 1.5 60 42 18 18 12 1 2 1 3 2 64 100k tCK tAC Symbol 64Mb SDRAM -55 -6 -7 -8 -10 Units Notes Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. 5.5 _ 4.5 _ 2.5 2.5 2.5 _ 5 _ 1 1 2 63 45 18 18 14 1 2 1 3 2 64 100k 6 _ 5.5 _ 3 3 2.5 1.5 5.5 5.5 1 1 2 64 46 18 18 16 1 2 1 3 2 64 100k 7 10 5.5 6 3 3 2.5 1.5 6 6 1 1 2 70 50 20 20 18 1 2 1 3 2 64 8 10 6 6 3 3 2.5 1.5 6 6 10 10 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 100k ns ns ns ns CLK CLK CLK CLK CLK ms 6 6 5 5 5 5 5 2 3 4 Clock cycle time Preliminary 18 Ascend Semiconductor Corporation Operating AC Characteristics-Continues 64Mb SDRAM ( V DD = 3.3V +/- 0.3 V, All Operating Range ) -15 Min. Max. CL = 1 tCK tAC tCH tCL CL = 1 tOH 3 3 2 15 12 ns ns ns ns ns 3 Parameter Symbol Units Notes Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time CL = 1 Data-out to high impedance time Data-out to low impedance time Input hold time Input setup time ACTIVE to ACTIVE command period CL = 1 tHZ tLZ tIH tIS tRC tRAS tRP tRCD tRRD tCCD tDPL tBDL 1 1 2 90 60 22 25 15 1 1 1 1 6 ns ns ns ns ns 4 6 6 5 5 5 5 5 ACTIVE to PRECHARGE command period PRECHARGE to ACTIVE command period ACTIVE to READ/WRITE delay time ACTIVE(one) to ACTIVE(another) command READ/WRITE command to READ/WRITE command Data-in to PRECHARGE command Data-in to BURST stop command Data-out to high impedance from PRECHARGE command Refresh time(4,096 cycle) CL = 1 100k ns ns ns ns CLK CLK CLK CLK 64 ms tROH tREF Note : 1. All voltages referenced to Vss. 2. For commercial range parts. 3. For industrial range parts. 4. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 5. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) 6.These parameters are for address/command/data/CLK/CKE. 7. Any “– “ sign on the data means “ No guarantee” . Preliminary 19 Ascend Semiconductor Corporation 64Mb SDRAM Package Dimension Dimension in Milimeter/Inchs 1.20 MAX 0.047 1.00+/- 0.10 0.039+/- 0.004 0.21+/- 0.05 0.008+/- 0.002 0.05 MIN 0.002 11.76 + /- 0.20 0.463 + /- 0.008 #1 #54 22.62 MAX 0.891 22.22+/- 0.10 0.875+/- 0.004 0.80 0.035 0.35 +0.1 / - 0.1 0.014+0.004 / - 0.004 #27 #28 0.125 +0.075 / - 0.035 0.005+0.003 / - 0.001 0.10 MAX 0.004 0.71 0.028 10.16 0.400 0.50 0.020 0.45 ~ 0.75 0.018 ~ 0.030 * Ascend reserves the right to change products or specification without notice. Preliminary 0.25 TYP 0.010 0 – 8’ 20