EM614163TS-30

EtronTech Features • Fast Access Time: 30/35/40/45ns • Fast EDO Page Cycle Time: 13.3/15/16/18ns • EDO Page Mode Operation • Single +5V ¡ Ó 10% Power Supply • Low Power Dissipation • Individual Byte Control via Dual CAS Inputs • Three Refresh Modes • 512-Cycle Refresh in 8ms(9 rows and 9 columns) • TTL Compatible • 40-Pin, 400-mil Plastic SOJ Package, or 40/44-Pin, 400-mil Plastic TSOP-II Package. Em614163A-30/35/40/45 256K x 16 High Speed EDO DRAM Preliminary Pin Assignment (Top View) 40-Pin SOJ Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vss I/O15 I/O14 I/O13 I/O12 Vss I/O11 I/O10 I/O9 I/O8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss 40/44-Pin TSOP-II Vcc I/O0 I/O1 I/O2 I/O3 Vcc I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 Vss I/O15 I/O14 I/O13 I/O12 Vss I/O11 I/O10 I/O9 I/O8 Ordering Information Part Number Em614163A-30 EM614163TS-30 Em614163A-35 EM614163TS-35 Em614163A-40 EM614163TS-40 Em614163A-45 EM614163TS-45 Speed 30ns 30ns 35ns 35ns 40ns 40ns 45ns 45ns Package SOJ TSOP-II SOJ TSOP-II SOJ TSOP-II SOJ TSOP-II NC NC WE RAS NC A0 A1 A2 A3 Vcc 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC LC AS UCAS OE A8 A7 A6 A5 A4 Vss Pin Names A0 - A8 RAS UCAS LCAS WE OE Address Inputs Row Address Strobe Column Address Strobe (Upper Byte Control) Column Address Strobe (Lower Byte Control) Write Enable Output Enable Data Input/Output +5V Power Supply Ground No Connection Key Specifications Speed -30 -35 -40 -45 tRAC 30ns 35ns 40ns 45ns tCAC 9ns 10ns 11ns 12ns tAA 16ns 18ns 20ns 22ns tOEA 9ns 9ns 10ns 10ns tRC tPC 53ns 13.3ns 60ns 15ns 66ns 16ns 75ns 18ns I/O0 - I/O15 VCC VSS NC Overview The Em614163A-30/35/40/45 is a high speed EDO(Extended Data Output) DRAM organized in 262,144 words by 16 bits. It supports EDO Page Mode and 16-bit data width for high data bandwidth applications. The EDO Page Mode is an accelerated access that provides a shorter page cycle and a faster data access time than the traditional Fast Page Mode. Compared with Fast Page Mode DRAM, the EDO DRAM data output will be held valid after CAS goes HIGH, as long as RAS and OE are held LOW and WE is held HIGH. This feature allows CAS precharge time to occur without the output data going invalid. Therefore, the EDO CAS timing can be condensed to carry more data out in a given period. The Em614163A-30/35/40/45 fully utilizes the EDO Page Mode advantages. It allows 512 random access within a page with a fast cycle time as short as 13.3/15/16/18 ns. The Em614163A-30/35/40/45 is ideally suitable for high performance graphics frame buffers, CDROMs, disk drivers, set top boxes, and DSP applications. Etron Technology, Inc. 1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5779001 Etro n Techn olo gy, Inc. reserves th e right to make chan ges to its pro ducts and specificat ion s without notice. April 1997 EtronTech Block Diagram Em614163A-30/35/40/45 RAS LCAS UCAS Clock Ge nerator Circuit Lower Upper Lower Data-In Buffer Vcc (5 V) x 3 Vss (0 V) x 3 DO0 DO1 .......... .......... WE Lower Data In pu ts/Ou tpu ts Lower Data-Out Buffer DO7 A0 - A8 Column Decoder .......... A0 A1 A2 A3 A4 A5 A6 A7 A8 Row & Column Addr ess Bu ffer Sense Amplifier & I/O Control Row Decoder Upper Data-In Buffer DO8 DO9 .......... A0 A8 Memo ry Cell Upper Data-Out Buffer DO15 .......... Upper Data In pu ts/Ou tpu ts .......... OE Ou tp ut Enable In pu t Preliminary 2 A pril 1997 EtronTech Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC IOUT PT TOPT TSTG Value Em614163A-30/35/40/45 Unit V V mA W °C °C - 0.5 to +7.0 - 0.5 to +7.0 50 1.0 0 to +70 - 55 to +125 Capacitance (Ta = 25°C; VCC = 5V ¡ Ó 10%; f = 1MHz) Parameter Input capacitance (A0 - A8) Input capacitance ( RAS , UCAS , LCAS , WE , OE ) Output capacitance(I/O0 - I/O15) Notes: 1. Capacitance is sampled and not 100% tested. Symbol Typ. Max. Unit CI 1 CI 2 CI/O ¡Ð ¡Ð ¡Ð 5 5 7 pF pF pF Note 1 1 1 Truth Table Function Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word (Early Write) Write: Lower Byte (Early) Write: Upper Byte (Early) Read Write EDO-PageMode Read EDO-PageMode Write EDOPage-Mode Read-Write Hidden Refresh CBR Refresh 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle Read Write RAS H L L L L L L L L L L L L L L →H →L L →H →L L H →L LCAS UCAS H →X L L H L L H L H →L H →L H →L H →L H →L H →L L L H L H →X L H L L H L L H →L H →L H →L H →L H →L H →L L L H L WE X H H H L L L H →L H H L L H →L H →L H L X X OE X L L L X X X L →H L L X X L →H L →H L X X X Addresses tR tC X ROW ROW ROW ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X X COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL n/a X High-Z DQs Data-out Lower byte, data-out Upper byte, high-Z Lower byte, high-Z Upper byte, data-out Data-in Lower byte, data-in Upper byte, high-Z Lower byte, high-Z Upper byte, data-in Data-out, Data-in Data-out Data-out Data-in Data-in Data-out, Data-in Data-out, Data-in Data-out Data-in High-Z High-Z Notes 1, 2 2 2 1 1 1, 2 1, 2 2 1, 3 4 RAS# only refresh Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. Preliminary 3 April 1997 EtronTech Em614163A-30/35/40/45 4. At least one of the two CAS signals must be active ( LCAS or UCAS ). Preliminary 4 April 1997 EtronTech Recommended Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Notes: Symbol VSS VCC VIH VIL Min 0 4.5 2.4 - 0.5 Typ 0 5.0 ¡Ð ¡Ð Em614163A-30/35/40/45 Max 0 5.5 VCC + 0.3 0.8 Unit V V V V Notes 2 1, 2 1 1, 3 1. All voltage referenced to VSS. 2. The supply voltage with all VCC pins must be the same level. The supply voltage with all VSS pins must be the same level. 3. VIL(min.) = - 1.2V for pulse width ¡ Ø 30ns. DC Characteristics TA = 0 to +70°C; Vcc = +5V ± 10%, Vss = 0V Em614163A Parameter Symbol Test Conditions Min Operating current ICC 1 RAS c ycling LCAS , UCAS c ycling ¡Ð -30/35/40/45 Max 280/250/225/200 Unit Notes mA 1, 2 Standby current ICC 2 RAS -only refresh ICC 3 current Standby current CAS -before- RAS refresh current tRC = min. RAS , LCAS , UCAS = VIH Dout = High-Z RAS , LCAS , UCAS , OE = VCC - 0.2V Dout = High-Z RAS c ycling, CAS = VIH tRC = min. RAS = VIH LCAS , UCAS = VIL Dout = enable tRC = min. RAS , CAS c ycling tPC = min. 0V¡ÕVin¡ÕVCC 0V¡ÕVout¡ÕVCC Dout = Disable IOH = - 2.5 mA IOL = + 2.1 mA ¡Ð ¡Ð ¡Ð 2 1 280/250/225/200 5 mA mA mA mA 2 1 ICC 5 ICC 6 ICC 7 ILI ILO VOH VOL ¡Ð ¡Ð ¡Ð 280/250/225/200 280/250/225/200 10 10 mA mA µA µA V 1, 3 Fast page mode current Input leakage current Output leakage current Output high voltage Output low voltage Notes: -10 -10 2.4 0.4 V 1. ICC depends on output load condition when the device is selected. ICC -max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while LCAS and UCAS = VIL. 4. All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage. Preliminary 5 April 1997 EtronTech AC Characteristics (2, 3, 4, 5) (Ta = 0 to +70°C; VCC = 5V ¡ Ó 10%, VSS = 0V) Test Conditions • Input rise and fall times: 2ns • AC test condition, input pulse levels 0V to 3V Em614163A-30/35/40/45 • Output load: 1 TTL loads and 50pF • Output timing reference levels: VOH = 2.0V VOL = 0.8V Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) Em614163A Parameter Random read or write cycle time RAS precharge time RAS pulse width U/LCAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to U/LCAS delay time RAS to column address delay time Column address to RAS lead time RAS hold time U/LCAS hold time Column address hold time from RAS Write command time from RAS Data-in hold time from RAS U/LCAS to RAS precharge time OE to data-in delay time Transition time (rise and fall) Refresh period CAS to output in Low-Z Symbol tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRAL tRSH tCSH tAR tWCR tDHR tCRP tOED tT tREF tCLZ -30/35/40/45 Min 53/60/66/75 19/21/22/26 30/35/40/45 5/6/7/8 0 6/6/6/7 0 5/6/6/7 10/11/12/13 8/9/10/11 16/18/20/22 6/7/7/8 30/35/40/45 22/25/30/35 22/25/30/35 22/25/30/35 5/5/5/5 7/7/8/8 1 ¡Ð 0 Max ¡Ð ¡Ð 100,000 100,000 ¡Ð ¡Ð ¡Ð ¡Ð 21/25/29/33 15/17/18/20 ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð 50 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns 12 11 8 8 9 10 6 7 1 Unit Notes Preliminary 6 April 1997 EtronTech Read Cycle Parameter Access time from RAS Access time from U/LCAS Access time from column address Access time from OE Read com m and s etup tim e Read command hold time to U/LCAS Read command hold time to RAS Output buffer turn-off tim e Output buffer turn-off OE Em614163A-30/35/40/45 Em614163A Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tOFF tOEZ -30/35/40/45 Min ¡Ð ¡Ð ¡Ð ¡Ð 0 0 0 0 0 Max 30/35/40/45 9/10/11/12 16/18/20/22 9/9/10/10 ¡Ð ¡Ð ¡Ð 6/7/8/8 6/7/8/8 ns ns ns ns ns ns ns ns ns 8 11, 18 18 19 19 13 14, 15, 16 15, 17 Unit Notes Write Cycle Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to U/LCAS lead time Data-in setup time Data-in hold time OE hold time from WE tWCS tWCH tWP tRWL tCWL tDS tDH tOEH 0 5/6/6/6 5/6/6/6 10 5/5/6/6 0 5/6/6/7 5/6/6/6 ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ns ns ns ns ns ns ns ns 21 22 22 8, 20 8 Read-Modify-Write Cycle Em614163A Parameter Read-modify-write cycle time RAS to W E delay time U/LCAS to W E delay time Column address to W E delay time Symbol tRWC tRWD tCWD tAWD -30/35/40/45 Min 73/83/90/100 41/49/54/60 20/24/25/27 33/40/44/49 Max ¡Ð ¡Ð ¡Ð ¡Ð ns ns ns ns 1 20 20 20 Unit Notes Refresh Cycle U/LCAS setup time ( CAS -before- RAS refresh cycle) U/LCAS hold time ( CAS -before- RAS refresh cycle) RAS precharge to U/LCAS hold time U/LCAS precharge time in normal mode tCSR tCHR tRPC tCPN 6/7/8/9 7/8/9/10 5 5/5/5/6 ¡Ð ¡Ð ¡Ð ¡Ð ns ns ns ns 8 11 8 23 Preliminary 7 April 1997 EtronTech EDO Page Mode Cycle Parameter EDO page mode cycle time EDO page mode U/LCAS precharge time EDO page mode RAS pulse width Access time from U/LCAS precharge RAS hold time from U/LCAS precharge EDO page mode read-modify-write cycle U/LCAS precharge to W E delay time EDO page mode read-modify-write cycle time OE low to CAS high setup time OE high hold time from CAS high OE high pulse width OE setup prior to RAS during hidden refresh cycle Data output hold after CAS low Output disable delay from W E WE pulse width for output disable when CAS high Symbol tPC tCP tRASP tCPA tCPRH tCPW tPRWC tOES tOEHC tOEP tORD tCOH tWHZ tWPZ Em614163A-30/35/40/45 Em614163A -30/35/40/45 Min 13.3/15/16/18 5/5/5/6 30/35/40/45 ¡Ð 13/14/15/16 27/31/36/41 35/40/45/50 5 6 6 0 3/3/3/5 0 6 Max ¡Ð ¡Ð 100,000 Unit Notes ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 25 23 24 11, 15 18/21/23/25 ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð ¡Ð 13 ¡Ð Counter Test Cycle U/LCAS precharge time in counter test cycle tCPT 30 ¡Ð ns 23 Preliminary 8 April 1997 EtronTech Notes: 1. Assume tT = 2ns. Em614163A-30/35/40/45 2. An initial pause of 100 us is required after power up followed by a minimum of eight initialization cycles ( RAS -only refresh cycle or CAS -beofre- RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS -before- RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the device. LCAS and UCAS c annot be straggered within the same write/read cycles. 5. All the VCC and all the VSS pins shall be supplied with the same voltages. 6. tRAS(min) = tRWD (min) + tRWL(min) + tT in read-modify-write cycle. 7. tCAS(min) = tCWD (min) + tCWL(min) + tT in read-modify-write cycle. 8. tASC , tCAH , tRCS, tCSR , tWCS, tWCH , and tRPC are determined by the earlier falling edge of UCAS or LCAS . 9. Operation with the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only: If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 10. Operation with the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only: If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 11. tCRP, tCHR , tRCH , tCPA and tCPW are determined by the later rising edge of UCAS or LCAS . 12. VIH (min) and VIL(max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH and VIL. 13. Assumes that tRCD ¡Ø tRCD (max) and tRAD ¡Ø tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 14. Assumes that tRCD ¡Ø tRCD (max) and tRAD ¡Ø tRAD (max). 15. Access time is determined by the longer of tAA or tCAC or tCPA. 16. tCAC is guaranteed for one TTL and 50pF load. 17. Assumes that tRCD ¡Ø tRCD (max) and tRAD ¡Ø tRAD (max). 18. Either tRCH or tRRH must be satisfied for a read cycle. 19. tOFF (max) and tOEZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. The tOFF is determined by the later rising edge of RAS or CAS . 20. tWCS, tRWD , tCWD , and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS¡Ù tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ¡Ù tRWD (min), tCWD ¡Ù tCWD (min), tAWD ¡Ù tAWD (min) and tCPW ¡Ù tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 21. tCWL s hall be satisfied by both UCAS , LCAS . 22. These parameters are referenced to UCAS or LCAS leading edge in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 23. tCPN , tCP, and tCPT are determined by the time that both UCAS and LCAS are high. 24. tRASP defines RAS pulse width in fast page mode cycles. 25. Assume tT = 2ns. Preliminary 9 April 1997 EtronTech T iming Waveforms • Read Cycle t RC t RAS RAS Em614163A-30/35/40/45 t RP t CSH t CRP t RSH t CAS t RCD tT UCAS LCAS t RAD t RAL t ASR t RAH t ASC t CAH Address Row Column t RRH t RCS t RCH WE t DZC t CDD DIN OPEN t DZO t ODD OE t OEA t CAC t AA t RAC DOUT D OUT t OFF t OEZ Preliminary 10 April 1997 EtronTech • Early Write Cycle t RC t RAS RAS Em614163A-30/35/40/45 t RP t CSH t RCD tT UCAS LCAS t RSH t CAS t CRP t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH DIN D in DOUT OPEN Preliminary 11 April 1997 EtronTech • Read-Modify-Write Cycle t RWC t RAS RAS Em614163A-30/35/40/45 t RP tT t RCD t CAS t CRP UCAS LCAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD t CWL t RWL t WP WE t DZC t DH t DS OPEN DIN D in t OEH t DZO t ODD OE t OEA t CAC t AA t RAC DOUT Dout OUT t OEZ Preliminary 12 April 1997 EtronTech • Delayed Write Cycle t RC t RAS RAS Em614163A-30/35/40/45 t RP t CSH t RCD tT UCAS LCAS t RSH t CAS t CRP t ASR t RAH t ASC t CAH Address Row Column t CWL t RWL t WP t RCS WE t DZC t DS t DH OPEN DIN Din t DZO t ODD t OEH OE t OEZ DOUT Invalid Dout Preliminary 13 April 1997 EtronTech • EDO Page Mode Read Cycle t RASP Em614163A-30/35/40/45 t CPRH t RP RAS tT t CSH t RCD UCAS LCAS t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t t RAD t ASR RAL t RAH t ASC t CAH t ASC t CAH tASC t CAH Address Row Column 1 Column 2 Column N t RCS t RCS t RCH t RCH t RCS t RRH t RCH WE OPEN DIN OPEN OPEN t OED t OEHC t OED t OEP OE t OEA t CAC t OEA t CAC t AA t CPA t AA t OEA t CAC t OES t AA t OFF t OFF t OFF t OEZ t OEZ t RAC t OEZ DOUT Dout 1 Dout 2 Valid Dout N DOU N T t COH Preliminary 14 April 1997 EtronTech •EDO Page Mode Early Write Cycle Em614163A-30/35/40/45 t RASP t RP RAS tT t CSH t RCD UCAS LCAS t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t ASR t RAH t ASC t CAH t ASC t CAH tASC t CAH Address Row Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH DIN Din 1 Din 2 Din N Dout OPEN Preliminary 15 April 1997 EtronTech • EDOage Mode Read P -Modify-Write Cycle t RASP Em614163A-30/35/40/45 t CPRH t RP RAS t T t PRWC t CP t UCAS LCAS RCD t CRP t CP t CAS t CAS t CAS t RAD t ASR t RAH t ASC t CAH t ASC t ASC t CAH t CAH Address Row Column 1 t RWD t AWD t CWD Column 2 t CWL t t CWL Column N CPW t CPW t AWD t CWL t RWL t AWD t RCS t CWD t RCS t CWD WE t RCS t WP t DS t DH t WP t DS t WP t DS t t DH DH OPEN D IN Din 1 OPEN Din 2 OPEN Din N t OED t OED t OED t OEH t OEH t OEH OE t OEA t CAC t AA t RAC t t t OEA OEA t CAC t AA t AA OEZ t CAC t CPA t OEZ t t CPA OEZ D OU T Dout 1 Dout 2 Dout N Preliminary 16 April 1997 EtronTech Read Cycle with WE Controlled Disable Em614163A-30/35/40/45 RAS t CSH t RCD tT UCAS LCAS t RAD t CAS t ASR t RAH t ASC t CAH Address Row Column t RCS t RCH t RRH WE t DZC t WHZ DIN OPEN t DZO t ODD OE t OEA t CAC t AA t RAC DOUT t D OUT t OEZ CLZ Preliminary 17 April 1997 EtronTech • EDO-Page-Mode Read-Early-Write Cycle Em614163A-30/35/40/45 RAS t CSH t tT UCAS LCAS RCD t CAS t CAS t CP t RAD t AS t ASR t RAH tASC t C CAH t CAH Address Row Column Column t RCS t RCH t WE WCS t WCH t DS t DH OPEN DIN DIN OE t OEA t CAC t AA t RAC t WHZ DOUT D OUT t CLZ Preliminary 18 April 1997 EtronTech •RAS-Only Refresh Cycle t RC t RAS RAS Em614163A-30/35/40/45 t RP tT t CRP t RPC t CRP UCAS LCAS t ASR t RAH Address Row t OFF OPEN DOUT •CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP t RAS t RC t RP RAS t RPC t CPN tT t RPC t CSR t CHR t CPN t CSR t CHR t CRP UCAS LCAS Address t OFF OPEN DOUT Preliminary 19 April 1997 EtronTech • Hi dden Refresh Cycle t RC t RAS (READ) Em614163A-30/35/40/45 t RC t RP t RAS (REF RE SH) t RC t RP t RAS (REFRE SH ) t RP RAS tT t RSH t RCD UCAS LCAS t CAS t CHR t CRP t RAD t RAL t ASR t RAH t ASC t CAH Address Row Co lu mn t RRH t RCS t RCH WE t DZC t CDD DIN t DZO OP EN t ODD OE t OEA t AA t CAC t OEZ t OFF t RAC DOUT Valid Do ut DOUT Preliminary 20 April 1997 EtronTech • CAS Before RAS Refresh Counter Check Cycle (WRITE) t RP t RAS Em614163A-30/35/40/45 t RP RAS t RPC t CPN tT t CSR t CHR t CPT t RSH t CAS t CRP UCAS LCAS t ASC t CAH Address Column t WCS t WCH WE t CDD t DS t DH t DZC Din Din OE t OFF OPEN Dout Preliminary 21 April 1997 EtronTech Outline Drawing 40-Pin SOJ 40 Em614163A-30/35/40/45 21 E HE 1 D 20 c A2 A A1 L θ e1 S Seating Plane b b1 e D y Symbol A A1 A2 b1 b c D E e e1 HE L S Y θ Notes: Dimension in inch Min Num Max ¡Ð ¡Ð 0.144 ¡Ð ¡Ð 0.025 0.105 0.110 0.115 0.026 0.028 0.032 0.016 0.018 0.022 0.008 0.010 0.014 ¡Ð 1.025 1.035 0.395 0.400 0.405 0.044 0.050 0.056 0.348 0.430 0.088 ¡Ð ¡Ð 0¢X 0.368 0.440 0.098 ¡Ð ¡Ð ¡Ð 0.388 0.450 0.108 0.050 0.004 10¢X Dimension in mm Min Num Max ¡Ð ¡Ð 3.66 ¡Ð ¡Ð 0.64 2.67 2.79 2.92 0.66 0.71 0.81 0.41 0.46 0.56 0.20 0.25 0.36 ¡Ð 26.04 26.29 10.03 10.16 10.29 1.12 1.2 1.42 8.84 10.92 2.24 ¡Ð ¡Ð 0¢X 9.35 11.18 2.49 ¡Ð ¡Ð ¡Ð 9.86 11.43 2.74 1.27 0.10 10¢X 1. Dimension D Max & S include mold flash or tie bar burrs. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Dimension D & E include mold mismatch and are determined at the mold parting line. 4. Controlling dimension : inch 5. General appearance spec. should be based on final visual inspection spec. Preliminary 22 April 1997 EtronTech 40/44-Pin TSOP-II 44 Em614163A-30/35/40/45 + HE E 0.254 θ° L + 1 D L1 A1 A2 A S B e y L L1 Symbol A A1 A2 B c D E e HE L L1 S y θ Notes : Dimension in inch Min Num Max ¡Ð ¡Ð 0.047 ¡Ð ¡Ð 0.002 0.037 0.039 0.041 0.010 0.014 0.018 ¡Ð ¡Ð 0.006 0.721 0.725 0.729 0.396 0.400 0.404 ¡Ð ¡Ð 0.031 0.455 0.016 ¡Ð ¡Ð ¡Ð 0¢X 0.463 0.020 0.031 ¡Ð ¡Ð ¡Ð 0.471 0.024 ¡Ð 0.036 0.004 5¢X Min ¡Ð 0.05 0.95 0.25 ¡Ð 18.31 10.06 ¡Ð 11.56 0.40 ¡Ð ¡Ð ¡Ð 0¢X Dimension in mm Num Max ¡Ð 1.20 ¡Ð ¡Ð 1.00 1.05 0.35 0.45 ¡Ð 0.15 18.41 18.51 10.16 10.26 ¡Ð 0.80 11.76 0.50 0.80 ¡Ð ¡Ð ¡Ð 11.96 0.60 ¡Ð 0.93 0.10 5¢X 1. Dimension D&E do not include interiead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : MM Preliminary 23 April 1997 C