SPCA751A-P101

Preliminary Description SPCA751A-P101 The SPCA751A is a single chip signal processor optimized for MPEG audio decoding and voice recording. It is developed to achieve a better performance/cost ratio for MPEG audio players. The SPCA751A is especially designed for standalone audio players, the system controller can easily carry out the MPEG audio decoding process by the use of a general serial IO/control interface for MPEG bit stream in/out and playback control. Decoded audio PCM data are output to external DAC through a programmable normal/I2S DAC interface, such that most of common audio DACs can be cooperated with SPCA751A to meet different customers' requirements. A high quality 10-bit 8KHz sampling rate ADC is embedded for voice recording. Based on the algorithm of SACM_S480 or SACM_S3200, voice is compressed to a low data rates of 4.8Kbps and 32Kbps respectively, while retaining a good resolution of the original speech/audio. The SPCA751A is designed for 3.3V applications, A built in PLL is able to synthesize the system clock from a 16.934MHz crystal oscillator source. The high performance SPCA751A signal processor can operate at 34MHz and dissipate low power, which makes the SPCA751A extremely suitable for portable systems. A common implementation utilizing the SPCA751A is presented below: LCD FM / AM Tuner Key Scan PC parallel or USB port DRAM ATAPI (CDROM/HD) FLASH/Plug-in Cards DSA / I 2C Normal / I 2S Audio DAC Microphone Speaker SPCA751A System uP (SPCP751A) 3.3V (8KHz 10bit) DC-DC Converter AA battery x 1 CDdsp interface CD Kit MPEG Audio Player System Block Diagram 1 Preliminary Features • Single chip MPEG audio decoder - Conforming to MPEG1/MPEG2 audio layer 2/3 - Extension to MPEG lower sampling rates • Digital sound control - Digital volume control - Stereo/Mono channel select - Digital sound equalizer • Internal auto-generate audio clock - Sampling frequency from 8 kHz up to 48 kHz • Programmable audio DAC interface - Support both normal and I2S audio DAC formats - Audio clock polarity programmable - Internal auto-generated oversampling clock for DAC
Accept external audio clock for sampling rate control • Serial data IO and control interface - Easy for the host processor to command • Low power dissipation SPCA751A-P101 • PLL embedded - Require only 16.934MHz crystal, resistors, and capacitors to supply the system clock • Built-in Digital Recording option - Embedded 10-bit 8 kHz audio ADC - SACM_S480 recording with 4.8 kbit/sec - SACM_S3200 recording with 32 kbit/sec • Device Parameter - Supply voltage : 3.0 ~ 3.6 volts - IO interface : 5 volts tolerance, TTL compatible - Package : 44-pin LQFP - Power consumption: less than 150 mW @ 3.6 volts SPCA751A BLOCK DIAGRAM AIP AIN ATO VM ADC MPEG Audio Decoder PLL Clock Synthesizer OSCOUT OSCIN Voice Encoder/Decoder Host Interface PCM Buffer AUD_LRCK AUD_BCK AUD_DATA AUD_XCK TFS RFS SCLK DR DT FCEB1 FCEB2 2 Preliminary Function Description SPCA751A-P101 The SPCA751A is a single-chip CMOS microprocessor optimized for real-time MPEG audio decoding and speech/audio recording. SPCA751A decodes the encoded MPEG audio data according to the commands passed through the Serial Control/Data I/O Interface by the host processor, the host processor can also check the status of decoding process by the use of this interface. Refer to Programming Guide for command definitions In the digital recorder mode, speech/Audio is sampled at 8Khz by the on-chip ADC into 10-bit digital words, after encoding, the datum is compressed into a data rate of 4.8Kbps or 32Kbps. Decoded audio PCM data are output to external DAC through a programmable normal/I2S PCM interface, this interface is compliant to most of the common audio DACs. The embedded PLL is capable of providing the 27 MHz system clock derived from a 16.934MHz clock source ! Serial Control/Data I/O Interface The host controller uses this interface to transfer MPEG bit-stream with the SPCA751A and to command the SPCA751A during the recording/decoding process. This interface consists of seven pins: FCEB1 FCEB2 Host Controller SCLK RFS1 TFS1 DR1 DT1 SPCA 751A Pin Pin Pin Pin Pin Pin Pin # 12 # 13 # 44 # # # # 1 2 3 4 FCEB2 FCEB1 SCLK1 DT1 TFS1 DR1 RFS1 Frame Decoded Indicator generated by the SPCA751A Data Request Flag generated by the SPCA751A Bit Clock controlled by the host processor Data from the SPCA751A to the host processor Transmit Frame Synchronization controlled by the host processor Data from the host processor to the SPCA751A Receive Frame Synchronization controlled by the host processor " FCEB1 - Data Request Flag The FCEB1 flag generated by the SPCA751A informs the status of the decoding/encoding process. When FCEB1 is high, it indicates that the SPCA751A is ready to receive data/command or to transfer data, the host processor is allowed to start the communication; When FCEB1 is low, the SPCA751A is busy processing internally and no I/O tasks could be taken, the commands sent by the host processor during low FCEB1 are not accepted by the SPCA751A and may cause the SPCA751A run into an unknown state. 3 Preliminary " FCEB2 - Frame Decoded Indicator SPCA751A-P101 Each time the SPCA751A has decoded one frame (512 bytes) of data, it changes the state of FCEB2 (either high to low or low to high) and progresses to the next frame. By counting the number of state-changes, the host processor is able to know the time elapsed in decoding. " Host Command The host commands consist of 8-bit command and 8-bit ID, totally 16-bit long. (Refer to the SPCA751A Programming Guide for command definitions) At the falling edges of SCLK1, the SPCA751A checks whether the RFS1 is high. Once it is high, the 16-bit long command is sampled at the following 16 consecutive falling edges of SCLK1 with MSB first. After the LSB is sent, the host processor should send at least one more cycle of SCLK1 to the SPCA751A. SCLK1 TSCLK RFS1 TFS TFH TDS TDH DR1 b15 b14 b1 b0 " Host processor writes 512 bytes to the SPCA751A At the falling edges of SCLK1, the SPCA751A checks whether the RFS1 is high. Once it is high, the 512-byte long data is sampled at the following 512x8 consecutive falling edges of SCLK1. RFS1 should remain high before the MSB of the last word. After the LSB of the last word is sent, the host processor should send at least three more cycles of SCLK1 to the SPCA751A. SCLK1 TSCLK RFS1 TFS TDS TDH TFH DR1 b15 b14 255 words b0 b15 Last word b0 Timing Requirements PARAMETER MIN. RFS1 setup before SCLK1 falls low RFS1 hold after SCLK1 falls low DR1 setup before SCLK1 falls low DR1 hold after SCLK1 falls low SCLK1 period 2 2 3 3 16 MAX. UNIT ns ns ns ns TFS TFH TDS TDH TSCLK * ns * The maximum period of SCLK1 depends on the sampling rate of the decoded data, too long a SCLK1 period makes the real-time decoding impossible. 4 Preliminary " Host processor reads 512 bytes from the SPCA751A SPCA751A-P101 To read data from the SPCA751A, the host processor first asserts the TFS1 at the falling edges of SCLK1, then the 512-byte long data is sampled out from the SPCA751A at the following 512x8 consecutive rising edges of SCLK1. The host processor is supposed to latch-in the data at the falling edges of SCLK1. TFS1 should remain high before the MSB of the last word. After the LSB of the last word is received, the host processor should send at least three more cycles of SCLK1 to the SPCA751A. SCLK1 TSCLK RFS1 TFS TFH TD TDH DR1 b15 b14 255 words b0 b15 Last word b0 Timing Requirements PARAMETER MIN. TFS1 setup before SCLK1 falls low TFS1 hold after SCLK1 falls low SCLK1 period 2 2 16 MAX. UNIT ns ns ns TFS TFH TSCLK Switching Characteristics PARAMETER MIN. DT1 access DT1 hold after SCLK1 falls low MAX. 5 UNIT ns ns TD TDH ! PLL TSCLK / 2 An independent analog power is applied through pin 41 VSSP and pin 42 VDDP to supply the power for the internal PLL. An oscillation circuit is built externally on pin 39 OSCIN and pin 40 OSCOUT. 10 M Ohm pin 40 OSCOUT pin 39 OSCIN 16.934MHz Crystal 12 pF 12 pF Oscillation Circuit 5 Preliminary ! PCM Interface SPCA751A-P101 The PCM Interface is used to output decoded audio data to external audio DAC. There are 4 signals, AUD_XCK, AUD_LRCK, AUD_BCK and AUD_DATA. The signal format of PCM Interface is programmable with register 0x3fDE. Register Name Register # Bits Description AUD_CONFIG 0x3FDE 14 Audio out configuration (RW) bit 0 = I2S control bit 1 = AUD_XCK select bit 2 = AUD_DATA LSB / MSB sent first bit 3 = AUD_BCK active edge bit 4 = AUD_XCK IO select bit 5 = LRCK polarity bit 12 = CD-DA pass through mode (Value set at initialization) (0x2103) (0 = I2S, 1 = normal) (0 = 256×Fs, 1 = 384×FS) (0 = MSB first, 1 = LSB first) (0 = falling, 1 = rising) (0 = output, 1 = input) (0 = LRCK low is right, 1 = LRCK low is left) (0 = disable, 1 = enable) Normal Mode: AUD_BCK AUD_LRCK AUD_DATA 0 15 14 1 0 15 14 1 0 15 14 BCK = 32 x Fs AUD_BCK AUD_LRCK AUD_DATA 0 15 14 10 15 14 10 15 BCK = 48 x Fs I2S Mode: AUD_BCK AUD_LRCK AUD_DATA 1 0 15 14 1 0 15 14 1 0 15 BCK = 32 x Fs AUD_BCK AUD_LRCK AUD_DATA 0 1514 0 1514 0 1514 BCK = 48 x Fs PCM Interface waveform 6 Preliminary ! ADC SPCA751A-P101 The SPCA751A has an audio-band sigma-delta analog-to-digital converter so as to meet the requirement of the digital recorder application. The circuit of converter consists of two main blocks: the analogto-digital converter (ADC) and internal reference and bias voltage. For the latter, it is 15-bit format with 10-bit resolution. The analog-to-digital conversion chain consists of a microphone amplifier (M.A.), a programmable gain amplifier (PGA), an analog oversampled modulator, and the decimation digital filter. The PGA has gain step from –12dB to 12dB (-12, -6, 0, 6, 12dB). The modulator is a sigma-delta feedback loop, which oversamples the signal at 1.024MHz and provides second-order noise shaping. It performs the conversion of the differential analog input signal to a pulse-density-modulated single-bit digital output. When a maximum positive differential input voltage is applied at the input of modulator, the resulting code at the output of the modulator is all ones. The decimation digital filter consists of a comb filter and a half-band filter. The comb filter is a third-order comb filter. Finally the encoder implements the half-band filter and data compression by software. ADC & DAC ELECTRICAL CHARACTERISTICS (TA = 25ºC, VDD = 3.3 V) PARAMETER ATO: Input Voltage PGA: Gain Range Step Size Step Variation Voltage Reference: Output Voltage 0.45VDD 0.5VDD 0.55VDD Vpp CONDITION MA gain = 0dB, PGA gain = 6dB Default: 6dB -12 6 0.5 12 dB dB dB 0.25*VDD Vpp MIN. TYP. MAX. UNIT ADC PATH CHARACTERISTICS PARAMETER ADC: Signal to noise ratio CONDITION FIN = 1kHz, PGA gain = 12dB ATO is full swing Without data compression 60 dB MIN. TYP. MAX. UNIT 7 Preliminary SPCA751A-P101 DIGITAL RECODER APPLICATION CIRCUIT A/D converter Analog reference voltage generator Microphone Amplifier P.G.A. (-12,-6,0, 6,12dB) ATO AIN AIP VM AVDD1
Ω MICVCC 390pF
Ω 10
F 0.1
F AVSS1 Ω 10
F 0.1
F Ω Ω Ω 47
F 0.1
F
Ω Controller IO port MICGND M Microphone 8 Preliminary Pin Description PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Mnemonic DT1 TFS1 DR1 RFS1 Type Description O I/O I I/O I I I I I I O O I I I I I I SPCA751A-P101 RESET CLKSEL VDD VSS VDDO VSSO N.C. FCEB2 FCEB1 VDD VSS N.C. VDDO VSSO VDD VSS N.C. N.C. VDDO VSSO AUD_XCK AUD_DATA AUD_BCK AUD_LRCK VDD VSS VDDA VSSA AIP AIN ATO VM VDDO VSSO OSCIN OSCOUT VSSP VDDP CLKIN SCLK1 I I I/O O O O I I I I I I O O I I I O I I I I/O Transmit Data of Serial Port Transmit Frame Synchronization of Serial Port Receive Data of Serial Port Receive Frame Synchronization of Serial Port System Reset (Active Low) System Clock Select (0: Internal PLL 1:External Oscillator) Digital Power Digital Ground Digital Power Digital Ground No Connection Frame Decoded Indicator Data Request Flag Digital Power Digital Ground No Connection Digital Power Digital Ground Digital Power Digital Ground No Connection No Connection Digital Power Digital Ground Oversampling Clock to external Audio DAC / from external source Serial Data Output to Stereo Audio DAC Bit Clock Output to Stereo Audio DAC Sample Rate Clock Output to Stereo Audio DAC Digital Power Digital Ground Analog Power for Audio ADC Analog Ground for Audio ADC Positive Input of the Audio ADC transmit input amplifier Negative Input of the Audio ADC transmit input amplifier Output of the Audio ADC transmit input amplifier 1/2 AVDD for the bias of the Audio ADC transmit input amplifier Digital Power Digital Ground 16.934MHz Oscillator Input 16.934MHz Oscillator Output Analog Ground for PLL Analog Power for PLL External System Clock (Connect to VSS if internal PLL is used (pin 82 CLKSEL == 0)) Bit Clock of Serial Port 9 Preliminary SPCA751A-P101 PIN Map 33 32 31 30 29 28 27 26 25 24 AIN ATO VM VDDO VSSO OSCIN OSCOUT VSSP VDDP CLKIN SCLK1 23 AIP VSSA VDDA VSS VDD AUD_LRCK AUD_BCK AUD_DATA AUD_XCK VSSO VDDO 34 35 36 37 38 39 40 41 42 43 44 10 11 1 2 3 4 5 6 7 8 9 22 21 20 19 18 17 16 15 14 13 12 SPCA751A LQFP 44 NC NC VSS VDD VSSO VDDO NC VSS VDD FCEB1 FCEB2 DT1 TFS1 DR1 RFS1 RESETB CLKSEL VDD VSS VDDO VSSO NC 10 SPCA751A-P101 10M
12 pF 12 pF 390pF 16.934MHz Crystal 100K
1K
F 0.1
M Microphone 10K
2.2K
F 0.1
F 47
VDD RFS1 DR1 TFS1 DT1 SCLK1 OSCOUT OSCIN VM ATO AIN AIP CLKIN F 10
2.2K
F 0.1
Preliminary 5K
AVSS F 10
RESET 0.1
F 2.2K
SPCA751A LQFP 44 AVDD 100K
20K
AUD_LRCK AUD_BCK AUD_DATA AUD_XCK FCEB2 FCEB1 DAC Host Processor SPCA751A Application Circuit 11 Preliminary SPCA751A-P101 ABSOLUTE MAXIMUM RATINGS Rating Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VDD VIN TA TSTG 0.0 - 0.3 0 -55 Value ~ ~ ~ ~ 3.6 VDD + 0.3 60 125 Unit V V ºC ºC DC ELECTRICAL CHARACTERISTICS (TA = 25ºC, VDD = 3.3 V) PARAMETER VDD VIL VIH VOH VOL IDD Supply Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Power Supply Current IOH = -4mA IOL = 4mA 30.0mA 0.8VDD 2.4V 0.3V 35.0mA VDD 0.6V 40.0mA CONDITION MIN. 3.0V TYP. 3.3V MAX. 3.6V 0.2VDD Ordering Information " Package type : 44 pin LQFP Note: SUNPLUS TECHNOLOGY CO. LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product 12 Preliminary Outline Dimensions SPCA751A-P101 D D1 D2 E E1 E2 e b c A2 L1 A1 A Symbol D D1 D2 E E1 E2 e b A A1 A2 c L1 Min. 0.22 0.05 1.35 0.09 - Nom. 12 10 8 12 10 8 0.80 0.30 1.40 1.0 Max. 0.38 1.60 0.15 1.45 0.20 - Unit : millimeter 13