V6130

EM MICROELECTRONIC-MARIN SA V6130 Accurate Power Surveillance and Software Monitoring Features n Standby mode, maximum current 35 µA n Reset output guaranteed for VDD voltage down to n Comparator for voltage monitoring, voltage reference n ±1.5% voltage reference accuracy at +25 °C n Programmable reset voltage monitoring n Programmable power-on reset (POR) delay n Watchdog with programmable time window Typical Operating Configuration 1.2 V 1.17 V ±3% voltage reference accuracy for -40 to +85 °C n n n n n n guarantees a minimum time and a maximum time between software clearing of the watchdog Time base accuracy ±10% System enable (EN) output offers added security TTL/CMOS compatible -40 to +85 °C temperature range On request extended temperature range, -40 to +125 °C DIP8 and SO8 packages Description The V6130 offers a high level of integration by voltage monitoring and software monitoring in an 8 lead package. A comparator monitors the voltage applied at the VIN input comparing it with an internal 1.17 V reference. The power-on reset function is initialized after VIN reaches 1.17 V and takes the reset output inactive after TPOR depending of external resistance. The reset output goes active low when the VIN voltage is less than 1.17 V. The RES and EN outputs are guaranteed to be in a correct state for a supply voltage as low as 1.2 V. The watchdog function monitors software cycle time and execution. If the software clears the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution) it will cause the system to be reset. The system enable output prevents critical control functions being activated until software has successfully cleared the watchdog three times. Such a security could be used to prevent motor controls being energized on repeated resets of a faulty system. Fig. 1 Pin Assignment Applications n n n n n Industrial electronics Cellular telephones Security systems Battery powered products Automotive electronics Fig. 2 1 V6130 Absolute Maximum Ratings Parameter Maximum voltage at VDD Minimum voltage at VDD Max. voltage at any signal pin Min. voltage at any signal pin Storage temperature Electrostatic discharge max. to MIL-STD-883C method 3015 Max. soldering conditions Symbol Conditions VDDmax VDDmin VMAX VMIN TSTO VSmax TSmax VSS + 8 V VSS - 0.3 V VDD+ 0.3 V VSS - 0.3 V -65 to +150 °C 1000V 250 °C x 10 s otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a defined logic voltage level. Operating Conditions Parameter Operating temperature 1) Supply voltage 2) RES & EN guaranteed 3) Comparator input voltage RC-oscillator programming 1) Symbol Min. Max. Units TJ VDD VDD VIN R -40 1.2 1.2 0 10 +125 7 VDD 1000 °C V V V kΩ Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction. Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless The maximum operating temperature is confirmed by sampling at initial device qualification. In production, all devices are tested at +85 °C. On request devices tested at +125 °C can be supplied. 2) A 100 nF decoupling capacitor is required on the supply voltage VDD for stability. 3) RES must be pulled up externally to VDD event if it is unused. (Note: RES and EN are used as inputs by EM test.) Table 2 Electrical Characteristics Parameter Supply current in standby mode Supply current 3.0 ≤ VDD ≤ 5.5 V, C = 100 nF, TA = -40 to +85 °C, unless otherwise specified Symbol Test Conditions ISS ISS REXT = don’t care, TCL = VDD, VIN = 0 V REXT = 100 kΩ, I/Ps at VDD, O/Ps 1 MΩ to VDD Min. Typ. 22 55 Max. 35 100 Unit µA µA RES and EN Output Low Voltage VOL VOL VOL VOL VDD = 4.5 V, IOL = 20 mA VDD = 4.5 V, IOL = 8 mA VDD = 2.0 V, IOL = 4 mA VDD = 1.2 V, IOL = 0.5 mA 0.4 0.2 0.2 0.06 0.4 0.4 0.2 V V V V EN Output High Voltage VOH VOH VOH VDD = 4.5 V, IOH = -1 mA VDD = 2.0 V, IOH = -100 µA VDD = 1.2 V, IOH = -30 µA 3.5 1.8 1.0 4.1 1.9 1.1 V V V TCL and VIN TCL input low level TCL input high level Leakage current TCL input VIN input resistance Comparator reference1) Comparator hysteresis1) VIL VIH ILI RVIN VREF VREF VREF VHY VSS ≤ VTCL ≤ VDD TA = +25 °C TA = -20 to +70 °C VSS 2.0 1.148 1.123 1.123 0.05 100 1.170 2 0.8 VDD 1 1.200 1.218 1.222 V V µA MΩ V V V mV Table 3 1) The comparator reference is the power-down reset threshold. The power-on reset threshold equals the comparator reference voltage plus the comparator hysteresis (see Fig.5). 2 V6130 ISS Standby versus Temperature at VDD = 5.5 V Fig. 3 Timing Characteristics Parameter Propagation delays: TCL to Output Pins VIN sensitivity Logic Transition Times on all Output Pins Power-on Reset delay Watchdog Time Open Window Percentage Closed Window Time Open Window Time Watchdog Reset Pulse TCL Input Pulse Width VDD= 5.0 V ± 3%, C = 100 nF, TA = -40 to +85°C, unless otherwise specified Symbol Test Conditions TDIDO TSEN TTR TPOR TWD OWP TCW TCW TOW TOW TWDR TWDR TTCL Load 10 kΩ, 50 pF REXT = 118 kΩ, ± 1% REXT = 118 kΩ, ± 1% REXT = 118 kΩ, ± 1% REXT = 118 kΩ, ± 1% REXT = 118 kΩ, ± 1% Min. Typ. 250 5 30 100 100 ±0.2 TWD 0.8 TWD 80 0.4 TWD 40 TWD / 40 2.5 Max. 500 20 100 110 110 88 44 Units ns µs ns ms ms ms ms ms ns 1 90 90 72 36 150 Table 4 Timing Waveforms Watchdog Timeout Period Fig. 4 3 V6130 Voltage Monitoring Fig. 5 Timer Reaction Fig. 6 Combined Voltage and Timer Reaction Fig. 7 4 V6130 Block Diagram Fig. 8 Pin Description Pin 1 2 3 4 5 6 7 8 Name EN RES TCL VSS NC VDD R VIN Function Push-pull active low enable output Open drain active low reset output. RES must be pulled up to VDD even if unused Watchdog timer clear input signal GND terminal No connection Voltage supply REXT input for RC oscillator tuning Voltage comparator input Table 5 Timer Programming The on-chip oscillator needs an external resistor REXT connected between the R pin and VSS (see Fig. 9). It allows the user to adjust the power-on reset (POR) delay, watchdog time T WD and with this also the closed and open time windows as well as the watchdog reset pulse width (TWD/40). With REXT = 118 kΩ, the typical delays are: - Power-on reset delay: TPOR is 100 ms - Watchdog time: TWD is 100 ms - Closed window: TCW is 80 ms - Open window: TOW is 40 ms - Watchdog reset: TWDR is 2.5 ms Note: The current consumption increases as the frequency increases. Watchdog Timeout Period Description The watchdog timeout period is divided into two parts, a “closed" window and an “open" window (see Fig.4) and is defined by two parameters, TWD and the Open Window Percentage (OWP). The closed window starts just after the watchdog timer resets and is defined by TCW = TWD - OWP(TWD). The open window starts after the closed time window finishes and lasts till TWD + OWP(TWD). The open window time is defined by TOW = 2 x OWP(TWD). For example if TWD = 100 ms (actual value) and OWP = ±20% this means the closed window lasts during first the 80 ms (TCW = 80 ms = 100 ms - 0.2 (100 ms)) and the open window the next 40 ms (TOW = 2 x 0.2 (100 ms) = 40 ms). The watchdog can be serviced between 80 ms and 120 ms after the timer reset. However as the time base is ±10% accurate, software must use the following calculation for servicing signal TCL during the open window: Related to curves (Fig. 10 to Fig. 20), especially Fig. 19 and Fig. 20, the relation between TWD and REXT could easily be defined. Let us take an example describing the variations due to production and temperature: 1. Choice, TWD = 26 ms. 2. Related to Fig. 20, the coefficient (TWD to REXT) is 1.125 where REXT is in kΩ and TWD in ms. 3. REXT (typ.) = 26 x 1.125 = 29.3 kΩ. Functional Description VIN Monitoring The power-on reset and the power-down reset are generated as a response to the external voltage level on the V IN input. The external voltage level is typically obtained from a voltage divider as shown in Fig. 9. The user defines an external voltage divider to set the desired threshold level for power-on reset and power-down reset in his system. The internal comparator reference voltage is typically 1.17 V. At power-up the reset output (RES) is held low (see Fig. 5). When VIN becomes greater than VREF, the RES output is held low for an additional power-on reset (POR) delay which is equal to the watchdog time T WD (typically 100 ms with an external resistor of 118 kΩ connected at R pin). The POR delay prevents repeated toggling of RES even if VIN and the INPUT voltage drops out and recovers. The POR delay allows the microprocessor’s crystal oscillator time to start and stabilize and ensures correct recognition of the reset signal to the microprocessor. The RES output goes active low generating the power-down reset whenever VIN falls below VREF. The sensitivity or reaction time of the internal comparator to the voltage level on VIN is typically 5 µs. 5 V6130 4. system enable output, EN, can be used to prevent critical control functions being activated in the event of the system going into this failure mode (see section “Enable - EN Output”). The RES output must be pulled up to VDD even if the output is not used by the system (see Fig. 9) The ratio between TWD = 26 ms and the (TCL period) = 25.4 ms is 0.975. Then the relation over the production and the full temperature range is, TCL period = 0.975 x TWD or TCL period = 0.975 x REXT 1.125 , as typical value. a) While PRODUCTION value unknown for the customer when REXT ≠ 118 kΩ. b) While operating TEMPERATURE range -40 °C ≤ TA ≤ +85 °C. 5. If you fixed a TCL period = 26 ms ⇒ REXT 26 x 1.125 0.975 = 30 kΩ. Combined Voltage and Timer Action The combination of voltage and timer actions is illustrated by the sequence of events shown in Fig. 7. On power-up, when the voltage at VIN reaches VREF, the power-on-reset, POR, delay is initialized and holds RES active for the time of the POR delay. A TCL pulse will have no effect until this power-on-reset delay is completed. After the POR delay has elapsed, RES goes inactive and the watchdog timer starts acting. If no TCL pulse occurs, RES goes active low for a short time TWDR after each closed and open window period. A TCL pulse coming during the open window clears the watchdog timer. When the TCL pulse occurs too early (during the closed window), RES goes active and a new timeout sequence starts. A voltage drop below the VREF level for longer than typically 5 µs, overrides the timer and immediately forces RES active and EN inactive. Any further TCL pulse has no effect until the next power-up sequence has completed. Enable - EN Output The system enable output, EN, is inactive always when RES is active and remains inactive after a RES pulse until the watchdog is serviced correctly 3 consecutive times (ie. the TCL pulse must come in the open window). After three consecutive services of the watchdog with TCL during the open window, the EN goes active low. A malfunctioning system would be repeatedly reset by the watchdog. In a conventional system critical motor controls could be energized each time reset goes inactive (time allowed for the system to restart) and in this way the electrical motors driven by the system could function out of control. The V6130 prevents the above failure mode by using the EN output to disable the motor controls until software has successfully cleared the watchdog three times (ie. the system has correctly restarted after a reset condition). If during your production the TWD time can be measured at TA = +25 °C and the µC can adjust the TCL period, then the TCL period range will be much larger for the full operating temperature. Timer Clearing and RES Action The watchdog circuit monitors the activity of the processor. If the user’s software does not send a pulse to the TCL input within the programmed open window timeout period, a short watchdog RES pulse is generated which is equal to TWD/40 = 2.5 ms typically (see Fig. 6). With the open window constraint, new security is added to conventional watchdogs by monitoring both software cycle time and execution. Should software clear the watchdog too quickly (incorrect cycle time) or too slowly (incorrect execution), it will cause the system to be reset. If the software is stuck in a loop which includes the routine to clear the watchdog, a conventional watchdog will not reset the system even though the software is malfunctioning; the V6130 will generate a system reset because the watchdog is cleared too quickly. If no TCL signal is applied before the closed and open windows expire, RES will start to generate square waves of period (TCW + TOW + T WDR). The watchdog will remain in this state until the next TCL falling edge appears during an open window, or until a fresh power-up sequence. The 6 V6130 Typical Application R Fig. 9 7 V6130 TWD versus Temperature at 5 V TWD versus R at 5 V Fig. 10 TWD versus VDD at TA = +25°C TWD versus R at TA = +25°C Fig. 11 Fig. 12 8 Fig. 13 V6130 TWD versus R at TA = +25 °C Fig. 14 9 V6130 TWD versus VDD at TA = +85°C TWD versus R at TA = +85°C Fig. 15 TWD versus VDD at TA = -40°C TWD versus R at TA = -40°C Fig. 16 Fig. 17 10 Fig. 18 V6130 TWD Coefficient versus REXT at TA = +25°C Fig. 19 REXT Coefficient versus TWD at TA = +25°C Fig. 20 11 V6130 Package and Ordering Information Dimensions of DIP8 Package Dimensions in mm Fig. 21 Dimensions of SO8 Package Dimensions in mm Fig. 22 Ordering Information The V6130 is available in the following packages: Type Package V6130 8P DIP8 V6130 8S SO8 When ordering please specify complete part number. EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version. E. & O.E. Printed in Switzerland, Th © 2000 EM Microelectronic-Marin SA, 10/00, Rev. D/330 EM 12 MICROELECTRONIC-MARIN SA, CH-2074 Marin, Switzerland, Tel. 032 - 755 51 11, Fax 032 - 755 54 03