IS61LV6464-6PQ

IS61LV6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM FEATURES • Fast access time: – -100 MHz; 6 ns-83 MHz • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Pentium™ or linear burst sequence control using MODE input • Five chip enables for simple depth expansion and address pipelining • Common data inputs and data outputs • Power-down control by ZZ input • JEDEC 128-Pin TQFP 14mm x 20mm package • Single +3.3V power supply • 2.5V VDDQ (I/O supply) • Control pins mode upon power-up: – MODE in interleave burst mode – ZZ in normal operation mode These control pins can be connected to GNDQ or VDDQ to alter their power-up state ISSI ® JANUARY 2004 DESCRIPTION The ISSI IS61LV6464 is a high-speed, low-power synchronous static RAM designed to provide a burstable, high-performance, secondary cache for the Pentium™, 680X0™, and PowerPC™ microprocessors. It is organized as 65,536 words by 64 bits, fabricated with ISSI's advanced CMOS technology. The device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to eight bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 controls I/ O17-I/O24, B W4 c ontrols I/O25-I/O32, B W5 c ontrols I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-I/ O56, BW8 controls I/O57-I/O64, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally by the IS61LV6464 and controlled by the ADV (burst address advance) input pin. Asynchronous signals include output enable (OE), sleep mode input (ZZ), and burst mode input (MODE). A HIGH input on the ZZ pin puts the SRAM in the power-down state. When ZZ is pulled LOW (or no connect), the SRAM normally operates after the wake-up period. A LOW input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VDDQ (or no connect) on MODE pin selects INTERLEAVED Burst. Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 1 IS61LV6464 BLOCK DIAGRAM ISSI MODE Q0 A0' ® CLK CLK A0 BINARY COUNTER ADV ADSC ADSP CE CLR Q1 A1' A1 64K x 64 MEMORY ARRAY 14 16 A15-A0 16 D Q ADDRESS REGISTER CE CLK 64 64 GW BWE BW8 D Q DQ57-DQ64 BYTE WRITE REGISTERS CLK D BW1 Q DQ8-DQ1 BYTE WRITE REGISTERS CLK CE CE2 CE2 CE3 CE3 D Q 8 ENABLE REGISTER CE CLK INPUT REGISTERS CLK OUTPUT REGISTERS CLK OE 64 DATA[64:1] D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 PIN CONFIGURATION 128-Pin TQFP/PQFP VDDQ CE3 CE2 CE3 CE2 GND VDD CE BW8 BW7 BW6 BW5 OE CLK BWE GW BW4 BW3 GND VDD BW2 BW1 ADSC ADSP ADV GNDQ ISSI ® 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 GNDQ I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 I/O43 VDDQ GNDQ I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 VDDQ GNDQ I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 VDDQ PIN DESCRIPTIONS A0-A15 CLK ADSP ADSC ADV BW1-BW8 BWE GW CE, CE2, CE2, CE3, CE3 OE Address Inputs Clock Processor Address Status Controller Address Status Burst Address Advance Synchronous Byte Write Enable Byte Write Enable Global Write Enable Synchronous Chip Enable Output Enable NC GNDQ DQ1-DQ64 ZZ MODE VDD GND VDDQ Data Input/Output Sleep Mode Burst Sequence Mode +3.3V Power Supply Ground Isolated Output Buffer Supply: +2.5V No Connect Isolated Output Buffer Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 GNDQ NC MODE A15 A14 A13 VDD GND A12 A11 A10 A9 A8 NC A7 A6 A5 A4 A3 VDD GND A2 A1 A0 ZZ VDDQ 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDDQ I/O32 I/O31 I/O30 I/O29 I/O28 I/O27 I/O26 I/O25 I/O24 I/O23 I/O22 GNDQ VDDQ I/O21 I/O20 I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 GNDQ VDDQ I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 GNDQ 3 IS61LV6464 TRUTH TABLE OPERATION Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst ADDRESS USED CE3 None None None None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current X L X X X L X X X H H H H H X X X X X X X X X X X X CE2 X X L X X X L X X H H H H H X X X X X X X X X X X X CE3 X X X H X X X H X L L L L L X X X X X X X X X X X X CE2 X X X X H X X X H L L L L L X X X X X X X X X X X X CE H L L L L L L L L L L L L L X X H H X H X X H H X H ADSP ADSC ADV WRITE X L L L L H H H H L L H H H H H X X H X H H X X H X L X X X X L L L L X X L L L H H H H H H H H H H H H X X X X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X X X X L H H H H H H L L H H H H L L ISSI OE CLK X X X X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H I/O ® High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Dout High-Z Din Dout High-Z Dout High-Z Dout High-Z Din Din Dout High-Z Dout High-Z Din Din Notes: 1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK). 2. Wait states are inserted by suspending burst. 3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW. WRITE=H means all byte write enable signals are HIGH. 4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH throughout the input data hold time. 5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 TRUTH TABLE Operation Pipelined Read Pipelined Read Write Write Deselect Sleep ZZ L L L L L H OE ISSI I/O STATUS Dout High-Z High-Z Din High-Z High-Z L H L H X X ® WRITE TRUTH TABLE Operation Read Read Write all bytes Write all bytes Write Byte 1 Write Byte 2 Write Byte 3 Write Byte 4 Write Byte 5 Write Byte 6 Write Byte 7 Write Byte 8 GW H H H L H H H H H H H H BWE H L L X L L L L L L L L BW8 X H L X H H H H H H H L BW7 X H L X H H H H H H L H BW6 X H L X H H H H H L H H BW5 X H L X H H H H L H H H BW4 X H L X H H H L H H H H BW3 X H L X H H L H H H H H BW2 X H L X H L H H H H H H BW1 X H L X L H H H H H H H Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 5 IS61LV6464 INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 ISSI ® LINEAR BURST ADDRESS TABLE (MODE = GNDQ) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol PD IOUT VIN, VOUT VIN VDD Parameter Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on VDD Supply Relative to GND Value 1.0 100 –0.5 to VDDQ + 0.3 –0.5 to 5.5 –0.5 to 4.6 Unit W mA V V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VDD 3.3V +10%, –5% 3.3V +10%, –5% VDDQ 2.375V min., 3.465V max. 2.375V min., 3.465V max. ISSI ® DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND ≤ VIN ≤ VDDQ(2) Com. Ind. Test Conditions IOH = –1.0 mA IOL = 1 mA Min. 2.0 — 1.7 –0.3 –2 –10 –2 –10 Max. — 0.4 VDDQ + 0.3 0.8 2 10 2 10 Unit V V V V µA µA GND ≤ VOUT ≤ VDDQ, OE = VIH Com. Ind. POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Cycle Time ≥ tKC min. Device Deselected, VDD = Max., All Inputs = VIH or VIL CLK Cycle Time ≥ tKC min. Com. Ind. -100 Typ. Max. 210 250 —— -6 Typ. Max. 190 200 200 220 Unit mA mA ISB1 Standby Current TTL Inputs Com. Ind. 45 — 70 — 45 50 70 75 mA mA ISB2 Standby Current CMOS Inputs Device Deselected, Com. VDD = Max., Ind. VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V CLK Cycle Time ≥ tKC min. ZZ = VDDQ, CLK Running All Inputs ≤ GND + 0.2V or ≥ VDD – 0.2V Com. Ind. 2 — 5 — 2 5 5 10 mA mA IZZ Power-Down Mode Current 1 — 5 — 1 2 5 15 mA mA Note: 1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to VDDQ. 2. The MODE pin should be tied to VDD or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V or ≥ VDD – 0.2V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 7 IS61LV6464 CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF ISSI ® Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. AC TEST CONDITIONS Parameter Input Pulse Level for Input Pins Input Pulse Level for I/O Pins Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 0V to 2.5V 1.5 ns 1.25V See Figures 1 and 2 AC TEST LOADS 317 Ω 2.5V ZO = 50Ω OUTPUT Output Buffer 30 pF 50Ω 5 pF Including jig and scope 351 Ω 1.25V Figure 1 Figure 2 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (1) (1,2) ISSI -100 Min. Max. 10 4 4 — 2.5 0 2 — 0 0 2 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 — — — 5 — — 5 5 — — 5 — — — — — — — — — — -6 Min. 12 4.5 4.5 — 2.5 0 2 — 0 0 2 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 Max. — — — 6 — — 5 5 — — 5 — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time tKQLZ tOEQ tKQHZ(1,2) tOEQX tOELZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH (1) (1,2) tOEHZ(1,2) Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 9 IS61LV6464 READ CYCLE TIMING tKC ISSI tSH tKH tKL ® CLK tSS ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVS tAVH Suspend Burst ADV tAS tAH A15-A0 RD1 tWS tWH RD2 RD3 GW tWS tWH BWE BW8-BW1 tCES tCEH CE Masks ADSP CE tCES tCEH CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC Unselected with CE2, CE3 CE2, CE3 tCES tCEH CE2, CE3 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a 2a 2b 2c 2d 3a tKQHZ DATAIN High-Z Pipelined Read Single Read Burst Read Unselected 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -100 Min. Max. 10 4 4 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — — — — — — — — — — — — — -6 Min. Max. 12 4.5 4.5 2.5 2.5 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 0.5 0.5 — — — — — — — — — — — — — — — ISSI Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 11 IS61LV6464 WRITE CYCLE TIMING tKC ISSI tSS tSH tKH tKL ® CLK ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV tAS tAH tAVH A15-A0 WR1 tWS tWH WR2 WR3 GW tWS tWH BWE tWS tWH tWS tWH BW8-BW1 tCES tCEH WR1 WR2 CE Masks ADSP WR3 CE tCES tCEH CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC Unselected with CE2, CE3 CE2, CE3 tCES tCEH CE2, CE3 OE DATAOUT High-Z tDS tDH BW8-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a DATAIN High-Z 1a Single Write Burst Write Write Unselected 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (1) (1,2) ISSI -100 Min. Max. 10 4 4 — 2.5 0 2 — 0 0 2 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 — — — 5 — — 5 5 — — 5 — — — — — — — — -6 Min. 12 4.5 4.5 — 2.5 0 2 — 0 0 2 2.5 2.5 2.5 2.5 0.5 0.5 0.5 0.5 Max. — — — 6 — — 5 5 — — 5 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time tKQLZ tOEQ tKQHZ(1,2) tOEQX tOELZ tAS tSS tWS tCES tAH tSH tWH tCEH (1) (1,2) tOEHZ(1,2) Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 13 IS61LV6464 READ/WRITE CYCLE TIMING tKC ISSI tSS tSH tKH tKL ® CLK ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS tAH A15-A0 RD1 tWS tWH WR1 RD2 RD3 GW tWS tWH BWE tWS tWH BW8-BW1 tCES tCEH WR1 CE Masks ADSP CE tCES tCEH CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC CE2, CE3 tCES tCEH Unselected with CE2, CE3 CE2, CE3 tOEQ tOEHZ OE tOELZ tOEQX tKQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ 2a 2b 2c 2d tKQHZ DATAIN High-Z tDS 1a tDH Single Read Single Write Burst Read Unselected 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 ISSI -100 Min. Max. 10 4 4 — 2.5 0 2 — 0 0 2 2.5 2.5 2.5 0.5 0.5 0.5 2 2 — — — 5 — — 5 5 — — 5 — — — — — — — — -6 Min. Max. 12 4.5 4.5 — 2.5 0 2 — 0 0 2 2.5 2.5 2.5 0.5 0.5 0.5 2 2 — — — 6 — — 5 5 — — 5 — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc ® SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC tKH tKL tKQ tKQX (3) (3,4) Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby (1) tKQLZ tOEQ tKQHZ(3,4) tOEQX tOELZ tAS tSS tCES tAH tSH tCEH tZZS tZZREC (3) (3,4) tOEHZ(3,4) ZZ Recovery(2) Notes: 1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data retention is guaranteed when ZZ is asserted and clock remains active. 2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state. 3. Guaranteed but not 100% tested. This parameter is periodically sampled. 4. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 15 IS61LV6464 SNOOZE AND RECOVERY CYCLE TIMING tKC ISSI tSS tSH tKH tKL ® CLK ADSP ADSC ADV tAS tAH A15-A0 RD1 RD2 GW BWE BW8-BW1 tCES tCEH CE tCES tCEH CE2, CE3 tCES tCEH CE2, CE3 tOEQ tOEHZ OE tOELZ tOEQX DATAOUT High-Z tKQLZ tKQ 1a tKQX tKQHZ DATAIN High-Z tZZS tZZREC ZZ Single Read 16 Snooze with Data Retention Read Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 IS61LV6464 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) 100 83 83 Order Part Number IS61LV6464-100TQ IS61LV6464-6TQ IS61LV6464-6PQ Package TQFP TQFP PQFP ISSI ® Industrial Range: –40°C to +85°C Speed (ns) 83 Order Part Number IS61LV6464-6TQI Package TQFP Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 01/15/04 17 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ ISSI D D1 ® E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 PACKAGING INFORMATION PQFP (Plastic Quad Flat Pack Package) Package Code: PQ ISSI ® D D1 E E1 N 1 C e SEATING PLANE L1 L A2 A1 b A Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — — — — A1 0.25 — 0.010 — A2 2.57 2.97 0.101 0.117 b 0.25 0.375 0.010 0.015 C 0.17 0.23 0.007 0.009 D 23.00 23.40 0.905 0.921 D1 19.90 20.10 0.783 0.791 E 17.00 17.40 0.669 0.685 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.65 0.95 0.025 0.037 L1 1.60 Nom. 0.063 Nom. Plastic Quad Flat Pack (PQ) Inches Millimeters Min Max Min Max 128 — 3.40 0.15 0.35 2.55 3.05 0.17 0.27 0.10 0.23 23.00 23.40 19.90 20.10 17.00 17.40 13.90 14.10 0.50 BSC 0.65 0.95 1.60 Nom. Inches Min Max — 0.134 0.008 0.014 0.100 0.120 0.007 0.011 0.004 0.009 0.906 0.921 0.783 0.791 0.669 0.685 0.547 0.555 0.020 BSC 0.026 0.037 0.063 Nom. Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2.. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. Integrated Silicon Solution, Inc. PK13197PQ Rev. D 09/29/97