KL5KUSB105

KL5KUSB105 USB to 4 Serial Ports Description The Kawasaki USB to 4 Serial enables your system to have the capability to communicate between the USB (Universal Serial Bus) port and up to four serial port peripherals. This device meets the USB 1.0/1.1 and standard serial port specifications. All the advantages of USB are available to peripherals with serial port interface such as plug and play capabilities. With the USB Standard of high-speed data transfers, this device is ideal for connections to high-speed modems or ISDN terminal adapters. Kawasaki’s device and software enable the USB interface to be transparent to the peripheral and requires no firmware changes. This makes it possible for peripherals with serial interfaces to easily interface with USB with minimum modifications. This feature is ideal for Legacy applications. Features • • • • • • Advanced 16 Bit processor for USB transaction processing and control data processing Compliant with the USB 1.0/1.1 (Universal Serial Bus) 4 Serial Port 230kbps 128 byte FIFO Plug and Play compatible • • • • • • I2C interface Utilizes low cost external crystal circuitry 1.5K x 16 internal RAM buffer for fast communications Debug UART for debug and code development USB host device drivers available Single-chip solution in a 100 pin LQFP Block Diagram VP VM USB Interface Watchdog Timer Channel 4 Channel 3 Channel 2 Serial Interface Channel 1 Serial Interface Serial Interface Serial Interface (4) Timer 1 16 Bit Processor Timer 0 Serial Interface Engine DTR RTS DCD DSR CTS RI Txd Rxd 16 Bit Address / Data Bus CLK X2 PLL & Clock Generator RAM (3KB) Mask ROM EEPROM Serial Interface Debug UART Txd Rxd SCL SDA Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 1 KL5KUSB105 USB to 4 Serial Ports KL5KUSB105 Application Block Diagram KL5KUSB105 Serial Port Serial Device Serial Device Serial Device Serial Device USB USB / 4 Serial Serial Port Serial Port Optional External Memory Serial EEPROM Serial Port Pin Diagram 100LQFP VDD XD_15 XD_14 GND XD_13 XD_12 XD_11 XD_10 XD_9 XD_8 XD_7 XD_6 XD_5 XD_4 XD_3 XD_2 XD_1 XD_0 GND XA_13 XA_12 XA_11 XA_10 XA_9 XA_8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD SDA PU#1 UART4_DCD UART4_DSR UART4_CTS UART4_DTR UART4_RTS UART4_Rxd UART4_Txd UART3_RI nPWR_DWN GND UART1_Txd UART1_Rxd UART1_RTS UART1_DTR UART1_CTS UART1_DSR UART1_DCD UART1_RI nTXD GND VP VM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 KL5KUSB105 100 LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 XA_7 XA_6 XA_5 XA_4 XA_3 XA_2 XA_1 GND nNTST nNRESET nXROMSEL nXWR nXRD UART3_DCD UART3_DSR UART3_CTS UART3_DTR UART3_RTS UART3_Rxd nXRAMSEL GND nXBHE XA_0 XA_14 VDD VDD 26 N/C 27 SCL 28 GND 29 VCO_IN 30 CP_OUT 31 VDD 32 PLLEN 33 nRXD 34 N/C 35 N/C 36 UART2_Txd 37 UART2_Rxd 38 UART2_RTS 39 UART2_DTR 40 UART2_CTS 41 UART2_DSR 42 UART2_DCD 43 UART2_RI 44 UART3_Txd 45 GND 46 CLK 47 X2 48 XA_15 49 VDD 50 Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 2 KL5KUSB105 USB to 4 Serial Ports Pin Description Pin # LQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 I/O Pin Name VDD SDA* PU#1* UART4_DCD* UART4_DSR* UART4_CTS* UART4_DTR* UART4_RTS* UART4_Rxd* UART4_Txd* UART3_RI* nPWR_DWN* GND UART1_Txd* UART1_Rxd* UART1_RTS* UART1_DTR* UART1_CTS* UART1_DSR* UART1_DCD* UART1_RI* nTXD GND VP VM VDD UART4_RI* SCL* GND VCO_IN CP_OUT VDD PLLEN* nRXD* N/C N/C UART2_Txd* UART2_Rxd* UART2_RTS* UART2_DTR* UART2_CTS* UART2_DSR* UART2_DCD* UART2_RI* UART3_Txd* Description VDD Serial EEPROM serial data. Connect to EEPROM/SDA Pull up to USB +Pin for High Speed Data Carrier Detect Data Set Ready Clear To Send Data Terminal Ready Request To Send Receive Data Transmit Data Ring Indicate Active low Powerdown mode signal GND Transmit Data Receive Data Request To Send Data Terminal Ready Clear To Send Data Set Ready Data Carrier Detect Ring Indicate Debug UART Txd USB GND USB + Pin USB - Pin USB VDD Ring Indicate Serial EEPROM clock. Connect to EEPROM/SCL GND PLL VCO In PLL VCO Out VDD PLL Enable Debug UART Rxd no connection no connection Transmit Data Receive Data Request To Send Data Terminal Ready Clear To Send Data Set Ready Data Carrier Detect Ring Indicate Transmit Data IN/OUT IN IN IN IN OUT OUT IN OUT IN OUT OUT IN OUT OUT IN IN IN IN OUT IN/OUT IN/OUT IN OUT IN OUT IN IN OUT IN OUT OUT IN IN IN IN OUT Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 3 KL5KUSB105 USB to 4 Serial Ports Pin # LQFP 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 I/O Pin Name GND CLK X2 XA_15 VDD VDD XA_14 XA_0 nXBHE GND nXRAMSEL UART3_Rxd* UART3_RTS* UART3_DTR* UART3_CTS* UART3_DSR* UART3_DCD* nXRD nXWR nXROMSEL nNRESET nNTST* GND XA_1 XA_2 XA_3 XA_4 XA_5 XA_6 XA_7 XA_8 XA_9 XA_10 XA_11 XA_12 XA_13 GND XD_0* XD_1* XD_2* XD_3* XD_4* XD_5* XD_6* XD_7* XD_8* XD_9* XD_10* XD_11* Description GND 12MHz Clock/Crystal Input 12MHz Crystal Output External Address Pin VDD VDD External Address Pin External Address Pin External byte High Enable (Active low) GND External RAM CS (Active low) Receive Data Request To Send Data Terminal Ready Clear To Send Data Set Ready Data Carrier Detect External Memory Read (Active low) External Memory Write (Active low) External ROM CS (Active low) Reset Pin Test Pin, Disconnect for Normal Operation GND External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin External Address Pin GND External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins External Data Pins IN OUT OUT OUT OUT OUT OUT IN OUT OUT IN IN IN OUT OUT OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT IN/OUT Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 4 KL5KUSB105 USB to 4 Serial Ports Pin # I/O LQFP 95 IN/OUT 96 IN/OUT 97 98 IN/OUT 99 IN/OUT 100 *Pins are 5V tolerant. Pin Name XD_12* XD_13* GND XD_14* XD_15* VDD External Data Pins External Data Pins GND External Data Pins External Data Pins VDD Description Function Description 16 Bit Processor The integrated 16 bit processor serves as a micro controller for USB peripherals. The processor can execute approximately five million instructions per second. With this processing power it allows the design of intelligent peripherals that can process data prior to passing it on to the host PC, thus improving overall performance of the system. The masked ROM in the this device or external memory contains a specialized instruction set that has been designed for highly efficient coding of processing algorithms and USB transaction processing. The 16-bit processor is designed for efficient data execution by having direct access to the RAM Buffer, external memory, I/O interfaces, and all the control and status registers The processor supports prioritized vectored hardware interrupts and has as many as 240 software interrupt vectors. The processor provides six addressing modes, supporting memory-to-memory, memory-toregister, register-to-register, immediate-to-register or immediate-to-memory operations. Register, direct, immediate, indirect, and indirect indexed addressing modes are supported. In addition, there is an auto-increment mode in which a register, used as an address pointer is automatically incremented after each use, making repetitive operations more efficient both from a programming and a performance standpoint. The processor features a full set of program control, logical, and integer arithmetic instructions. All instructions are sixteen bits wide, although some instructions require operands, which may occupy another one or two words. Several special “ short immediate” instructions are available, so that certain frequently used operations with small constant operand will fit into a 16-bit instruction. The Processor – Divide/Multiply function The processor’s divide/multiply function contains all the instructions of the base processor that additionally includes integer divide and multiply instructions. A signed multiply instructions takes two 16-bit operands and returns a 32-bit result. A signed divide instruction divides a 32-bit operand by a 16-bit operand. Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 5 KL5KUSB105 USB to 4 Serial Ports RAM Buffer The USB controller contains internal buffer memory. The memory is used to buffer data and USB packets and accessed by the 16 Bit processor and the SIE. USB transactions are automatically routed to the memory buffer. The 16-bit processor has the ability to set up pointers and block sizes in buffer memory for USB transactions. Data is read from the interface and is processed and packetized by the 16-bit I/O processor. PLL Clock Generator The PLL circuitry is provided to generate the internal 48MHz clock. This circuitry is designed to allow use of a low cost 12 MHz external crystal which is connected to CLK and X2. If an external 12 MHz clock is available in the application, it may be used in lieu of the crystal circuit and connected directly to the CLK input pin. USB Interface The USB controller meets the Universal Serial Bus (USB) specification ver 1.0/1.1. The transceiver is capable of transmitting and receiving serial data at the USB’s full speed, 12 Mbits/sec data rate. The driver portion of the transceiver is differential, while the receive section is comprised of a differential receiver and two single ended receivers. Internally, the transceiver interfaces to the SIE logic. Externally, the transceiver connects to the physical layer of the USB. Quad UART Serial Interface Four independent UART serial ports are provided. Each port can be configured for a wide selection of baud rates, 300 to 230.4 K baud, and support a set of control signals. Each UART provides a means for external serial devices to access the USB. Debug UART An independent UART serial port is provided for debug and code development. The port can be configured for a wide selection of baud rates, 7200 to 115.2K baud. The port provides transmit and receive data support only. Serial EEPROM Support The USB Controller serial interface is used to provide access to external EEPROM’s. interface can support a variety of serial EEPROM formats. The Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 6 KL5KUSB105 USB to 4 Serial Ports Electrical Characteristics ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN (Normal) VIN (5V Tolerant) TSTG Ratings -0.3 to 4.0 -0.3 to VDD+0.3 -0.3 to 6.0 -55 to 125 Unit V V V °C DC Characteristics and conditions (VDD @ 3.3V±.3V) Symbol Parameter Condition VDD VIH VIL V+ * V- * VH * IIH IIL VOH VOL IOZ Supply Voltage Input high voltage Input low voltage Input high voltage Input low voltage Hysteresis voltage Input high current Input low current Output high voltage Output low voltage 3-state leakage current Min 3.0 2.0 0.5 0.4 -10 -10 2.4 -10 -10 Schmitt Schmitt Schmitt VIN = VDD VIN = Vss VOH=VSS VOL=VDD Value Typ 3.3 1.8 0.9 - Unit Max 3.6 0.8 2.3 10 10 0.4 10 -10 V V V V V V µA µA V V µA µA *For reset pin (nNRESET, pin 66) Kawasaki LSI assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. There are no warranties extended or granted by this document. The information herein is subject to change without notice form Kawasaki LSI January 1999 • © Copyright 1999 • Kawasaki LSI • Printed in U.S.A Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com Ver. 1.8 7