RM3183

Electronics Semiconductor Division RM3183 Dual ARINC 429 Line Receiver Features • • • • • • • • Converts ARINC levels to serial data Adjustable noise filters TTL and CMOS compatible outputs Built-in test inputs Input protection circuitry Mil-Std-883B screening available 20-pin DIP and LCC packages available Dice with Mil visual screening available clamping diodes. Self-test logic inputs are provided for internal system tests. These inputs force the outputs to either a high, a low, or a null state for off-line system tests. Input noise filtering is accomplished with external capacitors. Two are required for each channel and can be adjusted for best noise immunity at a specific data rate. Three power supplies are needed plus ground. The input thresholds depend only on the logic supply, so a wide range of dual supplies can be accommodated. The Raytheon RM3183 line receiver is the companion chip to the RM3182 line driver. Together they provide all the analog functions needed for the ARINC 429 interface. Digital data processing involving serial-to-parallel conversion and clock recovery can be accomplished using one of the ARINC interface ICs available or by discrete or gate array implementations. Description The RM3183 is a dual line receiver designed to meet all requirements of the ARINC 429 interface specification. It contains two independent receiver channels which accept differential input signals and converts them to serial TTL data. Input overvoltage protection is provided by special circuitry including dielectrically-isolated thin-film resistors and Block Diagram +VS +VL 9 15 11 18 16 19 17 2 20 Input Protection & Level Shift In 1A In 1B Cap 1A Cap 1B Test A Test B C1A Out 1A C1B 12 Out 1B Test Interface In 2A In 2B Cap 2A Cap 2B 6 4 7 3 1 -VS C2A Input Protection & Level Shift C2B 8 Out 2A 5 Out 2B 14 Gnd 65-3183-01 Rev. 1.0.0 RM3183 PRODUCT SPECIFICATION Functional Description The RM3183 contains two discrete ARINC 429 receiver channels. Each channel contains three main sections: a resistor-diode input network, a window comparator, and a logic output buffer stage. The first stage provides overvoltage protection and biases the signal using voltage dividers and current sources which are internally connected to the +VL logic supply. This configuration provides excellent input common mode rejection and a stable reference voltage for the window comparators. Because the threshold for switching is determined by this circuitry, ±5% tolerance is recommended for the +VL supply. The test inputs will set the outputs to a predetermined state for built-in test capability. The ARINC inputs must be forced to 0V when using the test inputs. If the test inputs are not used, they should be grounded. The window comparator stage generates two serial data streams, one having logic 1 states corresponding to ARINC “High” states (OUTA), and the other having logic 1 states corresponding to ARINC “Low” states (OUTB). An ARINC “Null” state at the inputs forces both outputs to logic 0. Thus, the ARINC clock signal is recovered by applying a NOR function to OUTA and OUTB. The output stage generates a TTL compatible logic output capable of driving several gate inputs. Pin Assignments Ceramic Dip Top View 3 Cap2B LCC Top View 19 Cap1A 1 -VS 20 TestB 2 TestA -VS TestA Cap2B In2B Out2B In2A Cap2A Out2A +VL NC 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 65-3183-02 TestB Cap1A In1A In2B 4 Cap1B In1B Out1A GND Out2B 5 In2A 6 Cap2A 7 Out2A 8 18 17 16 15 14 In1A Cap1B In1B Out1A GND 9 NC 10 +VS 11 +VL NC Out1B +VS Out1B 12 NC 13 65-3183-03 Absolute Maximum Ratings Parameter Supply Voltage +VS –VS +VL Operating Temperature Range Storage Temperature Range Input Voltage Range Output Short Circuit Duration Internal Power Dissipation Lead Soldering Temperature (60 seconds) -55 -65 Min. Max. +20 –20 +7 +125 +150 ± 50 Not protected 900 +300 mW °C Units VDC VDC VDC °C °C V 2 PRODUCT SPECIFICATION RM3183 Thermal Characteristics Maximum Junction Temperature Maximum PD TA < 50°C Thermal Resistance, θJC Thermal Resistance, θJC (Still air, soldered into PC board) Ceramic DIP +175°C 1042 mW 60°C/W 120°C/W LCC +175°C 925 mW 37°C/W 105°C/W DC Electrical Characteristics TA = -55°C to +125°C, ± 12V ≤ VS ± 15V, VL = +5V, unless otherwise noted Symbol VIH VIL VIN VIC RI RH RG CI(1, 2) CH (1, 2) (1, 2) (2) Parameter V(A)-V(B) V(A)-V(B) V(A)-V(B) V(A) and V(B)-GND Input resistance, Input A to Input B Input resistance, Input A to Gnd Input resistance, B to Gnd Input capacitance, A to B Input capacitance, A to Gnd Input capacitance, B to Gnd Logic 1 input voltage Logic 0 input voltage Logic 1 input current Logic 0 input current IOH = 100 µA IOH = 2.8 mA IOL = 100 µA IOL = 2.0 mA Rise Time Fall Time Propagation delay Output low to high Output high to low Conditlons OUTA = 1 OUTB = 1 OUTA and OUTB = 0 Maximum common mode frequency = 80 kHz Min. 6.5 -6.5 -2.5 Typ. 10 -10 0 ±5 Max. 13 -13 +2.5 Units V V V V kΩ kΩ kΩ 30 19 19 Filter caps disconnected Filter caps disconnected Filter caps disconnected 2.7 VIH = 2.7V VIL = 0.0V TA = 25°C Full temperature range TA = 25°C Full temperature range CL = 50 pF, TA = 25°C CL = 50 pF, TA = 25°C CL = 50 pF, fO = 400 kHz Filter caps = 39 pF TA = 25°C 4.0 3.5 V(A) = 0V V(B) = 0V 50 25 25 3 3 3 10 10 10 pF pF pF V CG Test Inputs (TESTA, TESTB) VIH VIL IIH IIL Outputs VOH VOL Tr Tf TPLH TPHL 4.3 4.0 0.02 0.3 40 30 800 320 0.08 0.8 70 70 V V V V ns ns ns ns 0.0 5 0.5 15 1.0 V µA µA 3 RM3183 PRODUCT SPECIFICATION DC Electrical Characteristics (continued) TA = -55°C to +125°C, ± 12V ≤ VS ± 15V, VL = +5V, unless otherwise noted Symbol Supply Current ICC (+VS) IEE (-VS) IDD (+VL) Test inputs = 0V Test inputs = 0V Test inputs = 0V ± VS = 15V, TA = 15°C ± VS = 12V, TA = 15°C ± VS = 15V, TA = 15°C ± VS = 12V, TA = 15°C ± VS = 15V, TA = 15°C ± VS = 12V, TA = 15°C 3.7 3.0 8.7 7.4 9.0 8.6 7.0 6.0 15.0 14.0 20.0 18.0 mA mA mA mA mA mA Parameter Conditlons Min. Typ. Max. Units Notes: 1. With noise filter capacitors disconnected. 2. Guaranteed by design. Truth Table ARINC Inputs V(A) - V(B) Null Low High V(A) = 0V, V(B) = 0V V(A) = 0V, V(B) = 0V V(A) = 0V, V(B) = 0V Test Inputs TESTA 0 0 0 0 1 1 TESTB 0 0 0 1 0 1 OUTA 0 0 1 0 1 0 Outputs OUTB 0 1 0 1 0 0 4 PRODUCT SPECIFICATION RM3183 Typical Performance Characteristics 1000 900 Supply Current (mA) 800 Prop Delay (ns) 700 600 500 400 300 65-3183-04 12 11 10 9 8 7 6 +V S (I CC ) 65-3183-05 VL (I DD ) -VS (I EE ) VS = 15V VL = +5V T PLH T PHL 200 100 0 -60 -35 -10 15 40 65 90 115 5 4 3 -60 -35 -10 15 40 140 65 90 115 140 Temperature (°C) Temperature (°C) Figure 1. Propagation Delay vs. Temperature CL = 50 pF, CFILTER = 39 pF Figure 2. Supply Current vs. Temperature 1.00 4.5 +125°C 0.75 VOL (Volts) +125°C VOH (Volts) +25°C 4.3 4.1 3.9 3.7 3.5 0 0.5 1.0 1.5 IOH (mA) 2.0 2.5 -55°C 65-3183-07 +25°C 0.50 +55°C 0 0 0.5 1.0 1.5 IOL (mA) 2.0 2.5 3.0 65-3183-06 0.25 3.0 Figure 3. Output Voltage Low vs. Output Current Figure 4. Output Voltage High vs. Output Current 70 60 Rise/Fall Time (ns) 50 40 3.0 TR Prop Delay (µs) 2.5 2.0 T A = +25 C T PLH T PHL 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 Filter Capacitance (pF) 65-3183-09 TF 30 20 10 0 -60 -35 -10 15 40 65 90 115 65-3183-08 140 400 Temperature (°C) Figure 5. TR and TF vs. Temperature Figure 6. Propagation Delay vs. Filter Capacitance TA = 25°C 5 RM3183 PRODUCT SPECIFICATION AC Test Waveforms +10V ARINC In (Differential) 0V Logic Out Logic Out (A Output) TPLH TPHL 65-3183-10 90% 10% 90% 10% TR TF 65-3183-16 Figure 7. Propagation Delay Figure 8. Rise/Fall Times Test Circuit +15V 0.1 µF 0.01 µF -15V 0.01 µF 9 +5V VIN1 11 18 1 15 VOUT1 50 pF VOUT2 50 pF VOUT3 50 pF VOUT4 50 pF VIN2 6 12 RM3183 16 8 VREF 4 19 17 7 3 14 5 39pF 39pF 39pF 39pF Notes: 1. VIN = 400 kHz square wave, -3.5V to +3.5V. 2. Set VREF = +3.5 V to test VOUT1 and VOUT3. Set VREF = -3.5 V to test VOUT2 and VOUT4. 3. 50 pF load capacitance includes probe and wiring capacitance. 65-3183-11 Figure 9. AC Test Schematic Diagram 6 PRODUCT SPECIFICATION RM3183 Applications Information The standard connections for the RM3183 are shown in Figure 1. Dual supplies from ±12 to ±15 VDC are recommended for the ±VS supplies. Decoupling of all supplies should be done near the IC to avoid propagation of noise spikes due to switching transients. The ground connections should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possible. The noise filter capacitors are optional and are added to provide extra noise immunity by limiting the noise bandwidth of the input signal before it reaches the comparator. Two capacitors are required for each channel and they must all be the same value. The suggested capacitor value for a 100 KHz operation is 39 pF, which will give a noise bandwidth of approximately 800 KHz. For lower data rates, larger values of capacitance may be used to yield better noise performance. To get optimum performance, the following equation should be used to calculate capacitor value for a specific data rate: 3.95 × 10 C = --------------------------FO F O = Data Rate (bits/sec) –6 The RM3183 can be used with Raytheon’s RM3182 Line Driver to provide a complete analog ARINC 429 interface. A simple application which can be used for systems requiring a repeater-type circuit for long transmissions or test interfaces is given in Figure 2. More RM3182 drivers may be added to test multiple ARINC channels, as shown. An all digital IC is available which forms a complete receiver system when combined with the RM3183. The Thomson EF4442 is a four channel ARINC 429 receiver IC which contains all the digital circuitry required to interface with an 8-bit processor. Each channel consists of a 32-bit register, an 8-bit status word comparator, and a 24-bit latch. A multiplexer and 8-bit data bus buffer form the interface to the system microprocessor. Figure 3 shows a typical ARINC application having both transmit and receive functions using four ICs: the EF4442, the RM3182 driver and two RM3183 dual receivers. 7 RM3183 PRODUCT SPECIFICATION Applications +5V 9 +15V 11 RM3183 18 ARINC Channel 1 16 39 pF 19 In 1A In 1B Cap 1A 15 A Channel 1 Data Out To Logic 12 B 17 39 pF 6 ARINC Channel 2 4 39 pF 7 Cap 1B In 2A In 2B Cap 2A 8 A 5 Channel 2 Data Out To Logic B 3 39 pF 2 Logic Test Inputs 20 Cap 2B Test A Test B 1 65-3183-12 14 -15V Figure 9. ARINC Receiver Standard Connections ARINC Test Channel Input A In 1A In 1B B 1/2 RM3183 Out 1A Data (A) Data (B) A OUT RM3182 A B Out 2A Test Channel 1 B OUT Data (A) A OUT A RM3182 Test Channel 2 Data (B) B OUT B To Additional Channels 65-3183-13 Figure 10. Repeater Circuit 8 PRODUCT SPECIFICATION RM3183 Applications (continued) +5V +15V Inputs +V L ARINC Channel 0 In 1A In 1B Out 1A Out 1B VCC H0 L0 N1 N0 H1 L1 EF4442 -15V +15V +VS GND -VS ARINC Channel 2 In 1A In 1B Out 1A Out 1B H2 L2 Reset IRQ R/W Clock D0 - D8 H3 L3 A0 A1 CS To +5V From Address Decoder Microprocessor Data Bus From Microprocessor Gnd PE CA Data (A) VSS Mode V R V I Sync Clk +VS RM3182 A OUT B OUT ARINC Line Out RM3183 ARINC Channel 1 In 2A In 2B Out 2A Out 2B Data (B) -VS CB 75 pF -15V +VS GND -VS 75 pF RM3183 ARINC Channel 3 In 2A In 2B Out 2A Out 2B +VL 65-3183-14 Figure 11. Four-Channel ARINC Receiver Circuit -15V 10 Ω 1/2 W +15V 4 1 18 10K 10K 5 6 RM3183 16 10K 15 14 10K 8 9 11 12 10K 10K 10 Ω 1/2 W +5V 10Ω 1/2 W 65-3183-15 +15V Figure 12. Burn-In Circuit 9 PRODUCT SPECIFICATION RM3183 Mechanical Dimensions 20-Lead Ceramic DIP Inches Min. A b1 b2 c1 D E e eA L Q s1 α Max. Millimeters Min. Max. 8 2, 8 8 4 4 5, 9 7 3 6 Notes: 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 2. The minimum limit for dimension "b2" may be .023(.58mm) for leads number 1, 10, 11 and 20 only. 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within ±.010 (.25mm) of its exact longitudinal position relative to pins 1 and 20. 6. Applies to all four corner's (leads number 1, 10, 11, and 20). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "α" is 90°. 8. All leads – Increase maximum limit by .003(.08mm) measured at the center of the flat, when lead finish is applied. 9. Eighteen spaces. Symbol Notes — .200 .014 .023 .045 .065 .008 .015 — 1.060 .220 .310 .100 BSC .300 BSC .125 .200 .015 .060 .005 — 90° 105° — 5.08 .36 .58 1.14 1.65 .20 .38 — 25.92 5.59 7.87 2.54 BSC 7.62 BSC 3.18 5.08 .38 1.52 .13 — 90° 105° D Note 1 E s1 e A Q L b2 b1 eA α c1 10 RM3183 PRODUCT SPECIFICATION Mechanical Dimensions (continued) 20-Terminal LCC Inches Min. A A1 B1 B3 D/E D1/E1 D2/E2 D3/E3 e h j L1 L2 L3 ND/NE N .060 .050 .022 .006 Max. .100 .088 .028 .022 Millimeters Min. 1.52 1.27 .56 .15 Max. 2.54 2.24 .71 .56 3, 6 3, 6 2 2, 5 Notes: Notes 1. The index feature for terminal 1 identification, optical orientation or handling purposes, shall be within the shaded index areas shown on planes 1 and 2. Plane 1, terminal 1 identification may be an extension of the length of the metallized terminal which shall not be wider than the B1 dimension. 2. Unless otherwise specified, a minimum clearance of .015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.). 3. Dimension "A" controls the overall package thickness. The maximum "A" dimension is the package height before being solder dipped. 4 4 4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. The index corner shall be clearly unique. 5. Dimension "B3" minimum and "L3" minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed. Dimensions "B3" and "L3" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dripping. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. PLANE 2 E3 LID PLANE 1 A1 Symbol .342 .358 .200 BSC .100 BSC — .358 .050 BSC .040 REF .020 REF .045 .055 .075 .003 5 20 .095 .015 8.69 9.09 5.08 BSC 2.54 BSC — 9.09 1.27 BSC 1.02 REF .51 REF 1.14 1.40 1.91 .08 5 20 2.41 .38 5 E 1 (j) X 45° 4 D (h) X 45° 3 PLCS 4 D3 A INDEX CORNER E1 E2 B1 e D2 D1 L3 B3 L2 L1 DETAIL "A" DETAIL "A" 11 PRODUCT SPECIFICATION RM3183 Ordering Information Part Number RM3183S RM3183L Package 20 Lead Ceramic DIP 20 Terminal Leadless Chip Carrier Operating Temperature Range -55°C to +125°C -55°C to +125°C The information contained in this data sheet has been carefully compiled; however, it shall not by implication or otherwise become part of the terms and conditions of any subsequent sale. Raytheon’s liability shall be determined solely by its standard terms and conditions of sale. No representation as to application or use or that the circuits are either licensed or free from patent infringement is intended or implied. Raytheon reserves the right to change the circuitry and any other data at any time without notice and assumes no liability for errors. LIFE SUPPORT POLICY: Raytheon’s products are not designed for use in life support applications, wherein a failure or malfunction of the component can reasonably be expected to result in personal injury. The user of Raytheon components in life support applications assumes all risk of such use and indemnifies Raytheon Company against all damages. Raytheon Electronics Semiconductor Division 350 Ellis Street Mountain View, CA 94043 650.968.9211 FAX 650.966.7742 8/97 0.0m Stock# DS30003183 © Raytheon Company 1997