EM424M824VTB

16Mb SDRAM Ordering Information EM 48 1M 16 2 2 V T A – 6 L EOREX Memory EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM Density 16M : 1 6 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit : : : : : : 40 41 42 43 46 48 Power Blank : Standard L : Low power I : Industrial F: PB free package Organization 8 : x8 9 : x9 1 6 : x16 1 8 : x18 3 2 : x32 Refresh 1 : 1 K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 3 2Bank 8 : 8Bank Min Cycle Time ( Max Freq.) -5 : 5 ns ( 200MHz ) -6 : 6 ns ( 167MHz ) -7 : 7 ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8 ns ( 125MHz ) -10 : 10ns ( 100MHz ) Revision A : 1st B : 2 nd C : 3rd D :4th Interface V: 3.3V R: 2.5V Package C: CSP B: u BGA T: TSOP Q: TQFP P: PQFP ( QFP ) 1/18 Rev.01 16Mb SDRAM 16Mb ( 2Banks ) Synchronous DRAM EM481M1622VTA (1Mx16) Description The EM481M1622VTA is Synchronous Dynamic Random Access Memory (SDRAM) organized as 512K x 2 banks x 16 bits. All inputs and outputs are synchronized with the positive edge of the clock. The 16Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL . Feature • Fully • Single synchronous to positive clock edge 3.3V +/- 0.3V power supply • LVTTL compatible with multiplexed address • Programmable Burst Length (B/ L) - 1,2,4,8 or full page • Programmable CAS Latency (C/ L) - 2 or 3 • Data Mask (DQM) for Read / Write masking • Programmable wrap sequence - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) • Burst read with single-bit write operation • All inputs are sampled at the rising edge of the system clock. • Auto refresh and self refresh • 2,048 refresh cycles / 32ms * EOREX reserves the right to change products or specification without notice. 2/18 Rev.01 16Mb SDRAM Pin Assignment ( Top View ) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM /WE /CAS /RAS /CS BA A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS 50pin TSOP-II 3/18 Rev.01 16Mb SDRAM Pin Descriptions ( Simplified ) Pin CLK /CS CKE Name System Clock Chip select Clock Enable Pin Function Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A10) is determined by A0 to A10 level at the bank active command cycle CLK rising edge. CA(CA0 to CA7) is determined by A0 to A7 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. A0 ~ A10 Address BA Bank Address /RAS Row address strobe /CAS Column address strobe /WE Write Enable UDQM /LDQM Data input/output Mask DQM controls I/O buffers. DQ0 ~ 15 Data input/output DQ pins have the same function as I/O pins on a conventional DRAM. VDD/VSS VDDQ/VSSQ NC Power supply/Ground Power supply/Ground No connection VDD a nd VSS a re power supply pins for internal circuits. VDDQ a nd VSSQ a re power supply pins for the output buffers. This pin is recommended to be left No Connection on the device. 4/18 Rev.01 16Mb SDRAM Block Diagram A0 A1 A2 Row Add. Buffer Auto/Self Refresh Counter DQM Address Register Row Decoder A3 A4 A5 A6 A7 A8 A9 A10 BA Memory Array S/A & I/O gating Col. Decoder Col. Add. Buffer Write DQM Control Data In DQi Data Out Read DQM Control Mode Register Set Col. Add. Counter Burst Counter DQM /WE DQM Timing Register CLK CKE /CS /RAS /CAS 5/18 Rev.01 16Mb SDRAM Simplified State Diagram Self Refresh LF SE LF SE it Ex Mode Register Set MRS IDLE REF CBR Refresh CK E↓ CK E Write Row Active ad Re wi th ACT Wr ite Power Down CKE↓ CKE BS T Re ad Read Active Power Down th wi WRITE Suspend CKE↓ CKE WRITE Read READ CKE↓ CKE Write READ Suspend PR E WRITEA Suspend CKE↓ CKE WRITEA E PR READA CKE↓ CKE READA Suspend POWER ON Precharge Precharge Manual Input Automatic Sequence 6/18 Rev.01 16Mb SDRAM Address Input for Mode Register Set BA A10 A9 A8 A7 A6 A5 A4 A3 BT A2 A1 A0 Operation Mode CAS Latency Burst Length Sequential 1 2 4 8 Reserved Reserved Reserved Full Page Burst Type Interleave Sequential CAS Latency Reserved 2 3 Reserved Reserved Reserved Reserved Reserved BA 0 0 A10 0 0 A9 0 1 A8 0 0 A7 0 0 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 A3 0 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 A4 0 1 0 1 0 1 0 1 Operation Mode Normal Burst read with Single-bit Write 7/18 Rev.01 16Mb SDRAM Burst Type ( A3 ) Burst Length 2 4 A2 A1 A0 XX0 XX1 X0 0 X0 1 X1 0 X1 1 000 001 010 011 100 101 110 111 nnn Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 …... Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 - 8 Full Page * * Page length is a function of I/O organization and column addressing x16 (CA0 ~ CA7) : Full page = 256 bits 8/18 Rev.01 16Mb SDRAM Truth Table 1. Command Truth Table Command Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set Symbol DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL MRS CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X /CS /RAS /CAS /WE H L L L L L L L L L L X H H H H H L L L L L X H H L L L H H H H L X H L H H L H H L L L BA X X X V V V V V V X L A10 A9~A0 X X X L H L H V L H L X X X V V V V V X X V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. DQM Truth Table Command ( EM481M1622VT ) Data w rite / output enable Data mask / output disable ENB MASK BSTH READ READA WRIT WRITA ACT PRE PALL MRS H H H H H H H H H H H X X X X X X X X X X X H L L L L L L L L L L Symbol CKE n-1 n /CS ( EM481M1622VT ) Upper byte w rite enable / output enable Read Read w ith auto pre-charge Write Write w ith auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Command Activating Any Clock suspend Idle Idle Self refresh Idle Power down Command Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Pow er dow n entry Pow er dow n exit Symbol CKE n-1 H L L H H L L H L n L L H H L H H L H /CS /RAS /CAS /WE Addr. X X X L L L H X X X X X L L H X X X X X X L L H X X X X X X H H H X X X X X X X X X X X X REF SELF Re m ark H = High level, L = Low level, X = High or Low level (Don't care) 9/18 Rev.01 16Mb SDRAM 4. Operative Command Table Current state /CS /R /C /W H L L L L L L L H L L L L L L L H L L L L L L L L H L L L L L L L L X H H H L L L L X H H H L L L L X H H H L L L L L X H H H L L L L L X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L Addr. X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA A CT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA A CT PRE/PALL REF/SELF MRS Action Nop or pow er dow n Nop or pow er dow n ILLEGAL ILLEGAL Row activating Nop Refresh or self refresh Mode register accessing Nop Nop Begin read : Determine AP Begin w rite : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read : Determine AP Terminate burst, start w rite : Determine AP ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end → Write recovering Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read : Determine AP 7, 8 Terminate burst, new w rite : Determine AP 7 ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Notes 2 2 3 3 Idle 4 Row active 5 5 3 6 4 Re ad 7 7, 8 3 4 Write 7,8 7 3 9 Re m ark H = High level, L = Low level, X = High or Low level (Don't care) 10/18 Rev.01 16Mb SDRAM Current state /CS /R /C /W H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L Addr. Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Action Continue burst to end → Precharging Continue burst to end → Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst to end → Write recovering w ith auto precharge Continue burst to end → Write recovering w ith auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter idle after tRCD Nop → Enter idle after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes Re ad w ith AP X X H X L X H BA/CA/A10 L BA/CA/A10 H BA/RA L BA, A10 H X L Op-Code X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code 3 3 3 3 Write w ith AP 3 3 3 3 Pre charging 3 3 3 Row activating 3 3 3,10 3 Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge 11/18 Rev.01 16Mb SDRAM Current state /CS /R /C /W H L L L L L L L L H L L L L L L L L H L L L L H L L L L X H H H H L L L L X H H H H L L L L X H H L L X H H H L X H H L L H H L L X H H L L H H L L X H L H L X H H L X X H L H L H L H L X H L H L H L H L X X X X X X H L X X Addr. X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X X Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/ BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS Action Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP New w rite, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL Nop → Enter precharge after tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL Notes Write re cove ring 8 3 3 Write re cove ring w ith AP 3,8 3 3 Re freshing M ode Re giste r Acces sing Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge Notes 1. A ll entries assume that CKE w as active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode. All input buffers except CKE w ill be disabled. 3. Illegal to bank in specified states; → Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode. All input buffers except CKE w ill be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. Must mask preceding data w hich don't satisfy tDPL. 10. Illegal if tRRD is not satisfied. 12/18 Rev.01 16Mb SDRAM 5. Command Truth Table for CKE Current state CKE n X H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L n-1 H L L Se lf re fre sh L L L H H H Se lf re fre sh H re covery H H H H H Pow er dow n L L H H H H H Both banks H idle H H H H L H Row active L H Any state H other than L liste d above L /CS /R /C /W X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X X Addr. X X X X X X X X X X X X X X X X X Action INVALID, CLK (n – 1) w ould exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) w ould exit pow er dow n Exit pow er dow n → Idle Maintain pow er dow n mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self refresh Refer t o operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend Notes X Op-Code X Op-Code X X X X X X 1 1 1 2 Re m ark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Pow er dow n can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table. 13/18 Rev.01 16Mb SDRAM Absolute Maximum Ratings Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD IOS Item Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current Rating -0.3 ~ 4.6 -0.3 ~ 4.6 0 ~ 70 -55 ~ 150 1 50 Units V V °C °C W mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specif ication. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70°C ) Symbol VDD VDDQ VIH VIL Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input logic high voltage Input logic low voltage Min. 3.0 3.0 2.0 -0.3 Typical 3.3 3.3 Max. 3.6 3.6 VDD+0.3 0.8 Units V V V V Note : 1. All voltage referred to V SS. 2. V IH ( max) = 5.6V for pulse w idth ≤ 3ns 3. V IL ( min) = -2.0V for pulse w idth ≤ 3ns Capacitance ( Vcc =3.3V, f = 1MHz, Ta = 25°C ) Symbol CCLK CI CO Parameter Clock capacitance Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML,DQMU Input/Output capacitance Min. 2.5 2.5 4.0 Max. 4.0 5.0 6.5 Units pF pF pF 14/18 Rev.01 16Mb SDRAM Recommended DC Operating Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I) Parameter Symbol Test condition Burst length = 1, tRC ≥ tRC ( min), IOL = 0 mA, One bank active CKE ≤ V IL ( max.), tCk = 15 ns CKE ≤ V IL ( max.), tCk = ∞ CKE ≥ V IL ( min.), tCK = 15 ns, /CS ≥ V IH ( min.) Input signals are changed one time during 30ns CKE ≥ V IL ( min.), tCK = ∞ Input signals are stable MAX 5 100 6/6I/6L 7/7L 90 2 / 0.7* 2 / 0.7* 20 8 5 5 30 80 Units Notes Operating current Precharge standby current in power down mode Precharge standby current in non-power down mode Active standby current in power down mode ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N mA mA mA mA mA mA mA mA 1 5 5 CKE ≤ VIL(max), tCK = 1 5ns CKE ≤ VIL(max), tCK = ∞ CKE ≥ VIL(min), tCK = 15ns,/ CS ≥ VIH(min) Input signals are changed one time during 30ns CKE ≥ VIL(min), tCK = ∞ Input signals are stable tCCD = 2 CLKs , IOL = 0 m A tRC ≥ tRC(min.) CKE ≤ 0.2V CL=3 CL=2 180 130 Active standby current in non-power down mode operating current (Burst mode) Refresh current Self Refresh current ICC3NS ICC4 ICC5 ICC6 20 160 120 2 0.3 140 110 mA mA mA mA 2 3 4 5 Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard pow er version. 5. * Low pow er version. 15/18 Rev.01 16Mb SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Test condition 0 ≤ VI ≤ VDDQ, VDDQ=VDD All other pins not under test=0 V 0 ≤ VO ≤ VDDQ, DOUT is disabled Io = -4mA Io = +4mA Min. Max. Unit Input leakage current IIL -0.5 +0.5 uA Output leakage current High level output voltage Low level output voltage IOL VOH VOL -0.5 2.4 +0.5 uA V 0.4 V AC Operating Test Conditions ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I ) Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level 1.4V / 1.4V See diagram as below 2.4V / 0.4V 2ns 1.4V Vtt = 1.4V 50Ω Output Z = 50Ω 50pF 16/18 Rev.01 16Mb SDRAM Operating AC Characteristics ( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 °C , Ta = -40 to 85°C for 6I) Parameter Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 tCK tAC tCH tCL tOH tHZ tLZ tIH tIS tRC tRAS tRP tRCD tRRD tCCD tDPL tBDL tROH tREF 1.5 1.5 1.5 1.5 5 Symbol -5 Min. 5 7 4.5 5.5 -6/6I/6L Min. 6 7.5 5 5.5 2 2 2 2 6 Max. 7 8 -7/7L Min. Max. Max. Units Notes ns ns 5.5 5 2.75 2 2.75 2 2 2 2 2 7 ns ns ns ns ns ns ns ns Data-out high impedance time Data-out low impedance time Input hold time Input setup time 0 1 1 .5 54 40 18 14 10 1 2 1 3 100k 0 1 1 .5 60 42 18 18 12 1 2 1 3 100k 1 1 1.5 65 45 18 20 14 1 2 1 3 2 100k ns ns ns ns ns ns ns ns CLK CLK CLK CLK CLK 32 ms 2 2 2 2 2 ACTIVE to ACTIVE command period ACTIVE to PRECHARGE command period PRECHARGE to ACTIVE command period ACTIVE to READ/WRITE delay time ACTIVE(one) to ACTIVE(another) command READ/WRITE command to READ/WRITE command Data-in to PRECHARGE command Data-in to BURST stop command Data-out to high impedance from PRECHARGE command CL = 3 CL = 2 Refresh time(2,048 cycle) ＊ All voltages referenced to Vss. 32 32 Note : 1. tHZ d efines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 2. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number) 17/18 Rev.01 16Mb SDRAM Package Dimension 18/18 Rev.01