EM622FT16BT-45L

EM620FV8B Series Low Power, 256Kx8 SRAM Document Title 256K x8 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. 0.0 0.1 0.2 0.3 History Initial Draft 0.1 Revision 0.2 Revision 0.3 Revision Remove BYTE option information Remove UB, LB information Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns), tOE-55(30ns to 25ns), tWP-55(45ns to 40ns), tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns), ICC(2mA to 3mA), ICC1(2mA to 3mA) VIH level change from 2.0V to 2.2V Draft Date June 7, 2007 June 15, 2007 June 21, 2007 July 2, 2007 Remark 0.4 0.4 Revision Aug. 16, 2007 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM620FV8B Series Low Power, 256Kx8 SRAM 256K x8 Bit Low Power and Low Voltage CMOS Static RAM FEATURES - Process Technology : 0.15µm Full CMOS - Organization :256K x8 - Power Supply Voltage => EM620FV8B : 2.7~3.6V - Low Data Retention Voltage : 1.5V - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns GENERAL PHYSICAL SPECIFICATIONS - Backside die surface of polished bare silicon - Typical Die Thickness = 725um +/-15um - Typical top-level metallization : => Metal (Ti/AlCu/TiN/ARC SiON/SiO2) : 5.2K Angstroms - Topside Passivation : => Passivation (HDP/pNIT/PIQ) : 5.4K Angstroms - Wafer diameter : 8 inch OPTIONS - C1/W1 : DC Probed Die/Wafer @ Hot Temp - C2/W2 : DC/AC Probed Die/Wafer @ Hot Temp 1 56 29 EM620FV8B (Dual C/S) + (0.0) EMLSI LOGO 28 y x BONDING INSTRUCTIONS The 2M full CMOS SRAM die has total 56pads. Refer to the bond pad location and identification table for X, Y coordinates. EMLSI recommends using a bond wire on back side of die onto Vss bond pad for improved noise immunity. 2 EM620FV8B Series Low Power, 256Kx8 SRAM FUNCTIONAL SPECIFICATIONS There are 3 classifications for EMLSI die and wafers products, which are C1 and C2 for die and W1 and W2 for wafer, respectively. Each die and wafer support dedicated characteristics and probe the electrical parameters within their specifications. Followings are brief information for die and wafer classifications. Please refer to packaged specifications for more information but these parameters are not guaranteed at bare die and wafer. − C1 LEVEL DIE OR W1 LEVEL WAFER The DC parameters are measured by specification for C1 level die or W1 level wafer. The DC parameters measured at 70°C temperature, which called ‘Hot DC Sorting’ Other parameters are not guaranteed and warranted including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical parameters. − C2 LEVEL DIE OR W2 LEVEL WAFER The DC parameters and selected AC parameters are measured with for C2 level die or W2 level wafer. The DC characteristics of C2 die and W2 wafer is tested based on DC specifications of C1 level die and W1 level wafer. The DC and specified AC parameters are tested at 70°C temperature, which called ‘Hot DC & Selective AC Sorting’. Other parameters are not guaranteed and warranted including device reliability. Please refer to qualification report for device reliability and package level datasheets for electrical parameters. C2 level die and W2 level wafer probe following AC parameter. − tRC, tAA, tCO − tWC, tCW PACKAGING Individual device will be packed in anti-static trays. − Chip Trays : A 2-inch square waffle style carrier for die with separate compartments for each die. Com 0 Td ( )Tj 2.40138 0 Td (d)Tj 5.04289r ed 3 EM620FV8B Series Low Power, 256Kx8 SRAM ABSOLUTE MAXIMUM RATINGS * * Stresses greater than those listed above “Absolute 4 EM620FV8B Series Low Power, 256Kx8 SRAM S 6S 28761.8 ki 0 2. M OE DC AND OPERATING CHARACTERISTICS NOTES 1. Typica (8)Tj 6.72397 0 Td ( )s CE 6 MO 5 S SS M6 O 69Tj 6.72,344 0 6523SC MAC938.0I317 1.680(S)Tj /R1O 9.9Td /R191 0 0 Td (0 M 516531.999386 ,1 0 -133.519 -11052j2297 372 .16523S0 T 353.7270r)249.443.241=i 0 2.6827Tj 5.0430i 0 2.4 EM620FV8B Series Low Power, 256Kx8 SRAM VTM3) R12) AC OPERATING CONDITIONS Test Conditions (Test Load and Test Input/Output Reference) Input Pulse Level : 0.4 to 2.2V Input Rise and Fall Time : 5ns Input and Output reference Voltage : 1.5V Output Load (See right) : CL1) = 100pF + 1 TTL CL1) = 30pF + 1 TTL (only 45ns part) 1. Including scope and Jig capacitance 2. R1=3070 ohm, R2=3150 ohm 3. VTM=2.8V CL1) R22) Parameter Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tCO1, tCO2 tOE tLZ1, tLZ2 tOLZ tHZ1, tHZ2 tOHZ tOH 45ns Min 45 10 5 0 0 10 Max 45 45 25 20 15 Min 55 10 5 0 0 10 55ns Max 55 55 25 20 20 Min 70 10 5 0 0 10 70ns Max 70 70 35 25 25 - Unit ns ns ns ns ns ns ns ns ns Parameter Write cycle time Chip select to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to ouput Symbol tWC tCW1, tCW2 tAS tAW tWP tWR 45ns Min 45 45 0 45 35 0 Max 55 45 0 45 40 0 55ns Min Max Min 70 60 0 60 50 0 70ns Max - Unit ns ns ns ns ns ns 6 EM620FV8B Series Low Power, 256Kx8 SRAM tRC R t tR Rt 7 EM620FV8B Series Low Power, 256Kx8 SRAM TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED) tWC Address tCW(2) CS1 tWR(4) tAW tWP(1) WE tAS(3) tDH tDW D Data Valid D g Data in High-Z tWHZ t gh-ed High-Z tOW e Z Data out Data Undefined tWC Ad d edee 1 8 EM620FV8B Series Low Power, 256Kx8 SRAM 9 EM620FV8B Series Low Power, 256Kx8 SRAM DATA RETENTION CHARACTERISTICS Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time NOTES Symbol VDR IDR tSDR tRDR Test Condition ISB1 Test Condition (Chip Disabled) 1) VCC=1.5V, ISB1 Test Condition (Chip Disabled) 1) See data retention wave form Min 1.5 0 tRC Typ2) 0.5 - Max 3.6 - Unit V µA ns 1. See the ISB1 measurement condition of data sheet page 5. 2. Typical value is measured at TA=25oC and not 100% tested. D tSDR Vcc 3.0V Data Retention Mode tRDR 2.2V VDR CS1 GND Vcc 3.0V CS2 VDR 0.4V CS2 < 0.2V CS1 > Vcc-0.2V Data Retention Mode tSDR tRDR 10 EM620FV8B Series Low Power, 256Kx8 SRAM SRAM PART CODING SYSTEM EM X XX X X X XX X X - XX XX 1. EMLSI Memory 2. Product Type 3. Density 9. Package 5. Technology 6. Operating Voltage 1. Memory Component EM --------------------- Memory 2. Product Type 6 ------------------------ SRAM 3. Density 1 ------------------------- 1M 2 ------------------------- 2M 4 ------------------------- 4M 8 ------------------------- 8M 4. Function 0 ----------------------- Dual CS 1 ----------------------- Single CS 2 ----------------------- Multiplexed 3 ------------- Single CS / LBB, UBB(tBA=tOE) 4 ------------- Single CS / LBB, UBB(tBA=tCO) 5 ------------- Dual CS / LBB, UBB(tBA=tOE) 6 ------------- Dual CS / LBB, UBB(tBA=tCO) 5. Technology F ------------------------- Full CMOS 6. Operating Voltage T ------------------------- 5.0V V ------------------------- 3.3V U ------------------------- 3.0V S ------------------------- 2.5V R ------------------------- 2.0V P ------------------------- 1.8V 10. Speed 8. Generation 7. Organization 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 8. Generation Blank ----------------- 1st generation A ----------------------- 2nd generation B ----------------------- 3rd generation C ----------------------- 4th generation D ----------------------- 5th generation E ------------------------n ology ---------------------- y -- 5th genet Ty y -------------------- 11