GLT440L16

G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Features : ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 262,144 words by 16 bits organization. Fast access time and cycle time. Dual CAS Input. Low power dissipation. Read-Modify-Write, RAS -Only Refresh, CAS -Before- RAS Refresh, Hidden Refresh Description : The GLT440L16 is a 262,144 x 16 bit high-performance CMOS dynamic random access memory. The GLT44016 offers Fast Page mode with Extended Data Output, and has both BYTE WRITE and WORD WRITE access cycles via two CAS pins. The GLT440L16 has symmetric address and accepts 512-cycle refresh in 8ms interval. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 512 x 16 bits within a page, with cycle time as short as 14ns. The GLT440L16 is best suited for graphics, and DSP applications requiring high performance memories. and Test Mode Capability. 512 refresh cycles per 8ms. Available in 40-Pin 400 mil SOJ and 40/44 Pin TSOP(II) Single +3.3V±10% Power Supply. All inputs and Outputs are TTL compatible. Extended Data-Out(EDO) Page Mode operation. HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time, (tCAC) 35 35 ns 13 ns 14 ns 45 ns 11 ns 40 40 ns 20 ns 15 ns 75 ns 12 ns 50 50 ns 25 ns 19 ns 90 ns 13 ns G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Pin Configuration : GLT440L16 SOJ Top View TSOP(Type II) Top View Pin Descriptions: Name A0 - A8 RAS UCAS LCAS WE OE Function Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Inputs / Outputs +3.3V Power Supply 0V Supply No Connection DQ1 - DQ16 VCC VSS NC G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- G -LINK Absolute Maximum Ratings* Operating Temperature, TA (ambient) Capacitance* TA=25°C, VCC=3.3V±10%, VSS=0V .....................................-10°C to +70°C Storage Temperature(plastic)....-55°C to +150°C Voltage Relative to VSS............….-1.0V to + 4.6V Short Circuit Output Current......................50mA Power Dissipation......................................1.0W Symbol CIN1 CIN2 COUT Parameter Address Input RAS , LCAS , UCAS , WE , OE GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Typ Max. Unit 3 4 5 4 5 7 pF pF pF Data Input/Output *Note:Operation above Absolute Maximum Ratings can abversely affect device reliability. *Note: Capacitance is sampled and not 100% tested Electrical Specifications l l l CAS means UCAS and LCAS . All voltages are referenced to GND. After power up, wait more than 100µs and then, execute eight CAS -before- RAS or RAS -only refresh cycles as dummy cycles to initialize internal circuit. Block Diagram : OE WE UCAS LCAS RAS RAS C LOCK GENERATOR CAS C LOCK GENERATOR WE C LOCK GENERATOR OE C LOCK GENERATOR V CC V SS Data I/O BUS COLUMN DECODERS REFRESH COUNTER Y 0 - Y8 9 A0 A1 A7 A8 512 × 16 SENSE AMPLIFIERS I/O BUFFER . . ADDRESS BUFFERS AND PREDECODERS X 0 - x8 ROW DECODERS 512 MEMORY ARRAY I /O1 I /O2 I /O3 I /O4 I /O5 I /O6 I /O7 I /O8 I /O9 I /O10 I /O11 I /O12 I /O13 I /O14 I /O15 I /O16 G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK Truth Table: GLT440L16 Function Stanby Read: Word Read: Lower Byte Read: Upper Byte Write: Word(Early Write) Write: Lower Byte (Early) Write: Upper Byte (Early) Read Write EDO-Page- 1st Cycle Mode Read 2nd Cycle EDO-Page- 1st Cycle Mode Write 2nd Cycle EDO-Page- 1st Cycle Mode ReadWrite Hidden Refresh 2nd Cycle Read Write RAS -Only Refresh GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) RAS H L L L L L L L L L L L L CASL H L L H L L H L H→L H→L H→L H→L H→L CASH H L H L L H L L H→L H→L H→L H→L H→L WE X H H H L L L H→L H H L L H→L OE X L L L X X X L→H L L X X L→H ADDRESS High-Z DQs Notes ROW/COL Data Out ROW/COL Lower Byte,Data-Out Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-Out ROW/COL Data-In ROW/COL Lower Byte,Data-In Upper Byte,High-Z ROW/COL Lower Byte,High-Z Upper Byte,Data-In ROW/COL Data-Out,Data-In ROW/COL Data-Out COL Data-Out 1,2 2 2 2 2 1,2 ROW/COL Data-In COL Data-In ROW/COL Data-Out,Data-In L L→H→L L→H→L L H→L H→L L L H L H→L L L H L H→L H H X X L→H L L X X COL Data-Out,Data-In 1,2 2 2 ROW/COL Data-Out ROW/COL Data-In ROW High-Z High-Z CBR Refresh 3 Notes: 1. These READ cycles may also be BYTE READ cycles (either UCAS or LCAS active). 2. These WRITE cycles may also be BYTE READ cycles (either UCAS or LCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active ( UCAS or LCAS ). G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- G -LINK DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC=3.3V±10%, VSS=0V, unless otherwise specified. GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Sym. ILI Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE Standby Current,(TTL) Test Conditions 0V ≤ VIN ≤ 5.5V (All other pins not under test=0V) 0V ≤ Vout ≤ 5.5V Output is disabled (Hiz) tRC = tRC (min.) RAS , UCAS , LCAS at VIH other inputs ≥VSS RAS cycling, UCAS , LCAS at VIH Access Time Min. -10 Typ Max. +10 Unit Notes µA µA ILO ICC1 -10 tRAC = 35ns tRAC = 40ns tRAC = 50ns +10 160 145 125 4 mA 1,2 ICC2 mA ICC3 Refresh Current, RAS -Only tRAC = 35ns tRAC = 40ns tRAC = 50ns tRAC = 35ns tRAC = 40ns tRAC = 50ns tRAC = 35ns tRAC = 40ns tRAC = 50ns 160 145 125 160 145 125 160 145 125 1 mA 2 tRC = tRC (min.) ICC4 Operating Current, EDO Page Mode RAS at VIL, UCAS , LCAS address mA 1,2 cycling:tPC=tPC(min.) ICC5 Refresh Current, CAS Before RAS RAS , UCAS , LCAS mA 1 address cycling: tRC=tRC (min.) RAS ≥VCC-0.2V, UCAS ≥VCC-0.2V, LCAS ≥VCC-0.2V, All other inputs VSS ICC6 Standby Current, (CMOS) mA VCC VIL VIH VOL VOH Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 3.0 -0.3 2.0V IOL = 2mA IOH = -2mA 2.4 3.6 0.8 VCC+0.3 0.4 V V V V V 3 3 Notes: 1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2.ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and EDO Fast Page Mode. 3.Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to –0.3V for a period not to exceed 20ns. All AC parameters are measured with VIL(min.)≥VSS and VIH(max.)≤VCC. AC Characteristics G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK TA = 0°C to 70°C , VCC = 3.3 V ± 10% VIH/VIL = 2.0/0.8V , VOH/VOL = 2.0/0.8V GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) An initial pause of 100 µs and 8 CAS -before- RAS or RAS -only refresh cycles are required after power-up. 35 40 50 Parameter Read or Write Cycle Time Read Modify write Cycle Time RAS Precharge Time RAS Pulse Width Symbol Min. 70 90 25 35 Max. Min. 75 93 25 Max. Min. 90 109 30 Max. Unit ns ns ns Notes tRC tRWC tRP tRAS tRAC tCAC tAA tCLZ tCEZ tRSH tROH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL t 75k 35 11 18 40 100k 40 12 20 50 100k 50 13 25 ns ns ns ns ns 1,2,3 1,5,10 1,5,6 Access Time from RAS Access Time from CAS Access Time from Column Address CAS to Output Low-Z CAS to Output High-Z RAS Hold Time RAS Hold Time Referenced to OE CAS Hold Time CAS Pulse width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time 0 3 10 7 34 6 13 10 5 0 6 0 5 18 25 0 0 0 0 5 5 10 24 17 8 0 3 12 8 34 6 18 13 5 0 8 0 6 20 34 0 0 0 0 6 6 12 28 20 8 0 3 14 9 45 8 19 14 5 0 9 0 7 25 44 0 0 0 0 7 7 13 37 25 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4 4 8,9 7 Row Address Set-Up Time Row Address Hold Time Column Address Set-Up Time Column Address Hold Time Column Address to RAS Lead Time Column Address Hold Time Referenced to RAS AR Read Command Set-Up Time tRCS Read Command Hold Time Referenced to CAS tRCH t Read Command Hold Time Referenced to RAS RRH Write Command Set-Up Time tWCS Write Command Hold Time Write Command Pulse Width Write Command to RAS Lead Time tWCH tWP tRWL G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) AC Characteristics 35 Parameter Write Command to CAS Lead Time Data Set-Up Time Data Hold Time Data Hold Time Referenced to RAS RAS to WE Delay Time CAS to WE Delay Time 40 Min. 12 0 8 36 54 24 32 0 20 22 15 50 5 100k 11 40 100k 12 8 8 3 7 3 8 10 3 3 8 8 8 10 10 50 8 2 50 8 8 10 8 8 3 7 5 3 3 8 8 8 10 10 2 20 59 8 50 Max. Min. 13 0 9 46 64 25 37 0 50 Max. Unit ns ns ns ns ns ns ns ns 30 ns ns ns ns 100k Symbol Min. Max. Notes tCWL tDS tDH tDHR tRWD tCWD tAWD tRPC tCPA tPC tCP tRASP tOEA tOED tOEZ tOEH tDOH tREZ tWEZ tOCH tCHO tOEP tCSR tCHR tT tREF 8 0 5 25 46 23 29 0 Column Address to WE Delay Time RAS to CAS Precharge Time Access Time from CAS Precharge EDO Page Mode Cycle Time 14 45 4 35 EDO Page Mode Read-Modify-write Cycle Time tPRWC CAS Precharge Time (EDO Page Mode) RAS Pulse Width (EDO Page Mode Only) ns ns ns Access Time from OE OE to Data Delay Time OE to Output High-Z OE Command Hold Time 13 5 3 5 3 3 3 8 8 8 8 8 2 8 ns ns ns Data Output Hold after CAS Low RAS to Output High-Z WE to Output High-Z OE to CAS Hold Time CAS Hold Time to OE OE Precharge Time CAS Set-Up Time for CAS –before- RAS Cycle CAS Hold Time for CAS –before- RAS Cycle 8 12 ns ns ns ns ns ns ns Transition Time Refresh Period 50 8 ns ms G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Notes: 1. Measure with a load equivalent to one TTL inputs and 50 pF. 2. Assumes that tRCD ≤ tRCD (max.). If tRCD is greater than tRCD (max.), access time will be tAA dominant. 3. Assumes that tRAD ≤ tRAD (max.). If tRAD is greater than tRCD (max.), access time will be controlled by tCAC. 4. Either tRRH or tRCH must be satisfied for a Read Cycle. 5. Access time is determined by the longest of tCAA, tCAC and tCPA. 6. Assumes that tRAD ≥ tRAD (max.). 7. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC. 8. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. 9. tWCS (min.) must be satisfied in an Early Write Cycle. 10. tDS and tDH are referenced to the latter occurrence of CAS of WE . tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 1.5 ns. G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK Read Cycle tRC tRAS VIH- GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) tRP RAS VIL- tCRP VIH- tCSH tRCD tRSH tCAS tRAD tRAL tASC tCAH COLUMN ADDRESS tCRP CAS VIL- tASR Address V IHV IL- tRAH ROW ADDRESS tAR tRCS VIH- tRCH tRRH WE VIL- tAA VIH- tCEZ tOEZ tOEA OE VIL- tRAC DQ VOHVOL- tCAC tCLZ DATA-OUT Don't Care Early Write Cycle NOTE : DOUT = Open tRC tRP VIH- tRAS RAS VIL- tCSH tCRP VIH- tRCD tCAS tRSH tCRP CAS VIL- VIH- tASR tRAH ROW ADDRESS tRAD tASC tCAH COLUMN ADDRESS tRAL Address VIL- tCWL tRWL tAR VIH- tWCS WE VIL- tWCR tWCH tWP VIH- OE VIL- tDHR tDS VIH- tDH DATA - IN DQ VIL- Don't Care G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Late Write Cycle ( OE Controlled Write) VIHVIL- NOTE : DOUT = Open tRC tRP tRAS RAS tCSH tCRP CAS VIHVIL- tRCD tCAS tRSH tCRP VIH- tASR tRAH ROW ADDRESS tRAD tASC tRAL tCAH COLUMN ADDRESS Address VIL- tCWL tRWL tRCS WE VIHVIL- tWP OE VIHVIL- tOED tDS tOEH tDH COLUMN ADDRESS Don't Care VIH- DQ VIL- Read - Modify - Write Cycle tRC tRP RAS VIHVIL- tRAS tCRP CAS VIHVIL- tRCD tRSH tCAS tCSH tCRP tASR Address VIHVIL- tRAD tASC tCAH COLUMN ADDRESS tRAH ROW ADDR. tAWD tCWD WE VIHVIL- tRWL tCWL tWP OE VIHVIL- tOEA tCLZ tAA tCAC tOED tOEZ tDS tDH VALID DATA-IN Don't Care DQ VI/OHVI/OL- tRAC VALID DATA-OUT G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK Fast Page Read Cycle tRASP VIH- GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) tRP RAS VIL- tPC tCRP VIH- tPC tCAS tCP tRSH tCAS tRCD tCAS tCP CAS VIL- tRAD tCSH tASR tRAH tASC tCAH COLUMN ADDRESS tASC tCAH tASC tCAH Address VIHVIL- ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS tRCS VIH- tRCH tRCS tRCS tRRH tRCH WE VIL- tCAC tOEA tCAC tOEA VIH- OE VIL- tRAC tCLZ DQ VIHVIL- tAA tAA tOFF tCLZ tOEZ tAA tOFF tCLZ tOEZ tOFF tOEZ VALID DATA-UOT VALID DATA-UOT VALID DATA-UOT Don't Care Fast Page Write Cycle VIH- NOTE : DOUT = Open tRASP t RP tRHCP tPC tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tRAD tASR tRAH tASC tCSH tCAH COLUMN ADDRESS RAS VIL- VIH- CAS VIL- tASC tCAH tASC COLUMN ADDRESS tCAH Address VIHVIL- ROW ADDR. COLUMN ADDRESS tWCS VIH- tWCH tWP tCWL tWCS tWP tWCH tWCS tWCH tWP WE VIL- tCWL tCWL tRWL VIH- OE VIL- tDS VIH- tDH VALID DATA-IN tDS VALID DATA-IN tDS tDS VALID DATA-IN tDS DQ VIL- Don't Care G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK Fast Page Mode Late Write Cycle tRASP VIH- GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) t RP tRHCP RAS VIL- tCSH tCRP CAS VIHVIL- t PC tCAS tCP tCAS tCP tRSH tCAS tCRP tRCD tRAD tASR Address VIHVILROW ADDR. tCAH tASC COLUMN ADDRESS tRAH tASC COLUMN ADDRESS tCAH tASC COLUMN ADDRESS tRAL tCAH tRCS VIH- tCWL tWP tRCS tCWL tWP tRCS tCWL tRWL tWP WE VIL- tOEH VIH- tOEH tOEH OE VIL- tOED VIH- tDS tDH tOED tDS Hi-Z tDH tOED tDS Hi-Z tDH Hi-Z DQ VIL- VALID DATA-IN VALID DATA-IN VALID DATA-IN Don't Care Fast Page Read - Modify - Write Cycle tRASP VIH- tRP RAS tCSH tRSH tCAS VIL- tRCD VIH- tCAS tCP tCRP CAS VIL- tASR VIH- tRAD tRAH tASC tCAH tASC COL. ADDR. COL. ADDR. tPRWC tRAL tCAH Address VIL- ROW ADDR. tRCS VIH- tCWL tCWD tAWD tRWD tWP tCWD tAWD tCPWD tRWL tCWL tWP WE VIL- tOEH tDH tOED tOEZ tDS tOEA tCAC tAA tOED tOEZ tDH tDS VIH- OE tOEA tCAC tAA tRAC VIL- VI/OH- DQ VI/OL- tCLZ VALID DATA-OUT VALID DATA-IN tCLZ VALID DATA-OUT VALID DATA-IN Don't Care G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 - G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) CAS Before RAS Refresh Cycle tRC tRAS V IH- tRC tRP tRAS tRP RAS V IL- tCSR CAS V IHV IL- tCHR tRPC tCSR tCHR tRPC tCRP RAS -Only Refresh Cycle tRC tRAS RAS VIHVIL- tRC tRP tRAS tRP tCRP CAS VIHVIL- tRPC tCRP tASR VIH- tRAH ROW tASR tRAH ROW Address VIL- Hidden Refresh Cycle ( Read ) tRC tRAS RAS VIHVIL- tRC tRP tRAS tRP tCRP VIH- tRCD tRSH tCHR CAS VIL- tRAD tASR Address VIHVIL- tRAL tASC COLUMN ADDRESS tCAH tCAH ROW ADDRESS tRCS VIH- tWHR WE VIL- tAA tOEA VIH- OE VIL- tCAC tRAC DQ VIHVIL- tCLZ tOEZ DATA-OUT tOFF OPEN Don't Care G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 13 - G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) Hidden Refresh Cycle ( Write ) VIHVIL- NOTE : DOUT =Open tRC tRAS tRP tRAS tRC tRP RAS tCRP VIH- tRCD tRSH tCHR CAS VIL- tRAD tASC Address VIHVIL- tCAH tASC COLUMN ADDRESS tCAH ROW ADDRESS tWCS VIH- tWCH tWP WE VIL- VIH- OE VIL- tDS DQ VIHDATA-IN tDH VIL- Don't Care G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 14 - G -LINK GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) CAS - Before RAS Refresh Counter Test Cycle tRAS RAS VILVIHCAS VILVIH- tRP tCSR tCHR tCPT tRSH tCAS tRAL tCAH tASC AddressVIHVILCOLUMN ADDRESS Read Cycle VIHWE VIL- tWRP tWRH tAA tCAC tRCS tOEA tCLZ tOEZ VALID DATA-OUT tRRH tRCH OE VIL- VIH- tCEZ DQ VOL- VOH- Write Cycle VIHWE VIL- tWRP tWRH tWCS tWP tRWL tCWL tWCH OE VIL- VIH- tDS VIHDQ VIL- tDH VALID DATA-IN OPEN tRCS Read-Modify-Write WE VILVIH- tAWD tCWD tCAC tAA tOEA tOED tCLZ tOEZ tCWL tRWL tWP OE VIL- VIH- tDH tDS DQ VI/OL- VI/OH- VALID DATA-OUT VALID DATA-IN Don't Care G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 15 - G -LINK Ordering Information Part Number GLT440L16-35J4 GLT440L16-40J4 GLT440L16-50J4 GLT440L16-35TC GLT440L16-40TC GLT440L16-50TC GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) SPEED POWER FEATURE 35ns 40ns 50ns 35ns 40ns 50ns Normal Normal Normal Normal Normal Normal EDO EDO EDO EDO EDO EDO PACKAGE 40L 400mil SOJ 40L 400mil SOJ 40L 400mil SOJ 44L 400mil TSOP 44L 400mil TSOP 44L 400mil TSOP Parts Numbers (Top Mark) Definition : GLT 4 40 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note L 16 - 35 J4 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 30 : 30ns 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP VOLTAGE Blank : 5V L : 3.3V M : 2.5V N : 2.1V Note : CÙ CDROM , HÙ HDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 16 - G -LINK Package Information 40/44 Lead Thin Small Outline Package SOJ GLT440L16 256K X 16 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT Aug. 2000 (Rev.1.1) 40/44 Lead Thin Small Outline Package TSOP(Type II) G-Link Technology Corporation 2701Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 17 -