EiceDRIVER™ S ENSE
1EDI2010AS
High voltage IGBT driver for auto moti ve applicatio ns
Single channel isolated driver
Hardware description
A12 Step
Features
•
Single-channel IGBT-driver
•
On-chip galvanic insulation
•
Support of existing IGBT technologies up to 1200 V
•
Low propagation delay and minimal PWM distortion
•
Support of 5-V logic levels (primary side)
•
Supports both negative and zero-volt VEE2 supply voltage
•
16-bit standard SPI interface (up to 2 MBaud) with daisy chain support (primary side)
•
Enable input pin (primary side)
•
Pseudo-differential inputs for critical signals (primary side)
•
Power-on reset pin (primary side)
•
Debug mode
•
Internal pulse suppressor
•
Fully programmable active clamping inhibit signal (secondary side)
•
Fully programmable two-level turn-on (TTON)
•
Fully programmable two-level turn-off (TTOFF)
•
8-bit ADC with programmable offset and gain, and a flexible trigger mechanism
•
Emulated digital channel
•
Programmable desaturation monitoring
•
Overcurrent protection with programmable threshold
•
Automatic emergency turn-off in failure case
•
Undervoltage supervision of 5 V and 15 V supplies
•
Programmable UVLO2 and DESAT thresholds for MOSFET usage
•
Safe internal state machine
•
Internal lifesign watchdog
•
Weak turn-on
•
NFLTA and NFLTB notification pins for fast system response time (primary side)
•
Individual error and status flags readable via SPI
Datasheet
www.infineon.com/cms/en/product/power
1
Rev 2.1
2021-12-09
EiceDRIVER™ SENSE
1EDI2010AS
•
Compatible to EiceBoost family
•
36-pin PG-DSO-36 green package
•
Green Product (RoHS compliant)
Potential applications
•
Inverters for automotive hybrid electric vehicles (HEV) and electric vehicles (EV)
•
High-voltage DC/DC converter
•
Industrial drive
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The 1EDI2010AS is a high-voltage IGBT gate driver designed for motor drives above 5 kW. The 1EDI2010AS is
based on Infineon’s Coreless Transformer (CLT) technology, providing galvanic insulation between lowvoltage and high-voltage domains. The device has been designed to support IGBT technologies up to 1200 V.
The 1EDI2010AS can be connected on the low-voltage side (“primary” side) to 5-V logic. A standard SPI
interface allows the logic to configure and control the advanced functions implemented in the driver.
On the high-voltage side (“secondary” side), the 1EDI2010AS is dimensioned to drive an external booster
stage. Short propagation delays and controlled internal tolerances lead to minimal distortion of the PWM
signal.
The 1EDI2010AS supports advanced functions (such as two-level turn-on, two-level turn-off, etc.), that can be
controlled and configured via a standard SPI interface.
The internal 8-bit ADC (SAR) with programmable gain and offset enables the sensing of the DC link voltage, the
phase voltage, or of the temperature sensor located on the power module (such as NTC, temperature diode,
etc.). The digitalized value can be read via the SPI interface on the primary side. The ADC thus enables
significant cost savings at the system level, since it removes the need for discrete isolation ICs.
The 1EDI2010AS can be used optimally with Infineon’s 1EBN100XAE EiceDRIVER™ Boost booster stage family.
Type
Package
Ordering code
1EDI2010AS
PG-DSO-36
SP001299836
Datasheet
2
Rev 2.1
2021-12-09
EiceDRIVER™ SENSE
1EDI2010AS
Table of Contents
1
1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.2.3
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.4.1
1.4.4.2
1.4.4.3
1.4.4.4
1.4.4.5
1.4.5
1.4.5.1
1.4.5.2
1.4.5.3
1.4.5.4
1.4.5.5
1.4.5.6
1.4.6
1.4.6.1
1.4.6.2
1.4.6.3
1.4.7
1.4.8
1.4.9
1.4.9.1
1.4.9.2
1.4.9.3
1.4.9.4
1.4.10
1.4.11
1.4.11.1
1.4.11.2
1.4.11.3
1.4.12
1.4.13
1.4.13.1
1.4.13.2
Datasheet
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Primary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Secondary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pull devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PWM input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI data integrity support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Operation modes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Activating the device after a reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Activating the device after a Class A or Class B event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Driver functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Switching sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Passive clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fault notifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EN signal pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Internal supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Lifesign watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Oscillator monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Memory supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Hardware failure behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reset events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operation in Configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Static configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Dynamic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Delay calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Low-latency digital channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3
Rev 2.1
2021-12-09
EiceDRIVER™ SENSE
1EDI2010AS
1.4.13.3
Boundary checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.3.1
2.4
2.4.1
2.4.2
2.5
2.5.1
2.5.2
2.5.3
Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supervision overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection functions: Category A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection functions: Category B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power supply voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection functions: Category C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shoot-through protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection functions: Category D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation in Verification mode and Weak Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Weak turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal clock supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.1.1
3.1.2
3.1.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Primary register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Secondary registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Read/write address ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4
4.1
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
5.4.10
5.4.11
5.4.12
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary I/O electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Secondary I/O electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-latency digital channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error-detection timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Datasheet
4
52
52
53
53
56
57
58
58
59
59
60
61
61
61
63
106
106
107
108
109
109
110
111
113
115
118
119
119
120
121
122
123
Rev 2.1
2021-12-09
EiceDRIVER™ SENSE
1EDI2010AS
Functional description
1
Functional description
1.1
Introduction
The 1EDI2010AS is an advanced single-channel IGBT driver that can also be used for driving power MOS
devices. The device has been developed in order to optimize the design of high performance automotive
inverters.
The device is based on Infineon’s coreless transformer technology and consists of two chips separated by
galvanic isolation. The low-voltage (primary) side can be connected to standard 5-V logic. The high-voltage
(secondary) side is in the DC-link voltage domain.
Internally, the data transfers are ensured by two independent communication channels. One channel is
dedicated to transferring only the ON and OFF information of the PWM input signal. This channel is
unidirectional (from the primary to the secondary side). Because this channel is dedicated to the PWM
information, latency time and PWM distortion are minimized. The second channel is bidirectional and is used
for all other data transfers (for example, status information).
The 1EDI2010AS supports advanced functions, such as two-level turn-on and two-level turn-off, in order to
optimize the switching behavior of the IGBT. Furthermore, it supports several protection functions such as
DESAT, overcurrent protection, etc.
Datasheet
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1EDI2010AS
Functional description
1.2
Pin configuration and functionality
1.2.1
Pin configuration
1
VEE2
GND1
36
2
TON
IREF1
35
3
VCC2
VCC1
34
4
TOFF
INSTP
33
5
DESAT
6
INP
32
GATE
REF0
31
7
GND2
EN
30
8
IREF2
NRST/RDY
29
9
VEE2
GND1
28
10
OCP
NFLTA
27
11
OCPG
NFLTB
26
12
VREG
ADCT
25
13
DEBUG
SDO
24
14
DACLP
NCS
23
15
AIP
SDI
22
16
AIN
SCLK
21
17
DIO2
DIO1
20
18
VEE2
GND1
19
Figure 1
EiceSENSE pin configuration
Table 1
Pin configuration
Pin
number
Symbol
I/O
Voltage class
Function
1,9,18
VEE2
Supply
Supply
Negative power supply1)
2
TON
Output
15 V secondary Turn-on output
3
VCC2
Supply
Supply
4
TOFF
Output
15 V secondary Turn-off output
5
DESAT
Input
15 V secondary Desaturation protection input
6
GATE
Input
15 V secondary Gate monitoring input
7
GND2
Ground
Ground
Ground
8
IREF2
Input
5 V secondary
External reference input
10
OCP
Input
5 V secondary
Overcurrent protection
11
OCPG
Ground
Ground
Ground for the OCP function
12
VREG
Output
5 V secondary
Reference output voltage
13
DEBUG
Input
5 V secondary
Debug input
14
DACLP
Output
5 V secondary
Active clamping disable output
Datasheet
Positive power supply
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Functional description
Table 1
Pin configuration (cont’d)
Pin
number
Symbol
I/O
Voltage class
Function
15
AIP
Input
5 V analog
secondary
ADC positive analog input
16
AIN
Input
5 V analog
secondary
ADC negative analog input
17
DIO2
Input/output 5 V secondary
Digital I/O
19, 28, 36
GND1
Ground
Ground2)
20
DIO1
Input/output 5 V primary
Digital I/O
21
SCLK
Input
5 V primary
SPI serial clock input
22
SDI
Input
5 V primary
SPI serial data input
23
NCS
Input
5 V primary
SPI chip select input (low-active)
24
SDO
Output
5 V primary
SPI serial data output
25
ADCT
Input
5 V primary
ADC trigger input
26
NFLTB
Output
5 V primary
Fault B output (low-active, open drain)
27
NFLTA
Output
5 V primary
Fault A output (low-active, open drain)
29
NRST/RDY
Input/output 5 V primary
Reset input (low-active, open drain). This
signal notifies that the device is “ready”.
30
EN
Input
5 V primary
Enable input
31
REF0
Ref. ground
Ground
Reference ground for signals INP, INSTP, EN
32
INP
Input
5 V primary
Positive PWM input
33
INSTP
Input
5 V primary
Monitoring PWM input
34
VCC1
Supply input Supply
Positive power supply
35
IREF1
Input
External reference input
Ground
5 V primary
1) All VEE2 pins must be connected together.
2) All GND1 pins must be connected together.
Datasheet
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1EDI2010AS
Functional description
1.2.2
Pin functionality
1.2.2.1
Primary side
GND1
Ground connection for the primary side.
VCC1
5-V power supply for the primary side (referring to GND1).
INP
Non-inverting PWM input of the driver. The internal structure of the pad makes the IC robust against glitches.
An internal weak pull-down resistor to VREF0 drives this input to low-state in case the pin is floating.
INSTP
Monitoring PWM input for shoot-through protection. The internal structure of the pad makes the IC robust
against glitches. An internal weak pull-down resistor to VREF0 drives this input to the low state in case the pin
is floating.
REF0
Reference ground signal for the signals INP, INSTP, and EN. This pin must be connected to the ground signal
of the logic issuing those signals.
EN
Enable input signal. This signal allows the logic on the primary side to turn off and deactivate the device. An
internal weak pull-down resistor to VREF0 drives this input to the low state in case the pin is floating.
NFLTA
Open-drain output signal used to report major failure events (Class A event). In case of an error event, NFLTA
is driven to the low state. This pin must be connected externally to VCC1 with a pull-up resistance.
NFLTB
Open-drain output signal used to report major failure events (Class B event). In case of an error event, NFLTB
is driven to the low state. This pin must be connected externally to VCC1 with a pull-up resistance.
SCLK
Serial clock input for the SPI interface. An internal weak pull-up device to VCC1 drives this input to high state in
case the pin is floating.
SDO
Serial data output (push-pull) or the SPI interface.
SDI
Serial data input for the SPI interface. An internal weak pull-up device to VCC1 drives this input to high state in
case the pin is floating.
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Functional description
NCS
Chip select input for the SPI interface. This signal is low-active. An internal weak pull-up device to VCC1 drives
this input to the high state in case the pin is floating.
IREF1
Reference input of the primary chip. This pin must be connected to VGND1 via an external resistor.
NRST/RDY
Open-drain reset input. This signal is low-active. When a valid signal is received on this pin, the device is put
into its default state. This signal is also used as a “ready” notification. A high level on this pin indicates that the
primary chip is functional.
DIO1
I/O for the digital channel. Depending of the chosen configuration of the device, this pin can be an input or an
output (push-pull). An internal weak pull-down resistor to VGND1 drives this input to the low state in case the
pin is floating.
ADCT
ADC trigger input. An internal weak pull-down device to VGND1 drives this input to the low state in case the pin
is floating.
1.2.2.2
Secondary side
VEE2
Negative power supply for the secondary side, referring to VGND2.
VCC2
Positive power supply for the secondary side, referring to VGND2.
GND2
Reference ground for the secondary side.
DESAT
Desaturation protection input pin. The function associated with this pin monitors the VCE voltage of the IGBT.
The detection threshold is programmable. An internal pull-up resistor to VCC2 drives this signal to the high level
in case it is floating.
OCP
Overcurrent protection input pin. The function associated with this pin monitors the voltage across a sensing
resistance located on the auxiliary path of a current-sense IGBT. An internal weak pull-up resistor to the
internal 5-V reference drives this input to the high state in case the pin is floating.
OCPG
Overcurrent protection ground.
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Functional description
TON
Output pin for turning on the IGBT.
TOFF
Output pin for turning off the IGBT.
GATE
Input pin used to monitor the IGBT gate voltage.
DEBUG
Debug input pin. This pin is latched at power-up. When a high level is detected on this pin, the device enters a
special mode where it can be operated without SPI interface. This feature is provided for development
purpose only. This pin should normally be tied to VGND2. An internal weak pull-down resistor to VGND2 drives this
input to the low state in case the pin is floating.
IREF2
Reference input of the secondary chip. This pin must be connected to VGND2 via an external resistor.
VREG
Reference output voltage. This pin must be connected to an external capacitance to VGND2.
DACLP
Output pin used to disable the active clamping function of the booster.
DIO2
I/O for the digital channel. Depending of the chosen configuration of the device, this pin can be an input or an
output (push-pull). An internal weak pull-down resistor to VGND2 drives this input to the low state in case the
pin is floating.
AIP
ADC positive analog input.
AIN
ADC negative analog input.
1.2.2.3
Pull devices
Some of the pins are connected internally to pull-up or pull-down devices. This is summarized in Table 2.
Table 2
Internal pull devices
Signal
Device
INP
Weak pull-down to VREF0
INSTP
Weak pull-down to VREF0
EN
Weak pull-down to VREF0
SCLK
Weak pull-up to VCC1
SDI
Weak pull-up to VCC1
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Functional description
Table 2
Internal pull devices (cont’d)
Signal
Device
NCS
Weak pull-up to VCC1
ADCT
Weak pull-down to VGND1
DIO1
Weak pull-down to VGND1
DESAT
Weak pull-up to VCC2
DIO2
Weak pull-down to VGND2
OCP
Weak pull-up to 5-V internal reference
DEBUG
Weak pull-down to VGND2
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Functional description
1.3
Block diagram
IREF1
OSC1
WDG
WDG
OSC2
IREF2
VCC1
GND2
Power
supply
VEE2
GND1
Power
Supply
INP
EN/FEN
INSTP
VCC2
VREG
PWM
input
stage
DEBUG
Start-stop
osc
REF0
NCS
Primary
SPI
interface
Output
stage
switching
control
Secondary
SDI
logic
TON
logic
SDO
TOFF
GATE
DACLP
SCLK
OCP
OCP
NFLTA
OCPG
NFLTB
DESAT
ADCT
DESAT
AIP
ADC
NRST/RDY
AIN
DIO1
Figure 2
Datasheet
DIO2
Block diagram
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Functional description
1.4
Functional block description
1.4.1
Power supplies
On the primary side, the 1EDI2010AS needs a single 5-V supply source VCC1 for proper operation. This makes
the device compatible with most of the microcontrollers available for automotive applications.
On the secondary side, the 1EDI2010AS needs two power supplies for proper operation:
•
The positive power supply VCC2 is typically set to 15 V (referring to VGND2).
•
Optionally, a negative supply VEE2 (typically set to -8 V referring to VGND2) can be used. If no negative supply
is needed, VEE2 must be connected to VGND2.
Undervoltage monitoring on VCC1 and VCC2 is performed continuously during operation of the device (see
Chapter 2.3.1).
A 5-V supply for the digital domain on the secondary side is generated internally (present at the VREG pin).
1.4.2
Clock domains
The clock system of the 1EDI2010AS is based on three oscillators defining each a clock domain:
•
One RC oscillator (OSC1) for the primary chip.
•
One RC oscillator (OSC2) for the secondary chip excepting the output stage.
•
One start-stop oscillator (SSOSC2) for the output stage on the secondary side.
The two RC oscillators are running constantly. They are also monitored constantly, and large deviations from
the nominal frequency are identified as a system failure (Class B event, see Chapter 1.4.9.2).
The start-stop oscillator is controlled by the PWM command.
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Functional description
1.4.3
PWM input stage
The PWM input stage generates the turn-on and turn-off commands for the secondary side from the external
signals INP, INSTP, and EN. The general structure of the PWM input block is shown Figure 3.
VCC1
EN
inhibit_act.
en_valid
Logic
Inhibit time
generation
INSTP
Validity
ch eck
INP
pwm_cmd
REF0
Figure 3
PWM input stage
The signals INP, INSTP, and EN are pseudo-differential, in the sense that they are not referenced to the
common ground GND1 but to the REF0 signal. This is intended to make the device more robust against
ground-bouncing effects.
Note:
Glitches shorter than tINPR1 occurring on signal INP are filtered internally.
Note:
Pulses on INP shorter than tINPPD might be distorted or suppressed.
The 1EDI2010AS supports only non-inverted PWM signals. When a high level on the INP pin is detected while
signals INSTP and EN are valid, a turn-on command is issued to the secondary chip. A low level on INP issues
a turn-off command to the secondary chip.
The EN signal can inhibit turn-on commands received on INP. A valid EN signal is required in order to have
turn-on commands issued to the secondary chip. If an invalid signal is provided, the PWM input stage
constantly issues turn-off commands to the secondary chip. The functionality of the EN signal is detailed in
Chapter 1.4.8.
Note:
After an invalid-to valid transition of the EN signal, a minimum delay of tINPEN should be inserted
before turning INP on.
As shown in Figure 4, the INSTP signal provides shoot-through protection (STP) to the system. When the
signal on the INSTP pin is at the high level, the internal signal inhibit_act is activated. The inhibition time
is defined as the pulse duration of inhibit_act. It corresponds to the pulse duration of the INSTP signal to
which a minimum dead time is added. During the inhibition time, rising edges of the INP signal are inhibited.
The PSTAT2.STP bit is set for the duration of the inhibition time.
The deadtime is programmable through the PCFG2.STPDEL bit field.
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1EDI2010AS
Functional description
INSTP
Dead time
inhibit_act
INP
Inhibition time
pwm_cmd
Figure 4
STP: Inhibition time definition
During the inhibition time, the pwm_cmd signal is not forced to low. It means that if the device is already
turned on when INSTP is high, it stays on until the signal on the INP pin goes low. This is shown in Figure 5.
INSTP
Dead time
inhibit_act
Inhibited
edge
INP
pwm_cmd
Inhibition time
Figure 5
STP: Example of operation
When a condition occurs that inhibits a rising edge of the INP signal, an error notification is issued. See
Chapter 2.4.1 for details.
Note:
Datasheet
The failure notification via the PER.STPER bit is filtered internally for times shorter than one OSC1
clock cycle. No notification is raised but the INP signal may be delayed.
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Functional description
1.4.4
SPI interface
This chapter describes the functionality of the SPI block.
1.4.4.1
Overview
The standard SPI interface implemented on the 1EDI2010AS is compatible with most of the microcontrollers
available for automotive and industrial applications. The following features are supported by the SPI
interface:
•
Full-duplex bidirectional communication link
•
SPI slave mode (only)
•
16-bit frame format
•
Daisy-chain capability
•
MSB first
•
Parity check (optional) and parity-bit generation (LSB)
The SPI interface of the 1EDI2010AS provides a standardized bidirectional communication interface to the
main microcontroller. From the architectural point of view, it fulfills the following functions:
•
Initialization of the device
•
Configuration of the device (static and runtime)
•
Reading of the status of the device (static and runtime)
•
Operation of the verification modes of the device
The purpose of the SPI interface is to exchange data which have relaxed timing constraints compared to the
PWM signals (from the point of view of the motor-control algorithm). The IGBT switching behavior is, for
example, controlled directly by the PWM input. Similarly, critical application failures requiring fast reaction
are notified on the primary side via the feedback signals NFLTA, NFLTB, and NRST/RDY.
In order to minimize the complexity of the application and to optimize the microcontroller’s resources, the
implemented interface supports daisy-chaining. Several (typically six) 1EDI2010AS devices can be combined
into a single SPI bus.
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Functional description
1.4.4.2
General operation
The SPI interface of the 1EDI2010AS supports full-duplex operation. The interface relies on four
communication signals:
•
NCS: (Not) chip select
•
SCLK: Serial clock
•
SDI: Serial data in
•
SDO: Serial data out
The SPI interface of the 1EDI2010AS supports slave operation only. An SPI master (typically, the main
microcontroller) is connected to one or several 1EDI2010AS devices, forming an SPI bus. Several bus
topologies are supported.
A regular SPI bus topology can be used where each of the slaves is controlled by an individual chip-select
signal (Figure 6). In this case, the number of slaves on the bus is limited only by the application’s constraints.
SCLK
Master
SCLK
SDO
SDI
SDI
SDO
NCS1
NCS
Slave 1
NCS2
SCLK
...
SDI
NCSn
Slave 2
...
SDO
NCS
...
...
...
SCLK
SDI
Slave n
SDO
NCS
Figure 6
SPI regular bus topology
In order to simplify the layout of the PCB and to reduce the number of pins used on the microcontroller’s side,
a daisy-chain topology can also be used. The chain’s length is not limited by the 1EDI2010AS itself. A possible
topology is shown Figure 7.
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1EDI2010AS
Functional description
SCLK
Master
SCLK
SDO
SDI
SDI
SDO
NCS
NCS
Slave 1
SCLK
SDI
Slave 2
...
SDO
NCS
...
...
SCLK
...
SDI
Slave n
SDO
NCS
Figure 7
SPI daisy-chain bus topology
Physical layer
The SPI interface relies on two shift registers:
•
An output shift register, reacting on the rising edges of SCLK.
•
An input shift register, reacting on the falling edges of SCLK.
When the NCS is inactive, the signals on the SCLK and SDI pins are ignored. The SDO output is in tristate.
When NCS is activated, the output shift register is updated internally with the value requested by the previous
SPI access.
On each rising edge of the SCLK signal (while NCS is active), one bit of the output shift register is serially shifted
out on the SDO pin (MSB first). On each falling edge of the clock pulse, the data bit available at the SDI input
is latched and serially shifted into the input shift register.
When NCS is deactivated, the SPI logic checks how many rising and falling edges of the SCLK signal have been
received. In case both counts differ and / or are not a multiple of 16, an SPI error is generated. If no error was
generated, the SPI block checks the validity of the received 16-bit word. In case of invalid data, an SPI error is
generated. If no error is detected, the data is decoded by the internal logic.
The NCS signal is active low.
Input debouncing filters
The input stages of the SDI, SCLK, and NCS signals include each a debouncing filter which filters glitches and
noise out of the input signals.
The SDI and SCLK input signals are analyzed at each edge of the internal clock derived from OSC1. If the same
external signal value is sampled three times consecutively, the signal is considered valid and is processed by
the SPI logic. Otherwise, the transition is considered as glitch and is discarded.
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Functional description
The NCS input signal is sampled at a rate corresponding to the period of the internal clock derived from OSC1.
If the same external signal value is sampled two times consecutively, the signal is considered valid and is
processed by the SPI logic. Otherwise, the transition is considered a glitch and is discarded.
1.4.4.3
Definitions
Command
A command is a high-level instruction issued by the SPI master which aims at generating a specific reaction in
the addressed slave. The command is physically translated into a request message by the SPI master. The
correct reception of the request message by the SPI slave leads to a specific action inside the slave and to the
emission of an answer message by the slave.
Example: The READ command leads to the transfer of the value of the specified register from the device to the
SPI master.
Word
A word is a 16-bit sequence of data bits.
Transfer
A transfer is defined as the SPI data transmissions (in both directions) occurring between a falling edge of NCS
and the next consecutive rising edge of NCS.
Request message
A request message is a word issued by the SPI master that is addressing a single slave. A request message
relates to a specific command.
Answer message
An answer message is a well-defined word issued by a single SPI slave as a response to a request message.
Transmit frame
A transmit frame is a sequence of one or several words sent by the SPI master within one SPI transfer. In
regular SPI topologies, a transmit frame is in practice identical to a data word. In daisy-chain topologies, a
transmit frame is a sequence of data words belonging to different request messages.
Receive frame
A receive frame is a sequence of one or several words received by the SPI master within one SPI transfer. In
regular SPI topologies, a receive frame is in practice identical to a data word. In daisy-chain topologies, a
receive frame is a sequence of data words belonging to different answer messages.
The SPI protocol supported by the 1EDI2010AS is based on the request-answer principle. The master sends a
defined request message to which the slave replies with the corresponding answer message (Figure 8,
Figure 9). Due to the nature of the SPI interface, the answer message is shifted, compared to the request
message, by one SPI transfer. It means, for example, that the last word of the answer message n is being
transmitted by the slave while the master is sending the first word of request message n+1.
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Functional description
Transfer
...
Inactive
Chip select
NCS
Active
Word i
Transmit frame
Master
serial output
(seen at SDI)
...
RM1
...
...
RM2
...
...
...
RMn
Wn
...
...
AM2
...
...
...
...
...
AMn
...
Request message for slave i
Receive frame
Master
serial input
(seen at SDO)
...
...
...
...
AM1
...
...
Answer message of slave i
Figure 8
Request-answer principle – daisy-chain topology
Transfer
...
Inactive
Chip select
NCS for
slave i
Master
serial output
(seen at SDI)
Active
Transmit frame
Request message
RM1
RM2
...
...
RMn
Word
Master
serial input
(seen at SDO)
...
AM1
AM2
AMn
Answer message
Receive frame
Figure 9
...
Request-answer principle – regular topology
The first word transmitted by the device after power-up is the content of the PSTAT register.
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Functional description
1.4.4.4
1.4.4.4.1
SPI data integrity support
Parity bit
By default, the SPI link relies on an odd-parity protection scheme for each transmitted or received 16-bit word
in SPI messages. The parity bit corresponds to the LSB of the 16-bit word. Therefore, the effective payload of
a 16-bit word is 15 data bits (plus one parity bit). The parity-bit check (on the received data) can be disabled
by clearing the PCFG.PAREN bit. In that case, the parity bit is considered as “don’t care”. The generation of the
parity bit by the driver for transmitted words cannot be disabled (but can be considered as “don’t care” by the
SPI master).
Note:
1.4.4.4.2
For fixed-value commands (ENTER_CMODE, ENTER_VMODE, EXIT_CMODE, NOP), the value of the
parity bit must be correct even if parity checking is disabled. Otherwise, an SPI error is generated.
SPI error
When the device is unable to process an incoming request message, an SPI error is generated: The received
message is discarded by the driver, the PER.SPIER bit is set, and the erroneous message is answered with an
error notification (LMI bit set).
Several failures generate an SPI error:
•
A parity error is detected on the received word.
•
An invalid data word format is received (for example, not a 16-bit word).
•
A word is received which does not corresponding to a valid request message.
•
A command is received which cannot be processed. For example, the driver receives in Active mode a
command which is only valid in other operating modes. Another typical example is a read access to the
secondary side while the previous read access is not yet completed (device “busy”).
•
An SPI access to an invalid address.
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Functional description
1.4.4.5
Protocol description
1.4.4.5.1
Command catalog
Table 3 gives an overview of the command catalog supported by the device. The full description of the
commands and of the corresponding request and answer messages is provided in the following sections.
Table 3
SPI command catalog
Acronym
Short description
Valid in mode
ENTER_CMODE
Enters Configuration mode.
OPM0, OPM1
ENTER_VMODE
Enters Verification mode.
OPM2
EXIT_CMODE
Leaves Configuration mode to enter Configured mode.
OPM2
READ
Reads the register value at the specified address.
All
NOP
Triggers no action in the device (equivalent to a “nop”).
All
WRITEH
Updates the most significant byte of the internal write buffer. All
WRITEL
Updates the least significant byte of the internal write buffer All (with restrictions)
and copies the complete contents of the buffer into the
addressed register. The write buffer is cleared afterwards.
An overview of the commands is given Figure 10.
Message
ENTER_CMODE
ENTER_VMODE
EXIT_CMODE
NOP
READ
WRITEH
WRITEL
Figure 10
0
0
0
0
0
0
1
Command
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
1
0
0
0
A4
0
A4
0
0
0
1
A3
1
A3
0
0
1
0
A2
0
A2
0
1
0
0
A1
D15
A1
1
0
0
0
A0
D14
A0
Data
0
1
0
0
0
D13
D7
0
0
1
0
1
D12
D6
0
0
0
1
0
D11
D5
0
0
0
0
1
D10
D4
0
0
0
0
0
D9
D3
P
0
0
0
0
X
X
X
0
0
0
0
1
D8
D2
SPI commands overview
1.4.4.5.2
Word convention
In order to simplify the description of the SPI commands, the following conventions are used (Table 4).
Table 4
Word convention
Symbol
Value
Va(REGISTER)
Value of register REGISTER
PB
Parity bit
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