Data Sheet, Rev. 1.32, Nov. 2005
ADM5120P/PX
Di
st
rib
ut
io
n
wi
th
ND
A
Network Processor
Version AB
Communications
Edition 2005-11-09
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ADM5120P/PX
CONFIDENTIAL
ADM5120P/PX Network Processor
CONFIDENTIAL
Revision History: 2005-11-09, Rev. 1.32
Previous Version:
Page
Subjects (major changes since last revision)
31-Oct-2005: Updated Registers and deleted reference to 200 MHz support
12-Nov-2005:Updated Table 7-”MII Management”
Trademarks
ABM®, AOP®, BlueMoon®, ConverGate®, C166®, DuSLIC®, FALC®, GEMINAX®, INCA®, IOM®, IPVD®, Isac®,
IWE®, IWORX®, MuSLIC®, OCTALFALC®, OCTAT®, QUADFALC®, SCOUT®, SEROCCO®, S-GOLD®, SICOFI®,
SIEGET®, SMARTI®, SOCRATES®, VINETIC®, WDTC®, 10BaseS® are registered trademarks of Infineon
Technologies AG.
ACE™, ARCOFI™, ASM™, ASP™, BlueNIX™, DigiTape™, DUALFALC™, EasyPort™, E-GOLD™,
E-GOLDlite™, EPIC™, IPAT-2™, ELIC™, IDEC™, ITAC™, M-GOLD™, SCT™, S-GOLD2™, S-GOLD3™,
MUSAC™, POTSWIRE™, QUAT™, S-GOLDlite™, SICAT™, SIDEC™, SLICOFI™, VDSLite™, 10BaseV™,
10BaseVX™ are trademarks of Infineon Technologies AG.
Microsoft® and Visio® are registered trademarks of Microsoft Corporation. Linux® is a registered trademark of
Linus Torvalds. FrameMaker® is a registered trademark of Adobe Systems Incorporated. APOXI® is a registered
trademark of Comneon GmbH & Co. OHG. PrimeCell®, RealView®, ARM® are registered trademarks of ARM
Limited. OakDSPCore®, TeakLite® DSP Core, OCEM® are registered trademarks of ParthusCeva Inc.
IndoorGPS™, GL-20000™, GL-LN-22™ are trademarks of Global Locate. ARM926EJ-S™, ADS™, Multi-ICE™
are trademarks of ARM Limited.
Data Sheet
3
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1
1.1
1.2
1.2.1
1.2.1.1
1.2.1.2
1.2.1.3
1.2.1.4
1.2.2
1.2.3
1.3
1.3.1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ASIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
10
10
10
11
11
11
11
12
12
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.1.10
2.1.11
2.1.12
2.1.13
2.1.14
2.1.15
2.1.16
2.1.17
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram for P-FQFP-208-10 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADM5120P/PX Network Media Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock for Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External CS/INT/Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
14
15
16
16
17
18
19
21
22
22
23
24
25
25
27
27
3
3.1
3.1.1
3.2
3.2.1
ADM5120P/PX System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Mapping Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System and Interrupt Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
30
31
33
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
Main Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4Kc CPU Core Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Endianness Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coprocessor CP0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
40
40
40
41
41
Data Sheet
4
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table of Contents
4.2.5
4.2.6
4.2.7
4.3
4.3.1
4.3.1.1
4.3.2
4.3.2.1
Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cache System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EJTAG Debug Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
42
42
42
43
FPI Bus Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
46
5
5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.2
5.2.2.1
5.2.2.2
5.3
5.3.1
5.3.1.1
MultiPort Memory Controller (MPMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Wait Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Memory Read Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Static Memory Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Memory Controller Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Generic SDRAM Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPMC Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MPMC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.1.14
6.2
6.2.1
6.2.1.1
6.2.2
6.2.2.1
6.2.2.2
6.3
6.3.1
Ethernet Switch Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hashing Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Learning Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Half Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packet Priority and Class of Service (CoS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Table Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bandwidth Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MII Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Send Descriptors Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptors Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch Control Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
100
100
100
100
100
100
101
101
101
101
101
102
102
102
102
103
104
104
105
105
106
107
110
7
7.1
7.2
7.2.1
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMBA APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
167
167
167
168
Data Sheet
5
49
49
49
49
49
49
50
51
52
52
53
54
54
57
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table of Contents
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
168
168
168
169
169
169
170
172
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.3.1
8.3.1.1
8.3.1.2
8.3.2
8.4
8.4.1
USB 1.1 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 1.1 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operational Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Control Status Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Control Status Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180
180
180
180
181
181
181
182
182
182
183
185
187
190
193
195
9
9.1
9.2
9.3
9.3.1
9.3.2
9.3.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
211
211
211
212
212
215
216
10
10.1
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Plastic Quad Flat Package (P-FQFP) 208-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Data Sheet
6
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Data Sheet
ADM5120P/PX Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Diagram for P-FQFP-208-10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ADM5120P/PX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Main Processor Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read with Two Clock Delay for Read Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Read with Two Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Asynchronous Page Mode Read with 2 Wait State and 1 Sequential Wait State . . . . . . . . . . . . . 51
Bus Turnaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Write with Zero Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Write with Two Wait State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Write with Two Clock Delay for Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
UART block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Block Diagram of Infineon USB 1.1 Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
DMA Operation in Host Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Interrupt IN/OUT Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Active Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Write Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Memory Bus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Memory Bus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
P-FQFP-208-10 (Plastic Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
7
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Data Sheet
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Network Media Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock for Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LED Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
MII Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SDRAM Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General Purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External CS/INT/Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Regulator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Registers Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Endian Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Module Base Address - BIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Registers OverviewRegisters Overview from Chapter BIU Registers . . . . . . . . . . . . . . . . . . . . . 43
Module Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Registers OverviewRegisters Overview from Chapter FPI Bus Register Description . . . . . . . . 46
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Address Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Connection between ADM5120P/PX and MAC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Registers Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Registers Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Registers Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Registers Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Registers Access Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Registers Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
8
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 50
Table 51
Table 52
Table 53
Data Sheet
List of Tables
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bus Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Bus Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
211
212
215
216
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
1
Product Overview
Product Overview
The following chapter gives an overview of the ADM5120P/PX.
1.1
Overview
ADM5120P/PX is a high performance, highly integrated, and highly flexible SOC (System-On-Chip) that facilitates
the combined functions of a SOHO/SME Gateway, NAT Router, Print Server and VPN Gateway in one package.
ADM5120P/PX enables the sharing of IP-based broadband services throughout the home/office using wired
computers, entertainment equipment, printers, and other intelligent devices.
The ADM5120P/PX is the environmentally friendly 'green' package version.This is in compliance with Directive
2002/95/EC of the European Parliament and of the Council of 27 January 2003 on the restriction of the use of
certain hazardous substances in electrical and electronic equipment
Internally, the ADM5120P/PX ASIC consists of a high performance (227 MIPS) embedded MIPS CPU, an
embedded switch engine, a 10/100M PHY, an embedded USB host, and interfaces for UART, SDRAM and Flash.
The following diagram illustrates a system configuration that uses the supported functions/facilities of
ADM5120P/PX
1.2
Features
The following describes the features of the ADM5120P/PX
1.2.1
ASIC Features
Description of ASIC features:
1.2.1.1
Processor
Processor features:
•
•
•
•
MIPS 4Kc CPU
Embedded cache, 8 Kbyte I-cache, 8 Kbyte D-cache
Embedded memory management unit (MMU) – 32-entry TLB, organized as 16 entry pairs
175 MHz/227 MIPS
1.2.1.2
Networking
Networking features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
6 ports
IEEE 802.3 Fast Ethernet
5 auto-MDIX (auto-crossover) twisted paired LAN interfaces, embedded 10/100M PHY
1 MII interface
Flexible WAN port selection
Embedded switch engine
Embedded Data-buffer/Address-look-up table
Look-up table read/write-able
MAC layer security
MAC clone solution
MAC filtering, Bandwidth control
Class of Services (CoS) with two priority levels
Shared dynamic data buffer management, embedded SSRAM
Port grouping VLAN (overlap-able)
TCP/IP accelerator
Data Sheet
10
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
1.2.1.3
Product Overview
Memory Interface
Memory features:
•
•
•
•
•
•
•
SDRAM
Two bank support (2 chip select pins)
Each bank can support -- 1M x 32 up to 32M x 32bit (128M-byte)
Flash
NOR Flash boot
NOR Flash: one banks support (1 chip select pin)
NOR Flash: support – 1M x 8-bit, up to 1M x 32-bit (4M-byte)
1.2.1.4
•
•
•
•
•
•
•
•
•
System
UART interface
4 GPIO pins
USB 1.1 host
Clock source
25 MHz crystal for 10/100
48 MHz crystal for USB
0.18 µ CMOS process
1.8 V/3.3 V dual power
PQFP
1.2.2
Software Features
Description of software features:
•
•
•
•
•
•
•
•
•
•
•
•
•
Linux/Nucleus Real-Time OS
Linux-based and Nucleus-based turn key support
Telnet
IEEE 802.3 Ethernet Driver
RS232 Driver for Console User Interface
DHCP Server/Client
PPP over Ethernet (PPPoE)
Network Address Translation (NAT) for IP Address Mapping/Sharing/Security
DNS Proxy
Simple Network Time Protocol (SNTP)
Firewall
Web-Based Configuration: WEB and HTTP
TFTP upload/download
1.2.3
Typical Applications
The typical applications of the ADM5120P/PX are:
•
•
•
IEEE 802.3 SOHO/SME Gateway
NAT Router
Print Server (through USB1.1)
Data Sheet
11
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Product Overview
SDRAM
WAN
Memory Bus
ADM5120P
LAN*4
USB
Vinetic
Printer
Figure 1
ADM5120P/PX Application
1.3
Conventions
Flask
SLIC
RJ11
The convention descriptions are described below:
1.3.1
Data Lengths
qword = 64 bits
dword = 32 bits
word = 16 bits
byte = 8 bits
nibble = 4 bits
Data Sheet
12
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
2
Interface Description
2.1
Pin Description by Function
Interface Description
ADM5120P/PX pins are categorized into one of the following groups:
•
•
•
•
•
•
•
•
•
•
•
Section 2.1.4, ADM5120P/PX Network Media Connection
Section 2.1.5, Clock for Network
Section 2.1.6, LED
Section 2.1.7, MII Management
Section 2.1.8, Memory Bus
Section 2.1.9, SDRAM Control Signals
Section 2.1.10, UART
Section 2.1.11 JTAG
Section 2.1.12, General Purpose I/O (GPIO)
Section 2.1.13, USB
Section 2.1.14, External CS/INT/Wait
2.1.1
•
•
•
Section
Section 2.1.15, Power and Ground
Section 2.1.16, Regulator Interface
Section 2.1.17, Miscellaneous
Note: All default settings are 0.
Data Sheet
13
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
2.1.2
Interface Description
Pin Diagram for P-FQFP-208-10 Package
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
ADM5120P
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VCCRG
VCCBIAS
RTX
GNDRG
VREF
CONTROL
GNDPL L
VCCPLL
XO
XI
DVSS
GCRS
GCOL
G_TXD[3]
G_TXD[2]
G_TXD[1]
G_TXD[0]
VDD
T XC
G_TXE
VSS
G_RXC
DVDD
G_RXDV
G_RXD[0]
G_RXD[1]
G_RXD[2]
G_RXD[3]
MDC
MDIO
NC
DVSS
DATA[16]
DVDD
DATA[17]
DATA[18]
DATA[19]
DATA[31]
VSS
DATA[30]
VDD
DATA[29]
DATA[28]
DATA[20]
DVSS
DATA[21]
DVDD
DATA[22]
DATA[23]
DATA[27]
DATA[26]
DATA[25]
208PQFP
VSS
VSS
DATA[0]
DATA[1]
DATA[2]
DATA[3]
DATA[11]
VDD
DVDD
DATA[10]
DVSS
DVSS
DATA[9]
DATA[8]
DATA[4]
DATA[5]
DATA[6]
VSS
VDD
DATA[7]
DQM[2]
DQM[3]
ADDR[3]
ADDR[2]
DVDD
ADDR[1]
VSS
DVSS
ADDR[0]
ADDR[4]
ADDR[5]
ADDR[6]
ADDR[7]
ADDR[10]
VDD
VSS
ADDR[8]
ADDR[9]
ADDR[11]
ADDR[12]
SDRAM_CS0_N
DVDD
CLK_OUT
DVSS
RAS_N
CAS_N
SDRAM_CS1_N
VDD
DQM[1]
DQM[0]
DATA[24]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
DVSS
LED2[1]
DVDD
LED2[0]
LED1[2]
LED1[1]
LED1[0]
LED0[2]
LED0[1]
LED0[0]
VSS
CLK48M
VDD
AG33
DMNS1
DPLS1
AV33
DPLS0
DMNS0
VCCAD
RXN4
RXP4
GNDT
TXN4
TXP4
VCCA2
VCCA2
TXP3
TXN3
GNDR
RXP3
RXN3
VCCAD
RXN2
RXP2
GNDR
TXN2
TXP2
VCCA2
VCCA2
TXP1
TXN1
GNDR
RXP1
RXN1
VCCAD
RXN0
RXP0
GNDT
TXN0
TXP0
VCCA2
DATA[12]
DATA[13]
DATA[14]
DATA[15]
ADDR[13]
ADDR[14]
VSS
DVSS
ADDR[15]
VDD
DVDD
ADDR[16]
ADDR[17]
ADDR[18]
ADDR[19]
WE_N
F_OE_N
F_CS0_N
UDCD
UDSR
UCTS
DVSS
UDI0
DVDD
UDO0
UDI1
UDO1
VSS
VDD
TRST_N
TDI
TDO
TMS
DVSS
TCK
DVDD
LED4[2]
LED4[1]
LED4[0]
LED3[2]
LED3[1]
LED3[0]
LED2[2]
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
TEST
RESET_N
VDD
CLKO25M
VSS
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
Figure 2
Data Sheet
Pin Diagram for P-FQFP-208-10
14
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Interface Description
2.1.3
Abbreviations
Table 1
Abbreviations for Pin Type
Abbreviations
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
AO
Output. Analog levels.
AI/O
Input or Output. Analog levels.
PWR
Power
GND
Ground
MCL
Must be connected to Low (JEDEC Standard)
MCH
Must be connected to High (JEDEC Standard)
NU
Not Usable (JEDEC Standard)
NC
Not Connected (JEDEC Standard)
Table 2
Abbreviations for Buffer Type
Abbreviations
Description
Z
High impedance
PU1
Pull up, 10 kΩ
PD1
Pull down, 10 kΩ
PD2
Pull down, 20 kΩ
TS
Tristate capability: The corresponding pin has 3 operational states: Low, high and highimpedance.
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC
Open Collector
PP
Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP
Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST
Schmitt-Trigger characteristics
TTL
TTL characteristics
A
Analog Differential pair or Analog PAD
Data Sheet
15
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Interface Description
2.1.4
ADM5120P/PX Network Media Connection
Table 3
Network Media Connection
Ball No.
Name
Pin
Type
Buffer
Type
Function
178
RXP4
AI
A
187
RXP3
Receive Pair
Differential data is received on these pins.
191
RXP2
200
RXP1
204
RXP0
177
RXN4
188
RXN3
190
RXN2
201
RXN1
203
RXN0
181
TXP4
AO
A
184
TXP3
Transmit Pair
Differential data is transmitted on these pins.
194
TXP2
197
TXP1
207
TXP0
180
TXN4
185
TXN3
193
TXN2
198
TXN1
206
TXN0
2.1.5
Clock for Network
Table 4
Clock for Network
Ball No.
Name
Pin
Type
Buffer
Type
Function
9
XOI
O
A
Crystal Clock Output
25 MHz crystal output
10
XI
I
A
External Clock Input
25 MHz crystal input
3
RTX
I
A
Reference Voltage
Data Sheet
16
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
2.1.6
LED
Table 5
LED
Interface Description
Ball No.
Name
Pin
Type
Buffer
Type
Function
141
LED4_2
O
PD
142
LED4_1
143
LED4_0
LED 4
LED4_2 state, default = 1010, duplex/colLED4_1 state,
default = 0101, speedLED4_0 state, default = 1001,
link/activity
144
LED3_2
O
PD
145
LED3_1
146
LED3_0
LED 3
LED3_2 state, default = 1010, duplex/colLED3_1 state,
default = 0101, speedLED3_0 state, default = 1001,
link/activity
147
LED2_2
O
PD
158
LED2_1
160
LED2_0
LED 2
LED2_2 state, default = 1010, duplex/colLED2_1 state,
default = 0101, speedLED2_0 state, default = 1001,
link/activity
161
LED1_2
O
PD
162
LED1_1
163
LED1_0
LED 1
LED1_2 state, default = 1010, duplex/colLED1_1 state,
default = 0101, speedLED1_0 state, default = 1001,
link/activity
164
LED0_2
O
PD
165
LED0_1
166
LED0_0
LED 0
LED0_2 state, default = 1010, duplex/colLED0_1 state,
default = 0101, speedLED0_0 state, default = 1001,
link/activity
Note: Registers, not hardware pins, control the LED display. There are 3 LEDs per port, and they can be
programmed to any state, the programming information can be found in Table 6 below.
Table 6
LED Program
Function
State
GPIO_in (or GPIO_disable)
0000
GPIO_output_flash
0001
GPIO_output_1
0010
GPIO_output_0
0011
Link (steady)
0100
Speed (steady)
0101
Duplex (steady)
0110
Activity (flash)
0111
Collision (flash)
1000
Link+activity
1001
Duplex+collision
1010
10 M_link+activity
1011
100 M_link+activity
1100
Reserved
1101
Data Sheet
17
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 6
Interface Description
LED Program (cont’d)
Function
State
Reserved
1110
Reserved
1111
2.1.7
MII Management
Table 7
MII Management
Ball No.
Name
Pin
Type
Buffer
Type
Function
29
MDC
O
PP
Clock Input MDIO
Runs at a 1 MHz frequency clock for MII port autonegotiation result monitoring.
14
TXD_3
O
15
TXD_2
16
TXD_1
17
TXD_0
Transmit Data
All internal pull down.
1. The force speed, duplex & flow control can be set by
switch control register (B+14)
2. The reverse MII can only be set by switch control register
(B+30)
20
TXE
O
Transmit Enable
Internal pull down.
24
RXDV
I
TTL/PU
Receive Data Valid
Internal pull up.
28
RXD_3
I
TTL/PU
27
RXD_2
Receive Data
Internal pull up.
26
RXD_1
25
RXD_0
22
RXC
I
TTL/PD
Receive Clock
Internal pull down.
19
TXC
I
TTL/PD
Transmit Clock
Internal pull down.
12
CRS
I
TTL/PD
Carrier Sense
Internal pull down.
13
COL
I
TTL/PD
Collision
Internal pull down.
30
MDIO
BI
PD
Internal Pull Down
Bi-directional serial pin used to write and read from the
registers of the device.
Data Sheet
18
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
2.1.8
Memory Bus
Table 8
Memory Bus
Interface Description
Ball No.
Name
Pin
Type
Buffer
Type
Function
38
DATA_31
BI
PD
40
DATA_30
42
DATA_29
Data Bus 31-0
Internal pull down. Data bus for SDRAM, flash memory,
and external device.
43
DATA_28
50
DATA_27
51
DATA_26
52
DATA_25
54
DATA_24
49
DATA_23
48
DATA_22
46
DATA_21
44
DATA_20
37
DATA_19
36
DATA_18
35
DATA_17
33
DATA_16
108
DATA_15
107
DATA_14
106
DATA_13
105
DATA_12
98
DATA_11
95
DATA_10
92
DATA_9
91
DATA_8
85
DATA_7
88
DATA_6
89
DATA_5
90
DATA_4
99
DATA_3
100
DATA_2
101
DATA_1
102
DATA_0
Data Sheet
19
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 8
Interface Description
Memory Bus (cont’d)
Ball No.
Name
Pin
Type
Buffer
Type
Function
119
ADDR_19
O
PD
Address Bus 19
Address bus for SDRAM, flash memory, and external
device.
Internal pull down. Pull down = Little Endian. (default)
118
ADDR_18
117
ADDR_17
116
ADDR_16
113
ADDR_15
110
ADDR_14
109
ADDR_13
Address Bus 13
Default value: 0
0B
PHY separate power on disable
1B
PHY separate power on enable
65
ADDR_12
Address Bus 12
0B
BGA package(Default)
1B
208 PQFP package
66
ADDR_11
Address Bus 11-5
Address Bus 18-17
Internal pull down. Can be pulled up and down as following:
00B boot in 8-bit mode (Flash memory) (default)
01B boot in 16-bit mode
10B boot in 32-bit mode
11B Reserved
Address Bus 16-14
Test mode purpose. Normal mode = 000(Default)
71
ADDR_10
67
ADDR_9
68
ADDR_8
72
ADDR_7
73
ADDR_6
74
ADDR_5
75
ADDR_4
82
ADDR_3
81
ADDR_2
Address Bus 2
0B
Enable AutoMDIX
1B
Disable AutoMDIX (Default)
79
ADDR_1
Address Bus 1
Default value: 0B
0B
NAND boot disable
NAND boot enable
1B
76
ADDR_0
Address Bus 0
Default value: 0B
0B
Normal operation
1B
Simulation mode
Data Sheet
Address Bus 4-3
Can be pulled up and down as following: PLL frequency
setting.
00B 175 MHz (Default)
01B Reserved
1XB Reserved
20
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Interface Description
2.1.9
SDRAM Control Signals
Table 9
SDRAM Control Signals
Ball No.
Name
Pin
Type
Buffer
Type
Function
62
CLK_OUT
O
TS
Clock Out
SDRAM clock, the frequency is set by ADDR_4:3
Note: 1=pull up, 0=pull down
00D
01D
1XB
87.5 MHz (Default)
Reserved
Reserved
121
F_OE_N
O
PP
Output Enable for External Memory
Output enable for external memory banks, active low.
120
WE_N
O
PP
Write Enable for External Memory
Write Enable for external memory banks and SDRAM.
122
F_CS0_N
O
PP
Chip Select for External Memory
Chip select for external memory, like flash, bank0, active
low.
60
RAS_N
O
PP
Raw Address Strobe
Raw address strobe, active low.
64
SD_RAM_CS0_N O
PP
SDRAM Chip Select 0
SDRAM chip select 0.
59
CAS_N
O
PP
Column Address Strobe
Column address strobe, active low.
58
SD_RAM_CS1_N O
PP
SDRAM Chip Select 1
SDRAM chip select 1.
83
DQM_3
PD
Data Mask Output to SDRAM
84
DQM_2
56
DQM_1
55
DQM_0
Data Sheet
O
21
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
2.1.10
UART
Table 10
UART
Interface Description
Ball No.
Name
Pin
Type
Buffer
Type
Function
123
UDCD
I
PD
Data Carrier Detect
UART0 Data carrier detect (modem status input), active
low.
124
UDSR
Data Set Ready
UART0 Data set ready (modem status input), active low.
125
UCTS
Clear to Send
UART0 clear to send (modem status input), active low.
127
UDI0
Receive Serial Data Input
UART0 receive serial data input, Internal pull down.
129
UDO0
O
Transmit Serial Data Output
UART0 transmit serial data output.
130
UDI1
I
Receive Serial Data Input
UART1 receive serial data input, Internal pull down.
131
UDO1
O
Transmit Serial Data Output
UART1 transmit serial data output.
2.1.11
JTAG
Table 11
JTAG
Ball No.
Name
Pin
Type
Buffer
Type
Function
139
TCK
I
PD
Test Clock
JTAG test clock, Internal pull down.
137
TMS
136
TDO
O
Test Data Out
JTAG test data out.
135
TDI
I
Test Data In
JTAG test data in, Internal pull down.
134
TRST_N
I
Data Sheet
Test Mode Select
JTAG test mode select, Internal pull down.
TTL
Asynchronous Reset
JTAG asynchronous reset (active low).
22
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Interface Description
2.1.12
General Purpose I/O (GPIO)
Table 12
General Purpose I/O (GPIO)
Ball No.
Name
Pin
Type
Buffer
Type
Function
151
GPIO_3
BI
PD
150
GPIO_2
BI General Purpose I/O Pin
GPIO_3:0 are internal pull down.
149
GPIO_1
148
GPIO_0
Data Sheet
23
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
2.1.13
USB
Table 13
USB
Interface Description
Ball No.
Name
Pin
Type
Buffer
Type
Function
171
DMNS1
BI
A
Data- of USB Port1
Differential data bus conforming to the USB 1.1.
172
DPLS1
Data+ of USB Port1
Differential data bus conforming to the USB 1.1.
175
DMNS0
Data- of USB Port0
Differential data bus conforming to the USB 1.1.
174
DPLS0
Data+ of USB Port0
Differential data bus conforming to the USB 1.1.
168
CLK48M
Data Sheet
I
TTL
USB Clock Input
24
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Interface Description
2.1.14
External CS/INT/Wait
Table 14
External CS/INT/Wait
Ball No.
Name
Pin
Type
Buffer
Type
Function
148
WAIT
I
TTL
WAIT
WAIT is available in switch control register GPIO_conf2, bit
CSX0 and CSX1 and EW. When CSX is active and MPMC
is programmable then wait_state will time-out, then check
the WAIT if high, then complete the access if low, then wait
until WAIT goes high.
150
INTX0
I
149
CSX0
O
TS
External Chip Select 0
External chip select 0, active low, available if en_csx0_intx0
is enabled in the switch control register GPIO_conf2 bit[4]
CSX0.
151
CSX1
O
TS
External Chip Select 1
External chip select 1, active low, available if
en_csx1_intx1is enabled in the switch control register
GPIO_config2 (B+BC), bit[5].
Buffer
Type
Function
2.1.15
Power and Ground
Table 15
Power and Ground
Ball No.
Name
18, 41, 57,
70, 86, 97,
114, 133,
154, 169
VDD
A
Positive Power for Digital Core, 1.8 V
23, 34, 47,
63, 80, 96,
115, 128,
140, 159
DVDD
A
Positive Power for I/O, 3.3 V
182, 183,
195, 196,
208
VDDTS2
A
Positive Power for Analog Circuitry, 1.8 V
176, 189,
202
VCCAD
A
Positive Power for Analog Circuitry, 3.3 V
Data Sheet
Pin
Type
External Interrupt Input 0
External interrupt input 0, active high, available if
en_csx0_intx0 enable in the switch control register
GPIO_config2 (B+BC), bit[4].
25
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 15
Ball No.
Interface Description
Power and Ground (cont’d)
Buffer
Type
Function
7, 11, 21, 32, VSS
39, 45, 53,
61, 69, 78,
77, 87, 93,
94, 103, 104,
111, 112,
126, 132,
138, 156,
157, 167
A
GND for Digital Circuit
205, 199,
192, 186,
179
VSSA
A
GND for Analog Circuitry
8
VCCPLL
A
Power for Phase Lock Loop, 1.8 V
1
VCCRG
A
Power for Regulator, 3.3 V
2
VCCBIAS
A
Power for BIAS, 3.3 V
4
GNDRG
A
Ground
173
AV33
A
Power for USB PHY, 3.3 V
170
AG33
A
Power for USB GND
Data Sheet
Name
Pin
Type
26
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Interface Description
2.1.16
Regulator Interface
Table 16
Regulator Interface
Ball No.
Name
Pin
Type
Buffer
Type
Function
5
VREF
AI
A
Reference Voltage Input
This pin is used as the reference voltage for the regulator
and generates the 1.8 V output from the 3.3 V power
source.
6
CONTROL
A0
A
FET Control Output
2.1.17
Miscellaneous
Table 17
Miscellaneous
Ball No.
Name
Pin
Type
Buffer
Type
Function
152
TEST
I
TTL/PD
Test Pin
This pin is for test purposes and should be connected to
GND for normal operation.
153
RESET_N
I
TTL
System Reset
Active low will initialize the chip to default state.
155
CLKO25M
O
PP
25MHz clock output
31
NC
NC
Data Sheet
No connection
27
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
3
ADM5120P/PX System
ADM5120P/PX System
Figure 3 shows the blocks of ADM5120P/PX. The blocks are broken down into:
•
•
•
•
•
•
MIPS 4Kc
Multi port memory controller
USB 1.1 host controller
UART controller
Ether switch
– SW2CPU DMA: this block handles the TX/RX packets from/to the CPU
– Embedded data buffer
– Embedded link table/MC table/addr. table
– 802.3MAC and DMA
10/100 DSP PHY
embedded
MC table
embedded
link table
embedded data buffer
Arbitor/memory control
/ BIST
embedded
addr. table
MIPS 4Kc
with MMU
Arbitor/ link control / BIST
internal memory bus
TX/RX
MAC
TX/RX
MAC
TX/RX
MAC
DSP
DSP
DSP
DSP
DSP
10/100
auto
MDIX
PHY
10/100
auto
MDIX
PHY
10/100
auto
MDIX
PHY
10/100
auto
MDIX
PHY
10/100
auto
MDIX
PHY
Figure 3
ADM5120P/PX Block Diagram
3.1
System Memory Map
AHB
external chip-select
flash memory
SDRAM
MII
multi-port
memory controller
USB
1.1
host
bridge
APB
UART
i/f
UART
i/f
UART
TX/RX
MAC
UART
TX/RX
MAC
USB
TX/RX
MAC
SW2CPU
DMA
USB
port
DMA
TP
port
DMA
TP
port
DMA
TP
port
DMA
TP
port
DMA
TP
port
DMA
Figure 4 shows the system memory allocation. The following lists a detailed reference for each allocation:
•
•
•
Boot address is located in SRAM_0, for detailed information refer to Chapter 5.2.1 Static memory controller
– The address is fixed at 1FC0-0000H and the maximum size is 4 Mbyte. The data-width is pin setting and
register readable. The size is programmable.
For external IO, ext_IO_0 and ext_IO_1 are also the generic SRAM space, refer to Chapter 5.2.1 Static
memory controller
For SRAM_0, ext_IO_0 and ext_IO_1 the address and data width relation are
– Byte access, address = [20:0], max size = 2 Mbytes
Data Sheet
28
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
•
•
•
•
•
•
ADM5120P/PX System
– 16-bit access, address = [21:1] (shift A0 out), max size = 4 Mbytes
– 32-bit access, address = [22:2] (shift A0, A1 out), max size = 8 Mbytes
– Use DQM to select the bytes
SDRAM_0 is a generic SDRAM space, for detailed information refer to Chapter 5.2.2 Dynamic memory
controller
MPMC is the Multi Port Memory controller which includes both the Static and the Dynamic memory controller.
For detailed information refer to Chapter 5 MPMC.
USB 1.1 host controller, refer to the Chapter 8 USB
Switch part is Ether Switch which support 6 switch ports and one CPU DMA port. For detailed information refer
to Chapter 6 Switch
There are two serial ports UART_0 and UART_1, refer to Chapter 7 UART.
INTC is an interrupt controller, for detailed information refer to Chapter 3.2
Data Sheet
29
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Figure 4
System Memory Map
3.1.1
Memory Mapping Notes
ADM5120P/PX System
The following describes the memory mapping in detail:
Data Sheet
30
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
3.2
ADM5120P/PX System
System and Interrupt Registers Description
The following chapter describes both the system and the interrupt Registers.
Table 18
Registers Address Space
Module
Base Address
End Address
Note
Interrupt Control
1220 0000H
1220 0024H
–
Table 19
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
IRQS
Interrupt Request Status
00H
33
IRQRS
Interrupt Request Raw Status
04H
34
IRQE
Interrupt Request Enable
08H
34
IRQEC
Interrupt Request Enable Clear
0CH
35
Res_0
Reserved 0
10H
36
INT_M
Interrupt Mode
14H
36
FIQ_S
Fast Interrupt Request Status
18H
36
IRQ_TS
Interrupt Request Test Source
1CH
37
IRQSS
Interrupt Request Source Sel
20H
38
INT_L
Interrupt Level
24H
38
The register is addressed wordwise.
Data Sheet
31
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 20
Mode
ADM5120P/PX System
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
Basic Access Types
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read/write
virtual
rwv
Physically, there is no new register in
the generated register file. The real
readable and writable register resides
in the attached hardware.
Register is read and writable by SW (same
as rw type register)
read
r
Register is written by HW (register
Value written by SW is ignored by HW; that
between input and output -> one cycle is, SW may write any value to this field
delay)
without affecting HW behavior
read only
ro
Same as r type register
Same as r type register
read virtual
rv
Physically, there is no new register in
the generated register file. The real
readable register resides in the
attached hardware.
Value written by SW is ignored by HW; that
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
write
w
Register is written by software and
affects hardware behavior with every
write by software.
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
write virtual
wv
Physically, there is no new register in Register is writable by SW (same as w type
register)
the generated register file. The real
writable register resides in the attached
hardware.
read/write
hardware
affected
rwh
Register can be modified by hardware
and software at the same time. A
priority scheme decides, how the value
changes with simultaneous writes by
hardware and software.
Table 21
Registers Clock Domains
Clock Short Name
Description
–
–
Data Sheet
Register can be modified by HW and SW,
but the priority SW versus HW has to be
specified.
SW can read the register.
32
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
3.2.1
ADM5120P/PX System
Interrupt Control Register Map
The interrupt controller supports level sensitivity. The external input level can be programmed as active high or
low.
Interrupt register description:
Interrupt Request Status
IRQS
Interrupt Request Status
Offset
00H
Reset Value
0H
5HV
5HV
,, 8, 8, 8,
6 6 6 7,
UR
UR
UR UR UR UR UR
Field
Bits
Res
31:10
SWI
9
ro
Switch Interrupt status after mask
Switch interrupt, refer to switch registers offset 0xB0 and 0xB4 for more
detail.
Res
8:5
ro
Reserved
II0
4
ro
Internal Interrupt 0 status after mask
Internal interrupt 0, refer to switch registers offset 0xBC bit[4] for more
detail. pin GPIO 2 is the source.
UIS
3
ro
USB Interrupt Source status after mask
UIS1
2
ro
UART1 Interrupt Source status after mask
UIS0
1
ro
UART0 Interrupt Source status after mask
TI
0
ro
Timer Interrupt status after mask
Timer interrupt, refer to switch registers offset 0xF0 and 0xF4 for more
detail.
Data Sheet
Type
6:
,
Description
Reserved
33
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
ADM5120P/PX System
Interrupt Request Raw Status
IRQRS
Interrupt Request Raw Status
Offset
04H
Reset Value
0H
5HV
6:
,5
5HV
,, 8, 8, 8, 7,
5 65 6
6
5
UR
UR
UR
UR UR UR UR UR
Field
Bits
Type
Description
Res
31:10
ro
Reserved
SWIR
9
ro
Switch Interrupt Raw status
The Switch interrupt status before masking. refer to switch registers offset
0xB0 and 0xB4 for more detail.
Res
8:5
ro
Reserved
II0R
4
ro
Internal Interrupt 0 Raw status
Internal interrupt 0, refer to switch registers offset 0xBC bit[4] for more
detail. pin GPIO 2 is the source.
UISR
3
ro
USB Interrupt Raw Status
UIS1R
2
ro
UART1 Interrupt Raw status
UIS0R
1
ro
UART0 Interrupt Raw status
TIR
0
ro
Timer Interrupt Raw status
Timer interrupt, refer to switch registers offset 0xF0 and 0xF4 for more
detail.
Interrupt Request Enable
IRQE
Interrupt Request Enable
Offset
08H
Reset Value
0H
5HV
6:
,(
5HV
,, 8, 8, 8, 7,
( 6( 6
6
(
UR
UZ
UZ
UZ UZ UZ UZ UZ
Field
Bits
Type
Description
Res
31:10
ro
Reserved
Not Applicable.
Data Sheet
34
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
ADM5120P/PX System
Field
Bits
Type
Description
SWIE
9
rw
Switch Interrupt Enable
The enable register is used to mask the switch interrupt source.
0B
No effect
1B
Enable the interrupt and allow the interrupt request to MIPS
Res
8:5
rw
Reserved
II0E
4
rw
Internal Interrupt 0 Enable
The enable register is used to mask the GPIO 2 interrupt source.
0B
No effect
1B
Enable the interrupt and allow the interrupt request to MIPS
UISE
3
rw
USB Interrupt Enable
The enable register is used to mask the USB interrupt source.
0B
No effect
1B
Enable the interrupt and allow the interrupt request to MIPS
UIS1E
2
rw
UART1 Interrupt Enable
The enable register is used to mask the UART 1 interrupt source.
0B
No effect
1B
Enable the interrupt and allow the interrupt request to MIPS
UIS0E
1
rw
UART0 Interrupt Enable
The enable register is used to mask the UART 0 interrupt source.
0B
No effect
1B
Enable the interrupt and allow the interrupt request to MIPS
TIE
0
rw
Timer Interrupt Enable
The enable register is used to mask the Timer interrupt source. refer to
B+F0 and B+F4.
0B
No effect
1B
Enable the interrupt and allow the interrupt request to MIPS
Interrupt Request Enable Clear
IRQEC
Interrupt Request Enable Clear
Offset
0CH
Reset Value
0H
5HV
,54(&
UZ
Field
Bits
Res
31:10
IRQEC
9:0
Data Sheet
Type
Description
Reserved
Not Applicable.
rw
IRQ Enable Clear 9:0
This clears the bits of the IRQ_enable.
0B
No effect
1B
Clear the corresponding bit of IRQ_enable
35
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
ADM5120P/PX System
Reserved 0
Res_0
Reserved 0
Offset
10H
Reset Value
0H
5HVB
Field
Bits
Res_0
31:0
Type
Description
Reserved
Not Applicable.
Interrupt Mode
INT_M
Interrupt Mode
Offset
14H
Reset Value
0H
5HV
,170
UZ
Field
Bits
Res
31:10
INTM
9:0
Type
Description
Reserved
Not Applicable.
rw
INT Mode 9:0
The interrupt type of the interrupt sources.
0B
The corresponding Interrupt port generates the IRQ to MIPS
1B
The corresponding Interrupt port generates the FIQ to MIPS
Fast Interrupt Request Status
FIQ_S
Fast Interrupt Request Status
Data Sheet
Offset
18H
36
Reset Value
0H
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
ADM5120P/PX System
5HV
),46
UZ
Field
Bits
Res
31:10
FIQS
9:0
Type
Description
Reserved
Not Applicable.
rw
FIQ Status 9:0
The status of the fast interrupt sources after masking.
1B
The corresponding IRQ is active, and generates the interrupt to
MIPS
Interrupt Request Test Source
IRQ_TS
Interrupt Request Test Source
Offset
1CH
Reset Value
0H
5HV
,5476
UZ
Field
Bits
Res
31:10
IRQTS
9:0
Data Sheet
Type
Description
Reserved
Not Applicable.
rw
IRQ Test Source 9:0
The test data for the IRQ_raw_status.
37
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
ADM5120P/PX System
Interrupt Request Source Sel
IRQSS
Interrupt Request Source Sel
Offset
20H
Reset Value
0H
,5
4
5HV
UZ
Field
Bits
Res
31:1
IRQSS
0
Type
Description
Reserved
Not Applicable.
rw
IRQ Source Selection
1B
Load the IRQ_test_source into IRQ_raw_status
Interrupt Level
INT_L
Interrupt Level
Offset
24H
Reset Value
1C8H
5H ,,
V /
5HV
5HV
UZ UZ
Field
Bits
Res
31:6
Res
5
rw
Reserved
Not Applicable.
II0L
4
rw
Internal Interrupt 0 Level
Level specify for GPIO 2 interrupt source.
0B
Active high (default)
1B
Active low
Res
3:0
Data Sheet
Type
Description
Reserved
Not Applicable.
Reserved
Not Applicable.
38
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
4
Main Processor
Main Processor
The CPU description covers:
1. Feature list (Chapter 4.1)
2. Functional description (Chapter 4.2)
4.1
4Kc CPU Core Features
The 4Kc CPU supports:
•
32-bit Data and Address Paths
•
MIPS32™ Compatible Instruction Set
–
–
–
–
–
–
–
•
MIPS16e Application Specific Extension
–
–
–
–
–
•
16 bit encoding of 32 bit instructions to improve code density
Special PC relative instructions for efficient loading of addresses and constants
Data type conversion instructions (ZEB, SEB, ZEH, SEH)
Compact Jumps (JRC, JALRC)
Stack frame set-up and tear down “macro” instructions (SAVE and RESTORE)
Instruction and Data Cache
–
–
–
–
–
–
–
–
•
All MIPS II™ Instructions
Multiply-Add and Multiply-Subtract Instructions (MADD, MADDU, MSUB, MSUBU)
Targeted Multiply Instruction (MUL)
Zero and One Detect Instructions (CLZ, CLO)
Wait Instruction (WAIT)
Conditional Move Instructions (MOVZ, MOVN)
Prefetch Instructions (PREF)
8 KByte Instruction Cache Size in a 4-Way set associative organization
4 KByte Data Cache Size in a 2-Way set associative organization
Loads that miss in the cache are blocked only until the critical word is available
Supports Write-back with write-allocation and Write-through with or without write- allocation
16-byte cache line size, word sectored
Virtually indexed, physically tagged
Support for cache line locking
Non-blocking prefetches
MIPS32™ privileged resource architecture
– Count/Compare registers for real-time timer interrupts
– Instruction and Data watch registers for software breakpoints
– Separate interrupt exception vector
•
Memory Management Unit
– 16 dual-entry MIPS32 style JTLB with variable page sizes
– 4-entry instruction micro TLB
– 4-entry data micro TLB
•
Core Bus Interface Unit (Core BIU)
– All I/Os fully registered
– Separate, unidirectional 32-bit address and data buses
– Two 16 Byte collapsing write buffers
•
Multiply Divide Unit
– Maximum issue rate of one 32 x 16 multiply per clock
– Maximum issue rate of one 32 x 32 multiply every other clock
Data Sheet
39
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Main Processor
– Early-in divide control. Minimum 11, maximum 34 clock cycles
•
Power Control
– No minimum clock frequency
– Power Down mode (triggered by WAIT instruction)
– Support for software controlled clock divider
•
EJTAG Debug Support
–
–
–
–
–
CPU control with start, stop and single-step feature
Software Breakpoints via SDBBP instruction
Hardware Breakpoints on virtual addresses
Test Access Port (TAP) facilitates high speed download of application
Optional EJTAG Trace hardware to enable real-time tracing of executed code
4.2
Functional Description
The block diagram of the main processor subsystem is given in Figure 5.
MDU
I$
Power
Power
Management
Unit (PMU)
SubSystem
Bus Interface
Unit (SBIU)
Execution
Core
MMU
Cache
Controller
Core
BIU
CP0
TLB
D$
EJTAG
Interrupt Control Unit (ICU)
Reset and Boot (RCU)
Figure 5
JTAG
Trace
MIPS4Kc_Core
Main Processor Subsystem
The main processor subsystem consists of the below major parts :
•
The MMU enabled MIPS 4KC core and associated cache system
•
The bus wrapper block translates the MIPS 4Kc EC bus to the system bus
4.2.1
Endianness Mode
The main processor sub-system is capable of running in either big endian or little endian mode. By default, it is set
to little endian mode. It can be switched to big endian mode by pin strapping the signal : ADDR[19](Pin 119).
Table 22
Endian Setting
Signal
ADDR[19]
Mode
1
Big Endian
0
Little Endian (default)
4.2.2
Coprocessor CP0
In the MIPS architecture, the System Control Coprocessor (CP0) is responsible for the virtual-to-physical address
translation, cache protocols, exception control system, processor’s diagnostics capability, the operating mode
selection (Kernel, Supervisor, User, and Debug) and the enabling/disabling of interrupts. Information such as CPU
status, performance and configuration (including caches) are available by accessing the CP0 registers.
Data Sheet
40
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
4.2.3
Main Processor
Execution Unit
The 4Kc™ core execution unit implements a load/store architecture with single-cycle ALU operations (logical,
shift, add, subtract). The 4Kc™ core contains thirty-two 32-bit general-purpose registers used for scalar integer
operations and address calculation. The register file consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
•
•
•
•
•
•
•
•
32-bit adder used for calculating arithmetic results and the data addresses
Address Unit for calculating the next instruction address
Logic for branch determination and branch target address calculation
Load aligner
Bypass multiplexers used to avoid stalls when executing instructions streams where data producing
instructions are followed closely by consumers of their results
Zero/One detect unit for implementing the Count Leading Zero/One (CLZ, CLO) instructions
Logic unit for performing bitwise logical operations
Shifter & Store Aligner
4.2.4
Multiply Divide Unit
The multiply divide unit (MDU) performs multiply and divide operations. The pipeline MDU supports execution of
a 16:16 or a 32:16 on every clock cycle. 32:32 multiply operations can be issued every other clock cycle. Divide
operations are implemented with a 1-bit per clock iterative algorithm and requires 35 clock cycles in worst case to
complete. Early-in, the algorithm detects sign extensions of the dividend, reducing the amount of iterations. An
attempt to issue subsequent MDU instruction while a divide is still active, causes a pipeline stall until the divide
operation is completed.
The MUL instruction specifies that the lower 32 bits of the multiply result is placed in the register file instead of the
HI/LO register pair. By avoiding the explicit move from LO (MFLO) instruction, required when using the LO register,
and by supporting multiple destination registers, the throughput of multiplication intensive operations is increased.
The multiply add (MADD, MADDU) and multiply subtract (MSUB, MSUBU) are used to perform the multiply add
and multiply subtract operations, which are commonly used in Digital Signal Processing (DSP) algorithms.
4.2.5
Memory Management Unit
The Memory Management Unit (MMU) of the MIPS 4KcTM CPU is implemented as a Translation Lookaside Buffer
(TLB). The MMU translates any virtual address to a physical address as well as providing memory protection
mechanisms.
The MIPS 4KcTM CPU supports three operating modes: the User Mode, the Kernel Mode and the Debug Mode.
User Mode is often used for application programs. Kernel Mode is typically used for operating system tasks. Debug
Mode is used for software debugging purposes.
The address translation performed by the MMU depends on the mode in which the processor is operating. The
4 Gbyte virtual memory space addressed by a 32-bit virtual address is segmented differently depending on the
mode of operation (user, kernel, debug). Each of the segments are either mapped or unmapped. Mapped
segments use the TLB to translate from virtual to physical addresses, while the unmapped segments have a fixed
simple translation.
4.2.6
Cache System
The CPU Core incorporates both on-chip instruction and data caches that can each be accessed in a single
processor cycle.
•
•
•
8 Kbyte of instruction and an 8 KByte data cache
Instruction organized as 2-way set associative organization
Data cache organized as 2-way set associative organization
Data Sheet
41
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
•
•
•
•
•
•
•
•
•
•
•
Main Processor
Each cache has its own 32-bit data path, both caches can be accessed in the same pipeline clock cycle
Single processor cycle access
16 byte cache line size, word sectored
Cache locking on a per line basis, CACHE instruction to manipulate the Data and Tag arrays of the instruction
as well as the data cache, including cache line locking
Virtually indexed and physically tagged virtual to physical address translation occurs in parallel with the cache
access
Hit under refill
Support of streaming instruction or data is forwarded during cache refill
Non blocking prefetches
PREF instructions are supported by the data cache controller, which are used to increase the performance by
polling the processor
Non blocking loads
Supports Write-back with write-allocation and Write-through with or without write- allocation
4.2.7
EJTAG Debug Unit
All cores provide basic EJTAG support with debug mode, run control, single step and software breakpoint
instruction (SDBBP) as part of the core. These features allow for the basic software debug of user and kernel code.
Additional EJTAG features include:
•
•
•
Hardware breakpoints: The hardware instruction breakpoints can be configured to generate a debug
exception, when an instruction is executed anywhere in the virtual address space. Bit mask and Address
Space Identifier (ASID) values may apply in the address compare. These breakpoints are not limited to code
in RAM like the software instruction breakpoint (SDBBP). The data breakpoints can be configured to generate
a debug exception on a data transaction. The data transaction may be qualified with both virtual address, data
value, size and load/store transaction type. Bit mask and ASID values may apply in the address compare, and
byte mask may apply in the value compare.
A TAP, enabling communication between an EJTAG probe and the CPU through a dedicated port. This
provides the possibility for debugging without debug code in the application, and for download of application
code to the system.
An optional block is EJTAG Trace which enables real-time tracing capability. The trace information can be
stored to (either an on-chip trace memory, or to) an off-chip trace probe. The trace of program flow is highly
flexible and can include instruction program counter as well as data addresses and data values. The trace
features provides a powerful software debugging mechanism.
4.3
Register Description
The internal registers are for dug purpose only.
The register description is splitted into Bus Interface Unit (BIU) and FPI-Bus 0 (FB),
4.3.1
BIU Registers
Absolute Register Address = Module Base Address + Offset Address
Table 23
Module Base Address - BIU
Module Name
Base Address
End Address
BIU
1FA8 0000H
1FAF FFFFH
Data Sheet
42
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 24
Main Processor
Registers OverviewRegisters Overview from Chapter BIU Registers
Register Short Name
Register Long Name
Offset Address
BIU_ID
Bus Interface Identification Register
0000H
BIU_ERRCAUSE
BIU Error Cause Register
0100H
BIU_ERR_ADDR
BIU Error Address Register
0108H
BIU_AUXI
BIU Auxillary Port Input Register
0200H
BIU_AUXO
BIU Auxillary Port Output Register
0208H
Page Number
The register is addressed wordwise.
4.3.1.1
BIU Identification Register
Register BIU_ID holds module identification and the revision of the Subsystem BIU module.
BIU_ID
Bus Interface Identification Register
Offset
0000H
Reset Value
0000 0900H
Field
Bits
Type
Description
ARCH
16
r
Architecture
This bit identifies if the internal architecture of the logic block is either
64 bit or 32 bit.
0B
32-bit internal architecture.
1B
64-bit internal architecture.
ID
15:8
r
Identification Value
This bit field identifies the logic block of the CPU Subsystem. It is used as
manufacturer identification code only.
REV
7:0
r
Revision Number
The first revision starts with 00H
BIU Access Error Log Register (Error Cause)
The error cause log register holds log information about a detected write error. When the BIU detects an illegal
write access the cause of error is logged in this register and its address is logged in the BIU_ERR_ADDR register.
When the ERR register bit is set, an interrupt is generated to the CPU. While the ERR bit is set no new errors are
logged, and new errors are therefore ignored, until this bit has been cleared by the CPU. An illegal address error
is reported in the CAUSE field when an access is issued to a reserved memory area, non-existing SRAM memory
Data Sheet
43
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Main Processor
or a non-existing register in the BIU or RAM register area. An illegal access error is reported when the BIU detects
a non-word access to a defined register area.
Note: Please note that an interrupt is generated if the CPU writes a 1 to the ERR bit. This should only be used for
test. For normal operation the CPU will clear this bit in response to hardware setting it.
BIU_ERRCAUSE
BIU Error Cause Register
Offset
0100H
Field
Bits
Type
Description
ERR
31
rw
Error log bit
0B
1B
PORT
19:16
rw
Reset Value
0000 0000H
No Error No error logged
Error logged Error logged
Port number of the access Initiator
Note: Others are reserved.
0B
CAUSE
1:0
rw
CPU CPU to BIU
Error Cause
The CAUSE field indicates the cause of error according to the list below:
Note: Others are reserved.
00B Reset Reset State
01B Illegal address error caused by Illegal address
11B Illegal Access error caused by Illegal access
Bus Interface Unit Error Address
The accessed address error log register holds the address of a detected write error. When the Subsystem BIU
detects an illegal write (e.g. none existing address) the address is logged in this register and the cause of error is
logged in the BIU_ERRCAUSE register. The register can be written by the CPU but for normal operation the CPU
will only read it in response to an error.
BIU_ERR_ADDR
BIU Error Address Register
Offset
0108H
Field
Bits
Type
Description
ADDR
31:0
rw
Address of logged illegal access
Returns the illegal address.
Data Sheet
44
Reset Value
0000 0000H
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Main Processor
Bus Interface Auxillary Port Input
Returns the confirmation that the SIF was flushed.
BIU_AUXI
BIU Auxillary Port Input Register
Offset
0200H
Reset Value
0000 0000H
Field
Bits
Type
Description
ACK
0
r
SIF Flush ACK
Returns the acknlowdgement that the SIF was flushed.
0B
No action
1B
Flushed SIF was flushed.
Bus Interface Unit Auxillary Port Output
Used to configure the basic parameters of the BIU.
BIU_AUXO
BIU Auxillary Port Output Register
Offset
0208H
Field
Bits
Type
Description
max_read_ws
15:8
rw
Read WS
define number of waitstates for read
Sus
4
rw
OCDS suspend
should written with 0
Ndt
3
rw
delayed transaction
should written with 1
Ewa
2
rw
early_wr_abotr_sup
should written with 0
Era
1
rw
early_rd_abort_sup
should written with 0
SFR
0
rw
SIF Flush request
request flush operation from SIF module
4.3.2
Reset Value
0000 0000H
FPI Bus Register Description
Absolute Register Address = Module Base Address + Offset Address
Data Sheet
45
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 25
Main Processor
Module Base Address
Module Name
Base Address
End Address
FB
1F88 0000H
1F8F FFFFH
Table 26
Registers OverviewRegisters Overview from Chapter FPI Bus Register Description
Register Short Name
Register Long Name
Offset Address
FB_ID
FPI Bus Identification Register
0000H
FB_ERRCAUSE
FPI Bus Brodge Error Cause Register
0100H
FB_ERR_ADDR
FPI Bus Error Address Register
0108H
FB_CFG
FPI Bus Bridge Configuration Register
0800H
Page Number
The register is addressed wordwise.
4.3.2.1
FPI Bus Bridge Identification Register
Register FB_ID holds information about the FPI-Bus Bridge module.
FB_ID
FPI Bus Identification Register
Offset
0000H
Reset Value
0000 0800H
Field
Bits
Type
Description
ID
15:8
rw
Identification
Identification number of the FPI Bus Bridge
REV
7:0
rw
Revision
Indicates the revision of the module. The first revision is 00H
FPI Bus Error Address
Register FB_ERR_ADDR holds the address of a detected write error. When the CPU port of the FPI-Bus Bridge
detects an illegal write, the address is logged in register FB_ERR_ADDR and the cause of error is logged in
register FB_ERRCAUSE.
FB_ERR_ADDR
FPI Bus Error Address Register
Data Sheet
Offset
0108H
46
Reset Value
0000 0000H
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Main Processor
Field
Bits
Type
Description
ADDR
31:0
rw
Address of logged illegal access
Resturns the logged illegal address.
FPI Bus Bridge Configuration Register
The FPI Bus bridge configuration register controls the supervisor bit used for the FPI master interface commands.
The reset value is SVM = 1, i.e. the FPI-Bus is accessed in Supervisor mode after reset.
FB_CFG
FPI Bus Bridge Configuration Register
Offset
0800H
Field
Bits
Type
Description
SVM
0
rw
Supervisor/User mode
Configures the supervisor/user mode.
0B
User operates in User mode
1B
Supervisor operates in Supervisor mode
Reset Value
0000 0001H
FPI Bus Bridge Access Error log Register (Error Cause)
Register FB_ERRCAUSE holds log information about a detected write error. When the CPU port of the FPI-Bus
Bridge detects an illegal write, the cause of error is logged in register FB_ERRCAUSE and its address is logged
in the FB_ERR_ADDR register. When the ERR register bit is set, an interrupt to the CPU is issued. While the ERR
bit is set, no new errors are logged, hence new errors are ignored until this bit has been cleared by the CPU on
write action.
FB_ERRCAUSE
FPI Bus Brodge Error Cause Register
Offset
0100H
Field
Bits
Type
Description
ERR
31
rw
Error log bit
0B
1B
PORT
Data Sheet
19:16
rw
Reset Value
0000 0000H
No Error No error logged
Error Error logged
Port Number of the Access Initiator
Bit field PORT holds the port number of the access initiator in case of an
access error.
0100BFPI Bus Bridge port number of FPI Bus bridge
47
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Main Processor
Field
Bits
Type
Description
CAUSE
1:0
rw
Error Cause
The CAUSE field indicates the cause of error.
00B Reset Reset State
01B Illegal Address error caused by Illegal address An illegal address
error occurs on a write operation outside the address range used
for the FPI-Bus Bridge registers
10B Illegal Access error caused by Illegal access An illegal access
error occurs on a write operation with illegal byte lane configuration
11B Reserved reserved
Data Sheet
48
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
5
MultiPort Memory Controller (MPMC)
MultiPort Memory Controller (MPMC)
The MultiPort Memory Controller (MPMC) description covers:
•
Feature list (Chapter 5.1)
•
Functional description (Chapter 5.2)
•
External Interface; described in the dedicated chapter of the different interfaces
•
Registers (Chapter 5.3)
5.1
Feature List
The MPMC offers the following features:
•
•
•
•
•
•
Dynamic memory interface support including SDRAM, JEDEC low-power SDRAM
Asynchronous static memory device support including SRAM, ROM and NOR Flash with or without
asynchronous page mode
Read and write buffers to reduce latency and to improve performance
8-bit, 16-bit and 32-bit wide static memory support
Static memory features include:
– Programmable wait states
– Output enable, and write enable delays
– Extended wait
– Bus turnaround delay
– Asynchronous page mode read
Controller supports 2K, 4K and 8K row address synchronous memory parts. That is typical 512M, 256M, 128M
and 16MB parts with 8, 16 or 32DQ bits per device.
5.2
Functional Description
The following describes the MPMC’s functions
5.2.1
Static Memory Controller
Static memory descriptions:
5.2.1.1
Extended Wait Transfers
The static memory controller supports extremely long transfer times. In normal use the memory transfers are timed
using the MPMC Static Wait Rd 1 and MPMC Static Wait Wr 1 registers. These registers enable transfers with
up to 32 wait states. However, if an extremely slow static memory device has to be accessed you can enable the
Extended Wait(EW) bit in register . When this bit is enabled the MPMC Static Extended Wait register is used to
time both the read and write transfers. This register enables transfers to have up to 16368 wait states.
5.2.1.2
Wait State Generation
Each bank of the MPMC must be configured for external transfer wait states in read and write accesses. This is
achieved by programming the appropriate fields of the bank control registers:
•
•
•
•
•
•
•
MPMC Static Wait Wen 1
MPMC Static Wait Oen 1
MPMC Static Wait Rd 1
MPMC Static Wait Wr 1
MPMC Static Wait Page 1
MPMC Static Wait Turn 1
MPMC Static Extended Wait
Data Sheet
49
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
The number of cycles in which an AMBA transfer completes is controlled by two additional factors:
•
•
Access width
External memory width
5.2.1.3
Static Memory Read Control
The static memory read controls are described in the following:
•
•
•
The delay between the assertion of the chip select and the output enable is programmable from 0 to 15 cycles
using the WAITOEN bits of the MPMC Static Wait Oen 1 registers. The output enable is always deasserted
at the same time as the chip select, at the end of the transfer. Figure 6 shows that the WAIOEN is set to 2 in
the MPMC Static Wait Oen 1 registers.
The read access time is determined by the number of wait states programmed for the WAITRD field of the
MPMC Static Wait Rd 1 register. The WAITTURN field in the MPMC Static Wait Turn 1 register determines
the minimum number of bus turnaround wait states added between external read and write transfers. Figure 7
shows that the WAITRD is set to 2 in the MPMC Static Wait Rd 1 register.
The MPMC supports asynchronous page mode read up to four memory transfers by updating address bits A[1]
and A[0]. This feature increases the bandwidth by using a reduced access time for the read accesses that are
in page mode. The first read access takes MPMC Static Wait Rd 1 and WAITRD cycles. Subsequent read
accesses that are in page mode take MPMC Static Wait Page 1 and WAITPAGE cycles. The chip select and
output enable lines are held during the burst, and only the lower two address bits change between subsequent
accesses. At the end of the burst the chip select and output enable lines are deasserted together. The Figure 8
shows the page mode read with 2 WAITRD cycles and 1 WAITPAGE cycle.
CLK_OUT
ADDR[19:0]
Address
DATA[31:0]
Data
2T
F_CSX_N
1T
F_OE_N
Figure 6
Read with Two Clock Delay for Read Enable
CLK_OUT
ADDR[19:0]
Address
DATA[31:0]
Data
3T
F_CSX_N
F_OE_N
tDSU
Figure 7
Data Sheet
Read with Two Wait State
50
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
CLK_OUT
ADDR[19:0]
Address
DATA[31:0]
Address + 4
Data
3T
F_CSX_N
Address + 8
Data
2T
Data
2T
F_OE_N
Figure 8
Asynchronous Page Mode Read with 2 Wait State and 1 Sequential Wait State
CLK_OUT
ADDR[19:0]
DATA[31:0]
Address
Data
1T
F_CSX_N
F_OE_N
WE_N
turnaround
Figure 9
Bus Turnaround
5.2.1.4
Static Memory Write Control
Write timing is described in the following:
•
•
The delay between the assertion of the chip select and the write enable is programmable from 0 to 15 cycles
using the WAITWEN bits of the MPMC Static Wait Wen 1 registers. The write enable is asserted on the rising
edge of MPMCCLK after the assertion of the chip select for the zero wait state. The write enable is always
deasserted a cycle before the chip select, at the end of the transfer.
The write access time is determined by the number of wait states programmed for the WAITWR field of the
MPMC Static Wait Wr 1 register. The WAITTURN field in the MPMC Static Wait Turn 1 register determines
the number of bus turnaround wait states added between external read and write transfers.
CLK_OUT
ADDR[19:0]
Address
DATA[31:0]
Data
1T
F_CSX_N
WE_N
Figure 10
Data Sheet
1T
1T
Write with Zero Wait State
51
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
CLK_OUT
ADDR[19:0]
Address
DATA[31:0]
Data
3T
F_CSX_N
WE_N
Figure 11
Write with Two Wait State
CLK_OUT
ADDR[19:0]
Address
DATA[31:0]
Data
2T
F_CSX_N
WE_N
3T
Figure 12
Write with Two Clock Delay for Write Enable
5.2.2
Dynamic Memory Controller
The following describes the Dynamic Controller.
5.2.2.1
Dynamic Memory Controller Command Descriptions
The dynamic memory controller block in MPMC supports the SDRAM memory commands shown in list below:
•
•
•
•
•
•
•
•
ACT: Opens an SDRAM row
REF: CAS before RAS style refresh
SREF: self-refresh
PRE: Pre-charge, close a bank
RD: Read from an open row, row left open
WR: Write to an open row, row left open
RDA: Read followed by pre-charge
WRA: Write followed by pre-charge
The commands listed above are generated automatically.
The commands in the list below are generated under software control by programming the SDRAM initialization
and deep sleep mode fields of the MPMC Dynamic Control register.
•
•
•
•
MRS: Mode register set, programs SDRAM mode register
NOP: No operation, used during the SDRAM initialization sequence
PALL: Pre-charge all, used during the SDRAM initialization sequence
DSM: Deep sleep mode, for low-power SDRAM
Data Sheet
52
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
5.2.2.2
MultiPort Memory Controller (MPMC)
Generic SDRAM Initialization Example
On power-on reset, software must initialize the MPMC and each of the dynamic memories connected to the
controller. Check the dynamic memory data sheet for the start up procedure. A generic example initialization
sequence is shown below:
•
•
•
•
•
•
•
•
•
•
•
•
•
Wait 100 ms after the power is applied and the clocks have stabilized.
Set the SDRAM Initialization (I) value to NOP in the MPMC Dynamic Control register. This automatically
issues a NOP command to the SDRAM memories.
Wait 200 ms.
Set the SDRAM Initialization (I) value to PALL in the MPMC Dynamic Control register. This automatically
issues a pre-charge all instruction (PRE-ALL) to the SDRAM memories. This pre-charges all banks and places
the device into the all banks idle state.
Perform a number of refresh cycles, by writing 1 into the refresh register, MPMC Dynamic Refresh. This
provides a memory refresh every 16 AHB clock cycles.
Wait until eight SDRAM refresh cycles have occurred (128 AHB clock cycles)
Program the operational value into the refresh register, MPMC Dynamic Refresh
Program the operational value into the latency register, MPMC Dynamic RAS
Program the operational values into the configuration register, MPMC Dynamic Config 0. The buffers must
be disabled during initialization.
Set the SDRAM initialization value (I) to MODE in the MPMC Dynamic Control register.
Program the SDRAM memories mode register. The mode register enables the following parameters to be
programmed.
– Burst length
– Burst type
– CAS latency
– Operating mode
– Write burst mode
Set the SDRAM initialization value (I) to NORMAL in the MPMC Dynamic Control register.
Enable the buffers in the MPMC Dynamic Config 0 configuration register. The SDRAM is now ready for
normal operation.
Data Sheet
53
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
5.3
MultiPort Memory Controller (MPMC)
MPMC Registers Description
The below describes the MPMC registers in great detail.
Note: For ALL Reserved Registers please note: Read is defined and all must be written as zeros.
5.3.1
MPMC Registers
Table 27
Registers Address Space
Module
Base Address
End Address
MPMC
1100 0000H
1100 0278H
Table 28
Note
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
MPMC_C
MPMC Control
000H
57
MPMC_S
MPMC Status
004H
57
MPMC_Conf
MPMC Configuration
008H
59
MPMC_DC
MPMC Dynamic Control
020H
60
MPMC_DR
MPMC Dynamic Refresh
024H
61
MPMC_DRP
MPMC Dynamic RP
030H
62
MPMC_DRAS
MPMC Dynamic RAS
034H
62
MPMC_DSREX
MPMC Dynamic SREX
038H
62
MPMC_DAPR
MPMC Dynamic APR
03CH
64
MPMC_DDAL
MPMC Dynamic DAL
040H
64
MPMC_DWR
MPMC Dynamic WR
044H
64
MPMC_DRC
MPMC Dynamic RC
048H
66
MPMC_DRFC
MPMC Dynamic RFC
04CH
66
MPMC_DXSR
MPMC Dynamic XSR
050H
66
MPMC_DRRD
MPMC Dynamic RRD
054H
68
MPMC_DMRD
MPMC Dynamic MRD
058H
68
MPMC_SEW
MPMC Static Extended Wait
080H
68
MPMC_DC0
MPMC Dynamic Config 0
100H
70
MPMC_DRC0
MPMC Dynamic Ras Cas 0
104H
74
MPMC_DC1
MPMC Dynamic Config 1
120H
73
MPMC_DRC1
MPMC Dynamic Ras Cas 1
124H
75
MPMC_SC1
MPMC Static Config 1
220H
76
MPMC_SWW1
MPMC Static Wait Wen 1
224H
82
MPMC_SWO1
MPMC Static Wait Oen 1
228H
85
MPMC_SWR1
MPMC Static Wait Rd 1
22CH
88
MPMC_SWP1
MPMC Static Wait Page 1
230H
91
MPMC_SWWR1
MPMC Static Wait Wr 1
234H
94
MPMC_SWT1
MPMC Static Wait Turn 1
238H
97
MPMC_SC2
MPMC Static Config 2
240H
78
MPMC_SWW2
MPMC Static Wait Wen 2
244H
83
Data Sheet
54
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 28
MultiPort Memory Controller (MPMC)
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
MPMC_SWO2
MPMC Static Wait Oen 2
248H
86
MPMC_SWR2
MPMC Static Wait Rd 2
24CH
89
MPMC_SWP2
MPMC Static Wait Page 2
250H
92
MPMC_SWWR2
MPMC Static Wait Wr 2
254H
95
MPMC_SWT2
MPMC Static Wait Turn 2
258H
98
MPMC_SC3
MPMC Static Config 3
260H
80
MPMC_SWW3
MPMC Static Wait Wen 3
264H
84
MPMC_SWO3
MPMC Static Wait Oen 3
268H
87
MPMC_SWR3
MPMC Static Wait Rd 3
26CH
90
MPMC_SWP3
MPMC Static Wait Page 3
270H
93
MPMC_SWWR3
MPMC Static Wait Wr 3
274H
96
MPMC_SWT3
MPMC Static Wait Turn 3
278H
99
The register is addressed wordwise.
Data Sheet
55
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 29
Mode
MultiPort Memory Controller (MPMC)
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
Basic Access Types
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read/write
virtual
rwv
Physically, there is no new register in
the generated register file. The real
readable and writable register resides
in the attached hardware.
Register is read and writable by SW (same
as rw type register)
read
r
Register is written by HW (register
Value written by SW is ignored by HW; that
between input and output -> one cycle is, SW may write any value to this field
delay)
without affecting HW behavior
read only
ro
Same as r type register
Same as r type register
read virtual
rv
Physically, there is no new register in
the generated register file. The real
readable register resides in the
attached hardware.
Value written by SW is ignored by HW; that
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
write
w
Register is written by software and
affects hardware behavior with every
write by software.
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
write virtual
wv
Physically, there is no new register in Register is writable by SW (same as w type
register)
the generated register file. The real
writable register resides in the attached
hardware.
read/write
hardware
affected
rwh
Register can be modified by hardware
and software at the same time. A
priority scheme decides, how the value
changes with simultaneous writes by
hardware and software.
Data Sheet
56
Register can be modified by HW and SW,
but the priority SW versus HW has to be
specified.
SW can read the register.
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
5.3.1.1
MultiPort Memory Controller (MPMC)
Registers Description
MPMC Control
MPMC_C
MPMC Control
Offset
000H
Reset Value
1H
5HV
': /3
% 0 $00(
UZ UZ UZ UZ
Field
Bits
Type
Description
Res
31:4
-
Not applicable
DWB
3
rw
Drain Write Buffers
0B
Buffers operate normally (reset value on nPOR, and HRESETn)
1B
Drain write buffers.
LPM
2
Low-Power Mode
Indicate normal, or low-power mode.
Entering low-power mode reduces memory controller power
consumption. Dynamic memory is refreshed as necessary. The memory
controller returns to normal function mode by clearing the low-power
mode bit (L), or by system, or power-on reset.
0B
Normal mode (reset value on nPOR, and HRESETn)
1B
Low-power mode.
AM
1
Address Mirror
Indicates normal or reset memory map.
Static memory chip select 1 is mirrored onto chip select 0 and chip select
4 (reset value on nPOR). On power-on reset, chip select 1 is mirrored to
both chip select 0 and chip select 1 and chip 4 memory areas. Clearing
the M bit enables chip select 0 and chip select 4 memory to be accessed.
0B
Normal memory map
1B
Reset memory map.
ME
0
MPMC Enable
Indicates if the PrimeCell MPMC is enabled or disabled.
Disabling the PrimeCell MPMC reduces power consumption. When the
memory controller is disabled the memory is not refreshed. The memory
controller is enabled by setting the enable bit, or by system, or power-on
reset.
0B
Disabled
1B
Enabled (reset value on nPOR, and HRESETn).
MPMC Status
Data Sheet
57
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC_S
MPMC Status
Offset
004H
Reset Value
0H
65:%
$ 6 %8
5HV
U
U
Field
Bits
Res
31:3
SRA
2
WBS
1
Write Buffer Status
This read only bit enables the PrimeCell MPMC to enter low-power mode
or disabled mode cleanly.
0B
Write buffers empty (reset value on nPOR)
1B
Write buffers contain data.
BU
0
Busy
This read-only bit is used to ensure that the memory controller enters the
low-power or disabled mode cleanly.
0B
MPMC is idle (reset value on nPOR, and HRESETn)
1B
MPMC is busy performing memory transactions.
Data Sheet
Type
U
Description
Reserved
Not applicable
r
Self-Refresh Acknowledge
This read only bit indicates the operating mode of the MPMC.
0B
Normal mode (reset value on nPOR)
1B
Self-refresh acknowledge.
58
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Configuration
MPMC_Conf
MPMC Configuration
Offset
008H
Reset Value
0H
5HV
&/
.
5HV
(0
UZ
UZ
Field
Bits
Type
Description
Res
31:9
-
Reserved
Read undefined, must be written as zeros.
CLK
8
rw
Clock Ratio
HCLK: MPMCCLKOUT3:0 ratio.
0B
1:1 (reset value on nPOR)
1B
1:2.
Res
7:1
-
Reserved
Read undefined, must be written as zeros.
EM
0
rw
Endian Mode
The value of the endian bit on power-on-reset (nPOR) is determined by
the MPMCBIGENDIAN signal. This value can be overridden by software.
This field is unaffected by the AHB reset (HRESETn).
0B
Little-endian mode
Big-endian mode.
1B
Data Sheet
59
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic Control
MPMC_DC
MPMC Dynamic Control
Offset
020H
Reset Value
2H
5HV
'6
0
5HV
6,
5HV
65 '0
5 & &(
UZ
UZ
UZ UZ UZ
Field
Bits
Type
Description
Res
31:14
-
Reserved
Read undefined. Must be written as zeros.
DSM
13
rw
Low-Power SDRAM Deep Sleep Mode
0B
Normal operation (reset value on nPOR)
1B
Enter deep power down mode.
Res
12:9
-
Reserved
Read undefined. Must be written as zeros.
SI
8:7
rw
SDRAM Initialization
00B Issue SDRAM NORMAL operation command (reset value on
nPOR)
01B Issue SDRAM MODE command
10B Issue SDRAM PALL (precharge all) command
11B Issue SDRAM NOP (no operation) command.
Res
6:3
-
Reserved
Read undefined. Must be written as zeros.
SRR
2
rw
Self-Refresh Request (SR)
By writing 1 to this bit self-refresh can be entered under software control.
Writing 0 to this bit returns the MPMC to normal mode. The self-refresh
acknowledge bit in the MPMCStatus register must be polled to discover
the current operating mode of the MPMC.
0B
Normal mode (reset value on nPOR)
Enter self-refresh mode.
1B
DMC
1
rw
Dynamic Memory Clock Control
When clock control is LOW the output clock MPMCCLKOUT is stopped
when there are no SDRAM transactions. The clock is also stopped during
self-refresh mode.
0B
MPMCCLKOUT stops when all SDRAMs are idle and during selfrefresh mode
1B
MPMCCLKOUT runs continuously (reset value on nPOR).
CE
0
rw
Dynamic Memory Clock Enable
0B
Clock enable of devices are deasserted to save power (reset value
on nPOR)
1B
All clock enables are driven HIGH continuously.
Data Sheet
60
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic Refresh
MPMC_DR
MPMC Dynamic Refresh
Offset
024H
Reset Value
0H
5HV
57
UZ
Field
Bits
Type
Description
Res
31:11
-
Reserved
Read undefined. Must be written as zeros.
RT
10:0
rw
Refresh Timer
0D
Refresh disabled (reset value on nPOR)
1D
16 HCLK ticks between SDRAM refresh cycles
...D
nD
n x16 HCLK ticks between SDRAM refresh cycles.
Data Sheet
61
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic RP
Note: The delay is in MPMCCLK cycles.
MPMC_DRP
MPMC Dynamic RP
Offset
030H
Reset Value
FH
5HV
3&3
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
Read undefined. Must be written as zeros.
PCP
3:0
rw
Precharge Command Period
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
MPMC Dynamic RAS
Note: The delay is in MPMCCLK cycles.
MPMC_DRAS
MPMC Dynamic RAS
Offset
034H
Reset Value
FH
5HV
$3&3
UZ
Field
Bits
Res
31:4
APCP
3:0
Type
Description
Reserved
Read undefined. Must be written as zeros.
rw
Active to Precharge Command Period
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
MPMC Dynamic SREX
Note: The delay is in MPMCCLK cycles.
Data Sheet
62
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC_DSREX
MPMC Dynamic SREX
Offset
038H
Reset Value
FH
5HV
65(7
UZ
Field
Bits
Res
31:4
SRET
3:0
Data Sheet
Type
Description
Reserved
Read undefined. Must be written as zeros.
rw
Self-Refresh Exit Time
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
63
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic APR
Note: The delay is in MPMCCLK cycles.
MPMC_DAPR
MPMC Dynamic APR
Offset
03CH
Reset Value
FH
5HV
/$&7
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
Read undefined. Must be written as zeros.
LACT
3:0
rw
Last-Data-Out to Active Command Time
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
MPMC Dynamic DAL
Note: The delay is in MPMCCLK cycles.
MPMC_DDAL
MPMC Dynamic DAL
Offset
040H
Reset Value
FH
5HV
'$&7
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
Read undefined. Must be written as zeros.
DACT
3:0
rw
Data-In to Active Command Time
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
MPMC Dynamic WR
Note: The delay is in MPMCCLK cycles.
Data Sheet
64
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC_DWR
MPMC Dynamic WR
Offset
044H
Reset Value
FH
5HV
:57
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WRT
3:0
rw
Write Recovery Time
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
Data Sheet
65
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic RC
Note: The delay is in MPMCCLK cycles.
MPMC_DRC
MPMC Dynamic RC
Offset
048H
Reset Value
1FH
5HV
$$&3
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
AACP
4:0
rw
Active to Active Command Period
0H
1 clock cycle
...H
1FH 32 clock cycles (reset value on nPOR)
MPMC Dynamic RFC
Note: The delay is in MPMCCLK cycles.
MPMC_DRFC
MPMC Dynamic RFC
Offset
04CH
Reset Value
1FH
5HV
$5$&3
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
ARACP
4:0
rw
Auto Refresh Period and Auto Refresh to Active Command Period
0H
1 clock cycle
...H
1FH 32 clock cycles (reset value on nPOR)
MPMC Dynamic XSR
Note: The delay is in MPMCCLK cycles.
Data Sheet
66
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC_DXSR
MPMC Dynamic XSR
Offset
050H
Reset Value
1FH
5HV
($&3
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
EACP
4:0
rw
Exit Self-Refresh to Active Command Period
0H
1 clock cycle
...H
1FH 32 clock cycles (reset value on nPOR)
Data Sheet
67
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic RRD
Note: The delay is in MPMCCLK cycles.
MPMC_DRRD
MPMC Dynamic RRD
Offset
054H
Reset Value
FH
5HV
$%/
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
ABL
3:0
rw
Active Bank A to Active Bank B Latency
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
MPMC Dynamic MRD
Note: The delay is in MPMCCLK cycles.
MPMC_DMRD
MPMC Dynamic MRD
Offset
058H
Reset Value
FH
Field
Bits
5HV
/$&7
UZ
Type
Description
Res
31:4
-
Reserved
LACT
3:0
rw
Load Mode Register to Active Command Time
0H
1 clock cycle
...H
FH
16 clock cycles (reset value on nPOR)
MPMC Static Extended Wait
Note: The delay is in HCLK cycles.
Data Sheet
68
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC_SEW
MPMC Static Extended Wait
Offset
080H
Reset Value
0H
5HV
(:72
UZ
Field
Bits
Type
Description
Res
31:10
-
Reserved
EWTO
9:0
rw
External Wait Time Out
0D
16 clock cycles (reset value on nPOR)
...D
nD
(n+1) x16 clock cycles
Note: n = 0 to 3FFH
Data Sheet
69
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic Config 0
Note: The offset 100H and 120H is for SDRAM bank0 and bank1 respectively.
MPMC_DC0
MPMC Dynamic Config 0
Offset
100H
Reset Value
0H
5HV
5:
5HV
1%
5HV
&:
5HV
:3
%(
5HV
UZ
UZ
UZ
UZ
UZ
5HV $0B 5HV
UZ
$0B
5HV
0'
5HV
UZ
UZ
Field
Bits
Type
Description
Res
31:30
-
Reserved
RW
29:28
rw
Row Width
00B 11-bit (reset value on nPOR)
01B 12-bit
10B 13-bit
11B Reserved
Res
27
-
Reserved
NB
26
rw
Number of Banks
0B
Two banks (reset value on nPOR)
1B
Four banks
Res
25
-
Reserved
CW
24:22
rw
Column Width
000B 6-bit (reset value on nPOR)
001B 7-bit
010B 8-bit
011B 9-bit
100B 10-bit
101B 11-bit
110B Reserved
111B Reserved
Res
21
-
Reserved
WP
20
rw
Write Protect
0B
Writes not protected (reset value on nPOR)
1B
Write protected.
BE
19
rw
Buffer Enable
0B
Buffer disabled for accesses to this chip select (reset value on
nPOR)
1B
Buffer enabled for accesses to this chip select.
Data Sheet
70
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
Field
Bits
Type
Description
Res
18:15
-
Reserved
AM_1
14
rw
Address Mapping
See Table 30
0B
Reset value on nPOR
Res
13
-
Reserved
AM_2
12:7
rw
Address Mapping
See , Table 30
00000000B Reset value on nPOR
Res
6:5
-
Reserved
MD
4:3
rw
Memory Device
00B SDRAM(reset value on nPOR)
01B Low-power SDRAM
10B Reserved
11B Reserved
Res
2:0
-
Reserved
Table 30
[14]
Address Mapping Table
[12] [11:9] [8:7] Description
16-Bit external bus high performance address mapping (Row, Bank, Column)
0
0
000
00
16MB (2M X 8),2 banks row length=11, column length=9
0
0
000
01
16MB (1M X 16),2 banks, row length=11, column length=8
0
0
001
00
64MB (8M X 8),4 banks, row length=12, column length=9
0
0
001
01
64MB (4M X16),4 banks, row length=12, column length=8
0
0
010
00
128MB (16M X 8),4 banks, row length=12, column length=10
0
0
010
01
128MB (8M X 16), 4 banks, row length=12, column length=9
0
0
011
00
256MB (32M X 8), 4 banks, row length=13, column length=10
0
0
011
01
256MB (16M X 16), 4 banks, row length=13, column length=9
0
0
100
00
512MB (64M X 8), 4 banks, row length=13, column length=11
0
0
100
00
512MB (32M X 16),4 banks, row length=13, column length=10
16-Bit external bus Low-power SDRAM address mapping (Bank, row, Column)
0
1
000
00
16MB (2M X 8),2 banks row length=11, column length=9
0
1
000
01
16MB (1M X 16),2 banks, row length=11, column length=8
0
1
001
00
64MB (8M X 8),4 banks, row length=12, column length=9
0
1
001
01
64MB (4M X16),4 banks, row length=12, column length=8
0
1
010
00
128MB (16M X 8),4 banks, row length=12, column length=10
Data Sheet
71
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 30
MultiPort Memory Controller (MPMC)
Address Mapping Table
[14]
[12] [11:9] [8:7] Description
0
1
010
01
128MB (8M X 16), 4 banks, row length=12, column length=9
0
1
011
00
256MB (32M X 8), 4 banks, row length=13, column length=10
0
1
011
01
256MB (16M X 16), 4 banks, row length=13, column length=9
0
1
100
00
512MB (64M X 8), 4 banks, row length=13, column length=11
0
1
100
01
512MB (32M X 16), 4 banks, row length=13, column length=10
32-Bit external bus High-Performance address mapping (Row, Bank, Column)
1
0
000
00
16MB (2M X 8), 2 banks, row length=11, column length=9
1
0
000
01
16MB (1M X 16), 2 banks, row length=11, column length=8
1
0
001
00
64MB (8M X 8), 4 banks, row length=12, column length=9
1
0
001
01
64MB (4M X 16), 4 banks, row length=12, column length=8
1
0
001
10
64MB (2M X 32), 4 banks, row length=11, column length=8
1
0
010
00
128MB (16M X 8),4 banks, row length=12, column length=10
1
0
010
01
128MB (8M X 16), 4 banks, row length=12, column length=9
1
0
010
10
128MB (4M X 32), 4 banks, row length=12, column length=8
1
0
011
00
256MB (32M X 8), 4 banks, row length=13, column length=10
1
0
011
01
256MB (16M X 16), 4 banks, row length13, column length=9
1
0
011
10
256MB (8M X 32), 4 banks, row length=13, column length=8
1
0
100
00
512MB (64M X8),4 banks, row length=13, column length=11
1
0
100
01
512MB (32M X 16),4 banks, row length=13, column length=10
32-Bit external bus Low-Performance SDRAM mapping (Bank,Row, Column)
1
0
100
01
512MB (32M X 16),4 banks, row length=13, column length=10
1
1
000
00
16MB (2M X 8), 2 banks, row length=11, column length=9
1
1
000
01
16MB (1M X 16), 2 banks, row length=11, column length=8
1
1
001
00
64MB (8M X 8), 4 banks, row length=12, column length=9
1
1
001
01
64MB (4M X 16), 4 banks, row length=12, column length=8
1
1
001
10
64MB (2M X 32), 4 banks, row length=11, column length=8
1
1
010
00
128MB (16M X 8),4 banks, row length=12, column length=10
1
1
010
01
128MB (8M X 16), 4 banks, row length=12, column length=9
1
1
010
10
128MB (4M X 32), 4 banks, row length=12, column length=8
1
1
011
00
256MB (32M X 8), 4 banks, row length=13, column length=10
1
1
011
01
256MB (16M X 16), 4 banks, row length13, column length=9
1
1
011
10
256MB (8M X 32), 4 banks, row length=13, column length=8
1
1
100
00
512MB (64M X8),4 banks, row length=13, column length=11
1
1
100
01
512MB (32M X 16),4 banks, row length=13, column length=10
Data Sheet
72
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic Config 1
Note: The offset 100H and 120H is for SDRAM bank0 and bank1 respectively.
MPMC_DC1
MPMC Dynamic Config 1
Offset
120H
Reset Value
0H
5HV
5:
5HV
1%
5HV
&:
5HV
:3
%(
5HV
UZ
UZ
UZ
UZ
UZ
5HV $0B 5HV
UZ
$0B
5HV
0'
5HV
UZ
UZ
Field
Bits
Type
Description
Res
31:30
-
Reserved
RW
29:28
rw
Row Width
00B 11-bit (reset value on nPOR)
01B 12-bit
10B 13-bit
11B Reserved
Res
27
-
Reserved
NB
26
rw
Number of Banks
0B
Two banks (reset value on nPOR)
1B
Four banks
Res
25
-
Reserved
CW
24:22
rw
Column Width
000B 6-bit (reset value on nPOR)
001B 7-bit
010B 8-bit
011B 9-bit
100B 10-bit
101B 11-bit
110B Reserved
111B Reserved
Res
21
-
Reserved
WP
20
rw
Write Protect
0B
Writes not protected (reset value on nPOR)
1B
Write protected.
BE
19
rw
Buffer Enable
0B
Buffer disabled for accesses to this chip select (reset value on
nPOR)
1B
Buffer enabled for accesses to this chip select.
Data Sheet
73
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
Field
Bits
Type
Description
Res
18:15
-
Reserved
AM_1
14
rw
Address Mapping
See Table 30
0B
Reset value on nPOR
Res
13
-
Reserved
AM_2
12:7
rw
Address Mapping
See , Table 30
00000000B Reset value on nPOR
Res
6:5
-
Reserved
MD
4:3
rw
Memory Device
00B SDRAM(reset value on nPOR)
01B Low-power SDRAM
10B Reserved
11B Reserved
Res
2:0
-
Reserved
MPMC Dynamic Ras Cas 0
Notes
1. The RAS to CAS latency (RAS) and CAS latency (CAS) are both defined in MPMCCLK cycles.
2. The offset 104H and 124H is for SDRAM bank0 and bank1 respectively.
MPMC_DRC0
MPMC Dynamic Ras Cas 0
Offset
104H
Reset Value
303H
5HV
&$6/
5HV
5$6/
UZ
UZ
Field
Bits
Type
Description
Res
31:10
-
Reserved
CASL
9:8
rw
CAS Latency
00B Reserved
01B One clock cycle(a)
10B Two clock cycles
11B Three clock cycles(reset value on nPOR).
Res
7:2
-
Reserved
RASL
1:0
rw
RAS Latency
Active to read or write delay
00B Reserved
01B One clock cycle(a)
10B Two clock cycles
11B Three clock cycles (reset value on nPOR).
Data Sheet
74
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Dynamic Ras Cas 1
Notes
1. The RAS to CAS latency (RAS) and CAS latency (CAS) are both defined in MPMCCLK cycles.
2. The offset 104H and 124H is for SDRAM bank0 and bank1 respectively.
MPMC_DRC1
MPMC Dynamic Ras Cas 1
Offset
124H
Reset Value
303H
5HV
&$6/
5HV
5$6/
UZ
UZ
Field
Bits
Type
Description
Res
31:10
-
Reserved
CASL
9:8
rw
CAS Latency
00B Reserved
01B One clock cycle(a)
10B Two clock cycles
11B Three clock cycles(reset value on nPOR).
Res
7:2
-
Reserved
RASL
1:0
rw
RAS Latency
Active to read or write delay
00B Reserved
01B One clock cycle(a)
10B Two clock cycles
11B Three clock cycles (reset value on nPOR).
Data Sheet
75
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Config 1
Notes
1.
2.
3.
4.
Offset = 220H is for F_CS0_N respectively.
Offset = 240H, is for External IO CSX0.
Offset =260H is for External IO CSX1.
Synchronous burst mode memory devices are not supported.
MPMC_SC1
MPMC Static Config 1
Offset
220H
Reset Value
0H
5HV
:3 %(
5HV
UZ UZ
%/ &&
5H
(: 6 3 5HV 30 V 0:
UZ UZ UZ
UZ
Field
Bits
Type
Description
Res
31:21
-
Reserved
WP
20
rw
Write Protect
0B
Writes not protected (reset value on nPOR)
1B
Write protected
BE
19
Res
18:9
-
Reserved
EW
8
rw
Extended Wait
0B
Extended wait disabled (reset value on nPOR)
1B
Extended wait enabled
BLS
7
CCP
6
rw
Chip Select Polarity
The values of the chip select polarity on power-on-reset(nPOR) is
determined by the relevant MPMCSxPOL signal. This value can be
overridden by software. This field is Unaffected by AHB reset
(HRESETn).
0B
Active LOW chip select
1B
Active HIGH chip select
Res
5:4
-
Reserved
Data Sheet
UZ
Buffer Enable
0B
Write buffer disabled (reset value on nPOR)
1B
Write buffer enabled
Byte Lane State
0B
For reads all the bits in nMPMCBLSOUT[3:0] are HIGH(reset value
on nPOR).For writes the respective active bits
innMPMCBLSOUT[3:0] are LOW.
1B
For reads the respective active bits in nMPMCBLSOUT[3:0] are
LOW. For writes the respective active bits in nMPMCBLSOUT[3:0]
are LOW.
76
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
Field
Bits
Type
Description
PM
3
rw
Page Mode
0B
Disabled (reset value on nPOR)
1B
Async page mode four enabled.
Res
2
-
Reserved
MW
1:0
rw
Memory Width Define
The memory width field define the data width of F_CS0_N. And the
default value will be the reset latched value on pins A[18:17].
00B 8 bit
01B 16 bit
10B 32 bit
11B Reserved.
Data Sheet
77
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Config 2
Notes
1.
2.
3.
4.
Offset = 220H is for F_CS0_N respectively.
Offset = 240H, is for External IO CSX0.
Offset =260H is for External IO CSX1.
Synchronous burst mode memory devices are not supported.
MPMC_SC2
MPMC Static Config 2
Offset
240H
Reset Value
0H
5HV
:3 %(
5HV
UZ UZ
%/ &&
5H
(: 6 3 5HV 30 V 0:
UZ UZ UZ
UZ
Field
Bits
Type
Description
Res
31:21
-
Reserved
WP
20
rw
Write Protect
0B
Writes not protected (reset value on nPOR)
1B
Write protected
BE
19
Res
18:9
-
Reserved
EW
8
rw
Extended Wait
0B
Extended wait disabled (reset value on nPOR)
1B
Extended wait enabled
BLS
7
CCP
6
rw
Chip Select Polarity
The values of the chip select polarity on power-on-reset(nPOR) is
determined by the relevant MPMCSxPOL signal. This value can be
overridden by software. This field is Unaffected by AHB reset
(HRESETn).
0B
Active LOW chip select
1B
Active HIGH chip select
Res
5:4
-
Reserved
Data Sheet
UZ
Buffer Enable
0B
Write buffer disabled (reset value on nPOR)
1B
Write buffer enabled
Byte Lane State
0B
For reads all the bits in nMPMCBLSOUT[3:0] are HIGH(reset value
on nPOR).For writes the respective active bits
innMPMCBLSOUT[3:0] are LOW.
1B
For reads the respective active bits in nMPMCBLSOUT[3:0] are
LOW. For writes the respective active bits in nMPMCBLSOUT[3:0]
are LOW.
78
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
Field
Bits
Type
Description
PM
3
rw
Page Mode
0B
Disabled (reset value on nPOR)
1B
Async page mode four enabled.
Res
2
-
Reserved
MW
1:0
rw
Memory Width Define
The memory width field defines the data width of External IO CSX0.
00B 8 bit
01B 16 bit
10B 32 bit
11B Reserved.
Data Sheet
79
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Config 3
Notes
1.
2.
3.
4.
Offset = 220H is for F_CS0_N respectively.
Offset = 240H, is for External IO CSX0.
Offset =260H is for External IO CSX1.
Synchronous burst mode memory devices are not supported.
MPMC_SC3
MPMC Static Config 3
Offset
260H
Reset Value
0H
5HV
:3 %(
5HV
UZ UZ
%/ &&
5H
(: 6 3 5HV 30 V 0:
UZ UZ UZ
UZ
Field
Bits
Type
Description
Res
31:21
-
Reserved
WP
20
rw
Write Protect
0B
Writes not protected (reset value on nPOR)
1B
Write protected
BE
19
Res
18:9
-
Reserved
EW
8
rw
Extended Wait
0B
Extended wait disabled (reset value on nPOR)
1B
Extended wait enabled
BLS
7
CCP
6
rw
Chip Select Polarity
The values of the chip select polarity on power-on-reset(nPOR) is
determined by the relevant MPMCSxPOL signal. This value can be
overridden by software. This field is Unaffected by AHB reset
(HRESETn).
0B
Active LOW chip select
1B
Active HIGH chip select
Res
5:4
-
Reserved
Data Sheet
UZ
Buffer Enable
0B
Write buffer disabled (reset value on nPOR)
1B
Write buffer enabled
Byte Lane State
0B
For reads all the bits in nMPMCBLSOUT[3:0] are HIGH(reset value
on nPOR).For writes the respective active bits
innMPMCBLSOUT[3:0] are LOW.
1B
For reads the respective active bits in nMPMCBLSOUT[3:0] are
LOW. For writes the respective active bits in nMPMCBLSOUT[3:0]
are LOW.
80
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
Field
Bits
Type
Description
PM
3
rw
Page Mode
0B
Disabled (reset value on nPOR)
1B
Async page mode four enabled.
Res
2
-
Reserved
MW
1:0
rw
Memory Width
The memory width field defines the data width of External IO CSX1.
00B 8 bit
01B 16 bit
10B 32 bit
11B Reserved.
Data Sheet
81
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Wen 1
Notes
1. Offset = 224H is for F_CS0_N .
2. The delay is (WAITWEN+1) x tHCLK.
MPMC_SWW1
MPMC Static Wait Wen 1
Offset
224H
Reset Value
0H
5HV
::(
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WWE
3:0
rw
Wait Write Enable
Delay from chip select assertion to write enable.
0000B One HCLK cycle delay between assertion of chip select and write
enable (reset value on nPOR)
0001 to 1111B =(n+1) HCLK cycle delay.
Data Sheet
82
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Wen 2
Notes
1. Offset = 244H refers to External IO CSX0.
2. The delay is (WAITWEN+1) x tHCLK.
MPMC_SWW2
MPMC Static Wait Wen 2
Offset
244H
Reset Value
0H
5HV
::(
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WWE
3:0
rw
Wait Write Enable
Delay from chip select assertion to write enable.
0000B One HCLK cycle delay between assertion of chip select and write
enable (reset value on nPOR)
0001 to 1111B =(n+1) HCLK cycle delay.
Data Sheet
83
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Wen 3
Notes
1. Offset = 264H refers to External IO CSX1.
2. The delay is (WAITWEN+1) x tHCLK.
MPMC_SWW3
MPMC Static Wait Wen 3
Offset
264H
Reset Value
0H
5HV
::(
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WWE
3:0
rw
Wait Write Enable
Delay from chip select assertion to write enable.
0000B One HCLK cycle delay between assertion of chip select and write
enable (reset value on nPOR)
0001 to 1111B =(n+1) HCLK cycle delay.
Data Sheet
84
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Oen 1
Notes
1. Offset = 228H is for F_CS0_N .
2. The delay is WAITOEN x tHCLK.
MPMC_SWO1
MPMC Static Wait Oen 1
Offset
228H
Reset Value
0H
5HV
:2(
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WOE
3:0
rw
Wait Output Enable
Delay from chip select assertion to output enable.
0000B No delay (reset value on nPOR)
0001 to 1111B n cycle delay
Data Sheet
85
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Oen 2
Notes
1. Offset = 248H refers to EXTERNAL IO CSX0.
2. The delay is WAITOEN x tHCLK.
MPMC_SWO2
MPMC Static Wait Oen 2
Offset
248H
Reset Value
0H
5HV
:2(
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WOE
3:0
rw
Wait Output Enable
Delay from chip select assertion to output enable.
0000B No delay (reset value on nPOR)
0001 to 1111B n cycle delay
Data Sheet
86
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Oen 3
Notes
1. Offset = 268H refers to External IO CSX1.
2. The delay is WAITOEN x tHCLK.
MPMC_SWO3
MPMC Static Wait Oen 3
Offset
268H
Reset Value
0H
5HV
:2(
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WOE
3:0
rw
Wait Output Enable
Delay from chip select assertion to output enable.
0000B No delay (reset value on nPOR)
0001 to 1111B n cycle delay
Data Sheet
87
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Rd 1
Notes
1. Offset = 22CH is for F_CS0_N .
2. For non-sequential reads, the wait state time is (WAITRD+1) x tHCLK.
MPMC_SWR1
MPMC Static Wait Rd 1
Offset
22CH
Reset Value
1FH
5HV
105:
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
NMRW
4:0
rw
Nonpage Mode Read Wait
Nonpage mode read wait states or asynchronous page mode read first
access wait state.
Nonpage Mode
00000 to 11110B (n+1) HCLK cycles for read accesses
11111B
32 HCLK cycles for read accesses(reset value on nPOR).
Asynchronous Page Mode Read, First Read Only
00000 to 11110B (n+1) HCLK cycles for burst read accesses
11111B
32 HCLK cycles for page read accesses (reset value on
nPOR)
Data Sheet
88
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Rd 2
Note: Offset = 24CH refers to External IO CSX0.
MPMC_SWR2
MPMC Static Wait Rd 2
Offset
24CH
Reset Value
1FH
5HV
105:
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
NMRW
4:0
rw
Nonpage Mode Read Wait
Nonpage mode read wait states or asynchronous page mode read first
access wait state.
Nonpage Mode
00000 to 11110B (n+1) HCLK cycles for read accesses
11111B 32 HCLK cycles for read accesses(reset value on nPOR).
Asynchronous Page Mode Read, First Read Only
00000 to 11110B (n+1) HCLK cycles for burst read accesses
11111B 32 HCLK cycles for page read accesses (reset value on nPOR)
Data Sheet
89
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Rd 3
Note: Offset = 26CH refers to External CSX1.
MPMC_SWR3
MPMC Static Wait Rd 3
Offset
26CH
Reset Value
1FH
5HV
105:
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
NMRW
4:0
rw
Nonpage Mode Read Wait
Nonpage mode read wait states or asynchronous page mode read first
access wait state.
Nonpage Mode
00000 to 11110B (n+1) HCLK cycles for read accesses
11111B 32 HCLK cycles for read accesses(reset value on nPOR).
Asynchronous Page Mode Read, First Read Only
00000 to 11110B (n+1) HCLK cycles for burst read accesses
11111B 32 HCLK cycles for page read accesses (reset value on nPOR)
Data Sheet
90
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Page 1
Notes
1. Offset = 230H is for F_CS0_N .
2. For asynchronous page mode read for sequential read, the wait state time for page mode accesses after the
first read is (WAITPAGE+1) x tHCLK.
MPMC_SWP1
MPMC Static Wait Page 1
Offset
230H
Reset Value
1FH
5HV
:36
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
WPS
4:0
rw
Asynchronous Page Mode Read After the First Access Wait States
Number of wait states for asynchronous page mode read accesses after
the first read.
00000 to 11110B (n+1) HCLK cycle read access time
11111B 32 HCLK cycle read access time (reset value on nPOR).
Data Sheet
91
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Page 2
Note: Offset = 250H refers to External CSX0.
MPMC_SWP2
MPMC Static Wait Page 2
Offset
250H
Reset Value
1FH
5HV
:36
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
WPS
4:0
rw
Asynchronous Page Mode Read After the First Access Wait States
Number of wait states for asynchronous page mode read accesses after
the first read.
00000 to 11110B (n+1) HCLK cycle read access time
11111B 32 HCLK cycle read access time (reset value on nPOR).
Data Sheet
92
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Page 3
Note: Offset = 270H refers to External CSX1.
MPMC_SWP3
MPMC Static Wait Page 3
Offset
270H
Reset Value
1FH
5HV
:36
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
WPS
4:0
rw
Asynchronous Page Mode Read After the First Access Wait States
Number of wait states for asynchronous page mode read accesses after
the first read.
00000 to 11110B (n+1) HCLK cycle read access time
11111B 32 HCLK cycle read access time (reset value on nPOR).
Data Sheet
93
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Wr 1
Notes
1. Offset = 234H is for F_CS0_N .
2. The wait state time for write accesses after the first read is WAITWR x tHCLK.
MPMC_SWWR1
MPMC Static Wait Wr 1
Offset
234H
Reset Value
1FH
5HV
::6
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
WWS
4:0
rw
Write Wait States
SRAM wait state time for write accesses after the first read.
00000 to 11110B (n+2) HCLK cycle write access time
11111B 33 HCLK cycle write access time (reset value on nPOR).
Data Sheet
94
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Wr 2
Note: Offset = 254H refers to external CSX0.
MPMC_SWWR2
MPMC Static Wait Wr 2
Offset
254H
Reset Value
1FH
5HV
::6
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
WWS
4:0
rw
Write Wait States
SRAM wait state time for write accesses after the first read.
00000 to 11110B (n+2) HCLK cycle write access time
11111B 33 HCLK cycle write access time (reset value on nPOR).
Data Sheet
95
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Wr 3
Note: Offset = 274H refers to External CSX1.
MPMC_SWWR3
MPMC Static Wait Wr 3
Offset
274H
Reset Value
1FH
5HV
::6
UZ
Field
Bits
Type
Description
Res
31:5
-
Reserved
WWS
4:0
rw
Write Wait States
SRAM wait state time for write accesses after the first read.
00000 to 11110B (n+2) HCLK cycle write access time
11111B 33 HCLK cycle write access time (reset value on nPOR).
Data Sheet
96
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Turn 1
Notes
1. Offset = 238H is for F_CS0_N .
2. Bus turnaround time is (WAITTURN+1) x tHCLK.
MPMC_SWT1
MPMC Static Wait Turn 1
Offset
238H
Reset Value
FH
5HV
:$,7785
1
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WAITTURN
3:0
rw
Bus Turnaround Cycles
00000 to 1110B (n+1) HCLK turnaround cycles
1111B 16 HCLK turnaround cycles (reset value on nPOR).
Data Sheet
97
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Turn 2
Note: Offset = 258H refers to External CSX0.
MPMC_SWT2
MPMC Static Wait Turn 2
Offset
258H
Reset Value
FH
5HV
:$,7785
1
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WAITTURN
3:0
rw
Bus Turnaround Cycles
00000 to 1110B (n+1) HCLK turnaround cycles
1111B 16 HCLK turnaround cycles (reset value on nPOR).
Data Sheet
98
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
MultiPort Memory Controller (MPMC)
MPMC Static Wait Turn 3
Note: Offset = 278H refers to External CSX1.
MPMC_SWT3
MPMC Static Wait Turn 3
Offset
278H
Reset Value
FH
5HV
:$,7785
1
UZ
Field
Bits
Type
Description
Res
31:4
-
Reserved
WAITTURN
3:0
rw
Bus Turnaround Cycles
00000 to 1110B (n+1) HCLK turnaround cycles
1111B 16 HCLK turnaround cycles (reset value on nPOR).
Data Sheet
99
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
6
Ethernet Switch Controller
Ethernet Switch Controller
The following chapter describes the Ethernet Switch controller functions of the ADM5120P/PX.
6.1
Switch Engine
The switch engine description:
6.1.1
Hashing Function
ADM5120P/PX provides an embedded 1K MAC address look-up table to implement address recognition. The
entries of the hashing table are calculated by direct mapping or by an XOR function to produce a 10-bit hashing
address entry.
6.1.2
Learning Process
The address learning process is composed of the source address (SA) of packets and the hashing function.
ADM5120P/PX will compare the SA of each incoming packet:
•
•
If the source address of an incoming packet is the same as the source MAC address table, then the aging
status and port number will be updated.
If the source address is different from the source MAC address table (mean address collision), then no learning
process will occur.
Exceptional cases of address learning:
•
•
•
•
•
The packets have errors
The port learning has been disabled
Address collision
The source address is multicast
The packets are from the CPU
6.1.3
Routing
When a packet comes from port A, ADM5120P/PX will compare its destination MAC address with the MAC
address in the MAC address lookup table. If the address is the same and port is port A this means that the packet
is a local packet, it is thus discarded. If the address is the same but port numbers are different, the packet is a
unicast packet, and will be forwarded to the assigned port. If the incoming packet is a broadcasted one, a multicast
one, or an unknown one (i.e. the destination address cannot be found in the MAC address lookup table), then the
routing scheme will broadcast it to all ports.
If the MAC address is a VLAN address, then the packet will be routed to the CPU port. The VLAN address is
programmed by the CPU, but not from address learning.
6.1.4
Forwarding
ADM5120P/PX provides a store-and-forward method as a forwarding scheme. Each outgoing packet, including
“to-CPU” packets, will be stored,first in the buffer, and then directly sent to the assigned port or CPU via the DMA.
However, only the good and non-local packets will be sent.
6.1.5
Buffer Management
The buffer memory is embedded in ADM5120P/PX for the switch operations, which are designed based on output
queuing and dynamic shared memory management architecture. It will assign buffer resources based on the traffic
status. In addition, this efficiency method can avoid the problem of Head-on-Line (HOL) blocking and cause better
transmitting performance.
Data Sheet
100
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
6.1.6
Ethernet Switch Controller
Flow Control
The on/off status for flow control depends on the global empty buffer count and per-port waiting-transmit count.
Based on this intelligent scheme, if the packet transmits to a destination port that is full, then the flow control is
turned on. In this situation, the full condition is released, including packets transmitted out or disabled. The flow
control is then turned off.
ADM5120P/PX does not allow flow control to the CPU, i.e.. it never sends the flow control packets to the CPU port,
so the firmware needs to monitor the buffer status to prevent packet loss.
6.1.7
Full Duplex
In full duplex flow control, ADM5120P/PX follows IEEE 802.3x standards. If a PAUSE frame is received from a
certain port, it will stop the port transmission of packets until the timer times out or another PAUSE frame with zero
time is received. If the buffer is full and is in full-duplex mode, ADM5120P/PX will send a PAUSE frame with the
maximum value, to defer the receiving packet. When enough buffer space is released, the PAUSE frame with zero
delay is sent.
•
Pause Frame must meet all of the following specs:
– Right DA: DA=0180c2000001 or unicast MAC address belongs to the CPU
– Right type field = 8808
– Right op-code = 0001
– Right CRC
6.1.8
Half Duplex
In half-duplex operation, ADM5120P/PX supports a back pressure feature. If free blocks in the buffer memory are
below the threshold, a jam packet (jam mode) is sent to the connected segment, regardless of routing decisions.
6.1.9
Packet Priority and Class of Service (CoS)
ADM5120P/PX can set the packets as high priority via registers as follows:
•
•
•
•
Port based priority, refer to register Priority Control bits [5:0]
VLAN tag, refer to registers VLAN Priority
TCP/IP TOS/DS, refer to registers TOS Enable, TOS Map 0 and TOS Map 1
Customer defined type, refer to registers Custom Priority 1 and Custom Priority 2
The priority setting by port means that all the packets received by the port will be priority frames. ADM5120P/PX
can also judge the priority of frames by checking the specific bits of VLAN tag or TCP/IP TOS/DS in the frame or
the customer defined type.
It will determine the packet priority. First it will check if the packet type meets VLAN or TCP/IP. Then, it will check
whether the value of the VLAN tag or the TCP/IP TOS/DS field meets the registers setting. Depending on these
two conditions, the scheme of weighted round robin can determine the high and low priority of frames, and thus
set the transmitting order.
ADM5120P/PX provides a function to improve the delay-time sensitive traffic in the flow-control condition. When
the port receives a priority frame, the back pressure & 802.3x flow control can be turned off until no priority frame
occurs within 1 or 2 seconds, then turned back on again. So it can prevent the jitter caused by the flow control and
give a better timing-variation result for the priority traffic. This is a register programmable function.
All the packets from the CPU port will be treated as high priority for the switch ports and the best effort result for
the CPU traffic will be provided.
6.1.10
VLAN
ADM5120P/PX supports a seven port-grouping VLAN. Each of the VLAN will be treated as isolated ports.For the
VLAN grouping setting, refer to the registers VLAN Group I and VLAN Group II.
Data Sheet
101
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Ethernet Switch Controller
ADM5120P/PX provides the VLAN MAC address function, if the packet is assigned with the VLAN address as its
destination MAC address, then this packet will be forwarded to the CPU via DMA.
For example, port0 is the WAN port. The others are the LAN ports, then the WAN ports are set as VLAN1 and the
others set as VLAN2. The different MAC addresses for the VLAN1/2 are programmed into the address table. Then
if the LAN ports receive packets with VLAN2 addresses, the packets will be forward to the CPU via DMA. After
processing the packets (like NAT), the CPU can forward the packets to VLAN1.
6.1.11
Address Table Access
ADM5120P/PX provides the access for the embedded MAC address.
•
•
Read - refer to the registers Search CMD, Address ST0 and Address St1 Issue the search-start command.
ADM5120P/PX will automatically search the embedded address table and report the valid one only. If at the
end of a table, it will also report the status.
Write - refer to registers MAC Write Address 0 and MAC Write Address 1 Fill in the write address and other
information, like port number (or VLAN number), age-time (or static), then issue the write command and wait
for the write done bit.
6.1.12
Address Security
The ADM5120P/PX supports the source MAC address security function, register Port Conf1(B+2C) bits [31:26].
It can check all-incoming packets in the enable ports – find if the source MAC exists in the MAC address table or
not, if not, discard the packets and report the status, register Port St(B+18) bits [5:0].
6.1.13
Bandwidth Control Function
ADM5120P/PX can provide the RX/TX separated bandwidth control (or traffic shaping) function, which can be
programmed to 64 kbit / 128 kbit / 256 kbit / 512 kbit / 1 Mbit / 4 Mbit / 10 Mbit. Refer the registers Bandwidth
Control 0 and Bandwidth Control 1.
In a fixed period, ADM5120P/PX will count the per port RX and TX byte number, and compare with the bandwidth
control threshold. If it is over this threshold, ADM5120P/PX will turn on the proprietary scheme to control the RX/TX
behavior.
6.1.14
MII Port
The MII port can be programmed for the following: AN monitor on/off, force speed/duplex/flow-control, which can
be set by Switch Control Register Port Conf2(B+30).The MII direction is also programmable for the following:
connect to PHY or MAC, which can be set by Switch Control Register Port Conf2(B+30).The default MII mode is
normal mode that is ‘connect to PHY’. When it is configured to Reverse MII mode. The ADM5120P/PX will output
TXC, RXC, CRS and COL. The signals direction will change, and suggest the connection as below:
Table 31
Connection between ADM5120P/PX and MAC Controller
5120P Signal
MAC Signal
RXC
RXC
TXE
RXDV
TXD
RXD
RXDV
TXEN
RXD
TXD
COL
COL
CRS
CRS
Data Sheet
102
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
6.2
Ethernet Switch Controller
DMA Function Description
The DMA function provides the packets with transmit and receive to/from CPU. There are two priority queues in
each path -- transmit and receive. The start address is defined by the base address registers. You can refer to
registers in Send High Base Address, Send Low Base Address, Receive High Base Address and Receive
Low Base Address for details. Every queue is a ring architecture. See the tables for details.
When the packet is put on the data buffer and send descriptor is prepared, software can trigger the DMA to move
the data to the internal buffer by setting the Send Trigger register.
Data Sheet
103
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
6.2.1
Ethernet Switch Controller
Send Descriptors Content
If CPU sends the packet to a switch, either LAN or WAN, then the ‘send descriptors’ are used as follows:
Bit
Bit[31]
Type
Bit[28]
Bit[24:0]
Remark
Control
Function
Own bit
Bit
Bit[31]
Type
Control
Function
buffer2_enable
Controlled by CPU
except Own-bit
Ring end flag
buffer1_address[24:0]
Bit[24:0]
Remark
Controlled by CPU
buffer2_address[24:0]
Bit
Bit[10:0]
Remark
Type
Control
Controlled by CPU
Function
buffer1_length[10:0]
Bit
Bit[31]
Type
Control
Function
append_chksum
6.2.1.1
Control
•
•
•
•
•
Bit[26:16]
Bit[13:8]
Bit[5:0]
Remark
Controlled by CPU
pkt-length[10:0]
force destiport[5:0]
To_VLAN[5:0]
Own Bit:
– If 0, the descriptor belongs to CPU. After the data is put in the buffer and control bits are set, this bit will
change to 1 to indicate that SW can process this packet.
– If 1, the descriptor is for SW, and after the data is taken away, then it is loaded to SW data buffer, the bit will
be then set to 0.
Ring end:
– If 1, the descriptor is the last one, the next descriptor needs to return to the base address.
Buffer information:
– Each descriptor can support two buffers.
– The buffer address can be any byte alignment.
– Buffer1 has length information, if packet size is larger than buffer1 size, then get the rest of the data from
buffer2.
– Buffer address must be valid when a descriptor belongs to a switch, the switch engine will not check the
address status.
– Buffer2 has an enable bit to control whether the address is valid or not.
– If the buffer2 is disabled and buffer1 is not long enough, then the remaining data will not be padded 0 to
make the packet meet 64-bytes standard.
Append_chksum: need to append the IP (0800H) and PPPoE (8864H) packets IP-checksum by hardware
– The packet checksum field must be pre-filled with all 0’s
Packet length: the packet length in bytes, excluding CRC if CRC is not padded. (See the register, CPUp_conf)
– Auto-padding: the engine can automatically pad the 0 into the packet which data size is less than 60 B (or
64). The setting example: buffer 1 size=14, buffer 2 disable, the pkt length=60 (or 64 without CRC padding).
Data Sheet
104
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
•
•
Ethernet Switch Controller
Force desti-port[5:0]: the packet needs force forwarding to designated ports, and it is the highest priority of
routing. If forced, then ignore the routing and To_VLAN flag.
To_VLAN[5:0]: the bit-map, the packet forwards to the designated VLAN group. Use this flag to control the
packets to LAN, WAN, or HPNA ports.
6.2.2
Receive Descriptors Content
If switch sends the packet to CPU, either LAN or WAN, then the ‘receive descriptors’ are used as follows:
Bit
Bit[31]
Bit[28]
Type
Bit[24:0]
Remark
Control
Function
Own bit
Bit
Bit[31]
Type
Control
Function
buffer2_enable
Controlled by CPU
except Own-bit
Ring end flag
buffer1_address[24:0]
Bit[24:0]
Remark
Controlled by CPU
buffer2_address[24:0]
Bit
Bit[10:0]
Remark
Type
Control
Controlled by CPU
Function
buffer1_length[10:0]
Bit
[26:16]
Type
Packet status
Function
pktlength[10:0]
6.2.2.1
Control
•
•
[14:12]
[5:4]
[3]
[2]
[1:0]
Remark
Updated
by switch
Source
port
number
00: UC01: IP
MC10: BC checksum
fail
VLAN tag
00:
0800H01:
8864H11,
10:
reserved
Own bit:
– If 0, the descriptor belongs to CPU.
– If 1, the descriptor is released to the WAN MAC or to the LAN SW, which means it can store the incoming
packet based on the buffer address. If this is done, change the bit to 0.
Buffer information:
– Each descriptor can support two buffers.
– The buffer address can be any byte alignment.
– Buffer1 has length information, if packet size is over the buffer1 size, then put the rest of the data into
buffer2.
– Buffer1 address must be valid when descriptor belongs to switch.
– Buffer2 has a enable bit to control whether the address is valid or not.
– The buffer2 size must be larger than the remaining data.
Data Sheet
105
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Ethernet Switch Controller
– If buffer2 is disabled and buffer1 does not enough space, then the remaining data will be dropped, and no
status reported.
6.2.2.2
•
•
•
Status
Packet length: the packet length in bytes including 4-byte CRC
Source port: the source port of packet
DA status:
– 00: UC, the packet is the forwarded UC packet
– 01: MC, the packet has 1 in the LSB of first byte of DA
– 11: BC, the packet has DA=FFFFFFFFFFFF
– IP checksum fail: if 1 = the IP checksum result is error
Note: Only checked if type = 0800H (IP) or 8864H (PPPoE)
•
•
The VLAN tagged frame status (type = 8100H)
Packet type:
– 00: type = 0800H, IP
– 01: type = 8864H, PPPoE
– 10,11 reserved
Data Sheet
106
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
6.3
Ethernet Switch Controller
Switch Control Register Map
Although some registers may be marked with a certain type, it may be possible that some bits in this register are
different. This is explained in the register description.
Table 32
Registers Address Space
Module
Base Address
End Address
Note
Switch Control
1200 0000H
1200 0110H
–
Table 33
Registers Overview
Register Short Name
Register Long Name
Offset Address
Page Number
Code
Code
00H
110
Sft_Res
Software Reset
04H
111
Boot_D
Boot Done
08H
112
SW_Res
Software Reset
0CH
112
Gl_St
Global St
10H
112
PHY_St
PHY St
14H
113
Port_St
Port St
18H
114
Mem_Cont
Memory Control
1CH
116
SW_conf
SW Conf
20H
117
CPUp_conf
CPUp Conf
24H
119
Port_conf0
Port Conf0
28H
120
Port_conf1
Port Conf1
2CH
121
Port_conf2
Port Conf2
30H
122
Res_1
Reserved 1
34H
123
Res_2
Reserved 2
38H
124
Res_3
Reserved 3
3CH
124
VLAN_GI
VLAN Group I
40H
125
VLAN_GII
VLAN Group II
44H
126
Send_trig
Send Trigger
48H
126
Srch_cmd
Search CMD
4CH
126
ADDR_st0
Address ST0
50H
128
ADDR_st1
Address St1
54H
129
MAC_wt0
MAC Write Address 0
58H
129
MAC_wt1
MAC Write Address 1
5CH
129
BW_cntl0
Bandwidth Control 0
60H
130
BW_cntl1
Bandwidth Control 1
64H
131
PHY_cntl0
PHY Control 0
68H
132
PHY_cntl1
PHY Control 1
6CH
133
FC_th
Switch Control Threshold
70H
133
adj_port_th
Adj Port Threshold
74H
133
Port_th
Port Threshold
78H
135
PHY_cntl2
PHY Control 2
7CH
135
PHY_cntl3
PHY Control 3
80H
136
Data Sheet
107
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 33
Ethernet Switch Controller
Registers Overview (cont’d)
Register Short Name
Register Long Name
Offset Address
Page Number
Pri_cntl
Priority Control
84H
137
VLAN_pri
VLAN Priority
88H
138
TOS_en
TOS Enable
8CH
139
TOS_map0
TOS Map 0
90H
139
TOS_map1
TOS Map 1
94H
139
Custom_pri1
Custom Priority 1
98H
140
Custom_pri2
Custom Priority 2
9CH
140
PHY_cntl4
PHY Control 4
A0H
142
Empty_cnt
Empty Control
A4H
142
Port_cnt_sel
Port Control Select
A8H
144
Port_cnt
Port Controller
ACH
145
Int_st
Int St
B0H
146
Int_mask
Interrupt Mask
B4H
147
GPIO_conf0
GPIO Conf 0
B8H
149
GPIO_conf2
GPIO Conf 2
BCH
149
Wdog_0
Watchdog 0
C0H
151
Wdog_1
Watchdog 1
C4H
152
Swap_in
Swap In
C8H
153
Swap_out
Swap Out
CCH
153
send_Hbaddr
Send High Base Address
D0H
153
send_Lbaddr
Send Low Base Address
D4H
154
rec_Hbaddr
Receive High Base Address
D8H
155
rec_Lbaddr
Receive Low Base Address
DCH
155
send_Hwaddr
Send High Working Address
E0H
156
send_Lwaddr
Send Low Working Address
E4H
156
rec_Hwaddr
Receive High Working Address
E8H
157
rec_Lwaddr
Receive Low Working Address
ECH
157
Timer_int
Timer Interrupt
F0H
158
Timer
Timer
F4H
159
Res_4
Reserved 4
F8H
160
Res_5
Reserved 5
FCH
161
port0_LED
Port 0 LED
100H
161
port1_LED
Port 1 LED
104H
162
port2_LED
Port 2 LED
108H
164
port3_LED
Port 3 LED
10CH
165
port4_LED
Port 4 LED
110H
166
The register is addressed wordwise.
Data Sheet
108
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Table 34
Mode
Ethernet Switch Controller
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
Basic Access Types
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read/write
virtual
rwv
Physically, there is no new register in
the generated register file. The real
readable and writable register resides
in the attached hardware.
Register is read and writable by SW (same
as rw type register)
read
r
Register is written by HW (register
Value written by SW is ignored by HW; that
between input and output -> one cycle is, SW may write any value to this field
delay)
without affecting HW behavior
read only
ro
Same as r type register
Same as r type register
read virtual
rv
Physically, there is no new register in
the generated register file. The real
readable register resides in the
attached hardware.
Value written by SW is ignored by HW; that
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
write
w
Register is written by software and
affects hardware behavior with every
write by software.
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
write virtual
wv
Physically, there is no new register in Register is writable by SW (same as w type
register)
the generated register file. The real
writable register resides in the attached
hardware.
read/write
hardware
affected
rwh
Register can be modified by hardware
and software at the same time. A
priority scheme decides, how the value
changes with simultaneous writes by
hardware and software.
Table 35
Registers Clock Domains
Clock Short Name
Description
–
–
Data Sheet
Register can be modified by HW and SW,
but the priority SW versus HW has to be
specified.
SW can read the register.
109
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
6.3.1
Ethernet Switch Controller
Registers Description
Code
Code
Code
Offset
00H
Reset Value
12085120H
,& ,& '& '& 1$
5HV 3. 6, 6( 6, 6( % 5HV &/.6
UR UR UR UR UR UR
UR
3&
UR
UR
Field
Bits
Res
31:30
PK
29
ro
Package type
0B
BGA
1B
208 PQFP
ICSI
28
ro
Icache Size
0B
1 Way
1B
2 Ways
ICSE
27
ro
Icache Set
0B
4K per way
1B
2K per way
DCSI
26
ro
Dcache Size
0B
1 Way
1B
2 Ways
DCSE
25
ro
Dcache Set
0B
4K per way
2K per way
1B
NAB
24
ro
NAND Boot
Configured in the NAND flash boot.
Res
23:22
CLKS
21:20
ro
Clock SPD
The PLL setting.
00B
175 MHz (Default)
01B
Reserved
1xB
Reserved
REV
19:16
ro
Revision
Revision code = 1000
PC
15:0
ro
Product Code
Product code = 5120H
Data Sheet
Type
5(9
Description
Reserved
Not Applicable.
Reserved
110
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Ethernet Switch Controller
Software Reset
Note: Whenever you write the register offset 04H, the SftReset will be active.
Sft_Res
Software Reset
Offset
04H
Reset Value
1H
65
ZR
Field
Bits
Type
Description
SR
31:0
wo
Software Reset
Do Software reset when write, reset all logic, PHY and memory, and
down load the NAND flash content again. Same as hardware reset.
Data Sheet
111
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Ethernet Switch Controller
Boot Done
Boot_D
Boot Done
Offset
08H
Reset Value
0H
5HV
%2
UZ
Field
Bits
Res
31:1
BO
0
Type
Description
Reserved
rw
Boot
1B
The software boot process is done and the address table can
return to the switch controller.
Switch Reset
Note: Whenever you write the register offset 0CH the SWReset will be active.
SW_Res
Software Reset
Offset
0CH
Reset Value
1H
6:5
ZR
Field
Bits
Type
Description
SWR
31:0
wo
Switch Reset
Do Switch reset when write, including Switch engine, data-buffer, link
table, and PHY excluding address table. (Recommend stop PHY before
reset switch).
Global St
Gl_St
Global St
Data Sheet
Offset
10H
112
Reset Value
400H
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Ethernet Switch Controller
5HV
,& '& 5H
3 3 V
6%
UR UR
UR
Type
$0 ,& ,&'7 '& '&'7 $7 0& /% '%
76 7
)
7
) %5 %5 ) 5
UR UR
UR
UR
UR
UR UR UR UR
Field
Bits
Description
Res
31:23
ICP
22
DCP
21
Res
20
SB
19:11
ro
Skip Blocks
The number of block is skipped up to 64 blocks.
AMTS
10
ro
All Embedded Memory Test Completed
1B
Complete
ICTTF
9
ro
Icache Tag Test Fail
The memory of I-cache tag.
0B
Pass
ICDTF
8:7
ro
Icache Data Test Fail
Bit 8 and Bit 7 are respectively for the upper and lower 32-bit of I-cache
memory for data.
00B Pass
DCTTF
6
ro
Dcache Tag Test Fail
The memory of D-cache tag.
0B
Pass
DCDTF
5:4
ro
Dcache Data Test Fail
Bit 5 and Bit 4 are respectively for the upper and lower 32-bit of D-cache
memory for data.
00B Pass
ATBR
3
ro
Address Table BIST Result
0B
Pass
MCBR
2
ro
MC Table BIST Result
0B
Pass
LBF
1
ro
Link Table BIST Result
0B
Pass
DBR
0
ro
Data Buffer BIST Result
0B
Pass
Reserved
Not Applicable.
ro
Icache Portion
For debugging purpose of embedded SRAM.
Dcache Portion
For debugging purpose of embedded SRAM.
Reserved
PHY St
PHY_St
PHY St
Data Sheet
Offset
14H
113
Reset Value
0H
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Ethernet Switch Controller
5HV
0,
,
)&67
UR
UR
5HV
5H
V 0,,6
'83
UR
Type
UR
63
0,
5HV ,)
UR
UR
3+ one cycle is, SW may write any value to this field
delay)
without affecting HW behavior
read only
ro
Same as r type register
Same as r type register
read virtual
rv
Physically, there is no new register in
the generated register file. The real
readable register resides in the
attached hardware.
Value written by SW is ignored by HW; that
is, SW may write any value to this field
without affecting HW behavior (same as r
type register)
write
w
Register is written by software and
affects hardware behavior with every
write by software.
Register is writable by SW. When read, the
register does not return the value that has
been written previously, but some constant
value instead.
write virtual
wv
Physically, there is no new register in Register is writable by SW (same as w type
register)
the generated register file. The real
writable register resides in the attached
hardware.
read/write
hardware
affected
rwh
Register can be modified by hardware
and software at the same time. A
priority scheme decides, how the value
changes with simultaneous writes by
hardware and software.
Table 47
Registers Clock Domains
Clock Short Name
Description
–
–
Data Sheet
Register can be modified by HW and SW,
but the priority SW versus HW has to be
specified.
SW can read the register.
194
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
8.4.1
USB 1.1 Host Controller
USB Control Status Registers Description
Host processors can only access USB 1.1 host/device controller registers with double word (32 bits) reads or
writes on double word boundaries.
General Control
GC
General Control
Offset
00H
Reset Value
0H
'0 6, 8+
65 $$ 5 )(
5HV
UZ UZ UZ UZ
Field
Bits
Res
31:4
SR
3
DMAA
2
DMA Arbitration Control, Both Modes
0B
Receive = Transmit (1:1)
1B
Receive > Transmit
SIR
1
Software Interrupt Request, Both Modes
When this bit is set to 1, the controller’s interrupt pin becomes active.
Reading this bit always returns zero.When SW_INT in interrupt is clear,
this bit is clear as well.
UHFE
0
USB Host Function Enable, Both Modes
This bit enables the USB host functions, when 1’b1, the controller acts as
USB host.
Data Sheet
Type
Description
Reserved
Not Applicable.
rw
Software Reset, Both Modes
Setting this bit resets the device controller to its initial state. This bit is
auto-cleared after reset. Writing a 0 to this bit takes no effect.
195
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Interrupt Status
INT_S
Interrupt Status
Offset
04H
Reset Value
0H
,1 )$ 6:
7$ 7, ,
5HV
5HV
UR UZF
UZF
7'
&
)1
,1 %$ 5H 5H 5( 62
2 62 6
%, V V 6, ),
5HV
UZF
UZF
UZF
UZF
UZF
5HV
UZF
UZF
Field
Bits
Type
Description
INTA
31
ro
Interrupt Active
When this bit is set, it indicates that at least one unmasked interrupt
status is set.
FATI
30
rw1c
Fatal Interrupt, Device Mode
Reserved.
Host mode:
1B
Fatal system bus error occurs
SWI
29
Software Interrupt, Both Modes
1B
Software Interrupt. This bit is set when software set one to
SW_INT_REQ 00H, and is cleared after software writes one to this
bit.
Res
28:26
Reserved
Not Applicable
Res
25:21
Reserved
Not Applicable
TDC
20
Res
19:12
FNO
11
SO
10
Scheduling Overrun
This bit is set when USB schedules for current frame overruns.
INSMI
9
Root Hub Status Change
1B
Detected device insertion or remove. This bit will only be set for the
device or hub, which is attached to host directly.
BABI
8
Babble Detected, Host Mode
1B
Detected babble
Res
7
Reserved
Not Applicable
Res
6
Reserved
Not Applicable
Data Sheet
rw1c
A TD is Completed
Reserved
Not Applicable
rw1c
Frame Number Overflow
This bit is set when the MSB of the frame number changes.
196
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Field
Bits
Type
Description
RESI
5
rw1c
Resume Detected
1B
USB resume event is detected. Controller sets this bit to one when
resume signal is detected on USB bus.
SOFI
4
SOF Transmitted/Received, Host Mode
1B
Issue a SOF token. The frame number value is stored in 1CH
Frame Number
Res
3:0
Reserved
Not Applicable
Interrupt Enable
INT_E
Interrupt Enable
Offset
08H
Reset Value
0H
,1
7(
,170
UZ
Field
Bits
INTE
31
INTM
30:0
Data Sheet
Type
Description
Interrupt Enable
0B
Disable the controller to assert interrupt
1B
Enable the controller to assert interrupt
rw
Interrupt Mask
Bits are set to allow the corresponding interrupts (bit 21:0 in Interrupt
Status register) to generate an interrupt request. And cleared to prevent
the interrupt from happening.
197
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Reserved 6
Res_6
Reserved 6
Offset
0CH
Reset Value
0H
5HVB
Field
Bits
Res_6
31:0
Type
Description
Reserved
Not Applicable.
Host General Control
H_Gen_Cntl
Host General Control
Offset
10H
Reset Value
0H
'0
$( %866
5HV
UZ
Field
Bits
Res
31:3
DMAE
2
BUSS
1:0
Type
UZ
Description
Reserved
Not Applicable.
rw
USB Host DMA Enable
This bit enables the host controller DMA functionality. When enabled the
DMA will start to fetch the descriptor for processing.
USB Bus State
A transition to USB operational state will cause the SOF generation to
start 1 ms later.
00B USB reset state.
01B USB resume state
10B USB operational state
11B USB suspend state.
Reserved 7
Data Sheet
198
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Res_7
Reserved 7
Offset
14H
Reset Value
0H
5HVB
Field
Bits
Res_7
31:0
Data Sheet
Type
Description
Reserved
Not Applicable
199
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
SOF Frame Interval
SOF_FI
SOF Frame Interval
Offset
18H
Reset Value
2EDFH
),
7
)6/'3
UR
UZ
5HV
),
UZ
Field
Bits
Type
Description
FIT
31
ro
Frame Interval Toggle
Software toggles this bit whenever it loads a new value to
FM_INTERVAL.
FSLDP
30:16
rw
FS Largest Data Packet
This field specifies a value which is loaded into the Largest Data Packet
Counter at the beginning of each frame. The counter value represents the
largest amount of data in bits which can be sent or received by the HC in
a single transaction at any given time without causing scheduling
overrun. The field value is calculated by the software.
Res
15:14
FI
13:0
Data Sheet
Reserved
Not Applicable
rw
Frame Interval
This specifies the interval between two consecutive SOFs in bit times.
The nominal value is set to be 11,999. Software should store the current
value of this field before resetting HC.
200
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
SOF Frame Number
SOF_FN
SOF Frame Number
Offset
1CH
Reset Value
0H
)5 5H
7 V
)5
)1
UZ UR
UZ
UZ
Field
Bits
Type
Description
FRT
31
rw
Frame Remaining Toggle
This bit is loaded from the FM_INTERVAL_TOG field of FM_INTERVAL
whenever FM_REMAIN remaining reaches 0. This bit is used by software
for the synchronization between FM_INTERVALand FM_REMAIN.
Res
30
ro
Reserved
FR
29:16
rw
Frame Remaining
This counter is decremented at each bit time. When it reaches zero, it is
reset by loading the frame Interval value specified in FM_INTERVAL at
the next bit time boundary. When entering the USBOPERATIONAL state,
HC re-loads the content with the FM_INTERVAL of and uses the updated
value from the next SOF.
FN
15:0
Data Sheet
Frame Number
This field is a 16-bit counter. It provides a timing reference among events
happening in the Host Controller and the Host Controller Driver. The Host
Controller Driver may use the 16-bit value specified in this register and
generate a 32-bit frame number without requiring frequent access to the
register.
201
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Reserved 0
RR0
Reserved 0
Offset
20H
Reset Value
0H
5HV
Field
Bits
Res
31:0
Type
Description
Reserved
Not Applicable.
Similar Registers
Other Reserved Registers have the same structure and characteristics as Reserved 0; the names and offset
addresses are listed in Table 48.
Table 48
Reserved Registers
Register Short Name
Register Long Name
Offset Address
RR_1
Reserved Register 1
21H
RR_2
Reserved Register 2
22H
...
...
...H
RR_76
Reserved Register 76
6CH
Data Sheet
202
Page Number
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Low Speed Threshold
Low_STh
Low Speed Threshold
Offset
70H
Reset Value
628H
5HV
/67
U
Field
Bits
Type
Description
LST
11:0
r
Low Speed Threshold
This field contains a value which is compared to the FM_REMAIN field
prior to initiating a Low Speed transaction. The transaction is started only
if FM_REMAIN > = this field. The value is calculated by HCD with the
consideration of transmission and setup overhead.
Res
31:12
Reserved
RH Descriptor
RH_D
RH Descriptor
Offset
74H
Reset Value
1H
&5 '5 2& /3 2& /3
5HV :(:( ,& 6& , 6
UR
UZ UZ UZ UZ UZ UZ
33&0
5HV
12 2& 13 36
&3 30 6 0
180B3
UZ
UR
UZ UZ UZ UZ
UR
Field
Bits
Type
Description
Res
31:30
ro
Reserved
Not Applicable.
Data Sheet
203
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Field
Bits
Type
Description
CRWE
29
rw
Clear Remote Wakeup Enable
0B
Has no effect.
1B
Clears Device Remove Wakeup Enable
DRWE
28
Device Remote Wakeup Enable
This bit enables a Connect Status Change bit as a resume event, causing
a USBSUSPEND to USBRESUME state transition and setting the
Resume Detected interrupt.
0B
Connect Status Change is not a remote wakeup event
1B
Connect Status Change is a remote wakeup event
OCIC
27
Over Current Indication Change
This bit is set by hardware when a change has occurred to the OCI field
of this register. The HCD clears this bit by writing a 1. Writing a 0 has no
effect.
LPSC
26
Local Power Switch Change (read)
This bit is always read as 0.
Set Global Power (write)
In global power mode ( PSM =0), This bit is written to 1 to turn on power
to all ports (clearPPS). In per-port power mode, it sets PPS only on ports
whose PPCM bit is not set. Writing a 0 has no effect.
OCI
25
Over Current Indication
This bit reports overcurrent conditions when the global reporting is
implemented. When set, an overcurrent condition exists. When cleared,
all power operations are normal. If per-port overcurrent protection is
implemented this bit is always 0
LPS
24
Local Power Switch (read)
This bit is always read as 0.
Clear Global Power (write)
In global power mode (PSM =0), This bit is written to 1 to turn off power
to all ports (clearPPS). In per-port power mode, it clears PPS only on
ports whose PPCM bit is not set. Writing a 0 has no effect.
PPCM
23:16
Port Power Control
Each bit indicates if a port is affected by a global power control command
when PSM is set. When set, the port's power state is only affected by perport power control (Set/ClearPortPower). When cleared, the port is
controlled by the global power (switchSet/ClearGlobalPower ). If the
device is configured to global switching mode (PSM =0), this field is not
valid.
Bit 0: Reserved
Bit 1: Ganged-power mask on Port #1
Bit 2: Ganged-power mask on Port #2
...
Bit7: Ganged-power mask on Port #7
Res
15:12
Data Sheet
ro
Reserved
Not Applicable
204
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Field
Bits
Type
Description
NOCP
11
rw
No Over Current Protect
This bit describes how the overcurrent status for the Root Hub ports are
reported. When this bit is cleared, the OCPM field specifies global or perport reporting.
0B
Over-current status is reported collectively for all downstream ports
1B
No overcurrent protection supported
OCPM
10
Over Current Protect Mode
This bit describes how the overcurrent status for the Root Hub ports are
reported. At reset, this fields should reflect the same mode as PSM. This
field is valid only if the NOCP field is cleared.
0B
Over-current status is reported collectively for all downstream ports
1B
Over-current status is reported on a per-port basis
NPS
9
No Power Switch
These bits are used to specify whether power switching is supported or
port are always powered. It is implementation-specific. When this bit is
cleared, the PSM specifies global or per-port switching.
0B
Ports are power switched
1B
Ports are always powered on when the HC is powered on
PSM
8
Power Switch Mode
This bit is used to specify how the power switching of the Root Hub ports
is controlled. It is implementation-specific. This field is only valid if the
NPS field is cleared.
0B
All ports are powered at the same time
1B
Each port is powered individually. This mode allows portpower to
be controlled by either the global switch or per-port switching. If the
PPCM bit is set per-port switching. If the PPCM bit is set, the port
responds only to port power commands (Set/ClearPortPower). If
the port mask is cleared, then the port is controlled only by the
global power switch (Set/ClearGlobalPower ).
NUM_P
7:0
Data Sheet
ro
Number Port
205
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Port X Status
PX_St
Port X Status
Offset
78H
Reset Value
0H
5HV
35 2& 36 3( &6
6& ,& 6& 6& &
5HV
/6 33
'9 6
5HV
35 32 36 3( &&
6 &, 6 6 6
UR
UZ UZ UZ UZ UZ
UR
UZ UZ
UR
UZ UZ UZ UZ UZ
Field
Bits
Type
Description
Res
31:21
ro
Reserved
Not Applicable.
PRSC
20
rw
Port Reset Status Change
This bit is set at the end of the 10 ms port reset signal. The HCD writes a
1 to clear this bit. Writing a 0 has no effect.
0B
Port reset is not complete
1B
Port reset is complete
OCIC
19
Over Current Indicator Change
This bit is valid only if overcurrent conditions are reported on a per-port
basis. This bit is set when Root Hub changes the POCI bit. The HCD
writes a 1 to clear this bit. Writing a 0 has no effect.
0B
No change in POCI
1B
OCI has changed
PSSC
18
Port Suspend Status Change
This bit is set when the full resume sequence has been completed. This
sequence includes the 20 s resume pulse, LS EOP, and 3 ms re
synchronization delay. The HCD writes a 1 to clear this bit. Writing a 0 has
no effect. This bit is also cleared when RSC is set.
0B
Resume is not completed
1B
Resume completed
PESC
17
Port Enable Status Change
This bit is set when hardware events cause the PES bit to be cleared.
Changes from HCD writes do not set this bit. The HCD writes a 1 to clear
this bit. Writing a 0 has no effect.
0B
No change in PES
1B
Change in PES
Data Sheet
206
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Field
Bits
Type
Description
CSC
16
rw
Connect Status Change
This bit is set whenever a connect or disconnect event occurs. The HCD
writes a 1 to clear this bit. Writing a 0 has no effect. If CCS is cleared when
a SPR, SPE, or SPS write occurs, this bit is set to force the driver to reevaluate the connection status since these writes should not occur if the
port is disconnected.
Note: This bit is set only after a Root Hub reset to inform the system that
the device is attached.
0B
1B
No change in CCS
Change in CCS
Res
15:10
ro
Reserved
Not Applicable.
LSDV
9
rw
Low Speed Device Attached (read)
This bit indicates the speed of the device attached to this port. When set,
a Low Speed device is attached to this port. When clear, a Full Speed
device is attached to this port. This field is valid only when the
CurrentConnectStatus is set.
0B
Full speed device attached
1B
Low speed device attached
Clear Port Power (write)
The HCD clears the PortPowerStatus bit by writing a 1 to this bit. Writing
a 0 has no effect.
PPS
8
Port Power Status (read)
This bit reflects the port’s power status, regardless of the type of power
switching implemented. This bit is cleared if an overcurrent condition is
detected. HCD sets this bit by writing SPP or SGP. HCD clears this bit by
writing CPP or CGP. Which power control switches are enabled is
determined by PSM and PPCM[NDP] . In global switching mode (PSM
=0), only Set/ClearGlobalPower controls this bit. In per-port power
switching ( PSM =1), if the PPCM[NDP] bit for the port is set, only
Set/ClearPortPower commands are enabled. If the mask is not set, only
Set/ClearGlobalPower commands are enabled. When port power is
disabled, CCS,PES, PSS, and PRS should be reset.
0B
Port power is off
1B
Port power is on
Set Port Power (write)
The HCD writes a 1 to set the PPS bit. Writing a 0 has no effect.
Note: This bit is always reads 1 if power switching is not supported.
Res
Data Sheet
7:5
ro
Reserved
Not Applicable.
207
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Field
Bits
Type
Description
PRS
4
rw
Port Reset Status (read)
When this bit is set by a write to SPR, port reset signaling is asserted.
When reset is completed, this bit is cleared when PRSC is set. This bit
cannot be set if CCS is cleared.
0B
Port reset signal is not active
1B
Port reset signal is active
Set Port Reset (write)
The HCD sets the port reset signaling by writing a 1 to this bit. Writing a
0 has no effect. If CCS is cleared, this write does not set PRS, but instead
sets CSC. This informs the driver that it attempted to reset a disconnected
port.
Data Sheet
208
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Field
Bits
Type
Description
POCI
3
rw
Port Over Current Indicator (read)
This bit is only valid when the Root Hub is configured in such a way that
overcurrent conditions are reported on a per-port basis. If per-port
overcurrent reporting is not supported, this bit is set to 0. If cleared, all
power operations are normal for this port. If set, an overcurrent condition
exists on this port. This bit always reflects the overcurrent input signal.
0B
No overcurrent condition
1B
Overcurrent condition detected
Clear Suspend Status (write)
The HCD writes a 1 to initiate a resume. Writing a 0 has no effect. A
resume is initiated only if PSS is set.
PSS
2
Port Suspend Status (read)
This bit indicates the port is suspended or in the resume sequence. It is
set by a SSS write and cleared when PSSC is set at the end of the
resume interval. This bit cannot be set if CCS is cleared. This bit is also
cleared when PRSC is set at the end of the port reset or when the HC is
placed in the USBRESUME state. If an upstream resume is in progress,
it should propagate to the HC.
0B
Port is not suspended
1B
Port is suspended
Set Port Suspend (write)
The HCD sets the PSS bit by writing a 1 to this bit. Writing a 0 has no
effect. If CCS is cleared, this write does not set PSS; instead it sets CSC.
This informs the driver that it attempted to suspend a disconnected port.
PES
1
Port Enable Status (read)
This bit indicates whether the port is enabled or disabled. The Root Hub
may clear this bit when an overcurrent condition, disconnect event,
switched-off power, or operational bus error such as babble is detected.
This change also causes PESC to be set. HCD sets this bit by writing
SPE and clears it by writing CPE. This bit cannot be set when CCS is
cleared. This bit is also set, if not already, at the completion of a port reset
when RSC is set or port suspend when SSC is set.
Note: This informs the driver that it attempted to enable a disconnected
port.
0B
Port is disabled
1B
Port is enabled
Set Port Enable (write)
The HCD sets PortEnableStatus by writing a 1. Writing a 0 has no effect.
If CCS is cleared, this write does not set PES, but instead sets CSC.This
informs the driver that it attempted to enable a disconnected port.
CCS
0
Current Connect Status (read)
This bit reflects the current state of the downstream port.
0B
No device connected
1B
Device connected
Clear Port Enable (write)
The HCD writes a 1 to this bit to clear the PES. Writing a 0 has no effect.
The CCS is not affected by any write.
Note: This bit is always read 1 when the attached device is nonremovable
Data Sheet
209
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
USB 1.1 Host Controller
Host Descriptor Head Starting Address
HDHS_Ad
Host Descriptor Head Starting Address
Offset
80H
Reset Value
0H
'6&B$''5
5HV
UZ
UR
Field
Bits
Type
Description
DSC_ADDR
31:4
rw
Descriptor Chain Address
This field indicates the starting address of the host mode descriptor chain.
DMA read the descriptor from this location when it is first enabled.
Res
3:0
ro
Reserved
Data Sheet
210
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Electrical Characteristics
9
Electrical Characteristics
9.1
Absolute Maximum Ratings
Table 49
Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage
Input Voltage
VCC
VI
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
-0.5
–
1.9
V
–
-0.5
–
VCC
V
–
V
–
+0.3
Output Voltage
VO
-0.5
–
VCC
+0.3
Storage Temperature
Ambient Temperature
ESD Protection
TS
TA
VESD
-65
–
150
°C
–
-0
–
70
°C
–
-0
–
2000
V
–
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
9.2
DC Characteristics
Table 50
DC Characteristics
Parameter
Supply Voltage
I/O Supply Voltage
Power Supply Current
I/ O Power Supply Current
Input Low Voltage
Input High Voltage
Input Low Leakage Current
Input High Leakage Current
Output Low Voltage
Output High Voltage
Input Pin Capacitance
Pin Inductance
Data Sheet
Symbol
VCC
VIO_CC
ICC
IIO_CC
VIL
VIH
IILL
IIHL
VOL
VOH
CIP
LPI
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
1.7
1.8
1.9
V
–
3.0
3.3
3.6
V
–
–
–
–
mA
–
–
–
mA
VCC = 1.8 V
VCC = 3.3 V
-0.5
–
0.8
V
–
2.0
–
3.8
V
–
-10
–
10
µA
-10
–
10
µA
–
–
0.4
V
2.4
–
–
V
VIN = 0.8 V
VIN = 2.0 V
IOUT = 2~8 mA
IOUT = 2~-8 mA
5
–
8
pF
–
TBD
–
–
nH
–
211
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
9.3
AC Timing
9.3.1
SDRAM Interface
Electrical Characteristics
(Unit: ns, Min: best case, Max: worst case)
Table 51
SDRAM Interface Timing
Parameter
Symbol
tCK
Command/address setup delay time in tPS
Clock cycle time
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
–
11.4
–
ns
–
1.5
–
–
ns
–
1
–
–
ns
–
1.5
–
–
ns
–
1
–
–
ns
–
1.5
–
–
ns
–
1
–
–
ns
–
1.5
–
–
ns
–
1
–
–
ns
–
precharge stage
Command/address hold delay time in
precharge stage
tPH
Command/address setup delay time in tAS
active stage
Command/address hold delay time in
active stage
tAH
Command/address setup delay time in tWS
write stage
Command/address hold delay time in
write stage
tWH
Command/address setup delay time in tRS
read stage
Command/address hold delay time in
read stage
Data Sheet
tRH
212
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Figure 17
Precharge Command
Figure 18
Active Command
Data Sheet
Electrical Characteristics
213
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Figure 19
Write Command
Figure 20
Read Command
Data Sheet
Electrical Characteristics
214
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Electrical Characteristics
9.3.2
Memory Bus Read Timing
Figure 21
Memory Bus Read Timing
Note: T is the period of CLK_OUT (11.5 ns/87.5 MHz)
Table 52
Memory Bus Read Timing
Parameter
Data to CLK_OUT rising setup time
Data to CLK_OUT rising hold time
Address/F_CSX_N pulse width
Address/F_CSX_N to F_OE_N setup
Data Sheet
Symbol
tRDSU
tRDH
tAC
tAOE
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
TBD
–
–
–
TBD
–
–
–
–
(n+1)T –
–
–
nT
–
215
–
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Electrical Characteristics
9.3.3
Memory Bus Write Timing
Figure 22
Memory Bus Write Timing
Note: T is the period of CLK_OUT (11.5 ns/87.5 MHz)
Table 53
Memory Bus Write Timing
Parameter
Symbol
Address/CS to WE_N falling setup time tASU
Data to WE_N rising setup time
Data to WE_N rising hold time
WE_N pulse width
Data Sheet
tWDSU
tWDH
tWEP
Values
Unit
Note / Test Condition
Min.
Typ.
–
(n+1)T –
–
–
(n+1)T –
–
–
1T
–
–
–
(n+1)T –
–
216
Max.
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Package Outlines
10
Package Outlines
10.1
Plastic Quad Flat Package (P-FQFP) 208-pin
+0.08
0.15 -0.04
0˚...7˚
3.57 MAX.
0.25 MIN.
+0.28
3.32 -0.12
Dimensions in mm.
H
0.5
+0.07 2)
0.2 -0.03
0.88 ±0.15
208x
0.08 M A-B D C
0.1
C
51 x 0.5 = 25.5
31.2
28
1)
0.25 A-B D C 4x
Bottom View
0.2 A-B D H 4x
16
208
16
31.2
B
28
A
1)
D
208
R4
1
Index Marking
Heatslug
1) Does not include plastic or metal protrusion of 0.25 max. per side
2) Does not include dambar protrusion of 0.08 max. per side
Figure 23
Index Marking
RY
A
IN
IM
P
L
RE
GPF01107
P-FQFP-208-10 (Plastic Quad Flat Package)
Dimensions in mm.
Data Sheet
217
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Terminology
Terminology
A
AHB
Advance High performance Bus
ALE
Address Latch Enable
AN
Auto-Negotiation
APB
Advanced Peripheral Bus
ASB
Advanced System Bus
ASIC
Application Specific Integrated Circuit
B
BC
BroadCast
BP
Back Pressure
BPDU
Bridge Protocol Data Unit
BISS
Build In Self test error Skip
BIST
Build In Self Test
C
CLK
Clock
COL
Collision
CoS
Class of Service
CRC
Cyclic Redundancy Check
CRS
Carrier Sense
CSX
Chip Select for external I/O bank0
D
DFE
Decision Feedback Equalization
DMA
Direct Memory Access
F
FC
Flow Control
FIFO
First-In-First-Out
G
GND
Ground
GPIO
General Purpose I/O
GPIOL
GPIO of groupL
GPIOM
GPIO of groupM
GPSI
General Purpose Serial Interface
H
HOL
Head-on-Line
I
INTC
Interrupt Control Registers
INTX
Interrupt for external I/O bank0
IPG
Inter Packet Gap
IRQ
Interrupt ReQuest
J
JTAG
Data Sheet
Joint Test Action Group
218
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
Terminology
L
LSb
Least Significant Bit
LSB
Least Significant Byte
M
MAC
Media Access Control
MC
Multicast
MDC
Management Data Clock
MDIO
Management Data I/O
MDI
Medium dependent interface
MDIX
MDI Crossover
MII
Media Independent Interface
MIPS
Million Instructions Per Second
MMU
Memory Management Unit
N
NAT
Network Address Translation
NRZI
Non Return Zero Invert
NRZ
Non Return Zero
P
PCS
Physical Coding Sublayer
PHY
PHYsical Layer
PLL
Phase Locked Loop
PMA
Physical Medium Attachment
PMD
Physical medium Dependent
PQFP
Plastic Quad Flat Package
R
RISC
Reduced Instruction Set Computer
RX
Receive
RXD
Receive Data
RXDV
Receive Data Valid
S
SA
Source Address
SMC
Flash Control Registers
SW
Switch
SYSC
System Control Registers
T
TOS
Type Of Service
TX
Transmit
TXC
Transmit Clock
TXE
Transmit Enable
TXD
Transmit Data
U
UART
Universal Asynchronous Receiver Transmitter
V
Data Sheet
219
Rev. 1.32, 2005-11-09
ADM5120P/PX
CONFIDENTIAL
VLAN
Terminology
Virtual LAN
W
WAN
Data Sheet
Wide Area Networks
220
Rev. 1.32, 2005-11-09
www.infineon.com
Published by Infineon Technologies AG
工商网监
湘ICP备2023018690号
