CY8CLED04
EZ-Color™ HB LED Controller
Features
■
HB LED Controller
❐ Configurable dimmers support up to four
independent LED channels
❐ 8- to 32-bits of resolution per channel
❐ Dynamic reconfiguration enables led controller plus other
features: CapSense®, Battery Charging, and Motor Control
■
Visual embedded design
❐ LED-Based drivers
• Binning compensation
• Temperature feedback
• Optical feedback
• DMX512
■
■
■
PrISM™ modulation technology
❐ Reduces radiated EMI
❐ Reduces low frequency blinking
®
■ Advanced peripherals (PSoC blocks)
❐ Four digital PSoC blocks provide:
• 8 to 32-bit timers, counters, and PWMs
• Full-duplex UART
• Multiple SPI Masters or Slaves
• Connectable to all GPIO pins
❐ Six Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 9-bit DACs
• Programmable gain amplifiers (PGA)
• Programmable filters and comparators
❐ Complex peripherals by combining blocks
❐ Capacitive sensing application capability
Cypress Semiconductor Corporation
Document Number: 001-13108 Rev. *F
•
■
■
198 Champion Court
Complete development tools
❐ Free development software
• PSoC Designer™
❐ Full featured, in-circuit emulator (ICE) and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
Programmable pin configurations
❐ 25 mA sink, 10 mA source on all GPIO
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐ Up to 12 analog inputs on GPIO
❐ Four 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIO
Flexible on-chip memory
❐ 16K flash program storage 50,000 erase/write cycles
❐ 1K SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Full speed USB (12 Mbps)
❐ Four uni-directional endpoints
❐ One bi-directional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 256 byte buffer
❐ No external crystal required
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 13, 2011
CY8CLED04
Logic Block Diagram
Port 5 Port 4
System Bus
Port 7
Port 3
Global Digital Interconnect
Port 2 Port 1
Port 0 Analog
Drivers
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash 16 K
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
Clock Sources
( Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
2
Decimator
Clocks MACs
Type 2
Analog
Block
Array
I 2C
POR and LVD
System Resets
Internal
Voltage
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Document Number: 001-13108 Rev. *F
Page 2 of 49
CY8CLED04
Contents
EZ-Color™ Functional Overview ..................................... 4
Target Applications ...................................................... 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
The Analog Multiplexer System ................................... 6
Additional System Resources ..................................... 6
EZ-Color Device Characteristics ................................. 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 9
Select User Modules ................................................... 9
Configure User Modules .............................................. 9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pin Information ............................................................... 10
68-Pin Part Pinout ..................................................... 10
Register Conventions .................................................... 11
Abbreviations Used ................................................... 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Operating Temperature ............................................. 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 29
Document Number: 001-13108 Rev. *F
Packaging Information ................................................... 37
Thermal Impedance .................................................. 38
Solder Reflow Peak Temperature ............................. 38
Development Tools ........................................................ 39
Software .................................................................... 39
Evaluation Tools ........................................................ 39
Device Programmers ................................................. 40
Accessories (Emulation and Programming) .............. 40
Third Party Tools ....................................................... 40
Build a PSoC Emulator into Your Board .................... 40
Ordering Information ...................................................... 41
Key Device Features ................................................. 41
Ordering Code Definitions ......................................... 41
Acronyms ........................................................................ 42
Acronyms Used ......................................................... 42
Reference Documents .................................................... 42
Document Conventions ................................................. 43
Units of Measure ....................................................... 43
Numeric Conventions ................................................ 43
Glossary .......................................................................... 43
Document History Page ................................................. 48
Sales, Solutions, and Legal Information ...................... 49
Worldwide Sales and Design Support ....................... 49
Products .................................................................... 49
PSoC® Solutions ...................................................... 49
Page 3 of 49
CY8CLED04
EZ-Color™ Functional Overview
Cypress's EZ-Color family of devices offers the ideal control
solution for high brightness LED applications requiring intelligent
dimming control. EZ-Color devices combine the power and
flexibility of Programmable System-on-Chip (PSoC®); with
Cypress's precise illumination signal modulation (PrISM™)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify
implementation of fixed color points through temperature,
optical, and LED binning compensation. EZ-Color's virtually
limitless analog and digital customization enable simple
integration of features in addition to intelligent lighting, such as
CapSense, battery charging, image stabilization, and motor
control during the development process. These features, along
with Cypress's best-in-class quality and design support, make
EZ-Color the ideal choice for intelligent HB LED control
applications.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
The Digital System
The digital system is composed of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user module references.
Digital peripheral configurations include:
■
PrISM (8- to 32-bit)
■
Full speed USB (12 Mbps)
■
PWMs (8- to 32-bit)
■
PWMs with Dead band (8- to 24-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
UART 8-bit with selectable parity
■
SPI master and slave
Target Applications
■
I2C slave and multi-master
■
LCD Backlight
■
Cyclical Redundancy Checker (CRC)/Generator (8- to 32-bit)
■
Large Signs
■
IrDA
■
General Lighting
■
Generators (8- to 32-bit)
■
Architectural Lighting
■
Camera/Cell Phone Flash
■
Flashlights
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
General Purpose I/O (GPIO).
The M8C CPU core is a powerful processor with speeds up to
68 MHz, providing a four MIPS 8-bit Harvard-architecture
microprocessor. The CPU uses an interrupt controller with up to
20 vectors, to simplify programming of real time embedded
events. Program execution is timed and protected using the
included Sleep and watchdog timers (WDT).
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled EZ-Color Device
Characteristics.
Figure 1. Digital System Block Diagram
Port 7
Memory encompasses 16K of flash for program storage, 1K of
SRAM for data storage, and up to 2K of EEPROM emulated
using the flash. Program flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
Document Number: 001-13108 Rev. *F
Port 3
Port 1
Port 2
To System Bus
Digital Clocks
From Core
Port 0
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Row Output
Configuration
The EZ-Color family incorporates flexible internal clock
generators, including a 24 MHz internal main oscillator (IMO)
accurate to 8 percent over temperature and voltage. The 24 MHz
IMO can also be doubled to 48 MHz for use by the digital system.
A low power 32 kHz internal low speed oscillator (ILO) is
provided for the sleep timer and WDT. The clocks, together with
programmable clock dividers (as a system resource), provide the
flexibility to integrate almost any timing requirement into the
EZ-Color device. In USB systems, the IMO self-tunes to ± 0.25%
accuracy for USB communication.
Port 5
Port 4
Row Input
Configuration
The PSoC Core
8
8
GOE[7:0]
GOO[7:0]
Page 4 of 49
CY8CLED04
■
Analog-to-digital converters (up to 2, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to 2, with 16 selectable thresholds)
■
DACs (up to 2, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
Core Resource)
■
1.3-V reference (as a system resource)
■
DTMF Dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one Continuous Time (CT) and two Switched Capacitor (SC)
blocks, as shown in the figure below.
All IO
(Except Port 7)
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
Figure 2. Analog System Block Diagram
Analog
Mux Bus
The Analog System
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
ACI0[1:0]
ACI1[1:0]
Array Input
Configuration
Block
Array
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-13108 Rev. *F
Page 5 of 49
CY8CLED04
The Analog Multiplexer System
Additional System Resources
The Analog Mux Bus can connect to every GPIO pin in ports 0-5.
Pins can be connected to the bus individually or in any
combination. The bus also connects to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing. An additional 8:1 analog input multiplexer provides
a second path to bring Port 0 pins to the analog array.
System resources, provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief
statements describing the merits of each resource follow.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Track pad, finger sensing.
■
Chip-wide mux that allows analog input from up to 48 I/O pins.
■
Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >
Documentation. In general, and unless otherwise noted in the
relevant Application Notes, the minimum signal-to-noise ratio
(SNR) for CapSense applications is 5:1.
■
Full-speed USB (12 Mbps) with 5 configurable endpoints and
256 bytes of RAM. No external components required except
two series resistors. Wider than commercial temperature USB
operation (–10 °C to +85 °C).
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math as well
as digital filters.
■
Decimator provides a custom hardware filter for digital signal
processing apps. including creation of Delta Sigma ADCs.
■
The I2C module provides 100- and 400-kHz communication
over two wires. Slave, master, multi-master are supported.
■
Low-voltage detect (LVD) interrupts signal the application of
falling voltage levels, while the advanced Power-on reset
(POR) circuit eliminates the need for a system supervisor.
■
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
CY8CLED02
2
16
1
4
8
0
2
4
256 Bytes
4K
No
CY8CLED04
4
56
1
4
48
2
2
6
1K
16K
Yes
CY8CLED08
8
44
2
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
44
4
16
12
4
4
12
2K
32K
No
Document Number: 001-13108 Rev. *F
Flash
Size
PSoC Part
Number
LED
Channels
CapSense
Table 1. EZ-Color Device Characteristics
Page 6 of 49
CY8CLED04
Getting Started
Development Tools
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer integrated development
environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip
Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at http://www.cypress.com/ez-color.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Document Number: 001-13108 Rev. *F
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC's resources for an application.
Page 7 of 49
CY8CLED04
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
Document Number: 001-13108 Rev. *F
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 8 of 49
CY8CLED04
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All of the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information that you may need to
successfully implement your design.
Document Number: 001-13108 Rev. *F
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer. It lets you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
Page 9 of 49
CY8CLED04
Pin Information
68-Pin Part Pinout
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
35
36
37
38
39
40
41
42
43
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
M
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
44
45
46
47
48
49
NC
NC
XRES
Input
I/O
I/O
I/O
M
M
M
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
I2C serial clock (SCL).
I2C serial data (SDA).
I2C SCL ISSP SCLK.
Ground connection.
Supply voltage.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
29
30
31
32
33
34
No connection.
No connection.
Ground connection.
51
50
QFN
(Top View)
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
VSS
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
VSS
D+
DVDD
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
M, P1[3]
I2C SCL, M, P1[1]
Vss
D+
DVdd
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
I2C SDA, M, P1[0]
M, P1[2]
M, P1[4]
No. Digital Analog
1
I/O
M
2
I/O
M
3
I/O
M
4
I/O
M
5
6
7
Power
8
I/O
M
9
I/O
M
10
I/O
M
11
I/O
M
12
I/O
M
13
I/O
M
14
I/O
M
15
I/O
M
16
I/O
M
17
I/O
M
18
I/O
M
19
I/O
M
20
Power
21
USB
22
USB
23
Power
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
P2[1], M, AI
P2[3], M, AI
P2[5], M
P2[7], M
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
This Section describes, lists, and illustrates the CY8CLED04 EZ-Color device pins and pinout configuration. The CY8CLED04 device
is available in the following package. Every port pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, and XRES are
not capable of Digital I/O.
Table 2. 68-Pin Part Pinout (QFN)[1, 2]
Type
Pin
Figure 3. 68-Pin Device
Name
Description
I2C SDA, ISSP SDATA.
Optional external clock input
(EXTCLK).
No connection.
No connection.
Active high pin reset with internal
pull-down.
P4[0]
P4[2]
P4[4]
Type
Pin
No. Digital Analog
50
I/O
M
51
I/O
I,M
52
I/O
I,M
53
I/O
M
P4[6]
P2[0]
P2[2]
P2[4]
54
55
56
57
58
59
60
61
62
I/O
M
I/O
I,M
I/O
I,M
I/O
I,M
I/O
I,M
Power
Power
I/O
I,M
I/O
I/O,M
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
VSS
P0[7]
P0[5]
63
64
65
I/O
I/O
I/O
I/O,M
I,M
M
P0[3]
P0[1]
P2[7]
66
67
68
I/O
I/O
I/O
M
I,M
I,M
P2[5]
P2[3]
P2[1]
Name
Description
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND) input.
External Voltage Reference (VREF) input.
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
Ground connection.
Analog column mux input, integration input #1
Analog column mux input and column output,
integration input #2.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
LEGENDA = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Notes
1. These are the ISSP pins, which are not High Z at POR.
2. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 001-13108 Rev. *F
Page 10 of 49
CY8CLED04
Register Conventions
This section lists the registers of the CY8CLED04 EZ-Color device.
Abbreviations Used
The register conventions specific to this section are listed in the following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Register Mapping Tables
The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two
banks., Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI
bit is set to 1, the user is in Bank 1.
Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
Table 3. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
Addr (0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PRT3DR
0C
RW
Name
PMA0_DR
PMA1_DR
PMA2_DR
PMA3_DR
PMA4_DR
PMA5_DR
PMA6_DR
PMA7_DR
USB_SOF0
USB_SOF1
USB_CR0
USBI/O_CR
0
USBI/O_CR
1
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
0D
RW
0E
RW
EP1_CNT1
0F
RW
EP1_CNT
10
RW
EP2_CNT1
11
RW
EP2_CNT
12
RW
EP3_CNT1
13
RW
EP3_CNT
14
RW
EP4_CNT1
15
RW
EP4_CNT
16
RW
EP0_CR
17
RW
EP0_CNT
18
EP0_DR0
19
EP0_DR1
1A
EP0_DR2
1B
EP0_DR3
PRT7DR
1C
RW
EP0_DR4
PRT7IE
1D
RW
EP0_DR5
PRT7GS
1E
RW
EP0_DR6
PRT7DM2
1F
RW
EP0_DR7
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. *F
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
Access
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
#
4C
RW
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
#
RW
#
RW
#
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
Access
RW
RW
RW
RW
RW
RW
RW
RW
Name
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
# Access is bit specific.
Addr (0,Hex) Access
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
Page 11 of 49
CY8CLED04
Table 3. Register Map Bank 0 Table: User Space (continued)
Name
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
Addr (0,Hex)
22
23
24
25
26
27
28
29
2A
2B
2C
Access
RW
#
#
W
RW
#
#
W
RW
#
#
Name
TMP_DR0
Addr (0,Hex)
62
63
64
65
66
67
68
69
6A
6B
6C
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
DCB03CR0
2F
#
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
RW
MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
Addr (0,Hex)
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
W
W
R
R
RW
6D
RW
ACC1_DR0
AD
RW
TMP_DR2
6E
RW
ACC1_DR3
AE
RW
TMP_DR3
6F
RW
ACC1_DR2
AF
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
RW
RW
RW
RW
RW
RW
RW
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
Access
Name
RW
#
#
RW
7F
3F
Access
CPU_F
DAC_D
CPU_SCR
1
CPU_SCR
0
BF
Blank fields are Reserved and should not be accessed.
Name
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR
1
ACC0_DR
0
ACC0_DR
3
ACC0_DR
2
Addr (0,Hex)
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
Access
RC
W
RC
RC
RW
RW
W
W
R
R
RW
ED
RW
EE
RW
EF
RW
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
RL
FF
#
RW
#
# Access is bit specific.
Table 4. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
00
Access
RW
Name
PMA0_WA
Addr (1,Hex)
40
Access
RW
PRT0DM1
01
RW
PMA1_WA
41
RW
PRT0IC0
02
RW
PMA2_WA
42
RW
PRT0IC1
03
RW
PMA3_WA
43
RW
PRT1DM0
04
RW
PMA4_WA
44
RW
PRT1DM1
05
RW
PMA5_WA
45
RW
PRT1IC0
06
RW
PMA6_WA
46
RW
PRT1IC1
07
RW
PMA7_WA
47
RW
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
08
09
0A
0B
0C
0D
0E
0F
10
RW
RW
RW
RW
RW
RW
RW
RW
RW
PMA0_RA
48
49
4A
4B
4C
4D
4E
4F
50
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. *F
RW
Name
ASC10CR
0
ASC10CR
1
ASC10CR
2
ASC10CR
3
ASD11CR
0
ASD11CR
1
ASD11CR
2
ASD11CR
3
Addr (1,Hex) Access
80
RW
Name
USBI/O_CR2
Addr (1,Hex) Access
C0
RW
81
RW
USB_CR1
C1
#
82
RW
83
RW
84
RW
EP1_CR0
C4
#
85
RW
EP2_CR0
C5
#
86
RW
EP3_CR0
C6
#
87
RW
EP4_CR0
C7
#
GDI_O_IN
C8
C9
CA
CB
CC
CD
CE
CF
D0
RW
88
89
8A
8B
8C
8D
8E
8F
90
# Access is bit specific.
Page 12 of 49
CY8CLED04
Table 4. Register Map Bank 1 Table: Configuration Space (continued)
Name
PRT4DM1
Addr (1,Hex)
11
Access
RW
Name
PMA1_RA
Addr (1,Hex)
51
Access
RW
PRT4IC0
12
RW
PMA2_RA
52
RW
PRT4IC1
13
RW
PMA3_RA
53
RW
PRT5DM0
14
RW
PMA4_RA
54
RW
PRT5DM1
15
RW
PMA5_RA
55
RW
PRT5IC0
16
RW
PMA6_RA
56
RW
PRT5IC1
17
RW
PMA7_RA
57
RW
DBB01FN
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
RW
DBB01IN
25
RW
DBB01OU
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RW
PRT7DM0
PRT7DM1
PRT7IC0
PRT7IC1
DBB00FN
DBB00IN
DBB00OU
DCB02FN
DCB02IN
DCB02OU
DCB03FN
DCB03IN
DCB03OU
RW
RW
RW
RW
RW
RW
RW
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_E
N
CMP_GO_E
N1
AMD_CR1
ALT_CR0
RW
RW
RW
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
Blank fields are Reserved and should not be accessed.
Document Number: 001-13108 Rev. *F
Name
ASD20CR
1
ASD20CR
2
ASD20CR
3
ASC21CR
0
ASC21CR
1
ASC21CR
2
ASC21CR
3
Addr (1,Hex) Access
91
RW
Name
GDI_E_IN
Addr (1,Hex) Access
D1
RW
92
RW
GDI_O_OU
D2
RW
93
RW
GDI_E_OU
D3
RW
94
RW
D4
95
RW
D5
96
RW
D6
97
RW
D7
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
RW
RW
RW
RW
RW
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
65
RW
A5
E5
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
RW
RW
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
D8
D9
DA
DB
DC
OSC_GO_EN DD
OSC_CR4
DE
OSC_CR3
DF
OSC_CR0
E0
OSC_CR1
E1
OSC_CR2
E2
VLT_CR
E3
VLT_CMP
E4
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RW
RW
RL
RW
#
#
# Access is bit specific.
Page 13 of 49
CY8CLED04
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED04 EZ-Color device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at
http://www.cypress.com/ez-color.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications for devices running at greater
than 12 MHz are valid for –40 °C TA 70 °C and TJ 82 °C.
Figure 4. Voltage versus CPU Frequency
5.25
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
Document Number: 001-13108 Rev. *F
Page 14 of 49
CY8CLED04
Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TA
VDD
VI/O
Ambient temperature with power applied
Supply voltage on VDD relative to VSS
DC input voltage
VI/O2
DC voltage applied to tri-state
IMI/O
IMAI/O
Maximum current into any port pin
Maximum current into any port pin configured
as analog driver
Electrostatic discharge voltage
Latch-up current
ESD
LU
Min
–55
Typ
25
Max
+100
Units
°C
–40
–0.5
VSS 0.5
VSS 0.5
–25
–50
–
–
–
°C
V
V
–
–
+85
+6.0
VDD +
0.5
VDD +
0.5
+50
+50
mA
mA
2000
–
–
–
–
200
V
mA
Min
–40
–10
–40
Typ
–
–
–
Max
+85
+85
+100
Units
°C
°C
°C
–
Notes
Higher storage temperatures will
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C will
degrade reliability.
V
Human Body Model ESD.
Operating Temperature
Symbol
TA
TAUSB
TJ
Description
Ambient temperature
Ambient temperature using USB
Junction temperature
Document Number: 001-13108 Rev. *F
Notes
The temperature rise from ambient
to junction is package specific. See
“Thermal Impedance” on page 38.
The user must limit the power
consumption to comply with this
requirement.
Page 15 of 49
CY8CLED04
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
VDDP
Symbol
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
Units
V
VDDLV
Low VDD for verify
3
3.1
3.2
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
VDDIWRITE
Supply voltage for flash write operation
3.0
–
5.25
V
VDD
Supply voltage
3.0
–
5.25
V
IDD5
Supply current, IMO = 24 MHz (5V)
–
14
27
mA
IDD3
Supply current, IMO = 24 MHz (3.3V)
–
8
14
mA
ISB
Sleep (mode) current with POR, LVD, Sleep
Timer, and WDT[3]
–
3
6.5
A
ISBH
Sleep (mode) current with POR, LVD, Sleep
Timer, and WDT at high temperature.[3]
–
4
25
A
Notes
This specification applies to the
functional requirements of external
programmer tools
This specification applies to the
functional requirements of external
programmer tools
This specification applies to the
functional requirements of external
programmer tools
This specification applies to this
device when it is executing internal
flash writes
See DC POR and LVD specifications,
Table 15 on page 27.
Conditions are VDD = 5.0 V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.
Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.367 kHz,
analog power = off.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V, –40 °C
TA 55 °C, analog power = off.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V, 55 °C
< TA 85 °C, analog power = off.
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 5. DC GPI/O Specifications
Symbol
Description
Pull-up resistor
RPU
Pull-down resistor
RPD
High output level
VOH
VOL
Low output level
Min
4
4
VDD 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
k
k
V
–
–
0.75
V
Notes
I/OH = 10 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5])). 80 mA maximum combined
I/OH budget.
I/OL = 25 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5])). 200 mA maximum
combined I/OL budget.
Note
3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar
functions enabled.
Document Number: 001-13108 Rev. *F
Page 16 of 49
CY8CLED04
Table 5. DC GPI/O Specifications (continued)
Symbol
Description
IOH
High level source current
Min
10
Typ
–
Max
–
Units
mA
IOL
Low level sink current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysterisis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
–
–
10
V
V
mV
nA
pF
COUT
Capacitive load on pins as output
–
3.5
10
pF
Notes
VOH = VDD-1.0 V. See the
limitations of the total current in the
Note for VOH.
VOL = 0.75 V. See the limitations of
the total current in the Note for VOL.
VDD = 3.0 to 5.25.
VDD = 3.0 to 5.25.
Gross tested to 1 A.
Package and pin dependent.
Temp = 25 °C.
Package and pin dependent.
Temp = 25 °C.
DC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –10 °C TA 85 °C, or 3.0 V to 3.6 V and –10 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 6. DC Full-Speed (12 Mbps) USB Specifications
Symbol
Description
USB Interface
Differential input sensitivity
VDI
Differential input common mode range
VCM
VSE
Single ended receiver threshold
Transceiver capacitance
CIN
High-Z State data line leakage
II/O
REXT
External USB series resistor
Static output high, driven
VUOH
Min
Typ
Max
Units
0.2
0.8
0.8
–
–10
23
2.8
–
–
–
–
–
–
–
–
2.5
2.0
20
10
25
3.6
V
V
V
pF
A
W
V
VUOHI
Static output high, idle
2.7
–
3.6
V
VUOL
Static output low
–
–
0.3
V
ZO
VCRS
USB driver output impedance
D+/D- crossover voltage
28
1.3
–
–
44
2.0
W
V
Document Number: 001-13108 Rev. *F
Notes
| (D+) - (D-) |
0 V < VIN < 3.3 V.
In series with each USB pin.
15 k ± 5% to Ground. Internal
pull-up enabled.
15 k ± 5% to Ground. Internal
pull-up enabled.
15 k ± 5% to Ground. Internal
pull-up enabled.
Including REXT resistor.
Page 17 of 49
CY8CLED04
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
The Operational Amplifier is a component of both the analog continuous time PSoC blocks and the analog switched capacitor PSoC
blocks. The guaranteed specifications are measured in the analog continuous time PSoC block.
Table 7. 5-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
TCVOSOA Average input offset voltage drift
Input leakage current (Port 0 analog pins)
IEBOA
Input capacitance (Port 0 analog pins)
CINOA
VCMOA
Common mode voltage range
Common mode voltage range
(high power or high opamp bias)
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
7.0
20
4.5
10
8
7.5
35.0
–
9.5
mV
mV
mV
µV/°C
pA
pF
0.0
0.5
–
–
VDD
VDD – 0.5
V
V
60
60
80
–
–
–
–
–
–
dB
dB
dB
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
–
65
400
500
800
1200
2400
4600
80
800
900
1000
1600
3200
6400
–
µA
µA
µA
µA
µA
µA
dB
Notes
Gross tested to 1 µA.
Package and pin dependent.
Temp = 25 °C.
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics
of the analog output buffer.
GOLOA
Open loop gain
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
VOHIGHOA High output voltage swing (internal signals)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
VOLOWOA Low output voltage swing (internal signals)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
Supply current (including associated AGND
ISOA
buffer)
Power = low, opamp bias = low
Power = low, opamp bias = high
Power = medium, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = low
Power = high, opamp bias = high
PSRROA Supply voltage rejection ratio
Document Number: 001-13108 Rev. *F
VSS £ VIN £ (VDD – 2.25) or
(VDD – 1.25 V) £ VIN £ VDD.
Page 18 of 49
CY8CLED04
Table 8. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
TCVOSOA Average input offset voltage drift
Input leakage current (port 0 analog pins)
IEBOA
Input capacitance (port 0 analog pins)
CINOA
Min
Typ
Max
–
–
–
–
–
–
1.65
1.32
–
7.0
20
4.5
10
8
–
35.0
–
9.5
VCMOA
Common mode voltage range
0.2
–
GOLOA
Open loop gain
Power = low, opamp bias = low
Power = medium, opamp bias = low
Power = high, opamp bias = low
60
60
80
–
–
–
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
65
400
500
800
1200
2400
–
80
High output voltage swing (internal signals)
Power = low, opamp bias = low
A
Power = medium, opamp bias = low
Power = high, opamp bias = low
VOLOWOA Low output voltage swing (internal signals)
Power = low, opamp bias = low
Power = medium, opamp bias = low
Power = high, opamp bias = low
Supply current
ISOA
(including associated AGND buffer)
Power = low, opamp bias = low
Power = low, opamp bias = high
Power = medium, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = low
Power = high, opamp bias = high
PSRROA Supply voltage rejection ratio
VOHIGHO
Document Number: 001-13108 Rev. *F
Units
Notes
Power = high, opamp bias =
high setting is not allowed for
3.3 V VDD operation
mV
mV
mV
µV/°C
pA
Gross tested to 1 µA.
pF
Package and pin dependent.
Temp = 25 °C.
VDD – 0.2
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics
of the analog output buffer.
Specification is applicable at
–
dB
Low opamp bias. For high
–
dB
opamp bias mode (except high
–
dB
power, High opamp bias),
minimum is 60 dB.
Power = high, Opamp bias =
–
V
high setting is not allowed for
–
V
3.3 V VDD operation
–
V
Power = high, opamp bias =
0.2
V
high setting is not allowed for
0.2
V
3.3 V VDD operation
0.2
V
Power = high, opamp bias =
high setting is not allowed for
800
µA
3.3 V VDD operation
900
µA
1000
µA
1600
µA
3200
µA
–
µA
–
dB
VSS £ VIN £ (VDD – 2.25) or
(VDD – 1.25 V) £ VIN £ VDD
Page 19 of 49
CY8CLED04
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical
parameters are measured at 5 V at 25 °C and are for design guidance only.
Table 9. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC)
reference voltage range
LPC supply current
LPC voltage offset
Min
0.2
Typ
–
Max
VDD - 1
Units
V
–
–
10
2.5
40
30
A
mV
Notes
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 10. 5-V DC Analog Output Buffer Specifications
Symbol
CL
Description
Load capacitance
Min
–
Typ
–
Max
200
Input offset voltage (absolute value)
Average input offset voltage drift
Common mode input voltage range
Output resistance
Power = low
Power = high
VOHIGHOB High output voltage swing
(Load = 32 ohms to VDD/2)
Power = low
Power = high
VOLOWOB Low output voltage swing
(Load = 32 ohms to VDD/2)
Power = low
Power = high
ISOB
Supply current including opamp bias
cell
(No Load)
Power = low
Power = high
PSRROB Supply voltage rejection ratio
–
–
0.5
3
+6
–
12
–
VDD – 1.0
–
–
0.6
0.6
–
–
W
W
0.5 × VDD + 1.1
0.5 × VDD + 1.1
–
–
–
–
V
V
–
–
–
–
0.5 × VDD – 1.3
0.5 × VDD – 1.3
V
V
–
–
1.1
2.6
5.1
8.8
mA
mA
53
64
–
dB
VOSOB
TCVOSOB
VCMOB
ROUTOB
Document Number: 001-13108 Rev. *F
Units
Notes
pF
This specification applies to the
external circuit that is being
driven by the analog output
buffer.
mV
µV/°C
V
(0.5 × VDD – 1.3) £ VOUT £
(VDD – 2.3).
Page 20 of 49
CY8CLED04
Table 11. 3.3-V DC Analog Output Buffer Specifications
Symbol
CL
Description
Load capacitance
VOSOB
TCVOSOB
VCMOB
ROUTOB
Min
–
Input offset voltage (absolute value)
–
Average input offset voltage drift
–
Common mode input voltage range
0.5
Output resistance
–
Power = low
–
Power = high
VOHIGHOB High output voltage swing
(Load = 1 kto VDD/2)
Power = low
0.5 × VDD + 1.0
Power = high
0.5 × VDD + 1.0
VOLOWOB Low output voltage swing
(Load = 1 kto VDD/2)
–
Power = low
Power = high
–
ISOB
Supply current including opamp bias
cell (No load)
–
Power = low
–
Power = high
PSRROB Supply voltage rejection ratio
34
Document Number: 001-13108 Rev. *F
Typ
–
Max
200
Units
Notes
pF This specification applies to the
external circuit that is being
driven by the analog output
buffer.
mV
µV/°C
V
3
+6
–
12
–
VDD – 1.0
1
1
–
–
W
W
–
–
–
–
V
V
–
–
0.5 × VDD – 1.0
0.5 × VDD – 1.0
V
V
0.8
2.0
64
2.0
4.3
–
mA
mA
dB
(0.5 × VDD – 1.0) £ VOUT £
(0.5 × VDD + 0.9).
Page 21 of 49
CY8CLED04
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to
the power of the analog continuous time PSoC block. The power levels for RefHi and RefLo refer to the analog reference control
register. The limits stated for AGND include the offset error of the AGND buffer local to the analog continuous time PSoC block.
Reference control power is high.
Table 12. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b001
Symbol
Reference
Description
Min
Typ
Max
Units
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.229 VDD/2 + 1.290 VDD/2 + 1.346
V
VAGND
AGND
VDD/2
VDD/2 – 0.038
VDD/2 + 0.040
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.356 VDD/2 – 1.295 VDD/2 – 1.218
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.220 VDD/2 + 1.292 VDD/2 + 1.348
V
VAGND
AGND
VDD/2
VDD/2 – 0.036
VDD/2 + 0.036
V
VDD/2
VDD/2
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.357 VDD/2 – 1.297 VDD/2 – 1.225
V
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
VDD/2 + Bandgap
VDD/2 + 1.221 VDD/2 + 1.293 VDD/2 + 1.351
V
AGND
VDD/2
VDD/2 – 0.036
VDD/2 + 0.036
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.357 VDD/2 – 1.298 VDD/2 – 1.228
V
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
VDD/2 + Bandgap
VDD/2 + 1.219 VDD/2 + 1.293 VDD/2 + 1.353
V
AGND
VDD/2
VDD/2 – 0.037 VDD/2 – 0.001 VDD/2 + 0.036
V
VREFLO
Ref Low
VDD/2 – Bandgap
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
VDD/2 – 1.359 VDD/2 – 1.299 VDD/2 – 1.229
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.092
0.011
0.064
VAGND
AGND
P2[4]
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.031
0.007
0.056
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.078
0.008
0.063
V
VAGND
AGND
P2[4]
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.031
0.004
0.043
V
RefPower = medium VREFHI
Opamp bias = high
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.073
0.006
0.062
V
VAGND
AGND
P2[4]
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.032
0.003
0.038
V
RefPower = medium VREFHI
Opamp bias = low
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.073
0.006
0.062
V
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
VAGND
AGND
P2[4]
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
Document Number: 001-13108 Rev. *F
P2[4]
P2[4]
P2[4]
P2[4]
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.034
0.002
0.037
V
–
–
–
–
V
Page 22 of 49
CY8CLED04
Table 12. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b010
Reference Power
Settings
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b011
Reference
Description
VREFHI
Ref High
VDD
VAGND
AGND
VDD/2
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VDD/2
VREFLO
Ref Low
VSS
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
VDD
AGND
VDD/2
VREFLO
Ref Low
VSS
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
VDD
AGND
VDD/2
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b100
Symbol
Min
Typ
Max
Units
VDD – 0.037
VDD – 0.007
VDD
V
VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.036
VSS
VSS + 0.005
VSS + 0.029
VDD – 0.034
VDD – 0.006
VDD
VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.035
VSS
VSS + 0.004
VSS + 0.024
VDD – 0.032
VDD – 0.005
VDD
VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.035
VSS
VSS + 0.003
VSS + 0.022
VDD – 0.031
VDD – 0.005
VDD
VDD/2 – 0.037 VDD/2 – 0.001 VDD/2 + 0.035
VSS
VSS + 0.003
VSS + 0.020
V
V
V
V
V
V
V
V
V
V
VREFLO
Ref Low
VSS
VREFHI
Ref High
3 × Bandgap
3.760
3.884
4.006
V
VAGND
AGND
2 × Bandgap
2.522
2.593
2.669
V
VREFLO
Ref Low
Bandgap
1.252
1.299
1.342
V
VREFHI
Ref High
3 × Bandgap
3.766
3.887
4.010
V
VAGND
AGND
2 × Bandgap
2.523
2.594
2.670
V
V
VREFLO
Ref Low
Bandgap
1.252
1.297
1.342
V
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
3 × Bandgap
3.769
3.888
4.013
V
AGND
2 × Bandgap
2.523
2.594
2.671
V
VREFLO
Ref Low
Bandgap
1.251
1.296
1.343
V
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
3 × Bandgap
3.769
3.889
4.015
V
AGND
2 × Bandgap
2.523
2.595
2.671
V
VREFLO
Ref Low
Bandgap
1.251
1.296
1.344
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.483 – P2[6]
2.582 – P2[6]
2.674 – P2[6]
V
VAGND
AGND
2 × Bandgap
2.522
2.593
2.669
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.524 – P2[6]
2.600 – P2[6]
2.676 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.490 – P2[6]
2.586 – P2[6]
2.679 – P2[6]
V
VAGND
AGND
2 × Bandgap
2.523
2.594
2.669
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.523 – P2[6]
2.598 – P2[6]
2.675 – P2[6]
V
RefPower = medium VREFHI
Opamp bias = high
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.493 – P2[6]
2.588 – P2[6]
2.682 – P2[6]
V
VAGND
AGND
2 × Bandgap
2.523
2.594
2.670
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.523 – P2[6]
2.597 – P2[6]
2.675 – P2[6]
V
RefPower = medium VREFHI
Opamp bias = low
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.494 – P2[6]
2.589 – P2[6]
2.685 – P2[6]
V
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
VAGND
AGND
2 × Bandgap
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
Document Number: 001-13108 Rev. *F
2.523
2.595
2.671
V
2.522 – P2[6]
2.596 – P2[6]
2.676 – P2[6]
V
Page 23 of 49
CY8CLED04
Table 12. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b101
Reference Power
Settings
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b110
Reference
Description
Min
Typ
Max
Units
P2[4] + 1.218
P2[4] + 1.291
P2[4] + 1.354
V
P2[4]
P2[4]
P2[4]
–
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
VAGND
AGND
P2[4]
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.335
P2[4] – 1.294
P2[4] – 1.237
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.221
P2[4] + 1.293
P2[4] + 1.358
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.337
P2[4] – 1.297
P2[4] – 1.243
V
RefPower = medium VREFHI
Opamp bias = high
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.222
P2[4] + 1.294
P2[4] + 1.360
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.338
P2[4] – 1.298
P2[4] – 1.245
V
RefPower = medium VREFHI
Opamp bias = low
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.221
P2[4] + 1.294
P2[4] + 1.362
V
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b111
Symbol
VAGND
AGND
P2[4]
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4]
P2[4]
–
P2[4] – 1.340
P2[4] – 1.298
P2[4] – 1.245
V
VREFHI
Ref High
2 × Bandgap
2.513
2.593
2.672
V
VAGND
AGND
Bandgap
1.264
1.302
1.340
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.008
VSS + 0.038
V
VREFHI
Ref High
2 × Bandgap
2.514
2.593
2.674
V
VAGND
AGND
Bandgap
1.264
1.301
1.340
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.028
V
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
2 × Bandgap
2.514
2.593
2.676
V
AGND
Bandgap
1.264
1.301
1.340
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.024
V
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
2 × Bandgap
2.514
2.593
2.677
V
AGND
Bandgap
1.264
1.300
1.340
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.021
V
VREFHI
Ref High
3.2 × Bandgap
4.028
4.144
4.242
V
VAGND
AGND
1.6 × Bandgap
2.028
2.076
2.125
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.008
VSS + 0.034
V
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
VREFHI
Ref High
3.2 × Bandgap
4.032
4.142
4.245
V
VAGND
AGND
1.6 × Bandgap
2.029
2.076
2.126
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.025
V
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
3.2 × Bandgap
4.034
4.143
4.247
V
AGND
1.6 × Bandgap
2.029
2.076
2.126
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.021
V
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
3.2 × Bandgap
4.036
4.144
4.249
V
AGND
1.6 × Bandgap
2.029
2.076
2.126
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.019
V
Document Number: 001-13108 Rev. *F
Page 24 of 49
CY8CLED04
Table 13. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
RefPower = high
Opamp bias = high
Description
VREFHI
Ref High
VDD/2 + Bandgap
VAGND
AGND
VREFLO
Ref Low
VREFHI
Min
Typ
Max
Units
V
VDD/2
VDD/2 – Bandgap
VDD/2 – 1.346 VDD/2 – 1.292 VDD/2 – 1.208
V
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.196 VDD/2 + 1.292 VDD/2 + 1.374
VDD/2 – 0.029
VDD/2
VDD/2 + 0.031
VREFLO
Ref Low
VDD/2 – Bandgap
V
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
VDD/2 + Bandgap
VDD/2 – 1.349 VDD/2 – 1.295 VDD/2 – 1.227
VDD/2 + 1.204 VDD/2 + 1.293 VDD/2 + 1.369
AGND
VDD/2
VDD/2 – 0.030
VDD/2 + 0.030
V
VREFLO
Ref Low
VDD/2 – Bandgap
V
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
VDD/2 + Bandgap
VDD/2 – 1.351 VDD/2 – 1.297 VDD/2 – 1.229
VDD/2 + 1.189 VDD/2 + 1.294 VDD/2 + 1.384
AGND
VDD/2
VDD/2 – 0.032
VDD/2 + 0.029
V
VREFLO
Ref Low
VDD/2 – Bandgap
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
VDD/2 – 1.353 VDD/2 – 1.297 VDD/2 – 1.230
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.105
0.008
0.095
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
0b010
Reference
VDD/2 + 1.200 VDD/2 + 1.290 VDD/2 + 1.365
VDD/2 – 0.030
VDD/2
VDD/2 + 0.034
RefPower = high
Opamp bias = low
0b001
Symbol
P2[4]
VDD/2
VDD/2
V
V
V
VAGND
AGND
P2[4]
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.035
0.006
0.053
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.094
0.005
0.073
V
VAGND
AGND
P2[4]
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] +
0.033
0.002
0.042
V
RefPower = medium VREFHI
Opamp bias = high
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.094
0.003
0.075
V
VAGND
AGND
P2[4]
VREFLO
Ref Low
RefPower = medium VREFHI
Opamp bias = low
Ref High
P2[4]
P2[4]
–
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] –
0.035
P2[4] – P2[6]
P2[4] – P2[6] +
0.038
V
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] +
0.095
0.003
0.080
V
VAGND
AGND
P2[4]
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
VREFHI
Ref High
VDD
VAGND
AGND
VDD/2
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VDD/2
VREFLO
Ref Low
VSS
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
VDD
AGND
VDD/2
VREFLO
Ref Low
VSS
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
VDD
AGND
VDD/2
VREFLO
Ref Low
VSS
Document Number: 001-13108 Rev. *F
–
P2[4]
VREFLO
RefPower = high
Opamp bias = low
P2[4]
–
VREFLO
RefPower = high
Opamp bias = high
P2[4]
P2[4]
V
VREFLO
P2[4]
P2[4]
V
P2[4]
P2[4]
P2[4]
–
P2[4] – P2[6] –
0.038
P2[4] – P2[6]
P2[4] – P2[6] +
0.038
V
VDD – 0.119
VDD – 0.005
VDD
V
VDD/2 – 0.028
VDD/2
VDD/2 + 0.029
V
VSS
VSS + 0.004
VSS + 0.022
V
VDD – 0.131
VDD – 0.004
VDD
V
VDD/2 – 0.028
VDD/2
VDD/2 + 0.028
V
VSS
VSS + 0.003
VSS + 0.021
V
VDD – 0.111
VDD – 0.003
VDD
V
VDD/2 – 0.029
VDD/2
VDD/2 + 0.028
V
VSS
VSS + 0.002
VSS + 0.017
V
V
VDD – 0.128
VDD – 0.003
VDD
VDD/2 – 0.029
VDD/2
VDD/2 + 0.029
V
VSS
VSS + 0.002
VSS + 0.019
V
Page 25 of 49
CY8CLED04
Table 13. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
Description
Min
Typ
Max
Units
0b011
All power settings.
–
Not allowed for 3.3 V.
–
–
–
–
–
–
0b100
All power settings.
–
Not allowed for 3.3 V.
–
–
–
–
–
–
0b101
RefPower = high
Opamp bias = high
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.214
P2[4] + 1.291
P2[4] + 1.359
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.335
P2[4] – 1.292
P2[4] – 1.200
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.219
P2[4] + 1.293
P2[4] + 1.357
V
RefPower = high
Opamp bias = low
0b110
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.335
P2[4] – 1.295
P2[4] – 1.243
V
RefPower = medium VREFHI
Opamp bias = high
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.222
P2[4] + 1.294
P2[4] + 1.356
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.337
P2[4] – 1.296
P2[4] – 1.244
V
RefPower = medium VREFHI
Opamp bias = low
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.224
P2[4] + 1.295
P2[4] + 1.355
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.339
P2[4] – 1.297
P2[4] – 1.244
V
V
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
VREFHI
Ref High
2 × Bandgap
2.510
2.595
2.655
VAGND
AGND
Bandgap
1.276
1.301
1.332
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.031
V
VREFHI
Ref High
2 × Bandgap
2.513
2.594
2.656
V
VAGND
AGND
Bandgap
1.275
1.301
1.331
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.021
V
RefPower = medium VREFHI
Opamp bias = high V
AGND
Ref High
2 × Bandgap
2.516
2.595
2.657
V
AGND
Bandgap
1.275
1.301
1.331
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.017
V
RefPower = medium VREFHI
Opamp bias = low
VAGND
Ref High
2 × Bandgap
2.520
2.595
2.658
V
AGND
Bandgap
1.275
1.300
1.331
V
VSS
VSS + 0.002
VSS + 0.015
V
–
–
–
–
VREFLO
0b111
All power settings.
–
Not allowed for 3.3 V.
Document Number: 001-13108 Rev. *F
Ref Low
VSS
–
–
Page 26 of 49
CY8CLED04
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 14. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor unit value (continuous time)
Capacitor unit value (switched capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
k
fF
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V or 3.3 V
at 25 °C and are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 15. DC POR and LVD Specifications
Symbol
VPPOR0R
VPPOR1R
VPPOR2R
VPPOR0
VPPOR1
VPPOR2
VPH0
VPH1
VPH2
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Description
VDD Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VDD Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
–
–
–
92
0
0
–
–
–
mV
mV
mV
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[4]
3.08
3.20
4.08
4.57
4.74[5]
4.82
4.91
V
V
V
V
V
V
V
V
V
Notes
Notes
4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-13108 Rev. *F
Page 27 of 49
CY8CLED04
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 16. DC Programming Specifications
Symbol
Description
Min
IDDP
Supply current during programming or verify
–
VILP
Input low voltage during programming or
–
verify
VIHP
Input high voltage during programming or
2.1
verify
IILP
Input current when applying VILP to P1[0] or
–
P1[1] during programming or verify
IIHP
Input current when applying VIHP to P1[0] or
–
P1[1] during programming or Verify
VOLV
Output low voltage during programming or
–
verify
VOHV
Output high voltage during programming or VDD – 1.0
verify
FlashENP Flash endurance (per block)
50,000[6]
Typ
15
–
Max
30
0.8
Units
mA
V
–
–
V
–
0.2
mA
–
1.5
mA
–
VSS + 0.75
V
–
VDD
V
–
–
–
–
–
–
–
–
Years
Notes
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
Erase/write cycles per block.
B
FlashENT Flash endurance (total)[7]
FlashDR Flash data retention
1,800,000
10
Erase/write cycles.
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 17. DC I2C Specifications[8]
Symbol
VILI2C
Input low level
Description
VIHI2C
Input high level
Document Number: 001-13108 Rev. *F
Min
–
–
0.7 × VDD
Typ
–
–
–
Max
0.3 × VDD
0.25 × VDD
–
Units
V
V
V
Notes
3.0 V £ VDD £ 3.6 V
4.75 V £ VDD £ 5.25 V
3.0 V £ VDD £ 5.25 V
Page 28 of 49
CY8CLED04
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 18. AC Chip-Level Specifications
Symbol
FIMO245V
Description
Internal main oscillator frequency for
24 MHz (5 V)
FIMO243V
Internal main oscillator frequency for
24 MHz (3.3 V)
FIMOUSB5V Internal main oscillator frequency with USB
(5 V)
Frequency locking enabled and USB traffic
present.
FIMOUSB3V Internal main oscillator frequency with USB
(3.3 V)
Frequency locking enabled and USB traffic
present.
FCPU1
CPU frequency (5 V nominal)
FCPU2
CPU frequency (3.3 V nominal)
FBLK5
Digital PSoC Block frequency (5 V nominal)
Min
23.04
Typ
24
Max
24.96[6,7]
Units
MHz
22.08
24
25.92[7,8]
MHz
23.94
24
24.06[7]
MHz
23.94
24
24.06[7]
MHz
–0 °C TA 70 °C
3.15 VDD 3.45
0.093
0.093
0
24
12
48
24.96[6,7]
12.96[7,8]
49.92[6,7,9]
MHz
MHz
MHz
SLIMO mode = 0.
SLIMO mode = 0.
Refer to the AC digital block
specifications.
0
24
25.92[7,9]
MHz
15
5
32
–
64
100
kHz
kHz
20
–
46.08
50
50
48.0
80
–
49.92[6,8]
%
kHz
MHz
–
–
12.96
MHz
–
–
250
V/ms
TPOWERUP Time from end of POR to CPU executing
code
–
16
100
ms
tjit_IMO[10]
–
–
200
900
1200
6000
ps
ps
–
200
900
ps
FBLK3
F32K1
F32K_U
DCILO
Step24M
Fout48M
Digital PSoC block frequency (3.3 V
nominal)
Internal low speed oscillator frequency
Internal low speed oscillator untrimmed
frequency
Internal low speed oscillator duty cycle
24 MHz trim step size
48 MHz output frequency
FMAX
Maximum frequency of signal on row input
or row output.
SRPOWER_ Power supply slew rate
Notes
Trimmed for 5 V operation using
factory trim values.
Trimmed for 3.3 V operation
using factory trim values.
–10 °C TA 85 °C
4.35 VDD 5.15
After a reset and before the m8c
starts to run, the ILO is not
trimmed. See the System
Resets section of the PSoC
Technical Reference Manual for
details on timing this.
Trimmed. Utilizing factory trim
values.
VDD slew rate during power up.
UP
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle jitter
(RMS)
24 MHz IMO period jitter (RMS)
Power up from 0 V. See the
System Resets section of the
PSoC Technical Reference
Manual.
N=32
Notes
6. 4.75 V < VDD < 5.25 V.
7. Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range.
8. 3.0 V < VDD < 3.6 V.
9. See the individual user module data sheets for information on maximum frequencies for user modules.
10. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-13108 Rev. *F
Page 29 of 49
CY8CLED04
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 19. AC GPIO Specifications
Symbol
FGPI/O
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO operating frequency
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal strong mode
VDD = 4.5 to 5.25 V, 10% - 90%
VDD = 4.5 to 5.25 V, 10% - 90%
VDD = 3 to 5.25 V, 10% - 90%
VDD = 3 to 5.25 V, 10% - 90%
Figure 5. GPIO Timing Diagram
90%
G PIO
Pin
O utput
Voltage
10%
TR iseF
TRiseS
TFallF
TFallS
AC Full-Speed USB Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –10 °C TA 85 °C, or 3.0 V to 3.6 V and –10 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 20. AC Full-Speed (12 Mbps) USB Specifications
Symbol
TRFS
TFSS
TRFMFS
TDRATEFS
Description
Transition rise time
Transition fall time
Rise/fall time matching: (TR/TF)
Full-speed data rate
Document Number: 001-13108 Rev. *F
Min
4
4
90
12 - 0.25%
Typ
–
–
–
12
Max
20
20
111
12 + 0.25%
Units
ns
ns
%
Mbps
Notes
For 50 pF load.
For 50 pF load.
For 50 pF load.
Page 30 of 49
CY8CLED04
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3 V.
Table 21. 5-V AC Operational Amplifier Specifications
Symbol
Description
TROA
Rising settling time from 80% of DV to 0.1%
of DV (10 pF load, unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
TSOA
Falling settling time from 20% of DV to 0.1%
of DV (10 pF load, unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Rising slew rate (20% to 80%)(10 pF load,
SRROA
unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
SRFOA
Falling slew rate (20% to 80%)(10 pF load,
unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
BWOA
Gain bandwidth product
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Noise at 1 kHz (Power = Medium, opamp
ENOA
bias = High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
ms
ms
ms
–
–
–
–
–
–
5.9
0.92
0.72
ms
ms
ms
0.15
1.7
6.5
–
–
–
–
–
–
V/ms
V/ms
V/ms
0.01
0.5
4.0
–
–
–
–
–
–
V/ms
V/ms
V/ms
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Notes
Table 22. 3.3-V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising settling time from 80% of V to 0.1%
of V (10 pF load, unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Falling settling time from 20% of V to 0.1%
of V (10 pF load, unity gain)
Power = Low, opamp bias = Low
Power = Medium, Opamp Bias = High
Rising slew rate (20% to 80%)(10 pF load,
unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Falling slew rate (20% to 80%)(10 pF load,
unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Gain bandwidth product
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Noise at 1 kHz (Power = Medium, opamp
bias = High)
Document Number: 001-13108 Rev. *F
Notes
Page 31 of 49
CY8CLED04
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 6. Typical AGND Noise with P2[4] Bypass
nV /rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 7. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-13108 Rev. *F
0.01
0.1
Freq (kHz)
1
10
100
Page 32 of 49
CY8CLED04
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. Typical
parameters are measured at 5 V at 25 °C and are for design guidance only.
Table 23. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
s
Notes
50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 24. AC Digital Block Specifications
Function
All functions
Timer
Counter
CRCPRS
(PRS
Mode)
CRCPRS
(CRC
Mode)
SPIM
SPIS
Description
Block input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
No capture, VDD 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, VDD 4.75 V
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
Input clock frequency
Input clock (SCLK) frequency
Width of SS_negated between
transmissions
Min
Typ
Max
Unit
–
–
–
–
49.92
25.92
MHz
MHz
–
–
–
50[11]
–
–
–
–
49.92
25.92
25.92
–
MHz
MHz
MHz
ns
–
–
–
50[11]
–
–
–
–
49.92
25.92
25.92
–
MHz
MHz
MHz
ns
20
50[11]
50[11]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
49.92
25.92
MHz
MHz
–
–
–
–
–
–
49.92
25.92
24.6
MHz
MHz
MHz
–
–
8.2
MHz
–
50[11]
–
–
4.1
–
MHz
ns
Notes
The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
Note
11. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-13108 Rev. *F
Page 33 of 49
CY8CLED04
Table 24. AC Digital Block Specifications (continued)
Function
Transmitter
Receiver
Description
Input clock frequency
VDD 4.75 V, 2 stop bits
VDD 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
VDD 4.75 V, 2 stop bits
VDD 4.75 V, 1 stop bit
VDD < 4.75 V
Min
Typ
Max
Unit
–
–
–
–
–
–
49.92
24.6
24.6
MHz
MHz
MHz
–
–
–
–
–
–
49.92
24.6
24.6
MHz
MHz
MHz
Notes
The baud rate is equal to the input clock frequency
divided by 8.
The baud rate is equal to the input clock frequency
divided by 8.
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 25. AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency for USB applications
Min
Typ
Max
Units
23.94
24
24.06
MHz
–
Duty cycle
47
50
53
%
–
Power up to IMO switch
150
–
–
s
Notes
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 26. 5-V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = Low
Power = High
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = Low
Power = High
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF
load
Power = Low
Power = High
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = Low
Power = High
Document Number: 001-13108 Rev. *F
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
s
s
–
–
–
–
2.2
2.2
s
s
0.65
0.65
–
–
–
–
V/s
V/s
0.65
0.65
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
Page 34 of 49
CY8CLED04
Table 27. 3.3-V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = Low
Power = High
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = Low
Power = High
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = Low
Power = High
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
s
s
–
–
–
–
2.6
2.6
s
s
0.5
0.5
–
–
–
–
V/s
V/s
0.5
0.5
–
–
–
–
V/s
V/s
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 28. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise time of SCLK
1
–
20
ns
TFSCLK
Fall time of SCLK
1
–
20
ns
TSSCLK
Data setup time to falling edge of SCLK
40
–
–
ns
THSCLK
Data hold time from falling edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash erase time (Block)
–
10
–
ms
TWRITE
Flash block write time
–
40
–
ms
TDSCLK
Data out delay from falling edge of SCLK
–
–
45
ns
VDD 3.6
TDSCLK3
Data out delay from falling edge of SCLK
–
–
50
ns
3.0 VDD 3.6
TERASEALL
Flash erase time (Bulk)
–
40
–
TPROGRAM_HOT
Flash block erase + flash block write time
–
–
100[12] ms
0 °C TJ 100 °C
–
[12]
–40 °C TJ 0 °C
TPROGRAM_COLD Flash block erase + flash block write time
–
200
ms
ms
Erase all blocks and
protection fields at once.
Note
12. For the full industrial range, you must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing. Refer
to the Flash APIs Application Note, AN2015 - PSoC® 1 - Reading and Writing PSoC Flash for more information.
Document Number: 001-13108 Rev. *F
Page 35 of 49
CY8CLED04
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 29. AC Characteristics of the I2C SDA and SCL Pins for VDD
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Standard-Mode
Fast-Mode
Min
Max
Min
Max
SCL clock frequency
0
100
0
400
Hold time (repeated) START condition. After
4.0
–
0.6
–
this period, the first clock pulse is generated.
LOW period of the SCL clock
4.7
–
1.3
–
HIGH period of the SCL clock
4.0
–
0.6
–
Setup time for a repeated START condition.
4.7
–
0.6
–
Data hold time
0
–
0
–
Data setup time
250
–
100[13]
–
Setup time for STOP condition
4.0
–
0.6
–
Bus free time between a STOP and START
4.7
–
1.3
–
condition
Pulse width of spikes are suppressed by the
–
–
0
50
input filter.
Description
Units
Notes
kHz
s
s
s
s
s
ns
s
s
ns
Figure 8. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Note
13. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-13108 Rev. *F
Page 36 of 49
CY8CLED04
Packaging Information
This section illustrates the package specification for the CY8CLED04 EZ-Color device, along with the thermal impedance for the
package and solder reflow peak temperatures.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 9. 68-Pin (8 × 8 × 0.90 mm) QFN (Sawn Type)
001-09618 *C
Important Note
For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Pinned vias for thermal conduction are not required for the low-power device.
Document Number: 001-13108 Rev. *F
Page 37 of 49
CY8CLED04
Thermal Impedance
Package
Typical JA [14, 15]
68-pin QFN
13.05 C/W
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Package
68-pin QFN
Maximum Peak
Temperature
Time at Maximum Peak
Temperature
260 oC
30 s
Notes
14. TJ = TA + POWER x JA
15. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
Document Number: 001-13108 Rev. *F
Page 38 of 49
CY8CLED04
Development Tools
Software
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
This section presents the development tools available for all
current PSoC device families including the CY8CLED04
EZ-Color.
■
Evaluation Board with LCD Module
PSoC Designer
■
MiniProg Programming Unit
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com/psocprogrammer.
Device Programmers
All device programmers can be purchased from the Cypress
Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
Evaluation Tools
■
Modular Programmer Base
All evaluation tools can be purchased from the Cypress Online
Store.
■
3 Programming Module Cards
■
MiniProg Programming Unit
CY3210-MiniProg1
■
PSoC Designer Software CD
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■ MiniProg Programming Unit
■
Getting Started Guide
■
USB 2.0 Cable
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
PSoC Designer Software CD
Getting Started Guide
USB 2.0 Cable
■
■
■
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
Document Number: 001-13108 Rev. *F
CY3207ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
Note CY3207ISSP needs special software and is not compatible
with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240 V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
■
Page 39 of 49
CY8CLED04
Accessories (Emulation and Programming)
Table 30. Emulation and Programming Accessories
Part #
CY8CLED04-68LTXI
Pin
Package
68-pin QFN
Flex-Pod Kit[16]
CY3250-LED04
Adapter[17]
Adapters can be found at
http://www.emulation.com.
Third Party Tools
Build a PSoC Emulator into Your Board
Several tools have been specially designed by the following
third-party vendors to accompany PSoC devices during
development and production. Specific details for each of these
tools can be found at http://www.cypress.com under Design
Support >> Development Kits/Boards.
For details on how to emulate your circuit before going to volume
production using an on-chip debug (OCD) non-production PSoC
device, see Application Note Debugging - Build a PSoC
Emulator into Your Board - AN2323.
Document Number: 001-13108 Rev. *F
Page 40 of 49
CY8CLED04
Ordering Information
Key Device Features
The following table lists the CY8CLED04 EZ-Color device key package features and ordering codes.
Temperature
Range
Digital Blocks
Analog Blocks
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
CY8CLED04-68LTXI
CY8CLED04-68LTXIT
SRAM
(Bytes)
68-pin (8 × 8 mm) Sawn
68-pin (8 × 8 mm) Sawn
(Tape and Reel)
Flash
(Bytes)
Package
Ordering
Code
Table 31. Device Key Features and Ordering Information
16 K
16 K
1K
1K
–40 C to +85 C
–40 C to +85 C
4
4
6
6
56
56
48
48
2
2
Yes
Yes
Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-free
C = Commercial
SX = SOIC Pb-free
I = Industrial
PVX = SSOP Pb-free
E = Extended
LTX/LKX = QFN Pb-free
AX = TQFP Pb-free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Notes
16. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
17. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-13108 Rev. *F
Page 41 of 49
CY8CLED04
Acronyms
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym
Description
Acronym
Description
AC
alternating current
MAC
multiply-accumulate
ADC
analog-to-digital converter
MIPS
million instructions per second
API
application programming interface
PCB
printed circuit board
CMOS
complementary metal oxide semiconductor
PDIP
plastic dual-in-line package
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
POR
power-on reset
CT
continuous time
PPOR
precision power-on reset
DAC
digital-to-analog converter
PRS
pseudo-random sequence
PrISM™
precise illumination signal modulation
Programmable System-on-Chip™
DC
direct current
PSoC®
DTMF
dual-tone multi-frequency
PWM
pulse-width modulator
EEPROM electrically erasable programmable read-only
memory
QFN
quad flat no leads
GPIO
general purpose I/O
SAR
successive approximation register
I/O
input/output
SRAM
static random-access memory
ICE
in-circuit emulator
SC
switched capacitor
IDE
integrated development environment
SLIMO
slow IMO
ILO
internal low speed oscillator
SOIC
small-outline integrated circuit
IMO
internal main oscillator
SPI™
serial peripheral interface
IrDA
infrared data association
SROM
supervisory read-only memory
ISSP
In-System Serial Programming
UART
universal asynchronous receiver / transmitter
LCD
liquid crystal display
USB
universal serial bus
LED
light-emitting diode
WDT
watchdog timer
LPC
low power comparator
XRES
external reset
LVD
low-voltage detect
Reference Documents
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com
Document Number: 001-13108 Rev. *F
Page 42 of 49
CY8CLED04
Document Conventions
Units of Measure
Symbol
°C
dB
fF
kHz
k
MHz
A
s
V
mA
mm
ms
Unit of Measure
degree Celsius
decibels
femtofarads
kilohertz
kilohm
megahertz
microamperes
microseconds
microvolts
milliamperes
millimeter
milliseconds
Symbol
mV
mVpp
nA
ns
nV
pA
pF
ps
%
rt-Hz
V
W
Unit of Measure
millivolts
millivolts peak-to-peak
nanoamperes
nanoseconds
nanovolts
picoamperes
picofarads
picoseconds
percent
root hertz
volts
watts
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Glossary
active high
5. A logic signal having its asserted state as the logic 1 state.
6. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are switched capacitor (SC) and continuous time (CT) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
Application
Programming
Interface (API)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for
programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the
negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
Document Number: 001-13108 Rev. *F
Page 43 of 49
CY8CLED04
Glossary
(continued)
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register,
is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude.
The analog-to-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
Document Number: 001-13108 Rev. *F
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CY8CLED04
Glossary
(continued)
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides users with the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is off.
Flash block
The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in
standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a
(LVD)
selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the slave device.
Document Number: 001-13108 Rev. *F
Page 45 of 49
CY8CLED04
Glossary
(continued)
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
port
A group of pins, usually eight.
power-on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is
one type of hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse-width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
Document Number: 001-13108 Rev. *F
Page 46 of 49
CY8CLED04
Glossary
(continued)
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, after a value has been
loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is
removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform flash operations. The functions of the SROM may be
accessed in normal user code, operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high
level API for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually
5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Document Number: 001-13108 Rev. *F
Page 47 of 49
CY8CLED04
Document History Page
Document Title: CY8CLED04 EZ-Color™ HB LED Controller
Document Number: 001-13108
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
1148504
SFVTMP3
See ECN
*A
2657959
DPT/PYRS
02/11/2009
Added package diagram 001-09618 and updated Ordering Information table
*B
2794355
XBM
10/28/2009
Added “Contents” on page 3.
Updated “Development Tools” on page 7.
Corrected FCPU1 and FCPU2 parameters in “AC Chip-Level Specifications”
on page 29.
*C
2850593
FRE/DSG/HMT
01/14/2010
Removed pruned/obsolete parts (CY8CLED04-68LFXI).
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Modified TWRITE specifications.
Replaced TRAMP time) specification with SRPOWER_UP (slew rate) specification.
Added note to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL,
TPROGRAM_HOT, and TPROGRAM_COLD specifications.
Corrected the Pod Kit part numbers.
Updated Development Tools.
Updated copyright and Sales, Solutions, and Legal Information URLs.
Updated 68-Pin QFN (Sawn Type) package diagram.
*D
2900748
CGX
03/31/2010
Removed inactive parts from Ordering Information table.
Added active parts in Ordering Information table.
*E
3111560
NJF
12/15/10
Added DC I2C Specifications table.
Added F32K_U max limit.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and
I2C Timing Diagram. They were updated for clearer understanding.
Updated Figure 6 since the labelling for y-axis was incorrect.
Template and styles update.
*F
3283777
DIVA
07/13/11
Updated Getting Started, Development Tools, and Designing with PSoC
Designer.
Removed obsolete kits.
Removed reference to obsolete spec AN2012.
Document Number: 001-13108 Rev. *F
Description of Change
New document.
Page 48 of 49
CY8CLED04
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC® Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007- 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes
no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress
products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement
with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably
be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of
such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection
(United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable
license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and
or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction,
modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO,
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice
to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not
authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the
user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress
Document Number: 001-13108 Rev. *F
Revised July 13, 2011
Page 49 of 49
PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new
trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
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