IPU135N03LG

IPD135N03LG MOSFET OptiMOSª3Power-Transistor,30V DPAK tab Features •FastswitchingMOSFETforSMPS •OptimizedtechnologyforDC/DCconverters •QualifiedaccordingtoJEDEC1)fortargetapplications •N-channel,logiclevel •ExcellentgatechargexRDS(on)product(FOM) •Verylowon-resistanceRDS(on) •Avalancherated •Pb-freeplating;RoHScompliant •Halogen-freeaccordingtoIEC61249-2-21 1 2 3 Drain Pin 2, Tab Table1KeyPerformanceParameters Parameter Value Unit VDS 30 V RDS(on),max 13.5 mΩ ID 30 A Gate Pin 1 Source Pin 3 Type/OrderingCode Package Marking RelatedLinks IPD135N03L G PG-TO252-3 135N03L - 1) J-STD20 and JESD22 Final Data Sheet 1 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Final Data Sheet 2 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG 1Maximumratings atTA=25°C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Values Unit Note/TestCondition 30 26 30 21 A VGS=10V,TC=25°C VGS=10V,TC=100°C VGS=4.5V,TC=25°C VGS=4.5V,TC=100°C - 210 A TC=25°C - - 30 A TC=25°C EAS - - 20 mJ ID=10A,RGS=25Ω Reversediodedv/dt dv/dt - - 6 kV/µs ID=30A,VDS=24V,di/dt=200A/µs, Tj,max=175°C Gate source voltage VGS -20 - 20 V - Power dissipation Ptot - - 31 W TC=25°C Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche current, single pulse IAS Avalanche energy, single pulse Continuous drain current Pulsed drain current1) 2) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Values Min. Typ. Max. RthJC - - 4.9 K/W - SMD version, device on PCB, minimal footprint RthJA - - 75 K/W - SMD version, device on PCB, 6 cm² cooling area3) RthJA - - 50 K/W - 1) See figure 3 for more detailed information See figure 13 for more detailed information 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) Final Data Sheet 3 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG 3Electricalcharacteristics atTj=25°C,unlessotherwisespecified Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Unit Note/TestCondition - V VGS=0V,ID=1mA - 2.2 V VDS=VGS,ID=250µA - 0.1 10 1 100 µA VDS=30V,VGS=0V,Tj=25°C VDS=30V,VGS=0V,Tj=125°C IGSS - 10 100 nA VGS=20V,VDS=0V Drain-source on-state resistance1) RDS(on) - 16.4 11.3 20.5 13.5 mΩ VGS=4.5V,ID=20A VGS=10V,ID=30A Gate resistance RG - 1.2 - Ω - Transconductance gfs 22 43 - S |VDS|>2|ID|RDS(on)max,ID=30A Unit Note/TestCondition Min. Typ. Max. V(BR)DSS 30 - Gate threshold voltage VGS(th) 1 Zero gate voltage drain current IDSS Gate-source leakage current Table5Dynamiccharacteristics Parameter Symbol Input capacitance2) Values Min. Typ. Max. Ciss - 770 1000 pF VGS=0V,VDS=15V,f=1MHz Output capacitance2) Coss - 350 470 pF VGS=0V,VDS=15V,f=1MHz Reverse transfer capacitance Crss - 16 - pF VGS=0V,VDS=15V,f=1MHz Turn-on delay time td(on) - 3.0 - ns VDD=15V,VGS=10V,ID=30A, RG=1.6Ω Rise time tr - 3.0 - ns VDD=15V,VGS=10V,ID=30A, RG=1.6Ω Turn-off delay time td(off) - 12 - ns - Fall time tf - 2.2 - ns VDD=15V,VGS=10V,ID=30A, RG=1.6Ω Unit Note/TestCondition Table6Gatechargecharacteristics3) Parameter Symbol Gate to source charge Values Min. Typ. Max. Qgs - 2.7 - nC VDD=15V,ID=30A,VGS=0to4.5V Gate charge at threshold Qg(th) - 1.2 - nC VDD=15V,ID=30A,VGS=0to4.5V Gate to drain charge Qgd - 1.2 - nC VDD=15V,ID=30A,VGS=0to4.5V Switching charge Qsw - 2.6 - nC VDD=15V,ID=30A,VGS=0to4.5V Gate charge total Qg - 4.8 6.4 nC VDD=15V,ID=30A,VGS=0to4.5V Gate plateau voltage Vplateau - 3.5 - V VDD=15V,ID=30A,VGS=0to4.5V Qg - 10 - - VDD=15V,ID=30A,VGS=0to10V Gate charge total, sync. FET Qg(sync) - 4.2 5.5 nC VDS=0.1V,VGS=0to4.5V Output charge Qoss - 9 - - VDD=15V,VGS=0V 2) Gate charge total 2) 1) Measured from drain tab to source pin Defined by design. Not subject to production test 3) See ″Gate charge waveforms″ for parameter definition 2) Final Data Sheet 4 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG Table7Reversediode Parameter Symbol Diode continuous forward current Diode pulse current Diode forward voltage 1) Reverse recovery charge 1) Values Unit Note/TestCondition 25 A TC=25°C - 210 A TC=25°C - 0.98 1.2 V VGS=0V,IF=30A,Tj=25°C - - 10 nC VR=15V,IF=IS,diF/dt=400A/µs Min. Typ. Max. IS - - IS,pulse - VSD Qrr Defined by design. Not subject to production test Final Data Sheet 5 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG 4Electricalcharacteristicsdiagrams Diagram2:Draincurrent 35 35 30 30 25 25 20 20 ID[A] Ptot[W] Diagram1:Powerdissipation 15 15 10 10 5 5 0 0 50 100 150 0 200 0 50 100 TC[°C] 150 200 TC[°C] Ptot=f(TC) ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 101 10 100 ns 0.5 1 µs 2 10 10 µs 100 0.2 0.1 ZthJC[K/W] ID[A] 100 µs DC 101 1 ms 0.05 0.02 0.01 10 -1 single pulse 0 10 10-1 10-1 100 101 102 10-2 10-6 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25°C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 6 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 120 30 5V 100 25 10 V 3.5 V 4V 80 20 4.5 V RDS(on)[mΩ] 5V ID[A] 4.5 V 60 4V 40 0 1 2 11.5 V 5 3.2 V 3V 2.8 V 0 10 V 10 3.5 V 20 15 0 3 0 20 40 VDS[V] 60 80 100 80 100 ID[A] ID=f(VDS);Tj=25°C;parameter:VGS RDS(on)=f(ID);Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 100 80 80 60 ID[A] gfs[S] 60 40 40 20 20 175 °C 25 °C 0 0 1 2 3 4 5 0 0 VGS[V] 40 60 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 20 gfs=f(ID);Tj=25°C 7 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG Diagram10:Typ.gatethresholdvoltage 25 2.5 20 2.0 15 1.5 98 % VGS(th)[V] RDS(on)[mΩ] Diagram9:Drain-sourceon-stateresistance typ 10 5 1.0 0.5 0 -60 -20 20 60 100 140 0.0 -60 180 -20 20 Tj[°C] 60 100 140 180 Tj[°C] RDS(on)=f(Tj);ID=30A;VGS=10V VGS(th)=f(Tj);VGS=VDS;ID=250µA Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 103 10 25 °C 25 °C, max 175 °C 175 °C, max 103 Ciss 102 IF[A] C[pF] Coss 102 101 Crss 101 100 0 10 20 30 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 8 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 2 10 12 15 V 6V 10 24 V 101 100 °C 150 °C VGS[V] IAV[A] 8 25 °C 6 4 2 100 10-1 100 101 102 103 tAV[µs] 0 0 4 8 12 Qgate[nC] IAS=f(tAV);RGS=25Ω;parameter:Tj(start) VGS=f(Qgate);ID=30Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Diagram Gate charge waveforms 34 32 VBR(DSS)[V] 30 28 26 24 22 20 -60 -20 20 60 100 140 180 Tj[°C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 9 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG 5PackageOutlines DIMENSION A A1 b b2 b3 c c2 D D1 E E1 e e1 N H L L3 L4 MILLIMETERS MIN. MAX. 2.16 2.41 0.00 0.15 0.64 0.89 0.65 1.15 4,95 5.50 0.46 0.61 0.40 0.98 5.97 6.22 5.02 5.84 6.35 6.73 4.32 5.50 2.29 4.57 3 9.40 10.48 1.18 1.78 0.89 1.27 0.51 1.02 DOCUMENT NO. Z8B00003328 REVISION 07 SCALE: 10:1 0 1 2mm EUROPEAN PROJECTION ISSUE DATE 01.04.2020 Figure1OutlinePG-TO252-3,dimensionsinmm Final Data Sheet 10 Rev.2.2,2020-09-14 OptiMOSª3Power-Transistor,30V IPD135N03LG RevisionHistory IPD135N03L G Revision:2020-09-14,Rev.2.2 Previous Revision Revision Date Subjects (major changes since last revision) 2.2 2020-09-14 Update POD Trademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2020InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics (“Beschaffenheitsgarantie”). Withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Inaddition,anyinformationgiveninthisdocumentissubjecttocustomer’scompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomer’sproductsandanyuseofthe productofInfineonTechnologiesincustomer’sapplications. Thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.Itistheresponsibilityofcustomer’s technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 11 Rev.2.2,2020-09-14