IR3084U
XPHASETM VR10, VR11 & OPTERON/ATHLON64 CONTROL IC
DESCRIPTION
TM
The IR3084U Control IC combined with an IR XPhase Phase IC provides a full featured and flexible
way to implement a complete VR10, VR11, Opteron, or Athlon64 power solution. The “Control” IC
provides overall system control and interfaces with any number of “Phase” ICs which each drive and
TM
monitor a single phase of a multiphase converter. The XPhase architecture results in a power supply
that is smaller, less expensive, and easier to design while providing higher efficiency than conventional
approaches.
The IR3084U is based on the IR3084 VR10 Control IC, but incorporates the following modifications;
•
•
•
•
•
•
•
•
Supports VR11 7-bit VID, VR10 7-bit extended VID, and Opteron/Athlon64 5-bit VID codes
Supports both VR11 and legacy Opteron/Athlon64 start-up sequences
VID Select pin sets the DAC to VR10, VR11, or Opteron/Athlon64
INTL_MD output pin indicates which DAC is selected – Intel or AMD
VOSENS− float detection protects the CPU in the event that the VOSENS− trace is broken
Enable Input Thresholds set by VID Select pin to either VR10, VR11 or Opteron/Athlon64
VID Input Thresholds set by VID Select pin to either 0.6V (VR10/VR11) or 1.24V (AMD)
No-Load Setpoint Current changes polarity based on VID Select to accommodate VR10, VR11
(negative offset from DAC) or Opteron/Athlon64 (positive offset from DAC).
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 to X phase operation with matching Phase IC
7-bit VR 10/11 compatible VID with 0.5% overall system set point accuracy
5-bit Opteron/Athlon64 compatible VID with 1% overall system set point accuracy
Programmable Dynamic VID Slew Rate
+/-300mV Differential Remote Sense
Programmable VID Offset Voltage at the Error Amplifier’s Non-Inverting Input allows Zero Offset
Programmable 150kHz to 1MHz oscillator
Programmable VID Offset and Load Line output impedance
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified VR Ready output provides indication of proper operation and avoids false triggering
Operates from 12V input with 9.9V Under-Voltage Lockout
6.8V/6mA Bias Regulator provides System Reference Voltage
Phase IC Gate Driver Bias Regulator / VRHOT Comparator
Reduced Over-Current Detect Delay eliminates and external resistor in typical applications
Small thermally enhanced 28L MLPQ package
Page 1 of 47
June 1, 2009
IR3084U
TYPICAL APPLICATION CIRCUIT
CCP1
100pF
EA
+5.0V
RT2
R117
4.7K, B=4450 1.21K
RFB1
162
RCP
2.49K
VSS_SENSE
R1331
1
Q4
CJD200
VGDRIVE
EAOUT VRRDY
IIN
RMPOUT
VBIAS
FB
RDRP1
750
C204
0.1uF
U5
18
17
RFB
348
VREG_12V_FILTERED
R137
2K
CFB
12nF
VCC_SENSE
C1009
1nF
CCP
56nF
27
15
19
20
C135
1uF
VR_RDY
ISHARE
RMP
VBIAS
RDRP
750
C134
0.1uF
C89
100pF
IR3084UMTR
Q5
REGDRV
16
VDRP
REGFB
REGSET
28
9
8
7
6
5
4
3
1
OUTEN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID_SEL
ENABLE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VIDSEL
INTL_MD
R30
10
VCC
OCSET
26
SS/DEL
VDAC
CSS/DEL
0.1uF
VOSNS-- LGND ROSC
10
Page 2 of 47
2
RVGDRV
97.6K
CVGDRV
10nF
Q6
VSETPT
C130
0.1uF
25
RVSETPT1
124
VREG_12V_FILTERED
21
24
23
22
14
13
12
RVSETPT
124
ROCSET
12.7K
VDAC
RVDAC
3.5
11
ROSC
30.1K
CVDAC
33nF
June 1, 2009
IR3084U
ORDERING INFORAMATION
DEVICE
ORDER QUANTITY
IR3084UMTRPBF
3000 Tape and Reel
IR3084UMPBF
100 Piece Strip
ABSOLUTE MAXIMUM RATINGS
o
Operating Junction Temperature……………..0 to 150 C
o
o
Storage Temperature Range………………….−65 C to 150 C
ESD Rating………………………………………HBM Class 1B JEDEC standard
o
Moisture Sensitivity Level………………………JEDEC Level 2 @ 260 C
PIN #
1
2
3-9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Page 3 of 47
PIN NAME
VIDSEL
INTL_MD
VID6−VID0
VOSNSROSC
VDAC
OCSET
VSETPT
IIN
VDRP
FB
EAOUT
RMPOUT
VBIAS
VCC
LGND
REGFB
REGDRV
REGSET
SS/DEL
VRRDY
ENABLE
VMAX
20V
20V
20V
0.5V
20V
20V
20V
20V
20V
20V
20V
10V
20V
20V
20V
n/a
20V
20V
20V
20V
20V
20V
VMIN
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
ISOURCE
1mA
1mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
5mA
1mA
20mA
5mA
50mA
1mA
50mA
1mA
10mA
1mA
1mA
1mA
1mA
ISINK
1mA
1mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
5mA
1mA
20mA
5mA
10mA
50mA
1mA
1mA
50mA
1mA
1mA
20mA
1mA
June 1, 2009
IR3084U
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 9.5V ≤ VCC ≤ 16V, −0.3V ≤ VOSNS- ≤ 0.3V,
o
o
0 C ≤ TJ ≤ 100 C, ROSC = 24kΩ, CSS/DEL = 0.1µF ±10%
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
−0.5
0.5
%
−5
+5
mV
25 C ≤ TJ ≤ 100 C
−1
1
%
Includes OCSET and VSETPT currents
Includes OCSET and VSETPT currents
104
92
113
100
122
108
µA
µA
500
600
700
mV
1.04
1.24
1.44
V
0V < VIDx < VCC
Measure Time till VRRDY drives low
VIDSEL Floating
−5
0.5
1.95
2.25
0
1.3
2.4
4.5
5
2.1
2.85
9
µA
µs
V
KΩ
VIDSEL “LOW”
0.5
0.6
0.7
V
6.49K from VIDSEL to GND
0.9
1.3
1.7
V
1.8
1.95
2.1
V
−5
0.0
5
mV
−1
48.5
−54
90
6
0.5
53.5
−39
110
1.4
−1.2
0.5
−0.1
51
−47
100
10
200
3.2
−0.7
1.1
400
5
−0.35
1.7
µA
µA
µA
dB
MHz
Hz
V/µs
mA
mA
150
350
600
mV
30
125
200
mV
VDAC REFERENCE
VR10/VR11 System Set-Point
Accuracy (Deviation from
Tables 1 & 2 per test circuit in
Figure 1 which emulates in-VR
operation)
Opteron/Athlon64 System SetPoint Accuracy
Source Current
Sink Current
VR10/VR11 VIDx Input
Threshold
Opteron/Athlon64 VIDx Input
Threshold
VIDx Input Bias Current
VIDx 11111x Blanking Delay
VIDSEL Pull up Voltage
VIDSEL Pull up Resistor
VIDSEL VR10/Opteron
Threshold
VIDSEL Opteron Voltage
VIDSEL Opteron/VR11
Threshold
VID ≥ 1V, 10kΩ≤ROSC≤100kΩ,
o
o
25 C ≤ TJ ≤ 100 C
0.8V ≤ VID < 1V, 10kΩ≤ROSC≤100kΩ,
o
o
25 C ≤ TJ ≤ 100 C
o
o
ERROR AMPLIFIER
Input Offset Voltage
FB Bias Current
VSETPT Bias Current
VSETPT Bias Current
DC Gain
Gain Bandwidth Product
Corner Frequency
Slew Rate
Source Current
Sink Current
Max Voltage
Min Voltage
Page 4 of 47
Measure V(FB) – V(VSETPT) per test
circuit in Figure 1. Applies to all VID
codes. Note 2.
VR10/VR11 Mode
Opteron/Athlon64 Mode
Note 1
Note 1
45 deg Phase Shift, Note 1
Note 1
VBIAS–VEAOUT (referenced to
VBIAS)
Normal operation or Fault mode
June 1, 2009
IR3084U
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
V(SS/DEL) > 0.85V, V(EAOUT) > 0.5V
−2.0
−0.2
1.0
µA
V(SS/DEL) < 0.35V
5.6
12.5
19.4
KΩ
V(EAOUT)
0.20
0.35
0.50
V
V(SS/DEL)
0.35
0.60
0.85
V
V(VDRP) – V(IIN), 0.5V < V(IIN) < 5V
0.5V < V(IIN) < 5V
0.5V < V(IIN) < 5V
Note 1
Note 1
−10
−9.0
0.2
1
5
−2
−6.8
0.85
6
10
6
−4.0
4.1
mV
mA
mA
MHz
V/µs
−5mA < I(VBIAS) < 0mA
6.6
−35
6.9
−20
7.2
−6
V
mA
−10
−53.5
0
−51
10
−48.5
mV
µA
RDRP = ∞
RDRP = ∞, Time to reach 1.1V
VR10/VR11 mode only
1.2
0.8
0.2
1.8
1.8
1.0
2.6
2.8
2.5
ms
ms
ms
VR10/VR11 mode only
0.5
1.3
2.2
ms
Opteron/Athlon64 mode. Measured from
Vcore=1.1V to when VRRDY transitions HI.
0.7
2.3
4.7
ms
150
250
350
us
0.85
1.3
1.5
V
40
4
70
6.5
100
9
µA
µA
9.5
11.2
12.5
µA/µA
20
3.6
40
3.85
60
4.1
µA
V
CURRENT SENSE INPUT
IIN BIAS CURRENT
IIN Preconditioning Pull-Down
Resistance
IIN Preconditioning RESET
Threshold
IIN Preconditioning SET
Threshold
VDRP BUFFER AMPLIFIER
Input Offset Voltage
Source Current
Sink Current
Bandwidth (-3dB)
Slew Rate
VBIAS REGULATOR
Output Voltage
Current Limit
OVER-CURRENT COMPARATOR
Input Offset Voltage
OCSET Bias Current
1V < V(OCSET) < 5V
SOFT START AND DELAY
Start Delay (TD1)
Soft Start Time (TD2)
VID Sample Delay (TD3)
DVID Slew Time & VRRDY
Delay (TD4+TD5)
PowerGood Delay
OC Delay Time
SS/DEL to FB Input Offset
Voltage
SS/DEL Charge Current
SS/DEL Discharge Current
Charge/Discharge Current
Ratio
OC Discharge Current
Charge Voltage
OC/VRRDY Delay Comparator
Threshold
OC/VRRDY Delay Comparator
Threshold
Delay Comparator Hysteresis
VID Sample Delay
Comparator Threshold
SS/DEL Discharge
Comparator Threshold
Page 5 of 47
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
Note 1
Relative to Charge Voltage, SS/DEL
rising
Relative to Charge Voltage, SS/DEL
falling
Note 1
VR10/VR11 mode only
80
mV
100
mV
20
mV
3.10
V
215
mV
June 1, 2009
IR3084U
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
150
0
300
10
mV
µA
VRRDY OUTPUT
Output Voltage
Leakage Current
I(VRRDY) = 4mA
V(VRRDY) = 5.5V
ENABLE INPUT
VR10/11 Threshold Voltage
VR10/11 Threshold Voltage
VR10/11 Threshold Hysteresis
Opteron/Athlon64 Threshold
Voltage
Opteron/Athlon64 Threshold
Voltage
Opteron/Athlon64 Threshold
Hysteresis
Input Resistance
Blanking Time
ENABLE rising
ENABLE falling
800
700
70
850
750
100
900
800
130
mV
mV
mV
ENABLE rising
1.11
1.23
1.35
V
ENABLE falling
1.06
1.17
1.29
V
35
60
85
mV
50
100
200
KΩ
Noise Pulse < 250ns will not register
an ENABLE state change. Note 1
75
250
400
ns
ROSC = 24KΩ
450
500
550
kHz
70
71
74
%
10
13
15
%
100
250
50
200
750
170
400
300
1500
350
900
µA
µA
mV
mV
1.2
2
2.6
V
200
350
600
ns
−112
−99
−85
µA
−12
0
12
mV
10
20
50
mA
0.4
0.87
1.33
V
OSCILLATOR
Switching Frequency
Peak Voltage (4.8V typical,
measured as % of VBIAS)
Valley Voltage (0.9V typical,
measured as % of VBIAS)
INTL_MD OUTPUT
Source Current
Sink Current
Max Voltage
Min Voltage
V(INTL_MD)=2V, VR10 or VR11 mode
V(INTL_MD)=2V, Opteron mode
Pin Floating, V(VBIAS)−V(INTL_MD)
Pin Floating, LGND referenced
VOSNS− FLOAT DETECT
Detect Voltage
Detect Delay
V(VOSNS−) with respect to V(LGND),
Verify V(VRRDY) and V(EAOUT) are
low.
V(VOSNS-) 0V to 2.6V step, measure
time when V(VRRDY) falls. Note 1
DRIVER BIAS REGULATOR
REGSET Bias Current
Input Offset Voltage
Short Circuit Current
Dropout Voltage
Page 6 of 47
1.5V < V(REGSET) < VCC – 1.5V
1.5V < V(REGSET) < VCC – 1.5V,
100µA < I(REGDRV) < 10mA
V(REGDRV) = 0V,
1.5V < V(REGSET) < VCC – 1.5V,
Note 1
I(REGDRV) = 10mA, Note 1
June 1, 2009
IR3084U
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
9.3
8.5
550
9.9
9.1
800
10.3
9.5
1000
V
V
mV
9
14
18
mA
−1.45
−1.1
−0.75
mA
VCC UNDER-VOLTAGE LOCKOUT
Start Threshold
Stop Threshold
Hysteresis
Start – Stop
GENERAL
VCC Supply Current
−0.3V < VOSNS− < 0.3V,
All VID Codes
VOSNS− Current
Note 1: Guaranteed by design, but not tested in production
Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors
IR3084U
+
200 OHM
-
EAOUT
ERROR
AMP
FB
200 OHM
VDAC
BUFFER
AMP
VSETPT
ISOURCE
OCSET
VDAC
ISINK
+
INTEL: +IOFFSET
IROSC
AMD: --IOFFSET
IROSC IOCSET
RVDAC
+
CURRENT
SOURCE
GENERATOR
ROSC
BUFFER
AMP
CVDAC
-
-
+
"FAST"
VDAC
SYSTEM
SET POINT
VOLTAGE
ROSC
+
ROSC
1.2V
VOSNS-
Figure 1 – System Set Point Test Circuit
Page 7 of 47
June 1, 2009
IR3084U
PIN DESCRIPTIONS
PIN#
PIN SYMBOL
1
VIDSEL
2
INTL_MD
3-9
10
VID6−VID0
VOSNS−
11
ROSC
12
VDAC
13
OCSET
14
VSETPT
15
IIN
16
VDRP
17
18
19
FB
EAOUT
RMPOUT
20
VBIAS
21
22
VCC
LGND
23
REGFB
24
REGDRV
25
REGSET
26
SS/DEL
27
VRRDY
28
ENABLE
Page 8 of 47
DESCRIPTION
Selects the DAC table and the type of Soft Start. There are 3 possible modes of
operation: (1) GND selects VR10 DAC and VR11 type startup, (2) FLOAT (2.4V)
selects VR11 DAC and VR11 type startup, (3) 6.49K to GND (1.3V) selects
Opteron/Athlon64 DAC and legacy type startup. Additional details are provided in
the Theory of Operation section.
Output that indicates if the controller is in Intel Mode or AMD Mode. This pin will be
Low when in AMD mode and High when in Intel mode.
Inputs to the D to A Converter. Must be connected to an external pull up resistor.
Negative Remote Sense Input. Connect to ground at the Load.
Connect a resistor from this pin to VOSNS− to program the oscillator’s frequency,
OCSET, VSETPT, REGSET, and VDAC bias currents.
Regulated output voltage programmed by the VID inputs. Connect an external RC
network to from this pin to VOSNS− to program the Dynamic VID slew rate and
provide compensation for the internal Buffer Amplifier.
Programs the hiccup over-current threshold through an external resistor tied to
VDAC and an internal current source. Over-current protection can be disabled by
connecting a resistor from this pin to VDAC to program the threshold higher than the
possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not
float this pin as improper operation will occur).
Error Amp non-inverting input. The converter’s output voltage can be decreased
(Intel) or increased (AMD) from the VDAC voltage with an external resistor
connected between VDAC and an internal current source. Current sensing and
PWM operation are referenced to this pin.
Current Sense input from the Phase IC(s). Prior to startup, when SS/DEL0.6V and EAOUT>0.35V, this pin is released and current balancing
is enabled. If AVP or over-current protection is not required, connect this pin to
VDAC. To ensure proper do not float this pin.
Buffered IIN signal. Connect an external resistor from this pin to the FB pin to set the
converter’s output impedance.
Inverting input to the Error Amplifier.
Output of the Error Amplifier. When Low, provides UVL function to the Phase ICs.
Oscillator Output voltage. Used by the Phase ICs to program Phase Delay.
6.9V/6mA Regulated output used as a system reference voltage for internal circuitry
and for phase timing at the Phase ICs.
Power Input for the internal circuitry.
Local Ground for internal circuitry and IC substrate connection
Inverting input of the Bias Regulator Error Amp. Connect this pin to the collector of
the Phase IC Gate Driver Bias transistor.
Output of the Bias Regulator Error Amp.
Non-inverting input of the Bias Regulator Error Amp. The output voltage of the
Phase IC Gate Driver Bias Regulator is set by an internal current source supplying
an external resistor connected from this pin to ground.
Controls converter start-up and over-current timing. Connect an external capacitor
from this pin to LGND to program the soft start and delay times.
Open Collector output that drives low during start-up and when any external fault
occurs. Connect external pull-up resistor.
Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin
has a 100K pull-down resistor to GND.
June 1, 2009
IR3084U
SYSTEM THEORY OF OPERATION
XPhase
TM
Architecture
TM
The XPhase
architecture is designed for multiphase interleaved buck converters which are used in
applications requiring small size, design flexibility, low voltage, high current and fast transient response. The
architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility
facilitates the design trade-off of multiphase converters. The scalable architecture can be applied to other
applications which require high current or multiple output voltages.
TM
As shown in Figure 2, the XPhase architecture consists of a Control IC and a scalable array of phase
converters each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire
analog bus, i.e. bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control
IC incorporates all the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault
protections etc. The Phase IC implements the functions required by the converter of each phase, i.e. the gate
drivers, PWM comparator and latch, over-voltage protection, and current sensing and sharing.
TM
There is no unused or redundant silicon with the XPhase architecture compared to others such as a 4 phase
controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus
eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and
current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the
parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.
VR READY
PHASE FAULT
VR HOT
VR FAN
12V
ENABLE
VIDSEL
PHASE FAULT
VID6
VID5
VID4
IR3084
CONTROL
IC
CIN
>> BIAS VOLTAGE
VOUT SENSE+
>> PHASE TIMING
CURRENT SHARE
> PWM CONTROL
VID2
>> VID VOLTAGE
VOUT+
IR3086
PHASE
IC
COUT
VID1
VOUT-
VID0
CCS
RCS
CCS
RCS
VOUT SENSE-
PHASE FAULT
CURRENT SHARE
IR3086
PHASE
IC
ADDITIONAL PHASES
CONTROL BUS
INPUT/OUTPUT
Figure 2 – System Block Diagram
Page 9 of 47
June 1, 2009
IR3084U
PWM Control Method
TM
The PWM block diagram of the XPhase architecture is shown in Figure 3. Feed-forward voltage mode control
with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is
used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to
program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp
slope will change with the input voltage and automatically compensate for changes in the input voltage. The input
voltage can change due to variations in the silver box output voltage or due to drops in the PCB related to
changes in load current.
VIN
CONTROL IC
PHASE IC
SYSTEM
REFERENCE
VOLTAGE
BIASIN
RAMP GENERATOR
VPEAK
RMPOUT
RAMPIN+
RRAMP1
VVALLEY
RAMPIN-
-
VOUT
COUT
R
GATEL
+
GND
RPWMRMP
RVSETPT
ENABLE
RAMP
SLOPE
ADJUST
-
+
EAIN
PWMRMP
VDAC
VSETPT
VOSNS+
RESET
DOMINANT
RRAMP2
VOSNS-
-
PWM
COMPARATOR
+
VDAC
VBIAS
REGULATOR
GATEH
S
-
VBIAS
+
PWM
LATCH
CLOCK
PULSE
GENERATOR
+
50%
DUTY
CYCLE
VOSNS-
-
SCOMP
O% DUTY
CYCLE
COMPARATOR
+
RAMP
DISCHARGE
CLAMP
CPWMRMP
X
0.91
+
ISHARE
20mV
10K
-
FB
CURRENT
SENSE
AMP
-
X34
IOFFSET
-
+
+
RVFB
-
SHARE
ADJUST
ERROR
AMP
CSCOMP
CSIN+
+
EAOUT
ERROR
AMP
CCS
RCS
CCS
RCS
CSIN-
RDRP
IROSC
VDRP
AMP
DACIN
VDRP
+
-
IIN
PHASE IC
SYSTEM
REFERENCE
VOLTAGE
BIASIN
PWM
LATCH
CLOCK
PULSE
GENERATOR
+
RAMPIN+
RRAMP1
-
RAMPIN-
GATEH
S
PWM
COMPARATOR
-
EAIN
RESET
DOMINANT
R
GATEL
+
RRAMP2
-
RPWMRMP
RAMP
SLOPE
ADJUST
+
PWMRMP
ENABLE
-
SCOMP
O% DUTY
CYCLE
COMPARATOR
+
RAMP
DISCHARGE
CLAMP
CPWMRMP
+
10K
20mV
-
CURRENT
SENSE
AMP
X34
-
ISHARE
CSIN+
+
+
X
0.91
-
SHARE
ADJUST
ERROR
AMP
CSCOMP
CSIN-
DACIN
Figure 3 – IR3084U PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the
Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the
VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the
oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the
PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors.
Figure 4 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be
used for synchronization by swapping the RAMP + and – pins.
Page 10 of 47
June 1, 2009
IR3084U
50% RAMP
DUTY CYCLE
RAMP (FROM
CONTROL IC)
SLOPE = 80mV / % DC
VPEAK (5.0V)
VPHASE4&5 (4.5V)
SLOPE = 1.6mV / ns @ 200kHz
SLOPE = 8.0mV / ns @ 1MHz
VPHASE3&6 (3.5V)
VPHASE2&7 (2.5V)
VPHASE1&8 (1.5V)
VVALLEY (1.00V)
CLK1
PHASE IC CLOCK PULSES
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Figure 4 – 8 Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the
PWMRMP voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on.
When the PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the
high side driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly
discharges the PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It
also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes
in response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage is that differences in ground or input
voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Page 11 of 47
June 1, 2009
IR3084U
Body Braking
TM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW = [L x (IMAX - IMIN)] / Vout
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODY DIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW = [L x (IMAX - IMIN)] / (Vout + VBODY DIODE)
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amp’s output voltage drops below
91% of the VDAC voltage this comparator turns off the low side gate driver.
Figure 5 depicts PWM operating waveforms under various conditions
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
BODY BRAKING
THRESHOLD
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, VCCVID UV, OCP, VID=11111X)
STEADY-STATE
OPERATION
Figure 5 – PWM Operating Waveforms
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the
inductor and measuring the voltage across the capacitor. The equation of the sensing network is,
vC ( s ) = v L ( s)
R + sL
1
= i L ( s) L
1 + sRS C S
1 + sRS C S
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
Page 12 of 47
June 1, 2009
IR3084U
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with the inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side
sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they
suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of
frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10%
larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense
amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all
additional sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 6. Its gain
decreases with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This
reduction of gain tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the
Phase IC junction is hotter than the inductor these two effects tend to cancel such that no additional temperature
compensation of the load line is required.
The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC
and other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the
phases are tied together and the voltage on the share bus represents the average inductor current through all the
inductors and is used by the Control IC for voltage positioning and current limit protection.
vL
iL
CSA
L
RL
Rs
Cs
Vo
Co
vc
CO
Figure 6 – Inductor Current Sensing and Current Sense Amplifier
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each Phase
IC. The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a
phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source
that reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover
frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop
does not interact with the output voltage loop.
Page 13 of 47
June 1, 2009
IR3084U
IR3084U THEORY OF OPERATION
Block Diagram
VRRDY
VCC UVLO
COMPARATOR
UVLO
VOSNS OPEN
DISABLE
OVER CURRENT
-
0.215V DISCHARGE
COMPARATOR
-
+
+
80mV
100mV
VCHG
3.85V
-
-
OC
DISCHARGE
CURRENT
40uA
-
R
+
VID
FAULT
LATCH
R
ON
12.5K
S
0.35V
S
+
+
100k
DELAY
COMPARATOR
-
IIN
0.6V
VDRP
AMP
+
AMD
1.23V
1.17V
R
FAULT
LATCH
-
OC
COMPARATOR
IIN
PRECONDITIONING
LATCH
VDRP
+
OCSET
ON
LGND
IHICCUP
DISCHARGE
6.5uA
ICHG
70uA
S
SS/DEL
DISCHARGE
OFF
VID SAMPLE
DELAY COMPARATOR
3.1V
SS/DEL
-
SET
DOMINANT
INTEL
850mV
750mV
NO CPU LATCHED
+
+
NO CPU
+
ENABLE
COMPARATOR
250ns
BLANKING
ENABLE
-
+
SET
DOMINANT
+
-
-
S
-
2.0V
9.9V
9.1V
SET
DOMINANT
VOSNS FLOAT
DETECT
SET
DOMINANT
+
+
-
-
+
VCC
START
LATCH
R
+
+
VID0
2.4V
-
VID1
INTL_MD
IROSC
+
VID2
+
INTEL: 0.6V
AMD: 1.24V
IROSC
"FAST"
IROSC
VDAC
IROSC
+
+
+
+
IROSC
INTEL: IOFFSET
AMD: -IOFFSET
0.6V
IROSC
-
1.1V
-
4.5K
FB
VSETPT
VDAC
ISOURCE
IROSC
INTEL/AMD
SOFTSTART
CLAMP
IOCSETIROSC
-
+
EAOUT
ERROR
AMP
-
VID3
DISABLE
+
VID4
1.3V
+
VID5
DIGITAL TO
IROSC
ANALOG
IROSC
CONVERTER
IROSC
NO_CPU
-
VID INPUT
COMPARATORS
(1 OF 9
SHOWN)
VID6
1.3us
BLANKING
+
+
IROSC
1.95V
ISINK
-
VDAC
BUFFER
AMP
VID = 1.1V BOOT
VIDSEL
1.2V
+
-
VOSNSVBIAS
VBIAS
RAMP GENERATOR
-
6.9V
+
IROSC
CURRENT
SOURCE
GENERATOR
ROSC
BUFFER
AMP
IROSC
-
0.9V
+
RMPOUT
-
4.8V
INTL_MD
VBIAS
REGULATOR
+
50%
DUTY
CYCLE
VCC
BIAS
REGULATOR
ERROR AMP
REGDRV
REGFB
IREGSET
REGSET
ROSC
Figure 7 – IR3084U Block Diagram
VID Control
A 7-bit VID voltage compatible with VR10 (see Table 1) and VR11 (see Table 2) and Opteron/Athlon64 (see
Table 3) is available at the VDAC pin. The VIDSEL pin configures the DAC for VR10 if grounded, VR11 if
floating, and Opteron/Athlon64 if connected to GND via a 6.4K resistor. The VIDSEL pin is internally pulled-up to
2.4V through a 4.5Kohm resistor. The VID pins require an external bias voltage and should not be floated. The
VID input comparators, with 0.6V reference for VR10/VR11 and 1.24V for Opteron/Athlon64, monitor the VID
pins and control the 7-bit Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier.
The output of the buffer amp is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for
the input offsets of the Error Amp to provide a 0.5% system accuracy. The actual VDAC voltage does not
represent the system set point and has a wider tolerance.
Page 14 of 47
June 1, 2009
IR3084U
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
VID1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID5
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Voltage
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
1.21250
1.20625
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
VID1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
VID0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID5
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID6
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Voltage
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
FAULT
FAULT
FAULT
FAULT
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
Table 1 – VR10 7-bit VID Table with 6.25mV Extension
Page 15 of 47
June 1, 2009
IR3084U
Hex (VID7:VID0)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Dec (VID7:VID0)
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
Voltage
Fault
Fault
1.60000
1.59375
1.58750
1.58125
1.57500
1.56875
1.56250
1.55625
1.55000
1.54375
1.53750
1.53125
1.52500
1.51875
1.51250
1.50625
1.50000
1.49375
1.48750
1.48125
1.47500
1.46875
1.46250
1.45625
1.45000
1.44375
1.43750
1.43125
1.42500
1.41875
1.41250
1.40625
1.40000
1.39375
1.38750
1.38125
1.37500
1.36875
1.36250
1.35625
1.35000
1.34375
1.33750
1.33125
1.32500
1.31875
1.31250
1.30625
1.30000
1.29375
1.28750
1.28125
1.27500
1.26875
1.26250
1.25625
1.25000
1.24375
1.23750
1.23125
1.22500
1.21875
Hex (VID7:VID0)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Dec (VID7:VID0)
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
Voltage
1.21250
1.20625
1.20000
1.19375
1.18750
1.18125
1.17500
1.16875
1.16250
1.15625
1.15000
1.14375
1.13750
1.13125
1.12500
1.11875
1.11250
1.10625
1.10000
1.09375
1.08750
1.08125
1.07500
1.06875
1.06250
1.05625
1.05000
1.04375
1.03750
1.03125
1.02500
1.01875
1.01250
1.00625
1.00000
0.99375
0.98750
0.98125
0.97500
0.96875
0.96250
0.95625
0.95000
0.94375
0.93750
0.93125
0.92500
0.91875
0.91250
0.90625
0.90000
0.89375
0.88750
0.88125
0.87500
0.86875
0.86250
0.85625
0.85000
0.84375
0.83750
0.83125
0.82500
0.81875
Table 2 – VR11 7-bit VID Table
Page 16 of 47
June 1, 2009
IR3084U
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Vout (V)
1.550
1.525
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
0.900
0.875
0.850
0.825
0.800
4
OFF
Table 3 – Opteron 5-bit VID Table
Page 17 of 47
June 1, 2009
IR3084U
Dynamic VID Operation
The IR3084U can accept changes in the VID code while operating and vary the DAC voltage accordingly. The
sink/source capability of the VDAC buffer amp is programmed by the external resistor that sets the oscillator
frequency (Rosc). The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between
VDAC pin and the VOSNS− pin. A resistor connected in series with this capacitor is required to compensate the
VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and
converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output
voltage.
Adaptive Voltage Positioning (AVP)
Adaptive Voltage Positioning (AVP) is needed to reduce the total output voltage deviations during load transients
and to reduce the power dissipation of the load when it is drawing high current. The circuitry related to the voltage
positioning is shown in Figure 8.
Resistor RSETPT is connected between the VDAC pin and the VSETPT pin to set the desired amount of fixed
offset voltage above or below the DAC voltage. The VSETPT pin is internally connected to both the non-inverting
input of the voltage error amplifier and an internal current source, IOFFSET. The magnitude of IOFFSET is
programmed by the external resistor that programs the oscillator frequency (Rosc) while the polarity of IOFFSET is
set by the VIDSEL pin. When the VR10 and VR11 DAC tables are selected, the polarity of IOFFSET is positive
(current flows into the pin). When the Opteron/Athlon64 DAC table is selected, the polarity of IOFFSET is negative
(current flow out of the pin). The voltage across RSETPT sets the no load offset voltage above or below the
VDAC voltage.
The voltage at the VDRP pin is a buffered version of the current share bus (Iin) and represents the sum of the
VDAC voltage and the average inductor current of all the phases. The VDRP pin should be connected to the FB
pin through the resistor RDRP. Because the Error Amp will regulate the voltage at the FB pin equal to the
voltage at the VSETPT pin, a current will flow from the VDRP pin to the FB pin equal to (VDRP−VSETPT) / RDRP.
When the load current increases, the VDRP voltage will increase, additional current will flow through the
feedback resistor RFB and the converter’s output voltage will droop below the no load setpoint. The amount of
voltage droop can be programmed by the resistor RDRP so the converter’s output impedance meets the load-line
specification set by the CPU manufacturer. The offset and slope of the converter’s output impedance are
referenced to VDAC and are therefore independent of the exact VDAC (VID) setting.
Due to the difference between VDAC and FB, the voltage at the VDRP pin causes additional offset voltage
through RDRP and RFB. The total offset voltage is the sum of the voltage across RVSETPT and the voltage
drop across the RFB resistor at no load.
Control IC
VDAC
VDAC
Phase IC
Current Sense
Amplifier
+
VDAC
-
10k
CSIN-
Vo
RFB
Error
Amplifier
RDRP
Phase IC
VDRP
Current Sense
Amplifier
+
IIN
ISHARE
VDAC
10k
CSIN+
-
VDRP
Amplifier
... ...
FB
+
IOFFSET
EAOUT
CSIN+
-
ISHARE
+
VSETPT
RSETPT
CSIN-
Figure 8 - Adaptive voltage positioning
Page 18 of 47
June 1, 2009
IR3084U
Inductor DCR Temperature Correction
If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current
sense amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional
correction. The thermistor should be placed close to the inductor and connected in parallel with the feedback
resistor, as shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the
thermistor.
Control IC
VDAC
RSETPT
VSETPT
+
EAOUT
IOFFSET
Vo
RFB
Error
Amplifier
AVP
Amplifier
RFB2
Rt
RDRP
VDRP
+
IIN
Figure 9 - Temperature compensation of inductor DCR
Remote Voltage Sensing
To compensate for impedance in the ground plane, the VOSNS− pin is used for remote ground sensing and
connects directly to the load. The VDAC voltage is referenced to VOSNS− to avoid additional error terms or
delays related to a separate differential amplifier. The capacitor connecting the VDAC and VOSNS− pins ensure
that high speed transients are fed directly into the error amp without delay.
Start-up Modes
The IR3084U has a programmable soft-start function to limit the surge current during converter start-up. A
capacitor connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay,
and hiccup mode timing. A charge current of 70µA controls the positive slope of the voltage at the SS/DEL pin.
There are two types of start-up possible: VR11 and Opteron/Athlon64. In VR11 mode, the soft start circuitry will
set the voltage at the VDAC pin to the 1.1V Boot voltage and the converter’s output will slowly rise using the slew
rate set by the capacitor at the SS/DEL pin until it’s equal to the VDAC voltage. After Vcore reaches the 1.1V
Boot voltage there will be a short delay, the VID pins will be sampled, and the voltage at the VDAC pin and the
converter’s output will increase or decrease to the desired VID setting using the dynamic VID slew rate. In
Opteron/Athlon64 mode, the soft start sequence will ramp the voltage at the VDAC pin directly to the external VID
setting using the slew rate set by the capacitor at the SS/DEL pin without pausing at the 1.1V Boot voltage.
Page 19 of 47
June 1, 2009
IR3084U
Figure 10a depicts the start-up sequence without AVP in Boot mode − the VIDSEL pin is either grounded or
floated. First, the VDAC pin is charged to the 1.1V Boot voltage. Then, if there are no fault conditions, the
SS/DEL capacitor will begin to be charged. Initially, the error amplifier’s output will be clamped low until the
voltage at the SS/DEL reaches 1.3V. After the voltage at the SS/DEL pin rises to 1.3V, the error amplifier’s
output will begin to rise and the converter’s output voltage will be regulated 1.3V below the voltage at the SS/DEL
pin. The converter’s output voltage will slowly ramp to the 1.1V Boot voltage. The SS/DEL voltage will continue
to increase until it rises above the 3.10V threshold of the VID delay comparator. When the SS/DEL voltage
exceeds 3.10V, the VID inputs will be sampled and the VDAC pin will transition to the level determined by the VID
inputs at the dynamic VID slew rate. When the voltage on the SS/DEL pin rises above 3.77V the VRRDY Delay
Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise until finally settling at
3.85V, indicating the end of the start-up sequence.
Figure 10b depicts the start-up sequence in Opteron/Athlon64 mode − VIDSEL is connected to GND via a 6.49K
resistor. First, the external VID setting is sampled and the VDAC pin is set to the desired VID voltage. Then, if
there are no fault conditions, the SS/DEL capacitor will begin to charge. Initially, the error amplifier’s output will
be clamped low until the voltage at the SS/DEL rises to 1.3V. After the voltage at the SS/DEL pin reaches 1.3V,
the error amplifier’s output will begin to rise and the converter’s output voltage will be regulated 1.3V below the
voltage at the SS/DEL pin. As the voltage at the SS/DEL pin continues to rise, the converter’s output voltage will
slowly increase until it is equal to the voltage at the VDAC pin. When the voltage on the SS/DEL pin rises above
3.77V the VRRDY Delay Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise
until finally settling at 3.85V, indicating the end of the start-up sequence.
If AVP is used, the soft start timing will change slightly because of the resistor from the VDRP amplifier to the
Error Amplifier’s FB pin. During startup with AVP, the VDRP amplifier will produce a voltage at the FB pin equal
to VDAC times the resistor divider formed by the droop resistor and the feedback resistor from Vcore to the FB
pin. To offset the contribution from the VDRP amplifier, the voltage at the SS/DEL pin will have to rise to beyond
1.3V before the Error Amplifier’s output and Vcore begin to rise. For a DAC setting of 1.3V with typical VR11
AVP, the Error Amplifier’s output will begin to rise when the voltage at the SS/DEL pin reaches approximately
1.8V. The effect of this offset will be to slightly lengthen the Start Delay (TD1) and shorten the Soft Start Ramp
Time (TD2).
The following table summarizes the differences between the 3 modes associated with setting the VIDSEL pin. In
addition to changing the soft start sequence, the NO_CPU code may or may not be ignored during startup and
the NO_CPU code may or may not be latched.
VIDSEL
Voltage
GND
(1.8V)
6.49K to GND
(0.9V
工商网监
湘ICP备2023018690号
