IR3531AMTRPBF

IR3531A 4+1 Phase Dual Output Control IC FEATURES DESCRIPTION  Integrated 6.8V/0.8A Buck Regulator provides bias to Control and Driver IC(s)  Adjustable switching frequency from 250 KHz up to 1.5MHz per phase based on the synchronization SCLK input  Sink and source tracking capability  Margining via SVID for both rails  Pre-bias compatible  Soft Stop capability  0.5% overall system set point accuracy  Voltage Mode Modulation for excellent transient performance  Single NTC thermistor for current reporting, OC Threshold, and Load Line thermal compensation  Complete protection including over-current, over-voltage, over-temperature, open remote sense and open control loop The IR3531A control IC provides all the necessary control, communication and protection to support compact dual output power solutions up to 210W. The IR3531A can be combined with either discrete IR3535 driver ICs and Direct FetsTM or our IR35XX family of footprint compatible and scalable PowIRstagesTM which integrate the MOSFETs and driver into the same package. The IR3531A provides overall system control and current sharing while the Driver IC or power stages senses perphase current locally and communicates it to the Control IC. The IR3531A has tri-state PWM outputs to allow diode emulation during light load events. The IR3531A provides a high performance transient solution through classic voltage mode control and Body BrakingTM. Body BrakingTM automatically turns off the lowside MOSFET to help dissipate stored inductor energy at load turn-off.  Thermally enhanced 48L 7mm x 7mm MLPQ package  RoHS compliant IIN_R1 VDAC1 VDRP1 EA1 FB1 VO1 VOSEN1+ VOSEN1- TRACK1 IIN4 IIN3 PIN DIAGRAM PWM_R1 BASIC APPLICATION CIRCUIT 48 47 46 45 44 43 42 41 40 39 38 37 EN 1 36 VRHOT# 2 35 PWM4 VRRDY1 3 34 PWM3 VRRDY 4 VCC 5 SW 6 V12V 7 ALERT# 8 VCLK BBR1# 33 TSENS 32 ROSC/OVP 31 ADDR 30 ICCP 29 SCLK 9 28 PWM2 VDIO 10 27 PWM1 PHSSHED 11 26 BBR# IMON_R1 12 25 TRACK A IR3531A 48 Pin 7 x 7 MLPQ Top View Figure 1: IR3531A Basic Application Circuit, showing a 4+1 Configuration 1 March 22, 2012 | FINAL | V1.11 13 14 15 16 17 18 19 20 21 22 23 24 IMON VDAC VN VDRP EA PSC FB VO VOSEN+ VOSEN- IIN1 IIN2 49 GND Figure 2: IR3531A Package Top View 4+1 Phase Dual Output Control IC IR3531A ORDERING INFORMATION IR3531A ― M      Package PBF – Lead Free TR – Tape and Reel Tape & Reel Qty 48 Lead MLPQ (7x7 mm body) 100 IR3531A-MPBF 48 Lead MLPQ (7x7 mm body) 3000 IR3531A-MTRPBF 1 PWM_R1 IIN_R1 VDAC1 VDRP1 EA1 FB1 VO1 VOSEN1+ VOSEN1- TRACK1 IIN4 IIN3 Note : Samples only. 48 47 46 45 44 43 42 41 40 39 38 37 EN 1 36 BBR1# VRHOT# 2 35 PWM4 VRRDY1 3 34 PWM3 VRRDY 4 33 TSENS VCC 5 32 ROSC/OVP SW 6 31 ADDR V12V 7 30 ICCP ALERT# 8 29 SCLK VCLK 9 28 PWM2 VDIO 10 27 PWM1 PHSSHED 11 26 BBR# 25 TRACK IR3531A 48 Pin 7 x 7 MLPQ Top View 49 GND 15 16 17 18 19 20 21 22 23 24 VDRP EA PSC FB VO VOSEN+ VOSEN- IIN1 IIN2 14 VN 13 VDAC 12 IMON IMON_R1 Figure 3: Package Top View, Enlarged 2 March 22, 2012 | FINAL | V1.11 Part Number 1 4+1 Phase Dual Output Control IC FUNCTIONAL BLOCK DIAGRAM Figure 4: IR3531A Block Diagram 3 March 22, 2012 | FINAL | V1.11 IR3531A 4+1 Phase Dual Output Control IC IR3531A TYPICAL APPLICATION DIAGRAM RDRP1 PWM3 IIN3 TO IOUT SIGNALS OF PHASES 3, 4 PWM4 CEA1 IIN4 VOSEN1+ RFB1 TRACK1 CFB1 RCFB1 VOSEN1- CCP1 RCP1 TO PWM SIGNALS OF PHASES 3, 4 VDAC1 RSCALE3 RSCALE2 RSCALE1 RTHERM3 37 IIN3 38 IIN4 TRACK1 39 40 VOSEN1- 41 VOSEN1+ 43 42 VO1 44 FB1 EA1 45 VDRP1 46 VDAC1 VDIO PWM1 VDAC 36 35 RHOTSET1 RTHERM2 RHOTSET3 34 33 32 ROSC 31 30 29 28 RADDR2 RADDR1 VDAC RICCP1 RICCP2 SCLK 27 26 IIN2 25 24 IIN1 TRACK 23 GND 22 IMON_R1 VOSEN- BBR# VOSEN+ PHSSHED CIMON1 49 47 PWM2 VO 12 VCLK 21 11 PHSSHED SCLK 20 10 VDIO ICCP ALERT# FB 9 VCLK ADDR V12V 19 8 ALERT# PSC 12V COUTVCC IR3531A SW EA 7 ROSC/OVP 18 6 TSENS VCC VDRP 2 VRRDY 17 LVCC 1 PWM3 VN 5 VRRDY 1 16 4 VRRDY PWM4 15 VRRDY 1 RHOTSET2 BBR1# VRHOT# VDAC 3 IMON 2 VRHOT# EN 14 1 ENABLE PWM_R1 PWM_R1 IIN_R1 48 IOUT1 13 PWM2 PWM1 TO PWM SIGNALS OF PHASES 1, 2 BBR# TRACK CIMON IIN2 RTCMP3 VDAC IIN1 CCP RCP RCFB RTCMP1 RTHERM1 CEA RFB RTCMP2 CFB VOSEN- RPSC VOSEN+ RAIL1 SIGNALS BBR1# RDRP Figure 5: IR3531A Typical Application Diagram 4 March 22, 2012 | FINAL | V1.11 TO IOUT SIGNALS OF PHASES 1, 2 4+1 Phase Dual Output Control IC IR3531A PIN DESCRIPTIONS PIN # PIN NAME 1 EN 2 VRHOT# Open collector output of the VRHOT# comparator which drives low if Rail0 temperature exceeds the programmed threshold. Connect external pull-up to bias. 3 VDRRY1 Open collector output that drives low during startup and under any external fault condition for Rail1 regulator. Connect external pull-up to bias. 4 VDRRY Open collector output that drives low during startup and under any external fault condition for Rail0 regulator. Connect external pull-up to bias. 5 VCC Bias buck regulator output, feedback pin, and bias input for internal circuitry. 6 SW Switching node for bias buck regulator. 7 V12V 8 ALERT# 9 VCLK SVID Clock Input. Clock is a high impedance input pin. It is driven by the open collector output of a microprocessor and requires a pull-up resistor. 10 VDIO SVID Data Input/Output. High impedance input when address, command or data bits are shifted in, open drain output when acknowledging or sending data back to the microprocessor. Pin requires a pull up resistor. 11 PHSSHED Analog signal that represents the number of phases to be disabled. 0% to 25% VCC, no phases disabled. 25% to 50% VCC, disable 1 phase. 50% to 75% VCC, disable 2 phases. 75% to 100% VCC, disable 3 phases (if available). 12 IMON_R1 Voltage at this pin is proportional to Rail1 load current. It is also the input to the ADC for output current register. 13 IMON Voltage at this pin is proportional to Rail0 load current. It is also the input to the ADC for output current register. 14 VDAC Voltage Regulator Rail 0 reference voltage programmed by SVID. VDAC is also used as the A/D reference during power up for pins ADDR/PSN, TSENS and ICCP. 15 VN 16 VDRP 17 EA Output of the error amplifier for Rail0. 18 PSC Node for Power Savings mode compensation input. 19 FB Inverting input to the Error Amplifier for Rail0. 20 VO Remote sense amplifier output for Rail0. 21 VOSEN+ Rail0 remote sense amplifier input. Connect to output at the load. 22 VOSEN- Rail0 remote sense amplifier input. Connect to ground at the load. 23, 24, 37, 38 IIN1-4 Current signals from the driver IC-s of Rail0. 25 TRACK External tracking reference for Rail0. 26 BBR# Body-brakingTM bus for Rail0 driver ICs to disable synchronous switches. 27, 28, 34, 35 PWM1-4 PWM outputs for Rail0. Each output is connected to the input of the driver IC. Connecting the PWMx output to LGND disables the phase, allowing the IR3531A to operate as a 1, 2, 3, or 4 phase controller. 29 SCLK Synchronization clock input. Program ROSC using ROSC vs. Frequency to match the SCLK frequency. 5 PIN DESCRIPTION Enable input. Grounding this pin shuts down the voltage regulators. Do not float this pin as the logic state will be undefined. Power Supply input supply rail. Output pin for SVID Alert# interrupt. Open collector output that drives low to notify the master. Node for DCR thermal compensation network. Buffered, scaled and thermally compensated current signal for Rail0. Connect an external resistor to FB to program converter output impedance. March 22, 2012 | FINAL | V1.11 4+1 Phase Dual Output Control IC IR3531A PIN # PIN NAME 30 ICCP Program maximum load current for both Rail0 and Rail1. 31 ADDR Programs SVID address for Rail0 and Rail1. 32 ROSC/OVP 33 TSENS Pin for thermal network that senses the temperature of Rail0 and Rail1. 36 BBR1# Body-brakingTM bus for Rail1 driver ICs to disable synchronous switches. 39 TRACK1 External tracking reference for Rail1. 40 VOSEN1- Rail1 remote sense amplifier input. Connect to ground at the load. 41 VOSEN1+ Rail1 remote sense amplifier input. Connect to output at the load. 42 VO1 Remote sense amplifier output for Rail1. 43 FB1 Inverting input to the Error Amplifier for Rail1. 44 EA1 Output of the error amplifier for Rail1. 45 VDRP1 Buffered, scaled and thermally compensated current signal for Rail1. Connect an external resistor to FB1 to program converter output impedance. 46 VDAC1 Buffered Rail1 reference voltage. Voltage can be margined via SVID. 47 IIN_R1 Current signal from Rail1 driver IC. 48 PWM_R1 49 GND 6 PIN DESCRIPTION Connect a resistor to LGND to program oscillator frequency. Oscillator frequency equals switching frequency per phase. ROSC/OVP pin is pulled up to VCC when an over voltage event occurs. PWM output for Rail1. Local Ground for internal circuitry and IC substrate connection. March 22, 2012 | FINAL | V1.11 4+1 Phase Dual Output Control IC IR3531A ABSOLUTE MAXIMUM RATINGS Storage Temperature Range -65°C To 150°C Operating Junction Temperature 0°C To 150°C ESD Rating HBM Class 1C JEDEC Standard MSL Rating 2 Reflow Temperature 260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PIN Number PIN NAME VMAX VMIN ISOURCE ISINK 1 EN 3.5V -0.3V 25mA 1mA 2 VRHOT# VCC -0.3V 1mA 50mA 3 VDRRY1 VCC -0.3V 1mA 20mA 4 VDRRY VCC -0.3V 1mA 20mA 5 VCC 8V -0.3V 1mA 20mA 6 SW 16V -1.0V 3A 1mA 7 V12V 16V -0.5V 1mA 1.5A 8 ALERT# 3.5V -0.3V 1mA 50mA 9 VCLK 3.5V -0.3V 1mA 1mA 10 VDIO 3.5V -0.3V 1mA 50mA 11 PHSSHED VCC -0.3V 1mA 1mA 12 IMON_R1 3.5V -0.3V 25mA 1mA 13 IMON 3.5V -0.3V 25mA 1mA 14 VDAC 3.5V -0.3V 5mA 35mA 15 VN VCC -0.3V 1mA 1mA 16 VDRP VCC -0.3V 35mA 1mA 17 EA VCC -0.3V 35mA 5mA 18 PSC VCC -0.3V 1mA 1mA 19 FB VCC -0.3V 1mA 1mA 20 VO VCC -0.3V 35mA 5mA 21 VOSEN+ VCC -0.5V 5mA 1mA 22 VOSEN- 1.0V -0.5V 5mA 1mA 23 IIN1 VCC -0.3V 1mA 1mA 24 IIN2 VCC -0.3V 1mA 1mA 25 TRACK VCC -0.3V 1mA 1mA 26 BBR# VCC -0.3V 1mA 5mA 27 PWM1 VCC -0.3V 1mA 5mA 7 March 22, 2012 | FINAL | V1.11 4+1 Phase Dual Output Control IC IR3531A PIN Number PIN NAME VMAX VMIN ISOURCE ISINK 28 PWM2 VCC -0.3V 1mA 5mA 29 SCLK 3.5V -0.3V 1mA 5mA 30 ICCP 3.5V -0.3V 1mA 1mA 31 ADDR 3.5V -0.3V 1mA 1mA 32 ROSC VCC -0.3V 1mA 1mA 33 TSEN 3.5V -0.3V 1mA 1mA 34 PWM3 VCC -0.3V 1mA 5mA 35 PWM4 VCC -0.3V 1mA 5mA 36 BBR1# VCC -0.3V 1mA 5mA 37 IIN3 VCC -0.3V 1mA 1mA 38 IIN4 VCC -0.3V 1mA 1mA 39 TRACK1 VCC -0.3V 1mA 1mA 40 VOSEN1- 1.0V -0.5V 5mA 1mA 41 VOSEN1+ VCC -0.5V 5mA 1mA 42 VO1 VCC -0.5V 35mA 5mA 43 FB1 VCC -0.3V 1mA 1mA 44 EA1 VCC -0.3V 35mA 5mA 45 VDRP1 VCC -0.3V 35mA 1mA 46 VDAC1 3.5V -0.3V 1mA 35mA 47 IIN_R1 VCC -0.3V 1mA 1mA 48 PWM_R1 VCC -0.3V 1mA 1mA 49 GND N/A N/A 20mA 1mA 8 March 22, 2012 | FINAL | V1.11 IR3531A 4+1 Phase Dual Output Control IC ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN The electrical characteristics table lists the spread of values guaranteed within the recommended operating conditions. Typical values represent the median values, which are related to 25°C. Unless otherwise specified, these specifications apply over: -0.3V ≤ VOSEN- ≤ 0.3V, 7.75KΩ ≤ ROSC ≤ 50.0 KΩ Recommended V12V Range 10.8V 12 13.2V V Recommended VCC Range 6.6 6.8 7.0 V VOSEN- and VOSEN1- to LGND offset -0.3 0 0.3 V ROSC Resistor Programming Range 7.75 50 KΩ TJ 100 ºC MIN TYP MAX UNIT -0.5 - 0.5 % 0.8 ≤ VID < 1V -5 - +5 mV 0.25V ≤ VID < 0.8V -8 - +8 mV Recommended Operating Junction Temperature 0 ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL CONDITIONS VDAC Reference System Set-Point Accuracy SETACC VID ≥ 1V Slew Rate – Fast Mode VIDFAST 15 20 25 mV/µs Slew Rate – Slow Mode VIDSLOW 3.75 5 6.25 mV/µs Default VBOOT Rail 0 VBOOT0 Note 3 - 1.5 - V Default VBOOT Rail 1 VBOOT1 Note 3 - 1.5 - V ROSC Voltage VROSC ROSC = 24.5 KΩ 0.570 0.595 0.620 V PWM Frequency FSWMIN ROSC = 50.0 KΩ - 250 - kHz FSWTYP ROSC = 24.5 KΩ - 500 - kHz FSWMAX ROSC = 7.75 KΩ - 1.50 - MHz DACOFF V(VDAC, VDAC1) ― VID code + VID offset, 0.25V ≤ V(VDAC, VDAC1) ≤ 1.52V, < 1mA load -15 0 15 mV 0.25V ≤ V(VDAC1) ≤ 1.52V 0.3 0.44 0.6 0.25V ≤ V(VDAC) ≤ 1.52V 0.9 1.65 2.4 0.5V ≤ V(VDAC1) ≤ 1.52V 2 13 20 0.5 1.5 2 3 15 30 0.5 1.5 3 Oscillator (Note 4) VDAC Buffer Amplifier Input Outset Voltage Source Current Sink Current DACSRC DACSNK V(VDAC1) = 0.25V 0.5V ≤ V(VDAC) ≤ 1.52V V(VDAC) = 0.25V 9 March 22, 2012 | FINAL | V1.11 mA mA IR3531A 4+1 Phase Dual Output Control IC MIN TYP MAX UNIT Unity Gain Bandwidth PARAMETER SYMBOL CONDITIONS - 3.5 - MHz Slew Rate - 1.5 - V/µs -14 0 14 mV mA Thermal Compensation Amplifier (VDRP) Output Offset Voltage VDRPOUTOFF 0V ≤ V(IIN) – V(VDAC) ≤ 1.52V, 0.25V ≤ V(VDAC) ≤ 1.52V, Req/R2 = 2 Source Current VDRPSRC 0.25V ≤ V(VDAC) ≤ 1.52V 3 8 15 Sink Current VDRPSNK 0.5V ≤ V(VDRP) ≤ 1.52V 0.2 0.4 0.7 0.175 0.25 0.4 2 4.5 7 MHz - 5.5 - V/µs -2 0 2 µA VID = 250 mV 250 350 385 mV VID = 1.52 V 2 2.15 2.26 V VID = 250 mV, SF = 500 kHz 60 151 200 VID = 1.52 V, SF = 500 kHz 220 409 480 PS2COTMIN1 VID = 250 mV, SF = 500 kHz 50 100 200 PS2COTMAX1 VID = 1.52 V, SF = 500 kHz 220 358 480 PS1DELAY PS0 to PS1 only - 8 - PWM Cycle V(VDRP) = 0.25V Unity Gain Bandwidth Req/R2 = 2, Note 1 Slew Rate VN Bias Current V(VN) = 2 V mA Power Savings Mode Operation PS2/PS3 Turn-on Threshold PS2/PS3 Pulse Width Rail0 PS2/PS3 Pulse Width Rail1 PS Mode Enter Delay PS2THRSH PS2COT0 ns ns Enable Input Rising Threshold ENRISE 625 650 675 mV Falling Threshold ENFALL 575 600 625 mV Hysteresis ENHYST 25 50 75 mV Bias Current ENBIAS 0V ≤ V(ENABLE) ≤ 3.3V -5 0 5 µA Noise Pulse < 100ns will not register an ENABLE state change. Note 1 75 250 400 ns VDRP–VDAC = 0, 225, 450, 900mV 15 50 90 mV - 1 - MHz - 1 - µs 1.00 1.09 1.145 V Blanking Time IMONx Current Report Amplifier Output Offset Voltage IMONOFF Unity Gain Bandwidth Note 1 Input Filter Time Constant Max Output Voltage IMONMAX Current Report A/D Accuracy IMONACC VDRP–VDAC = 900mV -2 0 2 % VDRP1OFF 0V≤ V(IIN_R1) - V(VDAC1) ≤ 0.2V 0.25V ≤ V(IIN_R1) - V(VDAC1) ≤ 1.52V -75 0 75 mV Rail1 VDRP Amplifier Output Outset Voltage 10 March 22, 2012 | FINAL | V1.11 IR3531A 4+1 Phase Dual Output Control IC PARAMETER SYMBOL CONDITIONS Source Current VDRP1SRC 0.25V ≤ V(VDAC1) ≤ 1.52V Sink Current VDRP1SNK 0.5V≤ V(VDRP1) ≤ 1.52V V(VDRP1) = 0.25V MIN TYP MAX UNIT 3 8 15 mA 0.2 0.4 0.6 0.175 0.25 0.375 mA Closed Loop Gain Note 1 - 9 - V/V Unity Gain Bandwidth Note 1 0.8 1.5 3 MHz Slew Rate Note 1 - 5.5 - V/µs Note 2 (test mode only) - 0 - mV -1 0 1 µA Error Amplifier Input Offset Voltage FB Bias Current DC Gain Note 1 100 110 120 dB Unity Gain Bandwidth Note 1 20 30 40 MHz Slew Rate Note 1 7 12 20 V/µs Sink Current EASRC 0.40 0.85 1.35 mA Source Current EASNK 5 8 12 mA Maximum Voltage EAMAX 500 925 1100 mV Minimum Voltage EAMIN - 120 250 mV Open Voltage Loop Detection Threshold EAOPENTHR 100 300 1100 mV Open Loop Detection Delay EAOPENDEL V(EA), V(EA1) = V(VCC) to VRRDY = low - 8 - PWM PS2 Clamp Voltage EAPS2CLMP With respect to VDAC -240 -70 -10 mV Measure V(VCC) – V(EA), V(EA1) Measure V(VCCx) - V(EA), V(EA1), Relative to Error Amplifier maximum voltage Phase Firing Comparators Input Offset KEEPOFF -30 0 30 mV Propagation Delay KEEPDEL - - 320 ns Bias Current PHSDBIAS -2 0 2 µA Threshold PHSDTHRS Comparator 1 1.3 1.7 2.0 Comparator 2 3.0 3.4 3.85 Comparator 3 4.8 5.1 5.55 42 52.5 57 mV/ %DC 55 70 ns Phase Shedding Comparators V PWM Comparator PWM Ramp Slope PWMSLP V12V= 12V Minimum Pulse Width PWMMIN Note 1 Input Offset Voltage PWMOFF Note 1 -5 0 5 mV Input Offset Voltage SAAOFF Note 1 -3 0 3 mV Gain SAAGAIN CSIN+ = CSIN- = DACIN, Note 1 4 5.0 6 V/V Note 1 4 8.5 17 kHz Share Adjust Amplifier Unity Gain Bandwidth 11 March 22, 2012 | FINAL | V1.11 IR3531A 4+1 Phase Dual Output Control IC CONDITIONS MIN TYP MAX UNIT Maximum PWM Ramp Floor Voltage PARAMETER MINFLOOR SYMBOL IOUT = DACIN – 200mV Measure relative to floor voltage 100 180 22 0 mV Minimum PWM Ramp Floor Voltage MAXFLOOR IOUT = DACIN + 200mV Measure relative to floor voltage -220 -160 -100 mV 1.615 1.65 1.67 V 100 130 150 mV - 90 180 ns - 2 - µs V Over Voltage Protection (OVP) Comparators Threshold at Power-up OVPPUP Threshold during Normal Operation OVPTHR Compare to VID Voltage + VID offset Propagation Delay to OVP OVPPROP Measure time from V(FB), V(FB1) > VID voltage + VID offset (250mV overdrive) to V(PWM) transition to > 0.5 * V(VCC) Over-Current Comparator Input Filter Time Constant Over-Current Threshold OCTHRSH VDRP-VDAC, VDRP1-VDAC1 0.94 1.08 1.18 OC Threshold PSI Reduction Factor OCPSI PSI mode, 4ph to 2ph, 2ph to 1ph 450 540 610 PSI mode, 3ph to 1ph 310 360 410 3ph to 2ph 640 720 800 PSI mode, 4ph to 1ph 220 270 310 4ph to 3ph 690 800 900 Delay to OC shutdown 225 256 285 µs OC Delay Time OCDELAY mV VCC Undervoltage VCC UVL Start VCCSTART 5.5 5.85 6.4 V VCC UVL Stop VCCSTOP 4.85 5.2 5.65 V VCC UVL Hysteresis VCCHYST 515 650 830 mV VRRDY Output Output Voltage VRRDYLO I(VRRDY, VDRRY1) = 4mA - 150 300 mV Leakage Current VRRDYLEAK V(VRRDY, VDRRY1) = 5.5V - 0 10 µA VCC Activation Voltage VRRDYVCC I(VDRRY, VDRRY1) = 4mA,