IR3823MTRPBF

3A Highly Integrated SupIRBuck® Single-Input Voltage, Synchronous Buck Regulator FEATURES IR3823 DESCRIPTION • Single input voltage range from 5V to 21V • Wide Input voltage range from 1.0V to 21V with external VCC bias voltage • Output voltage from 0.6V to 0.86% of PVin • Enhanced line/load regulation with feedforward • Programmable switching frequency up to 1.5MHz • Three user selectable soft-start time options • Thermally compensated current limit with robust hiccup mode over current protection • Synchronization to an external clock • Precise reference voltage (0.6V+/-0.6%) • Open-drain PGood indication • Output over voltage protection The IR3823 SupIRBuck® is a 3A easy-to-use, fully integrated and highly efficient synchronous Buck regulator intended for Point-Of-Load (POL) applications. The IR3823 features programmable switching frequency from 300kHz to 1.5MHz, three selectable soft-start time options, and smooth synchronization to an external clock. The IR3823 uses voltage mode control employing a proprietary PWM modulator, allowing high control bandwidth and fast loop response with less output capacitors. The other important functions include thermally compensated over current protection, output over voltage protection and thermal shut-down, etc. The IR3823 is offered in a small 3.5mm x 3.5mm PQFN package with excellent thermal performance. • Enable Input with Under-Voltage Lockout (UVLO) APPLICATIONS • VCC Under-Voltage Lockout (UVLO) • Enhanced Pre-bias start-up • Computing Applications • Integrated MOSFET drivers and Bootstrap Diode • Set Top Box Applications • Storage Applications • Thermal shut-down • -40°C to 125°C operating junction temperature • 3.5mm x 3.5mm PQFN package • Lead-free, Halogen-free and RoHS6 Compliant • Data Center Applications • Telecom Applications • Distributed Point of Load Power Architectures ORDERING INFORMATION Base Part Number Package Type IR3823 PQFN 3.5 mm x 3.5 mm Standard Pack Form Quantity Tape and Reel 4000 Orderable Part Number IR3823MTRPBF IR3823       PBF – Lead Free TR – Tape and Reel M – PQFN Package 1 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 BASIC APPLICATION Vin Vcc Vin PVin Boot SS_Select PGood PGood Vo SW IR3823 Fb Enable Comp Rt/Sync Gnd PGnd Figure 1: IR3823 Basic Application Circuit Figure 2: IR3823 Efficiency PINOUT DIAGRAM IR3823 SW PVin 12 11 10 PGnd Gnd 13 9 Gnd GND Boot 14 16 6 c yn /S Rt Vin d 5 7 oo 4 Gn d m Co el e SS _S Fb 3 p 2 ct 1 Vcc/LDO_Out PG Enable 15 8 Figure 3: 3.5mm x 3.5mm PQFN (Top View) 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 BLOCK DIAGRAM 5.1V Internal LDO Vin VCC Vcc/ LDO_Out THERMAL TSD SHUT DOWN OC FAULT POR CONTROL UVcc Gnd UVcc Boot OV Comp + VREF + 0.6V - + FAULT E/A POR VCC PVin - 0.15V Vin Fb Fb HDrv POR INTL_SS VREF OV OVER VOLTAGE HDin SW GATE DRIVE LDin SS_Select SOFT START POR SSOK LDrv CONTROL VREF FAULT PGnd SEQ Enable LOGIC UVEN UVEN OC Over Current Protection POR UVcc POR Rt/Sync PGood Figure 4: Simplified Block Diagram 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 PIN DESCRIPTIONS PIN # PIN NAME 1 Fb 2 SS_Select 3 Comp 4,9,13, 16 Gnd 5 Rt/Sync Multi-function pin to set the switching frequency. The internal oscillator frequency is set with a resistor between this pin and Gnd. Or synchronization to an external clock by connecting this pin to the external clock signal through a diode. 6 PGood Open-drain power good indication pin. Connect a pull-up resistor from this pin to Vcc. 7 Vin 8 Vcc/LDO_Out 10 PGnd 11 SW Switch node. Connect this pin to the output inductor. 12 PVin Power stage input. 14 Boot 15 Enable 4 www.irf.com PIN DESCRIPTION Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Soft start selection pin. Three user selectable soft start time is available: 1.5ms (SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd) Output of the error amplifier. The loop compensation network should be connected between Comp and Fb pin. Analog ground for the internal reference and the control circuitry. Input of the Internal LDO. A 1.0µFceramic capacitor should be connected between this pin and PGnd. If an external Vcc voltage is used, this pin should be shorted to Vcc pin. Output of the internal LDO and optional input of an external biased supply voltage. A minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd. Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system power ground plane. Supply voltage for the high-side driver. A 100nF ceramic capacitor should be connected between this pin and SW pin. Enable pin to turn on/off the device. Connect this pin to PVin pin through a resistor divider to implement the input voltage UVLO. © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 ABSOLUTE MAXIMUM RATINGS Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. PVin, Vin to PGnd (Note 3) -0.3V to 25V Vcc/LDO_Out to PGnd (Note 3) -0.3V to 8V (Note 1) Boot to PGnd (Note 3) -0.3V to 33V SW to PGnd (Note 3) -0.3V to 25V (DC), -4V to 25V (AC, 100ns) Boot to SW -0.3V to VCC + 0.3V (Note 2) PGood, SS_Select to Gnd (Note 3) -0.3V to VCC + 0.3V (Note 2) Other Input/Output Pins to Gnd (Note 3) -0.3V to +3.9V PGnd to Gnd -0.3V to +0.3V THERMAL INFORMATION Junction to Ambient Thermal Resistance ƟjA 37.4 °C/W (Note 4) Junction to PCB Thermal Resistance Ɵj-PCB 10.1 °C/W Junction to Case Top Thermal Resistance Ɵj-CTop 120 °C/W Storage Temperature Range -55°C to 150°C Junction Temperature Range -40°C to 150°C Note 1: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C Note 2: Must not exceed 8V Note 3: PGnd pin and Gnd pin are connected together. Note 4: ƟjA is for the test in still air with IRDC3823 evaluation board. The IRDC3823 uses a 4-layer 2.6” x 2.2” FR4 PCB board. Each layer uses 2 oz. copper. 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 ELECTRICAL SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS SYMBOL MIN MAX UNITS Input Voltage Range with External Vcc (Note 5, Note 7) PVin 1.0 21 Input Voltage Range with Internal LDO (Note 6, Note 7) Vin, PVin 5.5 21 Supply Voltage Range (Note 6) VCC 4.5 7.5 Supply Voltage Range (Note 6) Boot to SW 4.5 7.5 Output Voltage Range V0 0.6 0.86 x PVin Output Current Range I0 0 3 A Switching Frequency FS 300 1500 kHz Operating Junction Temperature TJ -40 125 °C V Note 5: Vin is connected to Vcc to bypass the internal LDO. Note 6: Vin is connected to PVin. For single-rail applications with PVin=Vin= 4.5V-5.5V, please refer to the application information in the section of Internal LDO and the section of Over Current Protection. Note 7: Maximum SW node voltage should not exceed 25V. ELECTRICAL CHARACTERISTICS Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Stage Power Losses PLOSS PVin= Vin = 12V, Vo = 1.2V, Io = 3A, Fs = 1000kHz, L = 1.0uH, Note 8 0.6 W Top Switch RDS(ON) RDS(on)-T VBOOT -Vsw=5.1V,Io = 3A, Tj = 25°C 40 52 Bottom Switch RDS(ON) RDS(on)-B Vcc = 5.1V, Io = 3A, Tj = 25°C 26 34 260 470 mV 1 µA 1 µA Bootstrap Diode Forward Voltage SW Leakage Current Dead Band Time VD I(Boot) = 10mA ISW VSW = 0V, Enable = 0V, VFB=1V VSW = 0V, Enable = High, VFB=1V TD Note 8 180 12.5 mΩ ns Supply Current Vin Supply Current (standby) Vin Supply Current (dynamic) 6 www.irf.com Iin(Standby) Iin(Dyn) EN = Low, No Switching Vin=21V, PVin=0V EN = High, FSW =1000kHz, Vin = PVin = 16V © 2014 International Rectifier 200 10 12.5 Submit Datasheet Feedback µA mA April 18, 2014 IR3823 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Vcc Vin(min) = 5.5V, Io = 0-25mA CLOAD = 2.2uF 4.75 5.1 5.4 V 0.4 V VCC/LDO_Out Output Voltage LDO Dropout Voltage Vcc_drop Short Circuit Current Ishort Vin=4.7V, Io=15mA, CLOAD=2.2uF Vin=7.3V, PVin=Float, Vcc=0V 70 mA 1.0 V Oscillator Rt Voltage Frequency Range Ramp Amplitude VRt Fs 270 300 330 Rt = 23.2kΩ 900 1000 1100 Rt = 15kΩ 1350 1500 1650 Vin = 5.5V, Vin slew rate max = 1V/µs, Note 8 0.825 Vin = 12V, Vin slew rate max = 1V/µs, Note 8 1.80 Vin = 21V, Vin slew rate max = 1V/µs, Note 8 3.15 Vin=Vcc=5V, For external Vcc operation, Note 8 0.75 Note 8 0.16 Vramp Ramp Offset Minimum Pulse Width Tmin(ctrl) Maximum Duty Cycle Dmax Fixed Off Time Rt = 80.6kΩ Toff kHz Vp-p Note 8 Fs = 300kHz, Vin =PVin= 12V V 60 86 Note 8 % 200 Sync Frequency Range Fsync 270 Sync Pulse Duration Tsync 100 High 3.0 ns 250 ns 1650 kHz 200 ns V Sync Level Threshold Low 0.6 V +1 µA Error Amplifier Input Bias Current (VFB) IFB(E/A) -1 Output Sink Current Isink(E/A) 0.4 0.85 1.2 mA Isource(E/A) 4 7.5 11 mA Output Source Current Slew Rate Gain-Bandwidth Product 7 www.irf.com SR Note 8 7 12 20 V/µs GBWP Note 8 20 30 40 MHz © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 100 110 120 dB 1.7 2.0 2.3 V 100 mV Error Amplifier (Continued) DC Gain Gain Maximum Output Voltage Vmax(E/A) Minimum Output Voltage Vmin(E/A) Note 8 Reference Voltage (VREF) Feedback Voltage VFB 0.6 V 0°C < Tj < 70°C -0.6 +0.6 -40°C < Tj < 125°C ; Note 9 -1.2 +1.2 SS_Select=VCC 0.34 0.4 0.46 SS_Select=Float 0.16 0.2 0.24 SS_Select=Gnd 0.085 0.1 0.115 40 80 uA % Accuracy Soft Start Soft Start Ramp Rate SS_Select Input Bias Current SS_Select=Gnd mV/µs Power Good Power Good Turn on Threshold VPG (on) VFB rising 85 90 95 % VREF Power Good Lower Turn off Threshold VPG(lower) VFB falling 80 85 90 % VREF Power Good Turn on Delay TPG(ON)_D VFB rising, see VPG(on) Power Good Upper Turn off Threshold VPG(upper) VFB rising PGood Comparator Delay PGood Voltage Low VFB < VPG(lower) or VFB > VPG(upper) PG(voltage) 2.56 ms 115 120 125 % VREF 1 2 3.5 µs 0.5 V IPGood = -5mA Under-Voltage Lockout Vcc-Start Threshold VCC UVLO Start Vcc rising trip Level 3.9 4.1 4.3 V Vcc-Stop Threshold VCC UVLO Stop Vcc falling trip Level 3.6 3.8 4.0 V Enable-Start-Threshold Enable UVLO Start ramping up 1.14 1.2 1.26 V Enable-Stop-Threshold Enable UVLO Stop ramping down 0.95 1 1.05 Enable Leakage Current IEN_LK Enable = 3.3V 8 www.irf.com © 2014 International Rectifier 1 Submit Datasheet Feedback µA April 18, 2014 IR3823 ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, SS_Select=Float. Typical values are specified at Ta = 25°C. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 115 120 125 % VREF 1 2 3.5 µs 3.6 4.5 5.4 A Over-Voltage Protection OVP Trip Threshold OVP_Vth OVP Comparator Delay VFB rising TOVP_D Over-Current Protection Current Limit ILIMIT Hiccup Blanking Time TBLK_Hiccup Tj = 25°C, VCC=5.1V SS_Select = Vcc, Note 8 10 SS_Select = Float, Note 8 20 SS_Select = Gnd, Note 8 40 ms Over-Temperature Protection Thermal Shutdown Threshold Hysteresis Note 8 Note 8 145 °C 20 Note 8: Guaranteed by design, but not tested in production. Note 9: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. 9 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin=12V, VCC= Internal LDO, IO = 0A-3A, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N 1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.2 PIMB053T-1R2MS-39 (Cyntec) 15 4.9x5.2x3.0 3.3 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 5 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 10 www.irf.com © 2014 International Rectifier DCR (mΩ) Submit Datasheet Feedback SIZE (mm) April 18, 2014 IR3823 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = 12V, Vin=VCC= External 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N 1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.2 PIMB053T-1R2MS-39 (Cyntec) 15 4.9x5.2x3.0 3.3 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 5 1000 2.2 XAL5030-222ME (Coilcraft) 13.2 5.28x5.48x3.1 11 www.irf.com © 2014 International Rectifier DCR (mΩ) Submit Datasheet Feedback SIZE (mm) April 18, 2014 IR3823 TYPICAL EFFICIENCY AND POWER LOSS CURVES PVin = Vin = VCC = 5V, IO = 0A-3A, FS = 1000 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss curves include the losses of IR3823, the inductor losses and the losses of the input and output capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement. VOUT (V) FS (kHz) LOUT (µH) P/N 1.0 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.2 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 1.8 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 3.3 1000 1.0 XFL4020-102ME (Coilcraft) 10.8 4.0x4.0x2.1 12 www.irf.com © 2014 International Rectifier DCR (mΩ) Submit Datasheet Feedback SIZE (mm) April 18, 2014 IR3823 RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=5.1V 13 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C) 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C) 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 THEORY OF OPERATION DESCRIPTION The IR3823 SupIRBuck® is a 3A easy-to-use, fully integrated and highly efficient synchronous Buck regulator intended for Point-Of-Load (POL) applications. It includes two IR HEXFETs with low RDS(on). The bottom FET has an integrated monolithic schottky diode in place of a conventional body diode. The IR3823 provides precisely regulated output voltage programmed via two external resistors from 0.6V to 0.86×Vin. It uses voltage mode control employing a proprietary PWM modulator with input voltage feedforward. That provides excellent noise immunity, easy loop compensation design, and good line transient response. The IR3823 has an internal Low Dropout (LDO) Regulator, allowing single supply operation without resorting to an external bias supply voltage. To further improve the light load efficiency, the internal LDO can be bypassed by using an external bias supply. This mode allows the input bus voltage range extended down to 1.0V. A RC network has to be connected between the FB pin and the COMP pin to form a feedback compensator. The goal of the compensator design is to achieve a high control bandwidth with a phase margin of 45° or above. The high control bandwidth is beneficial for the loop dynamic response, which helps to reduce the number of output capacitors, the PCB size and the cost. A phase margin of 45° or higher is desired to ensure the system stability. For most applications, a gain margin of -10dB or higher is preferred to accommodate component variations and to eliminate jittering/noise. The proprietary PWM modulator in IR3823 significantly reduces the PWM jittering, allowing the control bandwidth in the range th th of 1/10 to 1/5 of the switching frequency. Two types of compensators are commonly used: Type II (PI) and Type III (PID), as shown in Figure 5. The selection of the compensation type is dependent on the ESR of the output capacitors. Electrolytic capacitors have relatively higher ESR. If the ESR pole is located at the frequency lower than the cross-over frequency, FC, the ESR pole will help to boost the phase margin. Thus a type II compensator can be used. For the output capacitors with lower ESR such as ceramic capacitors, type III compensation is often desired. The IR3823 features programmable switching frequency from 300kHz to 1.5MHz, three selectable soft-start time, and smooth synchronization to an external clock. The other important functions include thermally compensated over current protection, output over voltage protection, pre-bias start-up, enable with input voltage monitoring, PGood output and thermal shut-down. CC1 RC1 Rf1 - Fb Rf2 Comp E/A + VREF VOLTAGE LOOP COMPENSATION DESIGN The IR3823 uses PWM voltage mode control. The output voltage of the POL, sensed by a resistor divider, is fed into an internal Error Amplifier (E/A). The output of the E/R is then compared to an internal ramp voltage to determine the pulse width of the gate signal for the control FET. The amplitude of the ramp voltage is proportional to Vin so that the bandwidth of the voltage loop remains almost constant for different input voltages. This feature is called input voltage feedfoward. It allows the feedback loop design independent of the input voltage. Please refer to the next section for more information. CC2 Vout (a) Vout Rf3 CC2 Rf1 RC1 CC1 Cf3 Fb - Rf2 + E/A Comp VREF (b) Figure 5: Loop Compensator (a) Type II, (b) Type III 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback April 18, 2014 IR3823 Table 1 lists the compensation selection for different types of output capacitors. For more detailed design guideline of voltage loop compensation, please refer to the application note AN-1162, “Compensation Design Procedure for Buck Converter with Voltage-Mode Error-Amplifier”. SupBuck design tool is also available at www.irf.com providing the reference design based on user’s design requirements. function can also minimize impact on output voltage from fast Vin change. The maximum Vin slew rate is within 1V/µs. If an external bias voltage is used as Vcc, Vin pin should be connected to Vcc/LDO_out pin instead of PVin pin. Then the feedforward function is disabled. The control loop compensation might need to be adjusted. 16V 12V TABLE 1 RECOMMENDED COMPENSATION TYPE LOCATION OF CROSS-OVER FREQUENCY TYPE OF OUTPUT CAPACITORS Type II (PI) FLC