IRLR014NTR

PD- 94350 IRLR/U014N HEXFET® Power MOSFET





Logic-Level Gate Drive Surface Mount (IRLR024N) Straight Lead (IRLU024N) Advanced Process Technology Fast Switching Fully Avalanche Rated D VDSS = 55V RDS(on) = 0.14Ω G ID = 10A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. D-Pak TO-252AA The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. I-Pak TO-251AA Absolute Maximum Ratings Parameter ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current  Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt  Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Max. Units 10 7.1 40 28 0.2 ± 16 35 6.0 2.8 5.0 -55 to + 175 A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case ) Thermal Resistance Parameter RθJC RθJA RθJA Junction-to-Case Case-to-Ambient (PCB mount)** Junction-to-Ambient Typ. Max. Units ––– ––– ––– 5.3 50 110 °C/W ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 www.irf.com 1 5/4/99 IRLR/U014N Electrical Characteristics @ TJ = 25°C (unless otherwise specified) ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LD Internal Drain Inductance LS Internal Source Inductance Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance IGSS Min. Typ. Max. Units Conditions 55 ––– ––– V VGS = 0V, ID = 250µA ––– 0.056 ––– V/°C Reference to 25°C, ID = 1mA ––– ––– 0.14 VGS = 10V, ID = 6A
Ω ––– ––– 0.21 VGS = 4.5V, ID = 5A
1.0 ––– ––– V VDS = VGS, ID = 250µA 3.1 ––– ––– S VDS = 25V, ID = 6A ––– ––– 25 VDS = 55V, VGS = 0V µA ––– ––– 250 VDS = 55V, VGS = 0V, TJ = 150°C ––– ––– 100 VGS = 16V nA ––– ––– -100 VGS = -16V ––– ––– 7.9 ID = 6A ––– ––– 1.4 nC VDS = 44V ––– ––– 4.4 VGS = 5.0V, See Fig. 6 and 13
––– 6.5 ––– VDD = 28V ––– 47 ––– ID = 6A ns ––– 12 ––– RG = 6.2Ω, VGS = 5.0V ––– 23 ––– RD = 4.5Ω, See Fig. 10
Between lead, ––– 4.5 ––– nH 6mm (0.25in.) G from package ––– 7.5 ––– and center of die contact ––– 265 ––– VGS = 0V ––– 80 ––– pF VDS = 25V ––– 38 ––– ƒ = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics IS ISM VSD trr Q rr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)
Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions D MOSFET symbol ––– ––– 10 showing the A G integral reverse ––– ––– 40 S p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 6A, VGS = 0V  ––– 37 56 nS TJ = 25°C, IF = 6A ––– 48 71 nC di/dt = 100A/µs  Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) Notes:  Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 1.96mH RG = 25Ω, IAS = 6A. (See Figure 12)  ISD ≤ 6.0A, di/dt ≤ 210A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C 2  Pulse width ≤ 300µs; duty cycle ≤ 2%.  This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact www.irf.com IRLR/U014N 100 100 VGS VGS 15V 15V 10V 12V 5.0V 10V 4.5V 7.0V 3.5V 5.0V 3.0V 4.5V 2.7V 2.7V BOTTOM BOTTOM2.0V 2.5V 10 1 2.5V 20µs PULSE WIDTH TJ = 25 °C 0.1 0.1 1 10 10 100 TJ = 175 ° C 10 1 V DS = 50V 20µs PULSE WIDTH 10.0 VGS , Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics RDS(on) , Drain-to-Source On Resistance (Normalized) I D , Drain-to-Source Current (A) TJ = 25 ° C www.irf.com 10 100 Fig 2. Typical Output Characteristics 2.5 8.0 1 VDS , Drain-to-Source Voltage (V) 100 6.0 20µs PULSE WIDTH TJ = 175 °C 0.1 0.1 Fig 1. Typical Output Characteristics 4.0 2.5V 1 VDS , Drain-to-Source Voltage (V) 0.1 2.0 VGS VGS 15V 15V 12V 10V 10V 5.0V 7.0V 4.5V 5.0V 3.5V 4.5V 3.0V 2.7V 2.7V BOTTOM 2.0V BOTTOM 2.5V TOP TOP I D , Drain-to-Source Current (A) I D , Drain-to-Source Current (A) TOP TOP ID = 10A 2.0 1.5 1.0 0.5 0.0 -60 -40 -20 0 VGS = 10V 20 40 60 80 100 120 140 160 180 TJ , Junction Temperature ( °C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRLR/U014N Ciss 400 C, Capacitance (pF) VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd 300 Coss 200 Crss 100 15 VGS , Gate-to-Source Voltage (V) 500 0 1 10 ID = 6 A VDS = 44V VDS = 27V 10 5 FOR TEST CIRCUIT SEE FIGURE 13 0 100 0 VDS , Drain-to-Source Voltage (V) 4 6 8 10 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 1000 100 OPERATION IN THIS AREA LIMITED BY RDS(on) 100 ID , Drain Current (A) ISD , Reverse Drain Current (A) 2 QG , Total Gate Charge (nC) 10 TJ = 175 ° C 1 10us 10 100us 1ms 1 TJ = 25 ° C 0.1 0.2 0.6 1.0 V GS = 0 V 1.4 VSD ,Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 10ms TC = 25 ° C TJ = 175 ° C Single Pulse 0.1 1.8 1 10 100 VDS , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRLR/U014N 10.0 RD VDS VGS ID , Drain Current (A) 8.0 D.U.T. RG + -VDD 6.0 10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 4.0 Fig 10a. Switching Time Test Circuit 2.0 VDS 90% 0.0 25 50 75 100 125 150 175 TC , Case Temperature ( °C) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Thermal Response (Z thJC ) 10 D = 0.50 0.20 1 0.10 PDM 0.05 0.02 0.01 0.1 0.00001 t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1 1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 15V L VDS D.U.T RG IAS 10V 20V DRIVER + V - DD 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit A EAS , Single Pulse Avalanche Energy (mJ) IRLR/U014N 60 TOP 50 BOTTOM ID 2.4A 5.0A 6.0A 40 30 20 10 0 25 50 75 100 125 150 175 Starting TJ , Junction Temperature ( °C) V(BR)DSS tp Fig 12c. Maximum Avalanche Energy Vs. Drain Current I AS Current Regulator Same Type as D.U.T. Fig 12b. Unclamped Inductive Waveforms 50KΩ QG 12V .2µF .3µF 10 V QGS + V - DS VGS VG 3mA Charge Fig 13a. Basic Gate Charge Waveform 6 D.U.T. QGD IG ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit www.irf.com IRLR/U014N Peak Diode Recovery dv/dt Test Circuit + D.U.T Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer
+  - -  +  • • • • RG dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Driver Gate Drive P.W. Period D= + - VDD P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFETS www.irf.com 7 IRLR/U014N Package Outline TO-252AA Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) 1.14 (.045) 0.89 (.035) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 10.42 (.410) 9.40 (.370) 1 2 LEAD ASSIGNMENTS 3 1 - GATE 0.51 (.020) MIN. -B1.52 (.060) 1.15 (.045) 3X 2X 1.14 (.045) 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2 - DRAIN 3 - SOURCE 4 - DRAIN 0.58 (.023) 0.46 (.018) M A M B NOTES: 2.28 (.090) 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 4.57 (.180) 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). Part Marking Information TO-252AA (D-PAK) EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN THE ASSEMBLY LINE "A" PART NUMBER INTERNATIONAL RECTIFIER LOGO 12 ASSEMBLY LOT CODE 8 IRFU120 916A 34 DATE CODE YEAR 9 = 1999 WEEK 16 LINE A www.irf.com IRLR/U014N Package Outline TO-251AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) LEAD ASSIGNMENTS 4 1 - GATE 2 - DRAIN 6.45 (.245) 5.68 (.224) 1 2 3 -B2.28 (.090) 1.91 (.075) 3X 3 - SOURCE 4 - DRAIN 6.22 (.245) 5.97 (.235) 1.52 (.060) 1.15 (.045) 1.14 (.045) 0.76 (.030) 2.28 (.090) 3X 9.65 (.380) 8.89 (.350) NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-252AA. 4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP, SOLDER DIP MAX. +0.16 (.006). 0.89 (.035) 0.64 (.025) 1.14 (.045) 0.89 (.035) 0.25 (.010) M A M B 2X 0.58 (.023) 0.46 (.018) Part Marking Information TO-251AA (I-PAK) EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 1999 IN THE ASSEMBLY LINE "A" PART NUMBER INTERNATIONAL RECTIFIER LOGO IRFU120 919A 78 56 DATE CODE YEAR 9 = 1999 WEEK 19 LINE A ASSEMBLY LOT CODE www.irf.com 9 IRLR/U014N Tape & Reel Information TO-252AA Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive[Q101] market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 5/99 10 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/