IRS21571DSPBF

April 21st, 2008 IRS21571D FULLY INTEGRATED BALLAST CONTROL IC IC Features • • • • • • • • • • • • • • • Product Summary Programmable preheat time and frequency Programmable ignition ramp Protection from failure-to-strike Lamp filament sensing and protection Protection from operation below resonance 0.2V CS threshold sync’d to falling edge on LO Protection from low-line condition Automatic restart for lamp exchange Thermal overload protection Programmable deadtime Integrated 600V level-shifting gate driver Integrated bootstrap MOSFET Integrated 15.6V zener clamp diode on VCC Low micro-power start-up Latch immunity and ESD on all pins Topology Half-Bridge VOFFSET 600 V IO+ & IO- (typical) 180 mA & 260 mA Oscillator Frequency +/- 5% Start-up current (typical) 150 µA Package Options Typical Application • Fluorescent lamp ballast 16-Lead SOIC (Narrow Body) Typical Connection Diagram + Rectified AC Line + VBUS R2 R1 RSupply VDC HO 1 C1 2 CPH RPH 3 CRAMP RPH RT 4 RT RRUN RUN 5 CT 6 CT ROC RDT DT 7 16 IRS21571D CPH VS CBLOCK VB LRES CBS 14 CSNUBBER VCC 13 COM CVCC D1 12 D2 LO CRES 11 CS R3 RGLS 10 R5 SD OC 8 RGHS 15 R4 9 C2 RCS VBUS return www.irf.com © 2008 International Rectifier IRS21571D Table of Contents Page Typical Connection Diagram 1 Qualification Information 4 Absolute Maximum Ratings 5 Recommended Operating Conditions 6 Electrical Characteristics 7 Functional Block Diagram 9 Input/Output Pin Equivalent Circuit Diagrams 10 Lead Definitions 11 Lead Assignments 12 State Diagram 13 Application Information and Additional Details 14 Package Details 25 Part Marking Information 26 Ordering Information 27 Change History 28 www.irf.com 2 © 2008 International Rectifier IRS21571D Description The IRS21571D is a fully integrated, fully protected 600V ballast control IC designed to drive virtually all types of rapid start fluorescent lamp ballasts. Externally programmable features such as preheat time and frequency, ignition ramp characteristics, and running mode operating frequency provide a high degree of flexibility for the ballast design engineer. Comprehensive thermal overload, or lamp failure during normal operation, as well as an automatic restart function, have been included in the design. The heart of this control IC is a variable frequency, 50% duty cycle oscillator with externally programmable deadtime. An integrated bootstrap MOSFET is also included to supply the high-side gate drive circuitry. The IRS21571D is available in 16 pin narrow body SOIC package. www.irf.com © 2008 International Rectifier IRS21571D † Qualification Information Qualification Level Moisture Sensitivity Level Machine Model ESD Human Body Model IC Latch-Up Test RoHS Compliant Industrial†† Comments: This family of ICs has passed JEDEC’s Industrial qualification. IR’s Consumer qualification level is granted by extension of the higher Industrial level. MSL2††† SOIC16N (per IPC/JEDEC J-STD-020) Class C (per JEDEC standard EIA/JESD22-A115) Class 3A (per EIA/JEDEC standard JESD22-A114) Class , Level A (per JESD78) Yes † †† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. Please contact your International Rectifier sales representative for further information. www.irf.com 4 © 2008 International Rectifier IRS21571D Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol VB VS VHO VLO IOMAX IRT VCT VDC ICPH IRPH IRUN IDT VCS ICS IOC ISD ICC dV/dt PD PD RθJA RθJA TJ TS TL † www.irf.com Definition High Side Floating Supply Voltage High Side Floating Supply Offset Voltage High-Side Floating Output Voltage Low-Side Output Voltage Maximum Allowable Output Current (Either Output) Due to External Power Transistor Miller Effect RT Pin Current CT Pin Voltage VDC Pin Voltage CPH Pin Current RPH Pin Current RUN Pin Current Deadtime Pin Current Current Sense Pin Voltage Current Sense Pin Current Over-Current Threshold Pin Current Shutdown Pin Current † Supply Current Allowable Offset Voltage Slew Rate (16-Pin DIP) Package Power Dissipation @ TA ≤ +25ºC Package Power Dissipation @ TA ≤ +25ºC (16-Pin SOIC) Thermal Resistance, Junction to Ambient (16-Pin DIP) Thermal Resistance, Junction to Ambient (16-Pin SOIC) Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) Min. -0.3 Max. 625 Units V VB - 25 VS - 0.3 -0.3 VB + 0.3 VB + 0.3 VCC + 0.3 V V V -500 500 mA -5 -0.3 -0.3 -5 -5 -5 -5 -0.3 -5 -5 -5 -20 -50 ---------55 -55 --- 5 5.5 VCC + 0.3 5 5 5 5 5.5 5 5 5 20 50 1.60 1.25 75 100 150 150 300 mA V V mA mA mA mA V mA mA mA mA V/ns W W ºC/W ºC/W ºC This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the VCLAMP specified in the Electrical Characteristics section. © 2008 International Rectifier IRS21571D Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. Symbol VBS VS VCC ICC VDC CT RDT ROC IRT IRPH IRUN ISD ICS TJ † †† www.irf.com Definition High Side Floating Supply Voltage Steady State High Side Floating Supply Offset Voltage Supply Voltage Supply Current VDC Pin Voltage CT Pin Capacitance Deadtime Resistance Over-Current (CS+) Threshold Programming Resistance †† RT Pin Current †† RPH Pin Current †† RUN Pin Current Shutdown Pin Current Current Sense Pin Current Junction Temperature Min. VBSUV+ -3.0 VCCUV+ † 0 220 1.0 ---500 0 0 -1 -1 -40 Max. VCLAMP 600 VCLAMP 10 VCC ----50 -50 450 450 1 1 125 Units V V V mA V pF kΩ kΩ µA µA µA mA mA ºC Enough current should be supplied into the VCC pin to keep the internal 15.6V zener clamp diode on this pin regulating its voltage. Due to the fact that the RT input is a voltage-controlled current source, the total RT pin current is sum of all of the parallel current sources connected to that pin. For optimum oscillator current mirror performance, this total current should be kept between 50μA and 500μA. During the preheat mode, the total current flowing out of the RT pin consists of the RPH pin current plus the current due to the RT resistor. During the run mode, the total RT pin current consists of the RUN pin current plus the the current due to the RT resistor. 6 © 2008 International Rectifier IRS21571D Electrical Characteristics VCC = VBS = VBIAS = 14V +/- 0.25V, RT=16.9kΩ, CT = 470 pF, RPH and RUN pins no connection, VCPH = 0V, RDT = 6.1 kΩ, ROC = 20.0 kΩ, VCS = 0.5 V, VSD = 0 V, CL = 1000pF and TA = 25 °C unless otherwise specified. Symbol Definition Supply Characteristics VCC Supply Undervoltage Positive Going VCCUV+ Threshold Min Typ Max 11.5 12.5 13.5 Units Test Conditions VCC rising from 0V V VUVHYS VCC Supply Undervoltage Lockout Hysteresis --- 2.0 --- IQCCUV UVLO Mode Quiescent Current --- 150 300 IQCCFLT Fault-Mode Quiescent Current --- 400 600 IQCC Quiescent VCC Supply Current 2 4.3 µA VCC = VCCUV+ 100mV SD = 5V, CS = 2V, or Tj > TSD CT connected to COM mA IQCC40k VCC Supply Current, f = 40kHz 4.0 5.5 7.0 VCLAMP VCC Zener Clamp Voltage --- 15.6 --- Floating Supply Characteristics IQBS0 Quiescent VBS Supply Current --- 50 100 IQBS1 --- 72 140 --- 9.0 --- --- 8.0 --- --- --- 50 43.7 46 48.3 VBSUV+ VBSUVILK Quiescent VBS Supply Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold V uA VHO = VS VHO = VB VBS rising from 0V V Offset Supply Leakage Current ICC = 5mA µA VBS falling from 14V VB = VS = 600V Oscillator I/O Characteristics fOSC Oscillator Frequency d Oscillator Duty Cycle VCT+ Upper CT Ramp Voltage Threshold --- 4.0 --- VCT- Lower CT Ramp Voltage Threshold --- 2.0 --- VCTFLT Fault-Mode CT Pin Voltage --- 0 --- mV VRT RT Pin Voltage --- 2.0 --- V VRTFLT Fault-Mode RT Pin Voltage --- 0 --- mV tdlo LO Output Deadtime --- 2.3 --- µsec tdho HO Output Deadtime --- 2.3 --- µsec 0.98 µA 50 kHz % V SD = 5V, CS = 2V, or Tj > TSD SD = 5V, CS = 2V, or Tj > TSD Preheat Characteristics ICPH CPH Pin Charging Current VCPHIGN VCPHRUN CPH Pin Ignition Mode Threshold Voltage CPH Pin Run Mode Threshold Voltage 3.7 4.0 4.3 4.6 5.0 5.4 VCPHFLT Fault-Mode CPH Pin Voltage --- 0 --- www.irf.com 7 VCPH = 0V V mV SD = 5V, CS = 2V, or Tj > TSD © 2008 International Rectifier IRS21571D Electrical Characteristics VCC = VBS = VBIAS = 14V +/- 0.25V, RT=16.9kΩ, CT = 470 pF, RPH and RUN pins no connection, VCPH = 0V, RDT = 6.1 kΩ, ROC = 20.0 kΩ, VCS = 0.5 V, VSD = 0 V, CL = 1000pF and TA = 25 °C unless otherwise specified. Symbol Definition Min Typ Max Units Test Conditions RPH Characteristics IRPHLK Open Circuit RPH Pin Leakage Current --- --- 0.1 µA VRPH = 5V, VPH = 6V VRPHFLT Fault-Mode RPH Pin Voltage --- --- 50 mV SD = 5V, CS = 2V, or Tj > TSD RUN Characteristics IRUNLK Open Circuit RUN Pin Leakage Current --- --- 0.1 µA VRUN = 5V VRUNFLT Fault-Mode RUN Pin Voltage --- 0 --- mV SD = 5V, CS = 2V, or Tj > TSD Protection Circuitry Characteristics VSD+ Rising Shutdown Pin Threshold Voltage 2.0 2.2 2.4 V VSDHYS Shutdown Pin Threshold Hysteresis 270 395 520 VCS+ VCS- Over-Current Sense Threshold Voltage 0.99 1.1 1.21 mV V Under-Current Sense Threshold Voltage 0.15 0.2 0.26 V tcs Over-Current Sense Propagation Delay 250 400 nsec VDC+ Low VBUS/Rectified Line Input Upper Threshold 5.0 5.2 5.6 V VDC- Low VBUS/Rectified Line Input Lower Threshold 2.8 3.1 3.4 TSD Thermal Shutdown Junction Temperature --- 160 --- V ºC Gate Driver Output Characteristics VOL Low-Level Output Voltage 0 100 VOH High-Level Output Voltage 0 100 tr Turn-On Rise Time 120 220 tf Turn-Off Fall Time 50 220 IO+ Output source current --- 180 --- IO- Output sink current --- 260 --- † When the IC senses an overtemperature condition (Tj > 175ºC), the IC is latched off. In order to reset this Fault Latch, the SD pin must be cycled high and then low, or the VCC supply to the IC must be cycled below the falling undervoltage lockout threshold (VCCUV-). www.irf.com 8 Delay from CS to LO † IO = 0 mV VBIAS - VO , IO = 0 nsec mA © 2008 International Rectifier IRS21571D Functional Block Diagram VCC 3.0V VDC 1 S Q R Q 5.1V BOOTSTRAP MOSFET CONTROL LEVEL SHIFT PULSE FILTER & LATCH 1.0uA CPH 2 10.4V 14 VB 16 HO 15 VS 13 VCC 11 LO 12 COM 10 CS 5.1V S Q T Q R Q 4.0V R1 4.0V RPH 3 2.0V R2 Q IRT 15.6V RT 4 2.0V RUN 5 Q ICT = IRT D 0.2V CLK CT 6 Q S Q R Q R DT 7 10.4V 50uA OC 8 OVERTEMP DETECT UNDERVOLTAGE DETECT 9 10.4V 2.0V www.irf.com 9 SD 10.4V © 2008 International Rectifier IRS21571D Input/Output Pin Equivalent Circuit Diagrams www.irf.com 10 © 2008 International Rectifier IRS21571D Lead Definitions Symbol VDC Description DC Bus Sensing Input CPH Preheat Timing Capacitor RPH Preheat Frequency Resistor & Ignition Capacitor RT RUN Oscillator Timing Resistor Run Frequency Resistor CT Oscillator Timing Capacitor DT Deadtime Programming OC Over-current (CS+) Threshold Programming SD Shutdown Input CS Current Sensing Input LO Low-Side Gate Driver Output COM IC Power & Signal Ground VCC Logic & Low-side Gate Driver Floating Supply VB High-Side Gate Driver Floating Supply VS High Voltage Floating Return HO High-Side Gate Driver Outpur www.irf.com 11 © 2008 International Rectifier IRS21571D Lead Assignments www.irf.com 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 12 © 2008 International Rectifier IRS21571D State Diagram Power Turned On UVLO Mode 1 /2-Bridge Off IQCC ≅ 150μA CPH = 0V Oscillator Off SD > 2.2V (Lamp Removal) or VCC < 10.5V (Power Turned Off) FAULT Mode Fault Latch Set 1 /2-Bridge Off IQCC ≅ 150μA CPH = 0V VCC = 15.6V Oscillator Off TJ > 140C (Over-Temperature) CS > CS+ Threshold (Failure to Strike Lamp or Hard Switching) or TJ > 140C (Over-Temperature) CS > CS+ Threshold (Over-Current or Hard Switching) or CS < 0.2V (No-Load or Below Resonance) or TJ > 140C (Over-Temperature) www.irf.com VCC > 12.5V (UV+) and VDC > 5.2V (Bus OK) and SD < 1.7V (Lamp OK) and TJ < 140C (Tjmax) VCC < 10.5V (VCC Fault or Power Down) or VDC < 3.0V (dc Bus/ac Line Fault or Power Down) or SD > 2.2V (Lamp Fault or Lamp Removal) PREHEAT Mode 1 /2-Bridge @ fPH CPH Charging @ IPH = 1μA RPH = 0V RUN = Open Circuit CS Disabled CPH > 4.0V (End of PREHEAT Mode) IGNITION RAMP Mode fPH ramps to fMIN CPH Charging @ IPH = 1μA RPH = Open Circuit RUN = Open Circuit CS+ Threshold Enabled CPH > 5V (End of IGNITION RAMP) RUN Mode fMIN Ramps to fRUN CPH Charges to 10V Clamp RPH = Open Circuit RUN = 0V CS- Threshold Enabled 13 © 2008 International Rectifier IRS21571D Application Information and Additional Details Supply Bypassing and PCB Layout Rules Component selection and placement on the pc board is extremely important when using power control ICs. VCC should be bypassed to COM as close to the IC terminals as possible with a low ESR/ESL capacitor, as shown in Figure 1 below. CVCC (surface mount) IR21571 pin 1 CBOOT (surface mount) CVCC (through hole) Figure 1: Supply bypassing PCB layout example A rule of thumb for the value of this bypass capacitor is to keep its minimum value at least 2500 times the value of the total input capacitance (Ciss) of the power transistors being driven. This decoupling capacitor can be split between a higher valued electrolytic type and a lower valued ceramic type connected in parallel, although a good quality electrolytic (e.g., 10μF) placed immediately adjacent to the VCC and COM terminals will work well. In a typical application circuit, the supply voltage to the IC is normally derived by means of a high value startup resistor (1/4W) from the rectified line voltage, in combination with a charge pump from the output of the halfbridge. With this type of supply arrangement, the internal 15.6V zener clamp diode from VCC to COM will determine the steady state IC supply voltage. Connecting the IC Ground (COM) to the Power Ground Both the low power control circuitry and low side gate driver output stage grounds return to this pin within the IC. The COM pin should be connected to the bottom terminal of the current sense resistor in the source of the low side power MOSFET using an individual pc board trace, as shown in Figure 2. In addition, the ground return path of the timing components and VCC decoupling capacitor should be connected directly to the IC COM pin, and not via separate traces or jumpers to other ground traces on the board. IR21571 pin 1 CVCC (surface mount) CVCC (through hole) timing components RCS (through hole) VBUS return Figure 2: COM pin connection PCB layout example www.irf.com 14 © 2008 International Rectifier IRS21571D These connection techniques prevent high current ground loops from interfering with sensitive timing component operation, and allows the entire control circuit to reject common-mode noise due to output switching. The Control Sequence and Timing Component Selection The IRS21571D uses the following control sequence (Figure 3) to drive rapid start fluorescent lamps. frequency fStart fPH fRun fmin t 5V VCPH 2V VRPH 2V VRUN Preheat mode Ignition Run mode Ramp mode Figure 3: IRS21571D Control sequence The control sequence used in the IRS21571D allows the Run Mode operating frequency of the ballast to be higher than the ignition frequency (i.e., fstart > fph > frun > fign). This control sequence is recommended for lamp types where the ignition frequency is too close to the run frequency to ensure proper lamp striking for all production resonant LC component tolerances (please note that it is possible to use the IRS21571D in systems where fstart > fph > fign > frun, simply by leaving the RUN pin open). Six pins in the IC are used to control the Startup, Preheat, Ignition Ramp, and Run modes of operation, and to allow ballast and lamp engineers the flexibility to optimize their designs for virtually any lamp type. The heart of this controller is an oscillator which resembles those found in many popular PWM voltage regulator ICs. In its simplest form, this oscillator consists of a timing resistor and capacitor connected to ground. The voltage across the timing capacitor CT is a sawtooth, where the rising portion of the ramp is determined by the current in the RT pin, and the falling portion of the ramp is determined by an external deadtime resistor RDT. The oscillograph in Figure 4 illustrates the relationship between the oscillator capacitor waveform and the gate driver outputs. www.irf.com 15 © 2008 International Rectifier IRS21571D CT LO HO-VS Figure 4 The deadtime can be programmed by means of the external RDT resistor, given a certain range of CT capacitor values, using the graph shown in Figure 5. 10 tDEAD (usec) CT = 220 pF CT = 470 pF CT = 1 nF 1 0.1 1 10 100 RDT (Kohms) Figure 5: Deadtime versus RDT The RT input is a voltage-controlled current source, where the voltage is regulated to be approximately 2.0V. In order to maintain proper linearity between the RT pin current and the CT capacitor charging current, the value of the RT pin current should be kept between 50µA and 500µA. The RT pin can also be used as a feedback point for closed loop control. www.irf.com 16 © 2008 International Rectifier IRS21571D During the Startup Mode, the operating frequency is determined by the parallel combination of RPH and RT , combined with the values of CT and RDT , and the voltage at the RT pin, as shown in Figure 6. The voltage at the RT pin starts at an initial value above 2V, causing the initial start frequency to be higher than the preheat frequency. This frequency is high enough to ensure that the instantaneous voltage across the lamp during the first few cycles of operation does not exceed the strike potential of the lamp. As the voltage at the RT pin decreases to the final value of 2V, the output frequency ramps down to the preheat frequency. CPH 1.0uA 2 CPH 7.6V 5.1V S Q 4.0V R1 4.0V RPH 3 CIGN RPH RT 2.0V R2 Q IRT 4 RT RRUN 2.0V RUN 5 CT ICT = IRT 6 CT RDT DT 7 UNDERVOLTAGE DETECT Figure 6: Oscillator section block diagram with external component connection During the Preheat Mode, the operating frequency is determined by the parallel combination of RPH and RT , combined with the value of CT and RDT . This frequency, along with the Preheat Time, is normally chosen to ensure that adequate heating of the lamp filaments occurs. Typically, a 4.5:1 ratio of the hot filament-to-cold filament resistance is desired for maximum lamp life, as shown in Figure 7 below www.irf.com 17 © 2008 International Rectifier IRS21571D Preheat Ignition Ramp Run Figure 7: Lamp filament voltage during the preheat, ignition ramp and run modes The Preheat Time is programmed by means of the preheat capacitor, CPH, an internal 1μA current source, and an internal threshold on the CPH pin of 4.0V, according to the following formula: tPH = 4E6 ⋅ CPH, or CPH = 250E - 9 ⋅ tPH At the end of the Preheat Time, the internal, open-drain transistor holding the RPH pin to ground turns off, and the voltage on this pin charges exponentially up to the RT pin potential. During this Ignition Ramp Mode, the output frequency exponentially decays to a minimum value. The rate of decay of this frequency is a function of the RPH ∗ CRAMP time constant. Because the Ignition Ramp Mode ends when the voltage on the CPH pin reaches 5.15V, the Ignition Ramp Mode is always 1/4th as long as the preheat time. When the CPH pin reaches 5.15V, an open-drain transistor on the RUN pin turns on, and the external RRUN resistor is then in parallel with the RT resistor. The Run Mode operating frequency is therefore a function of the parallel combination of RRUN and RT, and this means that the operating power of the lamp can be programmed by means of RRUN . The following graphs, Figures 8 and 9, illustrate the relationship between the effective RT resistance (i.e., the parallel combination of resistors which programs the CT capacitor charging current) and the operating frequency. www.irf.com 18 © 2008 International Rectifier IRS21571D 250 150 200 FREQ (KHz) CT=220pF, RDT=5.6K CT=470pF, RDT=2.7K CT=1nF, RDT=1.2K CT=220pF,RDT=11K CT=470pF,RDT=6.2K 150 CT=1nF,RDT=3K 100 FREQ (KHz) 100 50 50 0 0 0 5 10 15 20 25 30 35 0 40 5 10 15 RT (K ohms) Figure 8: fOSC versus effective RT (tDEAD = 2.0 usec) 20 RT (K ohms) 25 30 35 40 Figure 9: fOSC versus effective RT (tDEAD = 1.0 usec) Lamp Protection & Automatic Restart Circuitry Operation Four pins on the IRS21571D are used for protection, as shown in Figure 10 below. These are VDC (dc bus monitor), SD (unlatched shutdown), CS (latched shutdown) and OC (CS+ threshold programming). +VBUS R2 VDC 3.0V 1 S Q R Q 5.1V R1 C1 from oscillator section CPH 1.0uA 2 T Q R Q Q2 7.6V 5.1V R3 4.0V Q D CS 0.2V Q S Q R Q 7 RCS 10 CLK DT R VCC 7.6V 50uA OC 8 ROC UNDERVOLTAGE DETECT OVERTEMP DETECT SD R4 R5 9 7.6V 2.0V 7.6V C2 from lower lamp cathode Figure 10: Lamp Protection & Automatic Restart circuitry block diagram with external component connection www.irf.com 19 © 2008 International Rectifier IRS21571D Sensing The DC Bus Voltage The first of these protection pins senses the voltage on the DC bus by means of an external resistor divider and an internal comparator with hysterisis. When power is first supplied to the IC at system startup, 3 conditions are required before oscillation is initiated: 1.) the voltage on the VCC pin must exceed the rising undervoltage lockout threshold (12.5V), 2.) the voltage at the VDC pin must exceed 5.1V, and 3.) the voltage on the SD pin must be below approximately 1.85V. If a low dc bus condition occurs during normal operation, or if power to the ballast is shut off, the dc bus will collapse prior to the VCC of the chip (assuming the VCC is derived from a charge pump off of the output of the half-bridge). In this case, the voltage on the VDC pin will shut the oscillator off, thereby protecting the power transistors from potentially hazardous hard switching. Approximately 2V of hysterisis has been designed into the internal comparator sensing the VDC pin, in order to account for variations in the dc bus voltage under varying load conditions. When the dc bus recovers, the chip restarts from the beginning of the control sequence, as shown in timing diagram Figure 11 below. 5 VDC 3 4 CT 8 CPH 15 LO 15 HO-VS RUN mode Low VDC Restart Figure 11: VDC pin fault and auto restart Lamp Presence Detection and Automatic Restart The second protection pin, SD, is used for both unlatched shutdown and automatic restart functions. The SD pin would normally be connected to an external circuit which senses the presence of the lamp (or lamps). A example circuit for a single lamp is shown in Figure 12. www.irf.com 20 © 2008 International Rectifier IRS21571D + rectified AC Line VDC + VBUS HO 1 16 IRS21571D CPH 2 RPH 3 RT 4 RUN 5 CT 6 DT 7 VS RGHS VB LRES CBS 14 RSupply VCC DBOOT COM CVCC CSNUBBER 13 D1 12 D2 CRES LO 11 CS R3 RGLS R5 10 OC SD 8 CBLOCK 15 R4 9 C2 RCS VBUS return Figure 12: Lamp presence detection circuit connection (shaded area) When the SD pin exceeds 2.0V (approximately 150mV of hysterisis is included to increase noise immunity), signaling either a lamp fault or lamp removal, the oscillator is disabled, both gate driver outputs are pulled low, and the chip is put into the micropower mode. Since a lamp fault would normally lead to a lamp exchange, when a new lamp is inserted into the fixture, the SD pin would be pulled back to near the ground potential. Under these conditions a reset signal would restart the chip from the beginning of the control sequence, as shown in the timing diagram in Figure 13. 2 SD 4 CT 8 CPH 15 LO 15 HO-VS RUN mode SD mode Restart Figure 13: SD pin fault and auto restart Thus, for a lamp removal and replacement, the ballast automatically restarts the lamp in the proper manner, maximizing lamp life and minimizing stress on the power MOSFETs or IGBTs. www.irf.com 21 © 2008 International Rectifier IRS21571D Half-Bridge Current Sensing and Protection The third pin used for protection is the CS pin, which is normally connected to a resistor in the source of the lower power MOSFET, as shown in Figure 14. The CS pin is used to sense fault conditions such as failure of a lamp to strike, over-current during normal operation, hard switching, no load, and operation below resonance. If any one of these conditions is sensed, the fault latch is set, the oscillator is disabled, the gate driver outputs go low, and the chip is put into the micropower mode. The CS pin performs its sensing functions on a cycle-by-cycle basis in order to maximize ballast reliability. rectifie d AC line VDC +VBUS HO 1 2 RPH 3 RT 4 RUN 5 CT 6 DT 7 16 IRS21571D CPH Q1 VS RGHS 1/ 15 VB CBOOT VCC DBOOT 14 RSUPPLY 2 Bridge output CSNUBBER D1 13 COM CVCC 12 LO 11 Q2 CS RGLS D2 10 R3 OC SD 8 9 RCS ROC VBUS return Figure 14: Half-bridge current sensing circuit connection (shaded area) For the over-current, failure-to-strike, and hard switching fault conditions, an externally programmable, positivegoing CS+ threshold is enabled at the end of the preheat time. The level of this positive-going threshold is determined by the value of the resistor ROC. The value of the resistor ROC is determined by the following formula: ROC = VCS+ , 50E - 6 or VCS + = 50E - 6 ⋅ ROC For the under-current and under-resonance conditions, there is a negative-going CS- threshold of 0.2V which is enabled at the onset of the run mode. The sensing of this CS- threshold is synchronized with the falling edge of the LO output. Figures 15, 16 and 17 are oscillographs of fault conditions. Figure 15 shows a failure of the lamp to strike, Figure 16 shows a hard switching condition and Figure 17 shows an under-current condition. www.irf.com 22 © 2008 International Rectifier IRS21571D CS VS Figure 15: Lamp failure to strike CS VS Figure 16: Hard switching condition www.irf.com 23 © 2008 International Rectifier IRS21571D CS VS Figure 17: Operation below resonance Recovery from such a fault condition is accomplished by cycling either SD pin or the VCC pin. When a lamp is removed, the SD pin goes high, the fault latch is reset, and the chip is held off in an unlatched state. Lamp replacement causes the SD pin to go low again, reinitiating the startup sequence. The fault latch can also be reset by the undervoltage lockout signal, if VCC falls below the lower undervoltage threshold. SD CPH VS Figure 18: Auto restart for lamp replacement www.irf.com 24 © 2008 International Rectifier IRS21571D Package Details: SO16N www.irf.com 25 © 2008 International Rectifier IRS21571D Package Details: SOIC16N, Tape and Reel LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 7.90 8.10 B 3.90 4.10 C 15.70 16.30 D 7.40 7.60 E 6.40 6.60 F 10.20 10.40 G 1.50 n/a H 1.50 1.60 16SOICN Imperial Min Max 0.311 0.318 0.153 0.161 0.618 0.641 0.291 0.299 0.252 0.260 0.402 0.409 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 16SOICN Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 22.40 n/a 0.881 G 18.50 21.10 0.728 0.830 H 16.40 18.40 0.645 0.724 www.irf.com 26 © 2008 International Rectifier IRS21571D Part Marking Information www.irf.com 27 © 2008 International Rectifier IRS21571D Ordering Information Standard Pack Base Part Number IRS21571D Package Type Complete Part Number Form Quantity SOIC16N Tube/Bulk 48 IRS21571DSPBF SOIC16N Tape and Reel 2500 IRS21571DSTRPBF The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document supersedes and replaces all information previously supplied. For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 www.irf.com 28 © 2008 International Rectifier