S29WS256N
S29WS128N
256/128 Mbit (16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write, Burst Flash
This product family has been retired and is not recommended for designs. For new and current designs, the S29WS128P and
S29WS256P supersede the S29WS128N and S29WS256N respectively. These are the factory-recommended migration paths.
Please refer to the S29WS-P Family data sheet for specifications and ordering information.
General Description
The Spansion S29WS256/128 are MirrorbitTM Flash products fabricated on 110 nm process technology. These burst mode Flash
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate
data and address pins. These products can operate up to 80 MHz and use a single VCC of 1.7 V to 1.95 V that makes them ideal for
today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
Hardware (WP#) protection of top and bottom sectors
110 nm MirrorBit™ Technology
Dual boot sector configuration (top and bottom)
Simultaneous Read/Write operation with zero latency
Offered Packages
32-word Write Buffer
WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low VCC write inhibit
es
ig
n
Single 1.8 V read/program/erase (1.70–1.95 V)
D
Sixteen-bank architecture consisting of 16/8 Mwords for WS256N/
128N, respectively
Persistent and Password methods of Advanced Sector Protection
ew
Four 16 Kword sectors at both top and bottom of memory array
Write operation status bits indicate program and erase operation
completion
Programmable linear (8/16/32) with or without wrap around and
continuous burst read modes
Suspend and Resume commands for Program and Erase
operations
Secured Silicon Sector region consisting of 128 words each for
factory and customer
Unlock Bypass program command to reduce programming time
fo
rN
254/126 64 Kword sectors (WS256N/128N)
d
Synchronous or Asynchronous program operation, independent of
burst control register settings
Cycling Endurance: 100,000 cycles per sector (typical)
ACC input pin to reduce factory programming time
om
m
en
RDY output indicates data available to system
de
20-year data retention (typical)
Support for Common Flash Interface (CFI)
Command set compatible with JEDEC (42.4) standard
Performance Characteristics
ec
Read Access Times
Max. Synch. Latency, ns (tIACC)
66
54
Continuous Burst Read @ 80 MHz
38 mA
80
80
80
Simultaneous Operation (asynchronous)
50 mA
9
11.2
13.5
Program (asynchronous)
19 mA
80
80
80
Erase (asynchronous)
19 mA
Max. Asynch. Page Access Time, ns (tPACC)
20
20
20
Standby Mode (asynchronous)
20 µA
Max CE# Access Time, ns (tCE)
80
80
80
Max OE# Access Time, ns (tOE)
13.5
13.5
13.5
ot
Max. Synch. Burst Access, ns (tBACC)
Current Consumption (typical values)
80
R
Speed Option (MHz)
N
Max. Asynch. Access Time, ns (tACC)
Typical Program & Erase Times
Single Word Programming
40 µs
Effective Write Buffer Programming (VCC) Per Word
9.4 µs
Effective Write Buffer Programming (VACC) Per Word
Cypress Semiconductor Corporation
Document Number: 002-01825 Rev. *B
•
6 µs
Sector Erase (16 Kword Sector)
150 ms
Sector Erase (64 Kword Sector)
600 ms
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 08, 2016
S29WS256N
S29WS128N
Contents
1.
1.1
Ordering Information ................................................... 3
Valid Combinations ........................................................ 3
11.7 DC Characteristics (CMOS Compatible)....................... 54
11.8 AC Characteristics ........................................................ 55
2.
Input/Output Descriptions & Logic Symbol .............. 4
3.
Block Diagram.............................................................. 5
12. Appendix ..................................................................... 72
12.1 Common Flash Memory Interface................................. 75
4.
4.1
4.2
4.3
Physical Dimensions/Connection Diagrams.............
Related Documents .......................................................
Special Handling Instructions for FBGA Package..........
MCP Look-ahead Connection Diagram .........................
5.
Additional Resources .................................................. 9
6.
6.1
Product Overview ...................................................... 10
Memory Map ................................................................ 10
7.
7.1
7.2
7.3
7.4
Device Operations .....................................................
Device Operation Table ...............................................
Asynchronous Read.....................................................
Page Read Mode .........................................................
Synchronous (Burst) Read Mode & Configuration
Register........................................................................
7.5 Autoselect ....................................................................
7.6 Program/Erase Operations ..........................................
7.7 Simultaneous Read/Write ............................................
7.8 Writing Commands/Command Sequences..................
7.9 Handshaking ................................................................
7.10 Hardware Reset ...........................................................
7.11 Software Reset ............................................................
12
12
12
13
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Advanced Sector Protection/Unprotection .............
Lock Register ...............................................................
Persistent Protection Bits.............................................
Dynamic Protection Bits...............................................
Persistent Protection Bit Lock Bit.................................
Password Protection Method .......................................
Advanced Sector Protection Software Examples ........
Hardware Data Protection Methods.............................
41
42
43
44
44
44
46
46
9.
9.1
9.2
9.3
9.4
Power Conservation Modes......................................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
Hardware RESET# Input Operation.............................
Output Disable (OE#)...................................................
47
47
47
47
47
10.
10.1
10.2
10.3
Secured Silicon Sector Flash Memory Region ....... 48
Factory Secured Silicon Sector .................................... 48
Customer Secured Silicon Sector ................................ 49
Secured Silicon Sector Entry/Exit Command
Sequences .................................................................... 49
11.
11.1
11.2
11.3
11.4
11.5
11.6
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Operating Ranges........................................................
Test Conditions ............................................................
Key to Switching Waveforms .......................................
Switching Waveforms ..................................................
VCC Power-up ..............................................................
13.
N
ot
R
ec
es
D
ew
rN
fo
om
m
en
de
d
14
18
21
38
38
39
39
40
Document History Page ............................................. 78
ig
n
5
5
5
7
Document Number: 002-01825 Rev. *B
51
51
52
52
52
53
53
Page 2 of 79
S29WS256N
S29WS128N
1.
Ordering Information
The order number is formed by a valid combinations of the following:
S29WS
256
N
0S
BA
W
01
0
Packing Type
0 = Tray (standard; (Note 1))
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number (Note 3)
(DYB Protect/Unprotect After Power-up)
01 = DYB Unprotect
11 = DYB Protect
ig
n
Temperature Range (Note 3)
W = Wireless (–25°C to +85°C)
D
rN
Process Technology
N = 110 nm MirrorBit™ Technology
ew
Speed Option (Burst Frequency)
0S = 80 MHz
0P = 66 MHz
0L = 54 MHz
es
Package Type & Material Set
BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package
BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package
d
fo
Flash Density
256= 256 Mb
128= 128 Mb
1.1
Valid Combinations
om
m
en
de
Product Family
S29WS =1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Speed
Option
S29WS256N
Preliminary
0S, 0P, 0L
Package Type, Material,
& Temperature Range
N
ot
R
Product
Status
ec
S29WS-N Valid Combinations (1), (2), (3)
Base Ordering
Part Number
S29WS128N
Preliminary
0S, 0P, 0L
Model
Number
Packing
Type
DYB Power
Up State
01
BAW (Lead (Pb)-free
Compliant),
BFW (Lead (Pb)-free)
11
01
Package Type (2)
Unprotect
0, 2, 3
(1)
11
Protect
Unprotect
8 mm x 11.6 mm
84-ball
MCP-Compatible
Protect
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S29” and packing type designator from ordering part number.
3. For other boot option contact your local sales office.
Document Number: 002-01825 Rev. *B
Page 3 of 79
S29WS256N
S29WS128N
2.
Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
Input/Output Descriptions
Type
Description
A23–A0
Input
DQ15–DQ0
I/O
CE#
Input
Chip Enable. Asynchronous relative to CLK.
OE#
Input
Output Enable. Asynchronous relative to CLK.
WE#
Input
VCC
Supply
Address lines for WS256N (A22-A0 for WS128).
Data input/output.
Write Enable.
Device Power Supply.
VSS
I/O
NC
No Connect
RDY
Output
CLK
Input
Ground.
ig
n
Symbol
Not connected internally.
es
Ready. Indicates when valid burst data is ready to be read.
D
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter.
ew
Input
rN
AVD#
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
Input
Hardware Reset. Low = device resets and returns to reading array data.
WP#
Input
Write Protect. At VIL, disables program and erase functions in the four outermost sectors. Should be at
VIH for all other conditions.
ACC
Input
Acceleration Input. At VHH, accelerates programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
RFU
Reserved
de
d
fo
RESET#
N
ot
R
ec
om
m
en
Reserved for future use (see Figure 4.3, MCP Look-ahead Diagram on page 8).
Document Number: 002-01825 Rev. *B
Page 4 of 79
S29WS256N
S29WS128N
3.
Block Diagram
DQ15–DQ0
VCC
RDY
Buffer
VSS
RDY
Input/Output
Buffers
Erase Voltage
Generator
WE#
State
Control
WP#
ACC
Command
Register
PGM Voltage
Generator
ig
n
RESET#
es
Chip Enable
Output Enable
Logic
Data
Latch
fo
VCC
Detector
Burst
State
Control
CLK
Amax–A0*
om
m
en
AVD#
de
d
Timer
Burst
Address
Counter
Address Latch
rN
ew
D
CE#
OE#
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
ot
R
ec
*WS256N: A23-A0
WS128N: A22-A0
N
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29WS-N.
4.1
Related Documents
The following documents contain information relating to the S29WS-N devices. Click on the title or go to www.amd.com/flash (click
on Technical Documentation) or www.fujitsu.com to download the PDF file, or request a copy from your sales office.
Migration to the S29WS256N Family Application Note
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Document Number: 002-01825 Rev. *B
Page 5 of 79
S29WS256N
S29WS128N
Figure 4.1 84-ball Fine-Pitch Ball Grid Array (S29WS256N, S29WS128N)
(Top View, Balls Facing Down, MCP Compatible)
A10
A1
B4
B5
B6
B7
B8
B9
AVD#
RFU
CLK
RFU
RFU
RFU
RFU
RFU
C2
C3
C4
C5
C6
C7
C8
C9
WP#
A7
RFU
ACC
WE#
A8
A11
RFU
D2
D3
D4
D5
D6
D7
D8
D9
A3
A6
RFU
RESET#
RFU
A19
A12
A15
E2
E3
E4
E5
A2
A5
A18
RDY
F2
F3
F4
A1
A4
A17
G2
G3
G4
A0
VSS
H2
H3
OE#
E8
E9
D
es
E7
A9
A13
A21
ew
A20
F6
F7
F8
F9
RFU
A23
A10
A14
A22
G5
G6
G7
G8
G9
RFU
RFU
DQ6
RFU
A16
H4
H5
H6
H7
H8
H9
DQ9
DQ3
DQ4
DQ13
DQ15
RFU
fo
rN
F5
DQ1
J3
J4
J5
J6
J7
J8
RFU
DQ0
DQ10
VCC
RFU
DQ12
DQ7
VSS
K2
K3
K4
K5
K6
K7
K8
K9
RFU
DQ8
DQ2
DQ11
RFU
DQ5
DQ14
RFU
L2
L3
L4
L5
L6
L7
L8
L9
RFU
RFU
RFU
VCC
RFU
RFU
RFU
RFU
R
ec
J2
ot
N
Document Number: 002-01825 Rev. *B
E6
om
m
en
CE#f1
ig
n
B3
d
Ball F6 is RFU on
128 Mb device.
B2
de
NC
NC
J9
M1
M10
NC
NC
Page 6 of 79
S29WS256N
S29WS128N
Figure 4.2 VBH084—84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm MCP Compatible Package
0.05 C
(2X)
D
D1
A
e
10
9
e
7
8
SE
7
6
E1
E
5
4
3
2
1
M
A1 CORNER
K
J
H
G
B
10
E
SD
6
0.05 C
(2X)
F
D
C
B
A
A1 CORNER
7
NXφb
ig
n
INDEX MARK
L
φ 0.08 M C
TOP VIEW
A1
0.08 C
C
ew
SEATING PLANE
BOTTOM VIEW
D
0.10 C
A2
A
es
φ 0.15 M C A B
PACKAGE
fo
rN
SIDE VIEW
VBH 084
d
N/A
NOM
MAX
de
JEDEC
---
1.00
OVERALL THICKNESS
SYMBOL
MIN
A
---
A1
0.18
A2
0.62
om
m
en
11.60 mm x 8.00 mm NOM
PACKAGE
---
---
---
0.76
BALL HEIGHT
11.60 BSC.
BODY SIZE
E
8.00 BSC.
BODY SIZE
7.20 BSC.
BALL FOOTPRINT
12
R
MD
ME
BALL FOOTPRINT
ec
8.80 BSC.
E1
ot
N
φb
0.33
ROW MATRIX SIZE D DIRECTION
10
ROW MATRIX SIZE E DIRECTION
84
TOTAL BALL COUNT
---
0.43
BALL DIAMETER
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
N
e
(A2-A9, B10-L10,
M2-M9, B1-L1)
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4.
DEPOPULATED SOLDER BALLS
e REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
D
D1
NOTE
NOTES:
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3339 \ 16-038.25b
Note:
BSC is an ANSI standard for Basic Space Centering.
4.3
MCP Look-ahead Connection Diagram
Figure 4.3 on page 8 shows a migration path from the S29WS-N to higher densities and the option to include additional die within a
single package. Spansion Inc. provides this standard look-ahead connection diagram that supports
NOR Flash and SRAM densities up to 4 Gigabits
NOR Flash and pSRAM densities up to 4 Gigabits
NOR Flash and pSRAM and data storage densities up to 4 Gigabits
Document Number: 002-01825 Rev. *B
Page 7 of 79
S29WS256N
S29WS128N
The following multi-chip package (MCP) data sheet(s) are based on the S29WS-N. Refer to these documents for input/output
descriptions for each product:
Publication Number S71WS256_512NC0.
The physical package outline may vary between connection diagrams and densities. The connection diagram for any MCP,
however, is a subset of the pinout in Figure 4.3.
In some cases, outrigger balls may exist in locations outside the grid shown. These outrigger balls are reserved; do not connect
them to any other signal.
For further information about the MCP look-ahead pinout, refer to the Design-In Scalable Wireless Solutions with Spansion Products
application note, available on the web or through a Spansion sales office.
Figure 4.3 MCP Look-ahead Diagram
B2
NC
NC
D
B1
A9
ew
NC
C3
C4
C5
AVD#
VSSds
CLK
CE#f2
D2
D3
D4
D5
WP#
A7
LB#s
E3
E4
A6
UB#s
C7
NC
B9
B10
NC
NC
C9
D6
D7
D8
D9
WE#
A8
A11
CE1#ds
E5
E6
E7
E8
E9
RESET#f
CE2s1
A19
A12
A15
F3
F4
F5
F6
F7
F8
F9
A18
RDY
A20
A9
A13
A21
ec
A2
G3
G4
G5
G6
G7
G8
G9
A1
A4
A17
CE1#s2
A23
A10
A14
A22
H3
H4
H5
H6
H7
H8
H9
A0
VSS
DQ1
VCCs2
CE2s2
DQ6
A24
A16
J2
J3
J4
J5
J6
J7
J8
J2
CE#f1
OE#
DQ9
DQ3
DQ4
DQ13
DQ15
CREs
K2
K3
K4
K5
K6
K7
K8
K9
VCCs1
DQ12
DQ7
VSS
L8
L9
R
G2
ot
H2
Shared
or NC (not connected)
Data-storage Only
C8
A5
F2
A10
NC
VCCds RESET#ds CLKds RY/BY#ds
d
WP/ACC
om
m
en
E2
C6
Legend:
fo
C2
A3
N
rN
A2
NC
de
A1
es
ig
n
96-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
Flash Shared Only
1st Flash Only
2nd Flash Only
1st RAM Only
2nd RAM Only
CE1#s1
DQ0
DQ10
VCCf
L2
L4
L4
L5
L6
L7
VCCnds
DQ8
DQ2
DQ11
A25
DQ5
RAM Shared Only
DoC Only
DQ14
LOCK
or WP#/ACCds
M2
M3
M4
M5
M6
M7
M8
M9
A27
A26
VSSnds
VCCf
CE2#ds
VCCQs1
NC
or VCCQds
DNU
NC or ds
N1
N2
N9
N10
NC
NC
NC
NC
P1
P2
P9
P10
NC
NC
NC
NC
Document Number: 002-01825 Rev. *B
Page 8 of 79
S29WS256N
S29WS128N
5.
Additional Resources
Visit www.spansion.com to obtain the following related documents:
Application Notes
Using the Operation Status Bits in AMD Devices
Understanding Burst Mode Flash Memory Devices
Simultaneous Read/Write vs. Erase Suspend/Resume
MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read
Design-In Scalable Wireless Solutions with Spansion Products
Common Flash Interface Version 1.4 Vendor Specific Extensions
ig
n
Specification Bulletins
es
Contact your local sales office for details.
Drivers and Software Support
D
Spansion low-level drivers
ew
Enhanced Flash drivers
rN
Flash file system
CAD Modeling Support
fo
VHDL and Verilog
d
IBIS
de
ORCAD
om
m
en
Technical Support
Contact your local sales office or contact Spansion Inc. directly for additional technical support:
Spansion Inc. Locations
N
ot
R
915 DeGuigne Drive, P.O. Box 3453
Sunnyvale, CA 94088-3453, USA
Telephone: 408-962-2500 or
1-866-SPANSION
ec
US: (408) 749-5703
Japan (03) 5322-3324
Spansion Japan Limited
Cube-Kawasaki 9F/10F,
1-14 Nisshin-cho, Kawasaki-ku, Kawasaki-shi,
Kanagawa, 210-0024, Japan
Phone : 044-223-1700
Document Number: 002-01825 Rev. *B
Page 9 of 79
S29WS256N
S29WS128N
6.
Product Overview
The S29WS-N family consists of 256, 128 Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for
today’s wireless designs that demand a large storage array, rich functionality, and low power consumption.
These devices are organized in 16 or 8 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear
read (8-, 16-, or 32-word aligned group) with or without wrap around. These products also offer single word programming or a 32word buffer for programming with program/erase and suspend functionality. Additional features include:
Advanced Sector Protection methods for protecting sectors as required
256 words of Secured Silicon area for storing customer and factory secured information. The Secured Silicon Sector is One Time
Programmable.
6.1
Memory Map
ig
n
The S29WS256/128N Mbit devices consist of 16 banks organized as shown in Table –Table .
Sector/
Sector Range
Address Range
SA000
000000h–003FFFh
SA001
004000h–007FFFh
32
0
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
SA004 to SA018
010000h–01FFFFh to 0F0000h–0FFFFFh
128
2 MB
16
128
1
SA019 to SA034
100000h–10FFFFh to 1F0000h–1FFFFFh
2 MB
16
128
2
SA035 to SA050
200000h–20FFFFh to 2F0000h–2FFFFFh
2 MB
16
128
3
SA051 to SA066
300000h–30FFFFh to 3F0000h–3FFFFFh
2 MB
16
128
4
SA067 to SA082
2 MB
16
128
5
SA083 to SA098
500000h–50FFFFh to 5F0000h–5FFFFFh
2 MB
16
128
6
SA099 to SA114
600000h–60FFFFh to 6F0000h–6FFFFFh
2 MB
16
128
7
SA115 to SA130
700000h–70FFFFh to 7F0000h–7FFFFFh
2 MB
16
128
8
SA131 to SA146
800000h–80FFFFh to 8F0000h–8FFFFFh
2 MB
16
128
9
SA147 to SA162
2 MB
16
128
10
SA163 to SA178
2 MB
16
128
11
SA179 to SA194
B00000h–B0FFFFh to BF0000h–BFFFFFh
2 MB
16
128
12
SA195 to SA210
C00000h–C0FFFFh to CF0000h–CFFFFFh
2 MB
16
128
13
SA211 to SA226
D00000h–D0FFFFh to DF0000h–DFFFFFh
2 MB
16
128
14
SA227 to SA242
E00000h–E0FFFFh to EF0000h–EFFFFFh
15
128
SA243 to SA257
F00000h–F0FFFFh to FE0000h–FEFFFFh
SA258
FF0000h–FF3FFFh
SA259
FF4000h–FF7FFFh
2 MB
Contains four smaller
sectors at bottom of
addressable memory.
de
om
m
en
ec
R
ot
15
4
Notes
d
15
N
2 MB
D
Bank
ew
4
Sector
Size (KB)
rN
Sector
Count
fo
Bank
Size
es
S29WS256N Sector & Memory Address Map
400000h–40FFFFh to 4F0000h–4FFFFFh
All 128 KB sectors.
Pattern for sector address
range is xx0000h–xxFFFFh.
(See Note)
900000h–90FFFFh to 9F0000h–9FFFFFh
A00000h–A0FFFFh to AF0000h–AFFFFFh
32
SA260
FF8000h–FFBFFFh
SA261
FFC000h–FFFFFFh
Contains four smaller
sectors at top of
addressable memory.
Note:
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA017) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
Document Number: 002-01825 Rev. *B
Page 10 of 79
S29WS256N
S29WS128N
S29WS128N Sector & Memory Address Map
Bank
Size
Sector
Count
Sector
Size (KB)
Sector/
Sector Range
Bank
Address Range
32
SA000
000000h–003FFFh
32
SA001
004000h–007FFFh
Notes
Contains four smaller
sectors at bottom of
addressable memory.
0
32
1 MB
7
128
8
128
1
SA002
008000h–00BFFFh
SA003
00C000h–00FFFFh
SA004 to SA010
010000h–01FFFFh to 070000h–07FFFFh
SA011 to SA018
080000h–08FFFFh to 0F0000h–0FFFFFh
1 MB
8
128
2
SA019 to SA026
100000h–10FFFFh to 170000h–17FFFFh
1 MB
8
128
3
SA027 to SA034
180000h–18FFFFh to 1F0000h–1FFFFFh
1 MB
8
128
4
SA035 to SA042
200000h–20FFFFh to 270000h–27FFFFh
1 MB
8
128
5
SA043 to SA050
280000h–28FFFFh to 2F0000h–2FFFFFh
1 MB
8
128
6
SA051 to SA058
300000h–30FFFFh to 370000h–37FFFFh
1 MB
8
128
7
SA059 to SA066
380000h–38FFFFh to 3F0000h–3FFFFFh
8
128
8
SA067 to SA074
400000h–40FFFFh to 470000h–47FFFFh
1 MB
8
128
9
SA075 to SA082
480000h–48FFFFh to 4F0000h–4FFFFFh
ew
D
1 MB
8
128
10
SA083 to SA090
500000h–50FFFFh to 570000h–57FFFFh
1 MB
8
128
11
SA091 to SA098
580000h–58FFFFh to 5F0000h–5FFFFFh
rN
1 MB
8
128
12
SA099 to SA106
600000h–60FFFFh to 670000h–67FFFFh
1 MB
8
128
13
SA107 to SA114
680000h–68FFFFh to 6F0000h–6FFFFFh
8
128
14
7
128
SA130
7F0000h–7F3FFFh
SA131
15
d
700000h–70FFFFh to 770000h–77FFFFh
780000h–78FFFFh to 7E0000h–7EFFFFh
7F4000h–7F7FFFh
om
m
en
32
SA115 to SA122
SA123 to SA129
de
32
1 MB
fo
1 MB
1 MB
4
All 128 KB sectors.
Pattern for sector address
range is xx0000h–xxFFFFh.
(See Note)
es
32
1 MB
ig
n
4
32
SA132
7F8000h–7FBFFFh
32
SA133
7FC000h–7FFFFFh
Contains four smaller
sectors at top of
addressable memory.
N
ot
R
ec
Note:
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
Document Number: 002-01825 Rev. *B
Page 11 of 79
S29WS256N
S29WS128N
7.
Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash
devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command
registers (see Table on page 72 and Table on page 46). The command register itself does not occupy any addressable memory
location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute
the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the
function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an
unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
7.1
Device Operation Table
CE#
OE#
WE#
Addresses
DQ15–0
L
L
H
Addr In
Data Out
Data Out
Asynchronous Read - Addresses Latched
RESET#
CLK
H
X
ew
Operation
D
Device Operations
es
ig
n
The device must be setup appropriately for each operation. Table describes the required state of each control pin for any particular
operation.
AVD#
L
L
H
Addr In
H
X
L
Asynchronous Write
L
H
L
Addr In
I/O
X
L
L
H
L
Addr In
I/O
H
X
X
X
X
X
Load Starting Burst Address
Advance Burst to next address with appropriate
Data presented on the Data Bus
X
X
L
X
X
L
X
H
Addr In
X
H
L
L
H
X
Burst
Data Out
H
H
H
X
H
X
HIGH Z
H
X
ec
Terminate current Burst read cycle
H
HIGH Z
X
om
m
en
Burst Read Operations (Synchronous)
HIGH Z
X
fo
H
Hardware Reset
de
Standby (CE#)
H
d
Synchronous Write
rN
Asynchronous Read - Addresses Steady State
X
X
H
X
HIGH Z
L
Terminate current Burst read cycle and start new
Burst read cycle
L
X
H
Addr In
I/O
H
X
X
ot
R
Terminate current Burst read cycle via RESET#
N
Legend:
L= Logic 0, H = Logic 1, X = Don’t Care, I/O = Input/Output.
7.2
Asynchronous Read
All memories require access time to output array data. In an asynchronous read operation, data is read from one memory location at
a time. Addresses are presented to the device in random order, and the propagation delay through the device causes the data on its
outputs to arrive asynchronously with the address on its inputs.
The device defaults to reading array data asynchronously after device power-up or hardware reset. To read data from the memory
array, the system must first assert a valid address on Amax–A0, while driving AVD# and CE# to VIL. WE# must remain at VIH. The
rising edge of AVD# latches the address. The OE# signal must be driven to VIL, once AVD# has been driven to VIH. Data is output
on A/DQ15-A/DQ0 pins after the access time (tOE) has elapsed from the falling edge of OE#.
Document Number: 002-01825 Rev. *B
Page 12 of 79
S29WS256N
S29WS128N
7.3
Page Read Mode
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides
faster read access speed for random locations within a page. The random or initial page access is tACC or tCE and subsequent page
read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is
deasserted (= VIH), the reassertion of CE# for subsequent access has access time of tACC or tCE. Here again, CE# selects the
device and OE# is the output control and should be used to gate data to the output inputs if the device is selected. Fast page mode
accesses are obtained by keeping Amax – A2 constant and changing A1 – A0 to select the specific word within that page.
Address bits Amax – A2 select a 4-word page, and address bits A1 – A0 select a specific word within that page. This is an
asynchronous operation with the microprocessor supplying the specific word location. See Table for details on selecting specific
words.
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank
is ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
ew
D
es
ig
n
Reads from the memory array may be performed in conjunction with the Erase Suspend and Program Suspend features. After the
device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system
can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read
timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. After the
device accepts a Program Suspend command, the corresponding bank enters the program-suspend-read mode, after which the
system can read data from any non-program-suspended sector within the same bank.
fo
rN
The de-assertion and re-assertion of AVD# creates a new tACC. It does not matter if AVD stays low or toggles once. However, the
address input must always be valid and stable if AVD# is low during the page read. The user must keep AVD# low during and
between page reads on address A(1:0).
de
d
During Simultaneous Operation (SO), the user needs to de-assert and re- assert either /CE# or /AVD# when performing data polling
to SO read.
om
m
en
Word Selection within a Page
Word
A1
Word 0
Word 1
Word 2
0
0
1
1
0
1
1
N
ot
R
ec
Word 3
A0
0
Document Number: 002-01825 Rev. *B
Page 13 of 79
S29WS256N
S29WS128N
7.4
Synchronous (Burst) Read Mode & Configuration Register
When a series of adjacent addresses needs to be read from the device (in order from lowest to highest address), the synchronous
(or burst read) mode can be used to significantly reduce the overall time needed for the device to output array data. Asynchronous
read mode can be automatically enabled for burst mode by setting the configuration register to enter Synchronous mode. After an
initial access time required for the data from the first address location, subsequent data is output synchronized to a clock input
provided by the system.
The device offers both continuous and linear methods of burst read operation, which are discussed in Continuous Burst Read Mode
on page 17 and 8-, 16-, 32-Word Linear Burst Read with Wrap Around on page 17, and 8-, 16-, 32-Word Linear Burst without Wrap
Around on page 17.
es
ig
n
Since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set to
enable the burst read mode. Other Configuration Register settings include the number of wait states to insert before the initial word
(tIACC) of each burst access, the burst mode in which to operate, and when RDY indicates data is ready to be read. Prior to entering
the burst mode, the system should first determine the configuration register settings (and read the current register settings if desired
via the Read Configuration Register command sequence), and then write the configuration register command sequence. See
Configuration Register on page 18, and Table on page 72, for further details.
ew
D
Figure 7.1 Synchronous/Asynchronous State Diagram
fo
rN
Power-up/
Hardware Reset
Set Burst Mode
Configuration Register
Command for
Synchronous Mode
(CR15 = 0)
Set Burst Mode
Configuration Register
Command for
Asynchronous Mode
(CR15 = 1)
N
ot
R
ec
om
m
en
de
d
Asynchronous Read
Mode Only
Synchronous Read
Mode Only
The device outputs the initial word subject to the following operational conditions:
tIACC specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device
outputs.
configuration register setting CR13–CR11: the total number of clock cycles (wait states) that occur before valid data appears on
the device outputs. The effect is that tIACC is lengthened.
The device outputs subsequent words tBACC after the active edge of each successive clock cycle, which also increments the internal
address counter. The device outputs burst data at this rate subject to the following operational conditions:
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-by-four address incurs the least number
of additional wait states that occur after the initial word. The number of additional wait states required increases for burst operations
in which the starting address is one, two, or three locations above the divisible-by-four address (i.e., where A[1:0] is 01, 10, or 11).
boundary crossing: There is a boundary at every 128 words due to the internal architecture of the device. One additional wait state
must be inserted when crossing this boundary if the memory bus is operating at a high clock frequency. Please refer to the tables
below.
Document Number: 002-01825 Rev. *B
Page 14 of 79
S29WS256N
S29WS128N
clock frequency: the speed at which the device is expected to burst data. Higher speeds require additional wait states after the
initial word for proper operation.
In all cases, with or without latency, the RDY output indicates when the next data is available to be read.
Table on page 15 to Table on page 16 reflect wait states required for S29WS256/128N devices. Refer to the table (CR11 - CR14)
and timing diagrams for more details.
Address Latency (S29WS256N)
Wait States
Cycle
0
x ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
x ws
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
x ws
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
x ws
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
D2
D3
D4
D5
D6
D7
D8
D5
ig
n
Word
D0
D1
Cycle
1
5, 6, 7 ws
D1
D2
D3
1 ws
D4
2
5, 6, 7 ws
D2
D3
1 ws
1 ws
D4
3
5, 6, 7 ws
D3
1 ws
1 ws
1 ws
D4
D6
D7
D8
D5
D6
D7
D8
D5
D6
D7
D8
fo
Address/Boundary Crossing Latency (S29WS256N @ 80MHz)
D
5, 6, 7 ws
ew
Wait States
0
rN
Word
es
Address Latency (S29WS128N)
D0
D1
D2
Cycle
1
7 ws
D1
D2
D3
2
7 ws
D2
D3
3
7 ws
D3
1 ws
D3
d
7 ws
1 ws
1 ws
D4
D5
D6
1 ws
1 ws
D4
D5
D6
de
Wait States
0
1 ws
om
m
en
Word
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
6 ws
D0
1
6 ws
D1
2
6 ws
3
6 ws
Cycle
D1
D2
D3
1 ws
D4
D5
D6
R
Wait States
0
D3
1 ws
1 ws
D4
D5
D6
D7
D2
ot
Word
ec
Address/Boundary Crossing Latency (S29WS256N @ 66 MHz)
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D3
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
N
D2
Address/Boundary Crossing Latency (S29WS256N @ 54MHz)
Word
Wait States
Cycle
0
5 ws
D0
D1
D2
D3
D4
D5
D6
D7
1
5 ws
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
5 ws
D2
D3
1 ws
1 ws
D4
D5
D6
D7
D8
3
5 ws
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
D8
Document Number: 002-01825 Rev. *B
Page 15 of 79
S29WS256N
S29WS128N
Address/Boundary Crossing Latency (S29WS128N)
Word
Wait States
0
5, 6, 7 ws
D0
D1
D2
D3
Cycle
1 ws
D4
D5
D6
D7
1
5, 6, 7 ws
D1
D2
D3
1 ws
1 ws
D4
D5
D6
D7
2
5, 6, 7 ws
D2
D3
1 ws
1 ws
1 ws
D4
D5
D6
D7
3
5, 6, 7 ws
D3
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
Figure 7.2 Synchronous Read
Unlock Cycle 1
Unlock Cycle 2
es
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
ig
n
Note: Setup Configuration Register parameters
rN
ew
D
Write Set Configuration Register
Command and Settings:
Address 555h, Data D0h
Address X00h, Data CR
fo
Load Initial Address
Address = RA
Read Initial Data
RD = DQ[15:0]
CR13-CR11 sets initial access time
(from address latched to
valid data) from 2 to 7 clock cycles
RD = Read Data
Refer to the Latency tables.
Read Next Data
RD = DQ[15:0]
ot
N
RA = Read Address
Wait X Clocks:
Additional Latency Due to Starting
Address, Clock Frequency, and
Boundary Crossing
R
ec
om
m
en
de
d
Wait tIACC +
Programmable Wait State Setting
Command Cycle
CR = Configuration Register Bits CR15-CR0
Delay X Clocks
Yes
Crossing
Boundary?
No
End of Data?
Yes
Completed
Document Number: 002-01825 Rev. *B
Page 16 of 79
S29WS256N
S29WS128N
7.4.1
Continuous Burst Read Mode
In the continuous burst read mode, the device outputs sequential burst data from the starting address given and then wrap around to
address 000000h when it reaches the highest addressable memory location. The burst read mode continues until the system drives
CE# high, or RESET= VIL. Continuous burst mode can also be aborted by asserting AVD# low and providing a new address to the
device.
If the address being read crosses a 128-word line boundary (as mentioned above) and the subsequent word line is not being
programmed or erased, additional latency cycles are required as reflected by the configuration register table (Table on page 18).
If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status
information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read
operation using a new address and AVD# pulse.
7.4.2
8-, 16-, 32-Word Linear Burst Read with Wrap Around
es
ig
n
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from consecutive addresses that are
determined by the group within which the starting address falls. The groups are sized according to the number of words read in a
single burst sequence for a given mode (see Table on page 17).
ew
D
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read would be 38-3Fh, and the burst
sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the device outputs all words in that burst address group until all word are
read, regardless of where the starting address occurs in the address group, and then terminates the burst read.
rN
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address provided to the
device, then wrap back to the first address in the selected address group.
d
fo
Note that in this mode the address pointer does not cross the boundary that occurs every 128 words; thus, no additional wait states
are inserted due to boundary crossing.
Group Size
8 words
16-word
16 words
32-word
32 words
0-7h, 8-Fh, 10-17h,...
0-Fh, 10-1Fh, 20-2Fh,...
00-1Fh, 20-3Fh, 40-5Fh,...
8-, 16-, 32-Word Linear Burst without Wrap Around
ec
7.4.3
Group Address Ranges
om
m
en
Mode
8-word
de
Burst Address Groups
ot
R
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-word burst executes up to the maximum
memory address of the selected number of words. The burst stops after 8, 16, or 32 addresses and does not wrap around to the first
address of the selected group.
N
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read would be 39-40h, and the burst
sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap around is not enabled. The next address to be read requires a new address
and AVD# pulse. Note that in this burst read mode, the address pointer may cross the boundary that occurs every 128 words, which
will incur the additional boundary crossing wait state.
Document Number: 002-01825 Rev. *B
Page 17 of 79
S29WS256N
S29WS128N
7.4.4
Configuration Register
The configuration register sets various operational parameters associated with burst mode. Upon power-up or hardware reset, the
device defaults to the asynchronous read mode, and the configuration register settings are in their default state. The host system
should determine the proper settings for the entire configuration register, and then execute the Set Configuration Register command
sequence, before attempting burst operations. The configuration register is not reset after deasserting CE#. The Configuration
Register can also be read using a command sequence (see Table on page 72). The following list describes the register settings.
Configuration Register
1 = S29WS256N at 6 or 7 Wait State setting
0 = All others
54 MHz
66 Mhz
80 MHz
0
1
1
1
0
0
1
0
1
S29WS128N
CR13
S29WS256N
S29WS128N
CR12
Programmable
Wait State
S29WS256N
S29WS128N
CR11
RDY Polarity
CR9
Reserved
0 = RDY signal active low
1 = RDY signal active high (default)
CR5
Reserved
CR4
Reserved
CR3
Burst Wrap
Around
CR2
CR1
om
m
en
Reserved
1 = default
1 = default
ec
Reserved
CR6
R
CR7
ot
RDY
1 = default
0 = RDY active one clock cycle before data
1 = RDY active with data (default)
When CR13-CR11 are set to 000, RDY is active with data
regardless of CR8 setting.
N
CR8
de
d
CR10
011 = Data valid on 5th active CLK edge after addresses
latched
100 = Data valid on 6th active CLK edge after addresses
latched
101 = Data valid on 7th active CLK edge after addresses
latched (default)
110 = Reserved
111 = Reserved
Inserts wait states before initial data is available. Setting
greater number of wait states before initial data reduces
latency after initial data.
(Notes 1, 2)
fo
S29WS256N
ig
n
Reserved
es
CR14
D
CR15
Settings (Binary)
0 = Synchronous Read (Burst Mode) Enabled
1 = Asynchronous Read Mode (default) Enabled
ew
Function
Set Device Read
Mode
rN
CR Bit
Burst Length
CR0
0 = default
0 = default
0 = No Wrap Around Burst
1 = Wrap Around Burst (default)
Ignored if in continuous mode
000 = Continuous (default)
010 = 8-Word Linear Burst
011 = 16-Word Linear Burst
100 = 32-Word Linear Burst
(All other bit settings are reserved)
Notes:
1. Refer to Table on page 15 - Table on page 16 for wait states requirements.
2. Refer to Synchronous/Burst Read on page 55 timing diagrams
3. Configuration Register is in the default state upon power-up or hardware reset.
Reading the Configuration Table
The configuration register can be read with a four-cycle command sequence. See Table on page 72 for sequence details. A
software reset command is required after reading or setting the configuration register to set the device into the correct state.
7.5
Autoselect
The Autoselect is used for manufacturer ID, Device identification, and sector protection information. This mode is primarily intended
for programming equipment to automatically match a device with its corresponding programming algorithm. The Autoselect codes
Document Number: 002-01825 Rev. *B
Page 18 of 79
S29WS256N
S29WS128N
can also be accessed in-system. When verifying sector protection, the sector address must appear on the appropriate highest order
address bits (see Table ). The remaining address bits are don't care. The most significant four bits of the address during the third
write cycle selects the bank from which the Autoselect codes are read by the host. All other banks can be accessed normally for data
read without exiting the Autoselect mode.
To access the Autoselect codes, the host system must issue the Autoselect command.
The Autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read
mode.
The Autoselect command may not be written while the device is actively programming or erasing. Autoselect does not support
simultaneous operations or burst mode.
The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in
Erase Suspend).
ig
n
See Table on page 72 for command sequence details.
es
Autoselect Addresses
Description
Address
Read Data
Manufacturer ID
(BA) + 00h
Device ID, Word 1
(BA) + 01h
227Eh
Device ID, Word 2
(BA) + 0Eh
2230 (WS256N)
2231 (WS128N)
Device ID, Word 3
(BA) + 0Fh
2200
Indicator Bits
(See Note)
(BA) + 03h
DQ15 - DQ8 = Reserved
DQ7 (Factory Lock Bit): 1 = Locked, 0 = Not Locked
DQ6 (Customer Lock Bit): 1 = Locked, 0 = Not Locked
DQ5 (Handshake Bit): 1 = Reserved, 0 = Standard Handshake
DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot
Sectors. 01, 10, 11 = Reserved
DQ2 = Reserved
DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option),
0 = Locked (default)
DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed,
0 = Erase disabled
Sector Block Lock/
Unlock
(SA) + 02h
0001h = Locked, 0000h = Unlocked
ec
om
m
en
de
d
fo
rN
ew
D
0001h
N
ot
R
Note:
For WS128N and WS064, DQ1 and DQ0 are reserved.
Document Number: 002-01825 Rev. *B
Page 19 of 79
S29WS256N
S29WS128N
Software Functions and Sample Code
Autoselect Entry
(LLD Function = lld_AutoselectEntryCmd)
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle 1
Write
Unlock Cycle 2
Write
BAxAAAh
BAx555h
0x00AAh
BAx555h
BAx2AAh
Autoselect Command
Write
0x0055h
BAxAAAh
BAx555h
0x0090h
Autoselect Exit
(LLD Function = lld_AutoselectExitCmd)
Operation
Byte Address
Word Address
Data
Write
base + XXXh
base + XXXh
0x00F0h
ig
n
Cycle
Unlock Cycle 1
es
Notes:
1. Any offset within the device works.
D
2. BA = Bank Address. The bank address is required.
ew
3. base = base address.
fo
rN
The following is a C source code example of using the autoselect function to read the manufacturer ID. Refer to the Spansion Low
Level Driver User’s Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory
software development guidelines.
/* Here is an example of Autoselect mode (getting manufacturer ID) */
de
d
/* Define UINT16 example: typedef unsigned short UINT16; */
om
m
en
UINT16 manuf_id;
/* Auto Select Entry */
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA; /* write unlock cycle 1 */
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055; /* write unlock cycle 2 */
R
ec
*( (UINT16 *)bank_addr + 0x555 ) = 0x0090; /* write autoselect command */
N
ot
/* multiple reads can be performed after entry */
manuf_id = *( (UINT16 *)bank_addr + 0x000 ); /* read manuf. id */
/*
Autoselect exit */
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */
Document Number: 002-01825 Rev. *B
Page 20 of 79
S29WS256N
S29WS128N
7.6
Program/Erase Operations
These devices are capable of several modes of programming and or erase operations which are described in detail in the following
sections. However, prior to any programming and or erase operation, devices must be setup appropriately as outlined in the
configuration register (Table on page 18).
For any synchronous write operations, including writing command sequences, the system must drive AVD# and CE# to VIL, and
OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH when writing commands or
programming data.
During asynchronous write operations, addresses are latched on the rising edge of AVD# while data is latched on the 1st rising edge
of WE# or CE#, whichever comes first.
Note the following:
When the Embedded Program algorithm is complete, the device returns to the read mode.
ig
n
The system can determine the status of the program operation by using DQ7 or DQ6. Refer to Write Operation Status on page 34
for information on these status bits.
D
es
A “0” cannot be programmed back to a “1.” Attempting to do so causes the device to set DQ5 = 1 (halting any further operation
and requiring a reset command). A succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.”
ew
Any commands written to the device during the Embedded Program Algorithm are ignored except the Program Suspend
command.
rN
Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.
fo
A hardware reset immediately terminates the program operation and the program command sequence should be reinitiated once
the device has returned to the read mode, to ensure data integrity.
Single Word Programming
om
m
en
7.6.1
de
d
Programming is allowed in any sequence and across sector boundaries for single word programming operation.
Single word programming mode is the simplest method of programming. In this mode, four Flash command write cycles are used to
program an individual Flash address. The data for this programming operation could be 8-, 16- or 32-bits wide. While this method is
supported by all Spansion devices, in general it is not recommended for devices that support Write Buffer Programming. See Table
on page 72 for the required bus cycles and Figure 7.3 on page 22 for the flowchart.
R
ec
When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched.
The system can determine the status of the program operation by using DQ7 or DQ6. Refer to Write Operation Status on page 34
for information on these status bits.
ot
During programming, any command (except the Suspend Program command) is ignored.
N
The Secured Silicon Sector, Autoselect, and CFI functions are unavailable when a program operation is in progress.
A hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the
device has returned to the read mode, to ensure data integrity.
Document Number: 002-01825 Rev. *B
Page 21 of 79
S29WS256N
S29WS128N
Figure 7.3 Single Word Program
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Program Command:
Address 555h, Data A0h
Setup Command
Program Address (PA),
Program Data (PD)
es
ig
n
Program Data to Address:
PA, PD
rN
ew
(see Write Operation Status
flowchart)
D
Perform Polling Algorithm
Yes
fo
Polling Status
= Busy?
om
m
en
Yes
de
d
No
No
Error condition
(Exceeded Timing Limits)
FAIL. Issue reset command
to return to read array mode.
N
ot
R
ec
PASS. Device is in
read mode.
Polling Status
= Done?
Document Number: 002-01825 Rev. *B
Page 22 of 79
S29WS256N
S29WS128N
Software Function and Sample Code
Single Word Program
(LLD Function = lld_ProgramCmd)
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle 1
Write
Unlock Cycle 2
Write
Base + AAAh
Base + 555h
00AAh
Base + 554h
Base + 2AAh
Program Setup
0055h
Write
Base + AAAh
Base + 555h
00A0h
Program
Write
Word Address
Word Address
Data Word
Note:
Base = Base Address.
*/
es
/* Example: Program Command
ig
n
The following is a C source code example of using the single word program function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00A0;
/* write program setup command
*/
*( (UINT16 *)pa )
/* write data to be programmed
ew
= data;
D
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
*/
Write Buffer Programming
d
7.6.2
fo
rN
/* Poll for program completion */
ec
om
m
en
de
Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster
effective word programming time than the standard “word” programming algorithms. The Write Buffer Programming command
sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load
command written at the Sector Address in which programming occurs. At this point, the system writes the number of “word locations
minus 1” that are loaded into the page buffer at the Sector Address in which programming occurs. This tells the device how many
write buffer addresses are loaded with data and therefore when to expect the “Program Buffer to Flash” confirm command. The
number of locations to program cannot exceed the size of the write buffer or the operation aborts. (Number loaded = the number of
locations to program minus 1. For example, if the system programs 6 address locations, then 05h should be written to the device.)
R
The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed,
and selects the “write-buffer-page” address. All subsequent address/data pairs must fall within the elected-write-buffer-page.
ot
The “write-buffer-page” is selected by using the addresses AMAX - A5.
N
The “write-buffer-page” addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer
Programming cannot be performed across multiple “write-buffer-pages.” This also means that Write Buffer Programming cannot be
performed across multiple sectors. If the system attempts to load programming data outside of the selected “write-buffer-page”, the
operation ABORTs.)
After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer.
Note that if a Write Buffer address location is loaded multiple times, the “address/data pair” counter is decremented for every data
load operation. Also, the last data loaded at a location before the “Program Buffer to Flash” confirm command is programmed into
the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The
counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of
write buffer locations have been loaded, the system must then write the “Program Buffer to Flash” command at the Sector Address.
Any other address/data write combinations abort the Write Buffer Programming operation. The device goes “busy.” The Data Bar
polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to
store an address in memory because the system can load the last address location, issue the program confirm command at the last
loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to
determine the device status during Write Buffer Programming.
The write-buffer “embedded” programming operation can be suspended using the standard suspend/resume commands. Upon
successful completion of the Write Buffer Programming operation, the device returns to READ mode.
Document Number: 002-01825 Rev. *B
Page 23 of 79
S29WS256N
S29WS128N
The Write Buffer Programming Sequence is ABORTED under any of the following conditions:
Load a value that is greater than the page buffer size during the “Number of Locations to Program” step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
Write an Address/Data pair to a different write-buffer-page than the one selected by the “Starting Address” during the “write buffer
data loading” stage of the operation.
Write data other than the “Confirm Command” after the specified number of “data load” cycles.
The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the “last address location loaded”), DQ6 = TOGGLE, DQ5 = 0.
This indicates that the Write Buffer Programming Operation was ABORTED. A “Write-to-Buffer-Abort reset” command sequence is
required when using the write buffer Programming features in Unlock Bypass mode. Note that the Secured Silicon sector,
autoselect, and CFI functions are unavailable when a program operation is in progress.
ig
n
Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling
multiple write buffer programming operations on the same write buffer address range without intervening erases.
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer
programming is approximately eight times faster than programming one word at a time.
Document Number: 002-01825 Rev. *B
Page 24 of 79
S29WS256N
S29WS128N
Software Functions and Sample Code
Write Buffer Program
(LLD Functions Used = lld_WriteToBufferCmd, lld_ProgramBufferToFlashCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
00AAh
1
Unlock
Write
Base + AAAh
Base + 555h
2
Unlock
Write
Base + 554h
Base + 2AAh
3
Write Buffer Load Command
Write
Program Address
0025h
4
Write Word Count
Write
Program Address
Word Count (N–1)h
5 to 36
Load Buffer Word N
Write
Program Address, Word N
Word N
Last
Write Buffer to Flash
Write
Sector Address
0029h
0055h
Number of words (N) loaded into the write buffer can be from 1 to 32 words.
ig
n
Notes:
1. Base = Base Address.
2. Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37.
D
es
3. For maximum efficiency, it is recommended that the write buffer be loaded with the highest number of words (N words) possible.
rN
ew
The following is a C source code example of using the write buffer program function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Write Buffer Programming Command
*/
fo
/* NOTES: Write buffer programming limited to 16 words. */
All addresses to be written to the flash in
/*
one operation must be within the same flash
/*
page. A flash page begins at addresses
de
evenly divisible by 0x20.
UINT16 *src = source_of_data;
*/
/* address of source data
UINT16 *dst = destination_of_data;
*/
/* flash destination address
= words_to_program -1;
*/
/* word count (minus 1)
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
ec
UINT16 wc
*/
*/
om
m
en
/*
*/
d
/*
*( (UINT16 *)sector_address )
= 0x0025;
/* write write buffer load command */
*( (UINT16 *)sector_address )
= wc;
/* write word count (minus 1)
*/
R
loop:
src++;
N
dst++;
ot
*dst = *src; /* ALL dst MUST BE SAME PAGE */ /* write source data to destination */
/* increment destination pointer
*/
/* increment source pointer
*/
if (wc == 0) goto confirm
/* done when word count equals zero */
wc--;
/* decrement word count
*/
goto loop;
/* do it again
*/
confirm:
*( (UINT16 *)sector_address )
= 0x0029;
/* write confirm command
*/
/* poll for completion */
/* Example: Write Buffer Abort Reset */
*( (UINT16 *)addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)addr + 0x555 ) = 0x00F0;
/* write buffer abort reset
*/
Document Number: 002-01825 Rev. *B
Page 25 of 79
S29WS256N
S29WS128N
Figure 7.4 Write Buffer Programming Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Issue
Write Buffer Load Command:
Address 555h, Data 25h
wc = number of words – 1
es
ig
n
Load Word Count to Program
Program Data to Address:
SA = wc
Yes
Confirm command:
SA = 0x29h
ew
D
wc = 0?
rN
No
fo
Write Next Word,
Decrement wc:
PA data , wc = wc – 1
Perform Polling Algorithm
de
d
(see Write Operation Status
flowchart)
om
m
en
Yes
Wait 4 μs
(Recommended)
Write Buffer
Abort?
Polling Status
= Done?
FAIL. Issue reset command
to return to read array mode.
ot
R
ec
No
Yes
No
No
Error?
N
Yes
RESET. Issue Write Buffer
Abort Reset Command
Document Number: 002-01825 Rev. *B
PASS. Device is in
read mode.
Page 26 of 79
S29WS256N
S29WS128N
7.6.3
Sector Erase
The sector erase function erases one or more sectors in the memory array. (See Table on page 72, and Figure 7.5 on page 28.)
The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and
verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful sector erase, all locations within the
erased sector contain FFFFh. The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of no less than tSEA occurs. During the time-out period, additional
sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and
the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any
sector erase address and command following the exceeded time-out (tSEA) may or may not be accepted. Any command other than
Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to
determine if the sector erase timer has timed out (See DQ3: Sector Erase Timeout State Indicator on page 37 .) The time-out begins
from the rising edge of the final WE# pulse in the command sequence.
es
ig
n
When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note
that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can
determine the status of the erase operation by reading DQ7 or DQ6/DQ2 in the erasing bank. Refer to Write Operation Status
on page 34 for information on these status bits.
ew
D
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However,
note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should
be reinitiated once that bank has returned to reading array data, to ensure data integrity.
rN
Figure 7.5 on page 28 illustrates the algorithm for the erase operation. Refer to Erase and Programming Performance on page 71
for parameters and timing diagrams.
fo
Software Functions and Sample Code
d
Sector Erase
Unlock
2
Unlock
3
Setup Command
4
Unlock
Word Address
Data
Write
Base + AAAh
Base + 555h
00AAh
Write
Base + 554h
Base + 2AAh
0055h
Write
Base + AAAh
Base + 555h
0080h
Write
Base + AAAh
Base + 555h
00AAh
Operation
Byte Address
om
m
en
Description
1
Unlock
6
Sector Erase Command
Write
Base + 554h
Base + 2AAh
0055h
Write
Sector Address
Sector Address
0030h
R
5
ec
Cycle
de
(LLD Function = lld_SectorEraseCmd)
ot
Unlimited additional sectors may be selected for erase; command(s) must be written within tSEA.
N
The following is a C source code example of using the sector erase function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Sector Erase Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
/* write setup command
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write additional unlock cycle 2 */
*( (UINT16 *)sector_address )
/* write sector erase command
Document Number: 002-01825 Rev. *B
= 0x0030;
*/
Page 27 of 79
S29WS256N
S29WS128N
Figure 7.5 Sector Erase Operation
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write Sector Erase Cycles:
Address 555h, Data 80h
Address 555h, Data AAh
Address 2AAh, Data 55h
Sector Address, Data 30h
Command Cycle 1
Command Cycle 2
Command Cycle 3
Specify first sector for erasure
ig
n
Select
Additional
Sectors?
No
es
Yes
Write Additional
Sector Addresses
D
• Each additional cycle must be written within tSEA timeout
• Timeout resets after each additional cycle is written
Yes
Poll DQ3.
DQ3 = 1?
Last Sector
Selected?
No
• Commands other than Erase Suspend or selecting
additional sectors for erasure during timeout reset device
to reading array data
de
Wait 4 μs
(Recommended)
d
fo
Yes
• No limit on number of sectors
rN
No
ew
• The host system may monitor DQ3 or wait tSEA to ensure
acceptance of erase commands
om
m
en
Perform Write Operation
Status Algorithm
N
ot
R
ec
Yes
PASS. Device returns
to reading array.
Status may be obtained by reading DQ7, DQ6 and/or DQ2.
Done?
(see Figure 7.6)
No
DQ5 = 1?
No
Error condition (Exceeded Timing Limits)
Yes
FAIL. Write reset command
to return to reading array.
Notes:
1. See Table on page 72 for erase command sequence.
2. See DQ3: Sector Erase Timeout State Indicator on page 37 for information on the sector erase timeout.
Document Number: 002-01825 Rev. *B
Page 28 of 79
S29WS256N
S29WS128N
7.6.4
Chip Erase Command Sequence
Chip erase is a six-bus cycle operation as indicated by Table on page 72. These commands invoke the Embedded Erase algorithm,
which does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. After a successful chip erase, all locations of the chip
contain FFFFh. The system is not required to provide any controls or timings during these operations. The Appendix on page 72
shows the address and data requirements for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The
system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to Write Operation Status on page 34 for
information on these status bits.
Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the
erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array
data, to ensure data integrity.
ig
n
Software Functions and Sample Code
D
(LLD Function = lld_ChipEraseCmd)
es
Chip Erase
Description
Operation
Byte Address
Word Address
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
Write
Base + 554h
Setup Command
Write
Base + AAAh
4
Unlock
Write
Base + AAAh
5
Unlock
Write
Base + 554h
6
Chip Erase Command
Write
Base + AAAh
Base + 2AAh
0055h
Base + 555h
0080h
Base + 555h
00AAh
rN
Unlock
3
Base + 2AAh
0055h
Base + 555h
0010h
de
d
fo
2
ew
Cycle
om
m
en
The following is a C source code example of using the chip erase function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Chip Erase Command */
/* Note: Cannot be suspended
*/
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0080;
/* write setup command
*/
R
ec
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write additional unlock cycle 1 */
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write additional unlock cycle 2 */
*( (UINT16 *)base_addr + 0x000 ) = 0x0010;
/* write chip erase command
*/
N
ot
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
Document Number: 002-01825 Rev. *B
Page 29 of 79
S29WS256N
S29WS128N
7.6.5
Erase Suspend/Erase Resume Commands
When the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out
period and suspends the erase operation. The Erase Suspend command allows the system to interrupt a sector erase operation and
then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this
command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the
sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation.
When the Erase Suspend command is written after the tSEA time-out period has expired and during the sector erase operation, the
device requires a maximum of tESL (erase suspend latency) to suspend the erase operation. Additionaly, when an Erase Suspend
command is written during an active erase operation, status information is unavailable during the transition from the sector erase
operation to the erase suspended state.
es
ig
n
After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or
program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any
address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6, and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. Refer to Table on page 38 for information on these
status bits.
D
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can
determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation.
ew
In the erase-suspend-read mode, the system can also issue the Autoselect command sequence. Refer to Write Buffer Programming
on page 23 and the “Autoselect Command Sequence” section for details.
fo
rN
To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erasesuspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase
Suspend command can be written after the chip has resumed erasing.
de
d
Software Functions and Sample Code
Erase Suspend
Cycle
Operation
1
Write
om
m
en
(LLD Function = lld_EraseSuspendCmd)
Byte Address
Word Address
Data
Bank Address
Bank Address
00B0h
R
ec
The following is a C source code example of using the erase suspend function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Erase suspend command */
Erase Resume
/* write suspend command
*/
N
ot
*( (UINT16 *)bank_addr + 0x000 ) = 0x00B0;
(LLD Function = lld_EraseResumeCmd)
Cycle
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0030h
The following is a C source code example of using the erase resume function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Erase resume command */
*( (UINT16 *)bank_addr + 0x000 ) = 0x0030;
/* write resume command
*/
/* The flash needs adequate time in the resume state */
Document Number: 002-01825 Rev. *B
Page 30 of 79
S29WS256N
S29WS128N
7.6.6
Program Suspend/Program Resume Commands
The Program Suspend command allows the system to interrupt an embedded programming operation or a “Write to Buffer”
programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written
during a programming process, the device halts the programming operation within tPSL (program suspend latency) and updates the
status bits. Addresses are “don't-cares” when writing the Program Suspend command.
After the programming operation has been suspended, the system can read array data from any non-suspended sector. The
Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data
may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector
area, then user must use the proper command sequences to enter and exit this region.
ig
n
The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows
reading Autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the
Autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See Autoselect
on page 18 for more information.
es
After the Program Resume command is written, the device reverts to programming. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status
on page 34 for more information.
rN
ew
D
The system must write the Program Resume command (address bits are “don't care”) to exit the Program Suspend mode and
continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend
command can be written after the device has resumed programming.
Software Functions and Sample Code
fo
Program Suspend
Byte Address
1
Write
Bank Address
Word Address
de
Operation
Bank Address
Data
00B0h
om
m
en
Cycle
d
(LLD Function = lld_ProgramSuspendCmd)
The following is a C source code example of using the program suspend function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program suspend command */
/* write suspend command
*/
R
ec
*( (UINT16 *)base_addr + 0x000 ) = 0x00B0;
ot
Program Resume
(LLD Function = lld_ProgramResumeCmd)
Operation
Byte Address
Word Address
Data
1
Write
Bank Address
Bank Address
0030h
N
Cycle
The following is a C source code example of using the program resume function. Refer to the Spansion Low Level Driver User’s
Guide (available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
/* Example: Program resume command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0030;
Document Number: 002-01825 Rev. *B
/* write resume command
*/
Page 31 of 79
S29WS256N
S29WS128N
7.6.7
Accelerated Program/Chip Erase
Accelerated single word programming, write buffer programming, sector erase, and chip erase operations are enabled through the
ACC function. This method is faster than the standard chip program and erase command sequences.
The accelerated chip program and erase functions must not be used more than 10 times per sector. In addition, accelerated
chip program and erase should be performed at room temperature (25C 10C).
If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the
higher voltage on the input to reduce the time required for program and erase operations. The system can then use the Write Buffer
Load command sequence provided by the Unlock Bypass mode. Note that if a “Write-to-Buffer-Abort Reset” is required while in
Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC
input, upon completion of the embedded program or erase operation, returns the device to normal operation.
Sectors must be unlocked prior to raising ACC to VHH.
ig
n
The ACC pin must not be at VHH for operations other than accelerated programming and accelerated chip erase, or device
damage may result.
D
ACC locks all sector if set to VIL; ACC should be set to VIH for all other conditions.
es
The ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Unlock Bypass
ew
7.6.8
rN
The device features an Unlock Bypass mode to facilitate faster word programming. Once the device enters the Unlock Bypass
mode, only two write cycles are required to program data, instead of the normal four cycles.
fo
This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total
programming time. The Appendix on page 72 shows the requirements for the unlock bypass command sequences.
N
ot
R
ec
om
m
en
de
d
During the unlock bypass mode, only the Read, Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the
unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the
bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode.
Document Number: 002-01825 Rev. *B
Page 32 of 79
S29WS256N
S29WS128N
Software Functions and Sample Code
The following are C source code examples of using the unlock bypass entry, program, and exit functions. Refer to the Spansion Low
Level Driver User’s Guide (available soon on www.amd.com and www.fujitsu.com) for general information on Spansion Flash
memory software development guidelines.
Unlock Bypass Entry
(LLD Function = lld_UnlockBypassEntryCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Unlock
Write
Base + AAAh
Base + 555h
00AAh
2
Unlock
Write
Base + 554h
Base + 2AAh
0055h
3
Entry Command
Write
Base + AAAh
Base + 555h
0020h
/* Example: Unlock Bypass Entry Command
*/
/* write unlock cycle 1
*( (UINT16 *)bank_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*( (UINT16 *)bank_addr + 0x555 ) = 0x0020;
/* write unlock bypass command
*/
/* operations (programming or sector erase) and then exit
*/
/* Unlock Bypass Mode before beginning a different type of
*/
*/
rN
/* operations.
es
/* Once you enter Unlock Bypass Mode, do a series of like
*/
D
*/
*/
ew
/* At this point, programming only takes two write cycles.
*/
ig
n
*( (UINT16 *)bank_addr + 0x555 ) = 0x00AA;
Unlock Bypass Program
fo
(LLD Function = lld_UnlockBypassProgramCmd)
Description
Operation
Byte Address
Word Address
Data
1
Program Setup Command
Write
Base + xxxh
Base +xxxh
00A0h
2
Program Command
Write
Program Address
Program Address
Program Data
om
m
en
de
d
Cycle
/* Example: Unlock Bypass Program Command
*/
/* Do while in Unlock Bypass Entry Mode!
*/
*( (UINT16 *)bank_addr + 0x555 ) = 0x00A0;
/* write program setup command
*/
*( (UINT16 *)pa )
/* write data to be programmed
*/
ec
= data;
*/
R
/* Poll until done or error.
/* If done and more to program, */
N
Unlock Bypass Reset
ot
/* do above two cycles again.
*/
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Reset Cycle 1
Write
Base + xxxh
Base +xxxh
0090h
2
Reset Cycle 2
Write
Base + xxxh
Base +xxxh
0000h
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr + 0x000 ) = 0x0090;
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
Document Number: 002-01825 Rev. *B
Page 33 of 79
S29WS256N
S29WS128N
7.6.9
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following subsections describe the
function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or
completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command
sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer
Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page returns
false status information.
ig
n
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# polling on DQ7 is active for approximately tPSP, then that bank returns to the read
mode.
D
es
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or
if the bank enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any
of the sectors selected for erasure to read valid status information on DQ7.
rN
ew
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an
address within a protected sector, the status may not be valid.
om
m
en
de
d
fo
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while
Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7.
Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-D00
appears on successive read cycles.
N
ot
R
ec
See the following for more information: Table on page 38, shows the outputs for Data# Polling on DQ7. Figure 7.6 on page 35,
shows the Data# Polling algorithm; and Figure 11.18 on page 64, shows the Data# Polling timing diagram.
Document Number: 002-01825 Rev. *B
Page 34 of 79
S29WS256N
S29WS128N
Figure 7.6 Write Operation Status Flowchart
START
Read 1
(Note 6)
YES
Erase
Operation
Complete
DQ7=valid
data?
ig
n
NO
YES
Read 2
NO
Read 3
Program
Operation
Failed
ew
YES
NO
Device BUSY,
Re-Poll
fo
Read 3
YES
rN
Write Buffer
Programming?
Programming
Operation?
NO
(Note 3)
(Note 1)
d
YES
om
m
en
NO
Device BUSY,
Re-Poll
Read 2
ec
NO
(Note 2)
YES
DQ2
toggling?
NO
Erase
Operation
Complete
Read 3
DEVICE
ERROR
Device in
Erase/Suspend
Mode
N
ot
R
YES
DQ6
toggling?
NO
YES
Read3
DQ1=1?
(Note 5)
(Note 1)
TIMEOUT
de
DQ6
toggling?
Device BUSY,
Re-Poll
Read3= valid
data?
es
D
NO
(Note 4)
YES
Read 2
Read 1
DQ5=1?
Read3 DQ1=1
AND DQ7 ?
Valid Data?
YES
Write Buffer
Operation Failed
NO
Device BUSY,
Re-Poll
Notes:
1. DQ6 is toggling if Read2 DQ6 does not equal Read3 DQ6.
2. DQ2 is toggling if Read2 DQ2 does not equal Read3 DQ2.
3. May be due to an attempt to program a 0 to 1. Use the RESET command to exit operation.
4. Write buffer error if DQ1 of last read =1.
5. Invalid state, use RESET command to exit operation.
6. Valid data is the data that is intended to be programmed or all 1's for an erase operation.
7. Data polling algorithm valid for all operations except advanced sector protection.
Document Number: 002-01825 Rev. *B
Page 35 of 79
S29WS256N
S29WS128N
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. When the
operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP [all
sectors protected toggle time], then returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
ig
n
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 34).
es
If a program address falls within a protected sector, DQ6 toggles for approximately tPAP after the program command sequence is
written, then returns to reading array data.
D
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program Algorithm is complete.
ew
See the following for additional information: Figure 7.6 on page 35; Figure 11.19 on page 64, and Table on page 36 and Table
on page 38.
rN
Toggle Bit I on DQ6 requires either OE# or CE# to be de-asserted and reasserted to show the change in state.
DQ2: Toggle Bit II
om
m
en
de
d
fo
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for
erasure. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table to compare outputs for DQ2 and DQ6. See the
following for additional information: Figure 7.6 on page 35, the DQ6: Toggle Bit I on page 36, and Figure 11.18 on page 64 to
Figure 11.25 on page 66.
ec
DQ6 and DQ2 Indications
and the system reads
then DQ6
and DQ2
at any address,
toggles,
does not toggle.
at an address within a sector selected
for erasure,
toggles,
also toggles.
at an address within sectors not
selected for erasure,
toggles,
does not toggle.
at an address within a sector selected
for erasure,
does not toggle,
toggles.
at an address within sectors not
selected for erasure,
returns array data,
returns array data. The system can read
from any sector not selected for erasure.
at any address,
toggles,
is not applicable.
ot
N
actively erasing,
R
If device is
programming,
erase suspended,
programming in erase
suspend
Document Number: 002-01825 Rev. *B
Page 36 of 79
S29WS256N
S29WS128N
Reading Toggle Bits DQ6/DQ2
ig
n
Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the
program or erases operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial
two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is
high (see DQ5: Exceeded Timing Limits on page 37). If it is, the system should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erases operation. If it is still toggling, the device did not complete the operation successfully,
and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. Refer to Figure 7.6 on page 35 for more details.
Note:
ew
D
es
When verifying the status of a write operation (embedded program/erase) of a memory bank, DQ6 and DQ2 toggle between high
and low states in a series of consecutive and con-tiguous status read cycles. In order for this toggling behavior to be properly
observed, the consecutive status bit reads must not be interleaved with read accesses to other memory banks. If it is not possible to
temporarily prevent reads to other memory banks, then it is recommended to use the DQ7 status bit as the alternative method of
determining the active or inactive status of the write operation.
fo
rN
Data polling provides erroneous results during erase suspend operation using DQ2 or DQ6 for any address changes after CE#
asseration or without AVD# pulsing low. THe user is required to pulse AVD# following an address change or assert CE# after
address is stable during status polling. See Figure 11.21 on page 65 through Figure 11.24 on page 66 .
DQ5: Exceeded Timing Limits
om
m
en
de
d
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if
the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase operation can change a “0”
back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a
“1.”Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read
mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timeout State Indicator
N
ot
R
ec
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The
sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also
applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the
time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor
DQ3. See Sector Erase on page 27 for more details.
After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure
that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun;
all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts
additional sector erase commands. To ensure the command has been accepted, the system software should check the status of
DQ3 prior to and following each sub-sequent sector erase command. If DQ3 is high on the second status check, the last command
might not have been accepted. Table shows the status of DQ3 relative to the other status bits.
Document Number: 002-01825 Rev. *B
Page 37 of 79
S29WS256N
S29WS128N
DQ1: Write to Buffer Abort
DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue
the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming
on page 23 for more details.
Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
N/A
INVALID
INVALID
INVALID
INVALID
INVALID
INVALID
Program
Suspend
Mode
(Note 3)
Reading within Program Suspended Sector
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
(Not
Allowed)
Data
Data
Data
Data
Data
Data
Erase
Suspend
Mode
(Note 6)
1
No toggle
0
N/A
Toggle
N/A
Erase-SuspendRead
Data
Data
Data
Data
Data
Data
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
N/A
BUSY State
DQ7#
Toggle
0
N/A
N/A
0
Exceeded Timing Limits
DQ7#
Toggle
ABORT State
DQ7#
Toggle
es
D
Non-Erase Suspended
Sector
ew
Erase
Suspended Sector
rN
Reading within Non-Program Suspended
Sector
1
N/A
N/A
0
0
N/A
N/A
1
fo
Write to
Buffer
(Note 5)
Embedded Erase Algorithm
DQ1
(Note 4)
ig
n
Status
de
d
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to DQ5: Exceeded Timing Limits
on page 37 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
om
m
en
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for
DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
Simultaneous Read/Write
R
7.7
ec
6. For any address changes after CE# assertion, re-assertion of CE# might be required after the addresses become stable for data polling during the erase suspend
operation using DQ2/DQ6.
N
ot
The simultaneous read/write feature allows the host system to read data from one bank of memory while programming or erasing
another bank of memory. An erase operation may also be suspended to read from or program another location within the same bank
(except the sector being erased). Figure 11.29 on page 70 shows how read and write cycles may be initiated for simultaneous
operation with zero latency. Refer to DC Characteristics (CMOS Compatible) on page 54 for read-while-program and read-whileerase current specification.
7.8
Writing Commands/Command Sequences
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and CLK is ignored. When
in the Synchronous read mode configuration, the device is able to perform both Asynchronous and Synchronous write operations.
CLK and AVD# induced address latches are supported in the Synchronous programming mode. During a synchronous write
operation, to write a command or command sequence (which includes programming data to the device and erasing sectors of
memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and
CE# to VIL, and OE# to VIH when writing commands or data. During an asynchronous write operation, the system must drive CE#
and WE# to VIL and OE# to VIH when providing an address, command, and data. Addresses are latched on the last falling edge of
WE# or CE#, while data is latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors,
or the entire device. Table on page 10 and Table on page 11 indicate the address space that each sector occupies. The device
address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while Banks 0 and 15 contain both
16 Kword boot sectors in addition to 64 Kword sectors. A “bank address” is the set of address bits required to uniquely select a bank.
Similarly, a “sector address” is the address bits required to uniquely select a sector. ICC2 inDC Characteristics (CMOS Compatible)
Document Number: 002-01825 Rev. *B
Page 38 of 79
S29WS256N
S29WS128N
on page 54 represents the active current specification for the write mode. “AC Characteristics-Synchronous” and “AC
Characteristics-Asynchronous” contain timing specification tables and timing diagrams for write operations.
7.9
Handshaking
The handshaking feature allows the host system to detect when data is ready to be read by simply monitoring the RDY (Ready) pin,
which is a dedicated output and controlled by CE#.
When the device is configured to operate in synchronous mode, and OE# is low (active), the initial word of burst data becomes
available after either the falling or rising edge of the RDY pin (depending on the setting for bit 10 in the Configuration Register). It is
recommended that the host system set CR13–CR11 in the Configuration Register to the appropriate number of wait states to ensure
optimal burst mode operation (see Table on page 18).
Hardware Reset
es
7.10
ig
n
Bit 8 in the Configuration Register allows the host to specify whether RDY is active at the same time that data is ready, or one cycle
before data is ready.
ew
D
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at
least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data.
fo
rN
To ensure data integrity the operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence.
d
When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not at VSS, the standby
current is greater.
om
m
en
de
RESET# may be tied to the system reset circuitry which enables the system to read the boot-up firmware from the Flash memory
upon a system reset.
N
ot
R
ec
See Figure 11.5 on page 53 and Figure 11.13 on page 60 for timing diagrams.
Document Number: 002-01825 Rev. *B
Page 39 of 79
S29WS256N
S29WS128N
7.11
Software Reset
Software reset is part of the command set (see Table on page 72) that also returns the device to array read mode and must be used
for the following conditions:
to exit Autoselect mode
when DQ5 goes high during write status operation that indicates program or erase cycle was not successfully completed
exit sector lock/unlock operation.
to return to erase-suspend-read mode if the device was previously in Erase Suspend mode.
after any aborted operations
exiting Read Configuration Registration Mode
ig
n
Software Functions and Sample Code
Reset
es
(LLD Function = lld_ResetCmd)
Operation
Byte Address
Word Address
Write
Base + xxxh
Base + xxxh
D
Cycle
Reset Command
ew
Note:
Base = Base Address.
Data
00F0h
fo
rN
The following is a C source code example of using the reset function. Refer to the Spansion Low Level Driver User’s Guide
(available on www.amd.com and www.fujitsu.com) for general information on Spansion Flash memory software development
guidelines.
de
*( (UINT16 *)base_addr + 0x000 ) = 0x00F0;
d
/* Example: Reset (software reset of Flash state machine) */
om
m
en
The following are additional points to consider when using the reset command:
This command resets the banks to the read and address bits are ignored.
Reset commands are ignored once erasure has begun until the operation is complete.
Once programming begins, the device ignores reset commands until the operation is complete
ec
The reset command may be written between the cycles in a program command sequence before programming begins (prior to
the third cycle). This resets the bank to which the system was writing to the read mode.
ot
R
If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
N
The reset command may be also written during an Autoselect command sequence.
If a bank has entered the Autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the
erase-suspend-read mode.
If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command
sequence to RESET the device to reading array data. The standard RESET command does not work during this condition.
To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see command table
for details].
Document Number: 002-01825 Rev. *B
Page 40 of 79
S29WS256N
S29WS128N
8. Advanced Sector Protection/Unprotection
The Advanced Sector Protection/Unprotection feature disables or enables programming or erase operations in any or all sectors and
can be implemented through software and/or hardware methods, which are independent of each other. This section describes the
various methods of protecting data stored in the memory array. An overview of these methods in shown in Figure 8.1 on page 41.
Figure 8.1 Advanced Sector Protection/Unprotection
Hardware Methods
Software Methods
Lock Register
ACC = VIL
(All sectors locked)
Password Method
ig
n
(One Time Programmable)
Persistent Method
(DQ1)
es
(DQ2)
D
WP# = VIL
(All boot
sectors locked)
ew
64-bit Password
de
d
fo
rN
(One Time Protect)
PPB Lock Bit1,2,3
om
m
en
0 = PPBs Locked
1 = PPBs Unlocked
1. Bit is volatile, and defaults to “1” on
reset.
2. Programming to “0” locks all PPBs to
their current state.
3. Once programmed to “0”, requires
hardware reset to unlock.
Sector 0
PPB 0
DYB 0
Sector 1
PPB 1
DYB 1
Sector 2
PPB 2
DYB 2
Sector N-2
PPB N-2
DYB N-2
Sector N-1
PPB N-1
DYB N-1
PPB N
DYB N
Dynamic
Protection Bit
(DYB)6,7,8
N
ot
R
ec
Memory Array
Persistent
Protection Bit
(PPB)4,5
3
Sector N
3. N = Highest Address Sector.
Document Number: 002-01825 Rev. *B
4. 0 = Sector Protected,
1 = Sector Unprotected.
5. PPBs programmed individually,
but cleared collectively
6. 0 = Sector Protected,
1 = Sector Unprotected.
7. Protect effective only if PPB Lock Bit
is unlocked and corresponding PPB
is “1” (unprotected).
8. Volatile Bits: defaults to user choice
upon power-up (see ordering
options).
Page 41 of 79
S29WS256N
S29WS128N
8.1
Lock Register
As shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected,
unless otherwise chosen through the DYB ordering option (see Ordering Information on page 3). The device programmer or host
system must then choose which sector protection method to use. Programming (setting to “0”) any one of the following two one-time
programmable, non-volatile bits locks the part permanently in that mode:
Lock Register Persistent Protection Mode Lock Bit (DQ1)
Lock Register Password Protection Mode Lock Bit (DQ2)
Lock Register
DQ15-05
DQ4
DQ3
DQ2
DQ1
DQ0
S29WS256N
1
1
1
Password
Protection Mode
Lock Bit
Persistent
Protection Mode
Lock Bit
Customer Secure
Silicon Sector
Protection Bit
Password
Protection Mode
Lock Bit
Persistent
Protection Mode
Lock Bit
1 = sectors
power up
unprotected
1 = All PPB Erase
command enabled
For programming lock register bits refer to Figure 12.1 on page 73.
es
0 = All PPB erase
command disabled
Secure Silicon
Sector Protection
Bit
ew
Undefined
rN
S29WS128N
PPB One-Time
Programmable Bit
0 = sectors
power up
protected
D
DYB Lock Boot Bit
ig
n
Device
fo
Notes:
1. If the password mode is chosen, the password must be programmed before setting the corresponding lock register bit.
d
2. After the Lock Register Bits Command Set Entry command sequence is written, reads and writes for Bank 0 are disabled, while reads from other banks are allowed
until exiting this mode.
de
3. If both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts.
om
m
en
4. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled, and no changes to the protection scheme are allowed.
Similarly, if the Persistent Mode Lock Bit is programmed, the Password Mode is permanently disabled.
5. During erase/program suspend, ASP entry commands are not allowed.
6. When the device lock register is programmed (PPB mode lock bit is programmed, password mode lock bit is programmed, or the Secured Silicon Sector lock bit is
programmed) all DYBs revert to the power-on default state.
R
ec
7. Lock register programming operation:
A. Data Polling can be done immediately after the lock register programming command sequence (no delay required). Note that status polling can be done only in bank
0 and the recommended 4-µs delay is for backward compatibility and is not required. This recommendation will be noted as such in the next revision of the data sheet.
B. Reads from other banks (simultaneous operation) are not allowed during lock register programming. This restriction applies to both synchronous and asynchronous
read operations.
C. The above clarifications are true for programming any bits of the Lock Register.
ot
After selecting a sector protection method, each sector can operate in any of the following three states:
N
1. Constantly locked. The selected sectors are protected and can not be reprogrammed unless PPB lock bit is cleared via a
password, hardware reset, or power cycle.
2. Dynamically locked. The selected sectors are protected and can be altered via software commands.
3. Unlocked. The sectors are unprotected and can be erased and/or programmed.
These states are controlled by the bit types described in Section 8.2 on page 43 to Section 8.6 on page 46.
Document Number: 002-01825 Rev. *B
Page 42 of 79
S29WS256N
S29WS128N
8.2
Persistent Protection Bits
The Persistent Protection Bits are unique and nonvolatile for each sector and have the same endurances as the Flash memory.
Preprogramming and verification prior to erasure are handled by the device, and therefore do not require system monitoring.
Notes:
1. Each PPB is individually programmed and all are erased in parallel.
2. PPB program/erase operation: Reads from other banks (simultaneous operation) are not allowed during PPB programming/erase operation. This restriction applies for
both synchronous and asynchronous read operations.
3. Entry command disables reads and writes for the bank selected.
4. Reads within that bank return the PPB status for that sector.
5. All Reads must be performed using the Asynchronous mode.
6. The specific sector address (A23-A14 WS256N, A22-A14 WS128N) are written at the same time as the program command.
7. If the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB.
8. There are no means for individually erasing a specific PPB and no specific sector address is required for this operation.
ig
n
9. Exit command must be issued after the execution which resets the device to read mode and re-enables reads and writes for Bank 0
es
10. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device as described by the flow chart shown in
Figure 8.2 on page 43.
D
Figure 8.2 PPB Program/Erase Algorithm
rN
fo
d
Program PPB Bit.
Addr = SA
ew
Enter PPB
Command Set.
Addr = BA
om
m
en
de
Read Byte Twice
Addr = SA0
DQ6 =
Toggle?
No
ec
Yes
N
ot
R
No
DQ5 = 1?
Wait 500 µs
Yes
Read Byte Twice
Addr = SA0
DQ6 =
Toggle?
No
Read Byte.
Addr = SA
Yes
No
FAIL
DQ0 =
'1' (Erase)
'0' (Pgm.)?
Yes
PASS
Exit PPB
Command Set
Document Number: 002-01825 Rev. *B
Page 43 of 79
S29WS256N
S29WS128N
8.3
Dynamic Protection Bits
Dynamic Protection Bits are volatile and unique for each sector and can be individually modified. DYBs only control the protection
scheme for unprotected sectors that have their PPBs cleared (erased to “1”). By issuing the DYB Set or Clear command sequences,
the DYBs are set (programmed to “0”) or cleared (erased to “1”), thus placing each sector in the protected or unprotected state
respectively. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy
removal of protection when changes are needed.
Notes:
1. The DYBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed.
When the parts are first shipped, the PPBs are cleared (erased to “1”) and upon power up or reset, the DYBs can be set or cleared depending upon the ordering
option chosen.
2. If the option to clear the DYBs after power up is chosen, (erased to “1”), then the sectorsmay be modified depending upon the PPB state of that sector (see Table
on page 46).
3. The sectors would be in the protected state If the option to set the DYBs after power up is chosen (programmed to “0”).
4. It is possible to have sectors that are persistently locked with sectors that are left in the dynamic state.
es
ig
n
5. The DYB Set or Clear commands for the dynamic sectors signify protected or unprotectedstate of the sectors respectively. However, if there is a need to change the
status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or
hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again locks the PPBs, and the device operates normally
again.
Persistent Protection Bit Lock Bit
rN
8.4
ew
D
6. To achieve the best protection, it is recommended to execute the PPB Lock Bit Set command early in the boot code and protect the boot code by holding WP# = VIL.
Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC =VIH.
fo
The Persistent Protection Bit Lock Bit is a global volatile bit for all sectors. When set (programmed to “0”), it locks all PPBs and when
cleared (programmed to “1”), allows the PPBs to be changed. There is only one PPB Lock Bit per device.
d
Notes:
1. No software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit.
8.5
om
m
en
de
2. The PPB Lock Bit must be set (programmed to “0”) only after all PPBs are configured to the desired settings.
Password Protection Method
ec
The Password Protection Method allows an even higher level of security than the Persistent Sector Protection Mode by requiring a
64 bit password for unlocking the device PPB Lock Bit. In addition to this password requirement, after power up and reset, the PPB
Lock Bit is set “0” to maintain the password mode of operation. Successful execution of the Password Unlock command by entering
the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications.
ot
R
Notes:
1. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set
in order to prevent access.
N
2. The Password Program Command is only capable of programming “0”s. Programming a “1” after a cell is programmed as a “0” results in a time-out with the cell as a
“0”.
3. The password is all “1”s when shipped from the factory.
4. All 64-bit password combinations are valid as a password.
5. There is no means to verify what the password is after it is set.
6. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the data bus and further password programming.
7. The Password Mode Lock Bit is not erasable.
8. The lower two address bits (A1–A0) are valid during the Password Read, Password Program, and Password Unlock.
9. The exact password must be entered in order for the unlocking function to occur.
10. The Password Unlock command cannot be issued any faster than 1 µs at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to
correctly match a password.
11. Approximately 1 µs is required for unlocking the device after the valid 64-bit password is given to the device.
12. Password verification is only allowed during the password programming operation.
13. All further commands to the password region are disabled and all operations are ignored.
14. If the password is lost after setting the Password Mode Lock Bit, there is no way to clear the PPB Lock Bit.
15. Entry command sequence must be issued prior to any of any operation and it disables reads and writes for Bank 0. Reads and writes for other banks excluding Bank
0 are allowed.
16. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode.
17. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector.
Document Number: 002-01825 Rev. *B
Page 44 of 79
S29WS256N
S29WS128N
18. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB
Lock Status to the device.
Figure 8.3 Lock Register Program Algorithm
Write Unlock Cycles:
Address 555h, Data AAh
Address 2AAh, Data 55h
Unlock Cycle 1
Unlock Cycle 2
Write
Enter Lock Register Command:
Address 555h, Data 40h
ig
n
XXXh = Address don’t care
Program Lock Register Data
Address XXXh, Data A0h
Address 77h*, Data PD
* Not on future devices
es
Program Data (PD): See text for Lock Register
definitions
D
Caution: Lock register can only be progammed
once.
rN
ew
Wait 4 μs
(Recommended)
Perform Polling Algorithm
om
m
en
Yes
de
d
fo
(see Write Operation Status
flowchart)
Done?
DQ5 = 1?
No
Error condition (Exceeded Timing Limits)
Yes
N
ot
R
ec
No
PASS. Write Lock Register
Exit Command:
Address XXXh, Data 90h
Address XXXh, Data 00h
Device returns to reading array.
Document Number: 002-01825 Rev. *B
FAIL. Write rest command
to return to reading array.
Page 45 of 79
S29WS256N
S29WS128N
8.6
Advanced Sector Protection Software Examples
Sector Protection Schemes
Unique Device PPB Lock Bit
0 = locked
1 = unlocked
Sector PPB
0 = protected
1 = unprotected
Sector DYB
0 = protected
1 = unprotected
Sector Protection Status
Any Sector
0
0
x
Protected through PPB
Any Sector
0
0
x
Protected through PPB
Any Sector
0
1
1
Unprotected
Any Sector
0
1
0
Protected through DYB
Any Sector
1
0
x
Protected through PPB
Any Sector
1
0
x
Protected through PPB
1
1
0
Protected through DYB
Any Sector
1
1
1
Unprotected
es
ig
n
Any Sector
8.7
rN
ew
D
Table on page 46 contains all possible combinations of the DYB, PPB, and PPB Lock Bit relating to the status of the sector. In
summary, if the PPB Lock Bit is locked (set to “0”), no changes to the PPBs are allowed. The PPB Lock Bit can only be unlocked
(reset to “1”) through a hardware reset or power cycle. See also Figure 8.1 on page 41 for an overview of the Advanced Sector
Protection feature.
Hardware Data Protection Methods
fo
The device offers two main types of data protection at the sector level via hardware control:
de
When ACC is at VIL, all sectors are locked.
d
When WP# is at VIL, the device disables program and erase functions in the outermost boot sectors.
8.7.1
om
m
en
There are additional methods by which intended or accidental erasure of any sectors can be prevented via hardware means. The
following subsections describes these methods:
WP# Method
ec
The Write Protect feature provides a hardware method of protecting the four outermost sectors. This function is provided by the WP#
pin and overrides the previously discussed Sector Protection/Unprotection method.
ot
R
If the system asserts VIL on the WP# pin, the device disables program and erase functions in the “outermost” boot sectors. The
outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-configured device.
N
If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected.
Note that the WP# pin must not be left floating or unconnected as inconsistent behavior of the device may result.
The WP# pin must be held stable during a command sequence execution
8.7.2
ACC Method
This method is similar to above, except it protects all sectors. Once ACC input is set to VIL, all program and erase functions are
disabled and hence all sectors are protected.
8.7.3
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent
writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent
unintentional writes when VCC is greater than VLKO.
Document Number: 002-01825 Rev. *B
Page 46 of 79
S29WS256N
S29WS128N
8.7.4
Write Pulse “Glitch Protection”
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.7.5
Power-Up Write Inhibit
If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#.
The internal state machine is automatically reset to the read mode on power-up.
9. Power Conservation Modes
9.1
Standby Mode
Automatic Sleep Mode
rN
9.2
ew
D
es
ig
n
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device
enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard
access time (tCE) for read access, before it is ready to read data. If the device is deselected during erasure or programming, the
device draws active current until the operation is completed. ICC3 in DC Characteristics (CMOS Compatible) on page 54 represents
the standby current specification
9.3
om
m
en
de
d
fo
The automatic sleep mode minimizes Flash device energy consumption while in asynchronous mode. the device automatically
enables this mode when addresses remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and
OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output
data is latched and always available to the system. While in synchronous mode, the automatic sleep mode is disabled. Note that a
new burst operation is required to provide new data. ICC6 in DC Characteristics (CMOS Compatible) on page 54 represents the
automatic sleep mode current specification.
Hardware RESET# Input Operation
ot
R
ec
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at
least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration
register, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another
command sequence to ensure data integrity.
N
When RESET# is held at VSS ± 0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS ±
0.2 V, the standby current is greater.
RESET# may be tied to the system reset circuitry and thus, a system reset would also reset the Flash memory, enabling the system
to read the boot-up firmware from the Flash memory.
9.4
Output Disable (OE#)
When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state.
Document Number: 002-01825 Rev. *B
Page 47 of 79
S29WS256N
S29WS128N
10. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector provides an extra Flash memory region that enables permanent part identification through an Electronic
Serial Number (ESN). The Secured Silicon Sector is 256 words in length that consists of 128 words for factory data and 128 words
for customer-secured areas. All Secured Silicon reads outside of the 256-word address range returns invalid data. The Factory
Indicator Bit, DQ7, (at Autoselect address 03h) is used to indicate whether or not the Factory Secured Silicon Sector is locked when
shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector
is locked when shipped from the factory.
Please note the following general conditions:
While Secured Silicon Sector access is enabled, simultaneous operations are allowed except for Bank 0.
On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space.
Reads can be performed in the Asynchronous or Synchronous mode.
ig
n
Burst mode reads within Secured Silicon Sector wrap from address FFh back to address 00h.
es
Reads outside of sector 0 return memory array data.
Continuous burst read past the maximum address is undefined.
D
Sector 0 is remapped from memory array to Secured Silicon Sector array.
ew
Once the Secured Silicon Sector Entry Command is issued, the Secured Silicon Sector Exit command must be issued to exit
Secured Silicon Sector Mode.
rN
The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.
128 words
Factory
128 words
d
Sector Size
de
Sector
Customer
Address Range
000080h-0000FFh
000000h-00007Fh
om
m
en
10.1
fo
Secured Silicon Sector Addresses
Factory Secured Silicon Sector
ec
The Factory Secured Silicon Sector is always protected when shipped from the factory and has the Factory Indicator Bit (DQ7)
permanently set to a “1”. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code once
the product is shipped to the field.
R
These devices are available pre programmed with one of the following:
ot
A random, 8 Word secure ESN only within the Factory Secured Silicon Sector
N
Customer code within the Customer Secured Silicon Sector through the SpansionTM programming service.
Both a random, secure ESN and customer code through the Spansion programming service.
Customers may opt to have their code programmed through the Spansion programming services. Spansion programs the
customer's code, with or without the random ESN. The devices are then shipped from the Spansion factory with the Factory Secured
Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using
Spansion programming services.
Document Number: 002-01825 Rev. *B
Page 48 of 79
S29WS256N
S29WS128N
10.2
Customer Secured Silicon Sector
The Customer Secured Silicon Sector is typically shipped unprotected (DQ6 set to “0”), allowing customers to utilize that sector in
any manner they choose. If the security feature is not required, the Customer Secured Silicon Sector can be treated as an additional
Flash memory space.
Please note the following:
Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit is permanently set to “1.”
The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. The
Customer Secured Silicon Sector lock must be used with caution as once locked, there is no procedure available for unlocking the
Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified
in any way.
ig
n
The accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured
Silicon Sector, but reading in Banks 1 through 15 is available.
Secured Silicon Sector Entry/Exit Command Sequences
ew
10.3
D
es
Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region
command sequence which return the device to the memory array at sector 0.
rN
The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command
sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured
Silicon Sector command sequence.
fo
See Table on page 72 for address and data requirements for both command sequences.
om
m
en
Program the customer Secured Silicon Sector
de
Read customer and factory Secured Silicon areas
d
The Secured Silicon Sector Entry Command allows the following commands to be executed
N
ot
R
ec
After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using
the addresses normally occupied by sector SA0 within the memory array. This mode of operation continues until the system issues
the Exit Secured Silicon Sector command sequence, or until power is removed from the device.
Document Number: 002-01825 Rev. *B
Page 49 of 79
S29WS256N
S29WS128N
Software Functions and Sample Code
The following are C functions and source code examples of using the Secured Silicon Sector Entry, Program, and exit commands.
Refer to the Spansion Low Level Driver User’s Guide (available soon on www.spansion.com) for general information on Spansion
Flash memory software development guidelines.
Secured Silicon Sector Entry
(LLD Function = lld_SecSiSectorEntryCmd)
Cycle
Operation
Byte Address
Word Address
Data
Unlock Cycle 1
Write
Base + AAAh
Base + 555h
00AAh
Unlock Cycle 2
Write
Base + 554h
Base + 2AAh
0055h
Entry Cycle
Write
Base + AAAh
Base + 555h
0088h
ig
n
Note:
Base = Base Address.
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0088;
/* write Secsi Sector Entry Cmd
*/
Secured Silicon Sector Program
rN
ew
D
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
es
/* Example: SecSi Sector Entry Command */
(LLD Function = lld_ProgramCmd)
Operation
Byte Address
Write
Base + AAAh
Unlock Cycle 2
Write
Base + 554h
Write
d
de
Write
Program
Base + AAAh
om
m
en
Program Setup
fo
Cycle
Unlock Cycle 1
Note:
Base = Base Address.
Word Address
Word Address
Data
Base + 555h
00AAh
Base + 2AAh
0055h
Base + 555h
00A0h
Word Address
Data Word
/* Once in the SecSi Sector mode, you program */
*/
R
ec
/* words using the programming algorithm.
Cycle
N
ot
Secured Silicon Sector Exit
(LLD Function = lld_SecSiSectorExitCmd)
Operation
Byte Address
Word Address
Data
Write
Base + AAAh
Base + 555h
00AAh
Unlock Cycle 1
Unlock Cycle 2
Write
Base + 554h
Base + 2AAh
0055h
Exit Cycle
Write
Base + AAAh
Base + 555h
0090h
Note:
Base = Base Address.
/* Example: SecSi Sector Exit Command */
*( (UINT16 *)base_addr + 0x555 ) = 0x00AA;
/* write unlock cycle 1
*/
*( (UINT16 *)base_addr + 0x2AA ) = 0x0055;
/* write unlock cycle 2
*/
*( (UINT16 *)base_addr + 0x555 ) = 0x0090;
/* write SecSi Sector Exit cycle 3 */
*( (UINT16 *)base_addr + 0x000 ) = 0x0000;
/* write SecSi Sector Exit cycle 4 */
Document Number: 002-01825 Rev. *B
Page 50 of 79
S29WS256N
S29WS128N
11. Electrical Specifications
11.1
Absolute Maximum Ratings
Storage Temperature Plastic Packages
–65°C to +150°C
Ambient Temperature with Power Applied
–65°C to +125°C
Voltage with Respect to Ground: All Inputs and I/Os except as noted below (1)
–0.5 V to VCC + 0.5 V
VCC (1)
–0.5 V to +2.5 V
ACC (2)
–0.5 V to +9.5 V
Output Short Circuit Current (3)
100 mA
es
ig
n
Notes:
1. Minimum DC voltage on input or I/Os is –0.5 V. During voltage transitions, inputs or I/Os may undershoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1
on page 51. Maximum DC voltage on input or I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See
Figure 11.2 on page 51.
D
2. Minimum DC input voltage on pin ACC is -0.5V. During voltage transitions, ACC may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 11.1 on page 51.
Maximum DC voltage on pin ACC is +9.5 V, which may overshoot to 10.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
rN
ew
4. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
fo
Figure 11.1 Maximum Negative Overshoot Waveform
om
m
en
–0.5 V
de
+0.8 V
20 ns
d
20 ns
–2.0 V
ec
20 ns
N
ot
R
Figure 11.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
1.0 V
20 ns
20 ns
Note:
The content in this document is Advance information for the S29WS128N. Content in this document is Preliminary for the S29W256N.
Document Number: 002-01825 Rev. *B
Page 51 of 79
S29WS256N
S29WS128N
11.2
Operating Ranges
Wireless (W) Devices
Supply Voltages
Ambient Temperature (TA): –25°C to +85°C
VCC Supply Voltages: +1.70 V to +1.95 V
Note:
Operating ranges define those limits between which the functionality of the device is guaranteed.
11.3
Test Conditions
Figure 11.3 Test Setup
es
ig
n
Device
Under
Test
rN
ew
D
CL
fo
Test Specifications
Test Condition
Unit
30
pF
de
3.0 @ 54, 66 MHz
om
m
en
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement reference levels
2.5 @ 80 MHz
ns
0.0–VCC
V
VCC/2
V
VCC/2
V
ec
Output timing measurement reference levels
Key to Switching Waveforms
Inputs
N
ot
Waveform
R
11.4
All Speed Options
d
Output Load Capacitance, CL
(including jig capacitance)
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Document Number: 002-01825 Rev. *B
Page 52 of 79
S29WS256N
S29WS128N
11.5
Switching Waveforms
Figure 11.4 Input Waveforms and Measurement Levels
All Inputs and Outputs
VCC
Input
VCC/2
Measurement Level
VCC/2
Output
0.0 V
11.6
VCC Power-up
Parameter
Description
Test Setup
Speed
Unit
tVCS
VCC Setup Time
Min
1
ms
ig
n
Notes:
1. All VCC signals must be ramped simultaneously to ensure correct power-up.
ew
tVCS
D
Figure 11.5 VCC Power-up Diagram
es
2. S29WS128N: VCC ramp rate is > 1V/ 100 µs and for VCC ramp rate of < 1 V / 100 µs a hardware reset is required.
fo
rN
VCC
N
ot
R
ec
om
m
en
de
d
RESET#
Document Number: 002-01825 Rev. *B
Page 53 of 79
S29WS256N
S29WS128N
11.7
Parameter
DC Characteristics (CMOS Compatible)
Description (Notes)
Test Conditions (Notes 1, 8)
Min
Typ
Max
Unit
Input Load Current
VIN = VSS to VCC, VCC = VCCmax
±1
µA
Output Leakage Current (2)
VOUT = VSS to VCC, VCC = VCCmax
±1
µA
VCC Active burst Read Current
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 32
CE# = VIL, OE# = VIH, WE#
= VIH, burst length =
Continuous
54
mA
28
60
mA
80 MHz
30
66
mA
54 MHz
28
48
mA
66 MHz
30
54
mA
80 MHz
32
60
mA
54 MHz
29
42
mA
66 MHz
32
48
mA
80 MHz
34
54
mA
54 MHz
32
36
mA
42
mA
es
ICCB
27
66 MHz
66 MHz
35
D
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 16
54 MHz
80 MHz
38
48
mA
34
45
mA
17
26
mA
1 MHz
4
7
mA
VACC
1
5
µA
VCC
24
52.5
mA
VACC
5
µA
VCC Active Asynchronous
Read Current (3)
CE# = VIL, OE# = VIH, WE#
= VIH
ICC2
VCC Active Write Current (4)
CE# = VIL, OE# = VIH, ACC
= VIH
VCC Standby Current (5, 6)
CE# = RESET# =
VCC ± 0.2 V
1
ICC3
d
10 MHz
ew
CE# = VIL, OE# = VIH, WE#
= VIH, burst length = 8
ig
n
ILI
ILO
VCC
20
70
µA
ICC4
VCC Reset Current (6)
RESET# = VIL, CLK = VIL
70
250
µA
ICC5
VCC Active Current
(Read While Write) (6)
CE# = VIL, OE# = VIH, ACC = VIH @
5 MHz
50
60
mA
ICC6
VCC Sleep Current (6)
CE# = VIL, OE# = VIH
2
70
µA
ICC7
VCC Page Mode Read Current
12
mA
VACC
6
20
mA
VCC
14
20
mA
VIL
Input Low Voltage
rN
fo
de
om
m
en
Accelerated Program Current (7)
OE# = VIH, CE# = VIL
CE# = VIL, OE# = VIH,
VACC = 9.5 V
ec
IACC
5 MHz
VCC = 1.8 V
–0.5
0.4
V
VCC = 1.8 V
VCC – 0.4
VCC + 0.4
V
0.1
V
9.5
V
1.4
V
R
ICC1
Input High Voltage
Output Low Voltage
VOH
Output High Voltage
VHH
Voltage for Accelerated Program
VLKO
Low VCC Lock-out Voltage
N
ot
VIH
VOL
IOL = 100 µA, VCC = VCC min
IOH = –100 µA, VCC = VCC min
VCC
8.5
V
Notes:
1. Maximum ICC specifications are tested with VCC = VCCmax.
2. CE# must be set high when measuring the RDY pin.
3. The ICC current listed is typically less than 3.5 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3.
6. VIH = VCC ± 0.2 V and VIL > –0.1 V.
7. Total current during accelerated programming is the sum of VACC and VCC currents.
8. VACC = VHH on ACC input.
Document Number: 002-01825 Rev. *B
Page 54 of 79
S29WS256N
S29WS128N
11.8
AC Characteristics
11.8.1
CLK Characterization
Parameter
54 MHz
66 MHz
80 MHz
Unit
fCLK
CLK Frequency
Description
Max
54
66
80
MHz
tCLK
CLK Period
Min
18.5
15.1
12.5
ns
tCH
CLK High Time
Min
7.4
6.1
5.0
ns
tCL
CLK Low Time
tCR
CLK Rise Time
Max
3
3
2.5
ns
tCF
CLK Fall Time
ig
n
Note:
Not 100% tested.
D
es
Figure 11.6 CLK Characterization
ew
tCLK
tCL
CLK
fo
rN
tCH
tCF
Synchronous/Burst Read
om
m
en
11.8.2
de
d
tCR
Parameter
Description
Standard
54 MHz
80 MHz
Burst Access Time Valid Clock to Output Delay
Max
13.5
tACS
Address Setup Time to CLK (Note 1)
Min
5
4
ns
tACH
Address Hold Time from CLK (Note 1)
Min
7
6
ns
tBDH
Data Hold Time from Next Clock Cycle
Min
4
3
ns
tCR
Chip Enable to RDY Valid
Max
13.5
tOE
Output Enable to Output Valid
Max
13.5
ec
tBACC
R
80
Unit
Latency
ot
Max
66 MHz
tIACC
N
JEDEC
ns
11.2
9
11.2
9
11.2
ns
ns
ns
tCEZ
Chip Enable to High Z (Note 2)
Max
10
ns
tOEZ
Output Enable to High Z (Note 2)
Max
10
ns
tCES
CE# Setup Time to CLK
Min
tRDYS
RDY Setup Time to CLK
Min
5
4
3.5
tRACC
Ready Access Time from CLK
Max
13.5
11.2
8.5
tCAS
CE# Setup Time to AVD#
Min
0
ns
tAVC
AVD# Low to CLK
Min
4
ns
tAVD
AVD# Pulse
Min
7
ns
tAVDH
AVD# Hold
Min
3
ns
Minimum clock frequency
Min
fCLK
4
1
1
ns
1
ns
ns
MHz
Notes:
1. Addresses are latched on the first rising edge of CLK.
2. Not 100% tested.
Document Number: 002-01825 Rev. *B
Page 55 of 79
S29WS256N
S29WS128N
Synchronous Wait State Requirements
Max Frequency
Wait State Requirement
01 MHz < Freq. 14 MHz
2
14 MHz < Freq. 27 MHz
3
27 MHz < Freq. 40 MHz
4
40 MHz < Freq. 54 MHz
5
54 MHz < Freq. 67 MHz
6
67 MHz < Freq. 80 MHz
7
Timing Diagrams
Figure 11.7 CLK Synchronous Burst Mode Read
tCES
18.5 ns typ. (54 MHz)
1
2
3
4
tAVC
AVD#
Aa
tBACC
d
tACH
de
Hi-Z
om
m
en
tIACC
OE#
tOE
RDY (n)
Hi-Z
Da
Da + 1
Da + 2
Da + 3
Da + n
tOEZ
tBDH
tRACC
Hi-Z
tRDYS
Hi-Z
Da
Da + 1
Da + 2
Da + 2
Da + n
ot
R
Data (n + 1)
ec
tCR
7
fo
tACS
Data (n)
6
rN
tAVD
tAVDH
Addresses
5
tCEZ
ew
CLK
D
CE#
es
5 cycles for initial access shown.
ig
n
11.8.3
Hi-Z
Hi-Z
N
RDY (n + 1)
Hi-Z
Data (n + 2)
Da
RDY (n + 2)
Da + 1
Da + 1
Da + 1
Da + n
Hi-Z
Hi-Z
Hi-Z
Data (n + 3)
Da
RDY (n + 3)
Da
Da
Da
Hi-Z
Da + n
Hi-Z
Notes:
1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from two cycles to seven cycles.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in synchronous mode.
Document Number: 002-01825 Rev. *B
Page 56 of 79
S29WS256N
S29WS128N
Figure 11.8 8-word Linear Burst with Wrap Around
7 cycles for initial access shown.
tCES
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVDH
tAVD
tACS
Addresses
Ac
tBACC
tACH
Data
tIACC
RDY
tCR
DF
DB
D8
tRACC
tRACC
tOE
Hi-Z
DE
DD
tBDH
tRDYS
ig
n
OE#
DC
es
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles.
D
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated by RDY.
ew
3. The device is in synchronous mode with wrap around.
rN
4. D8–DF in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 4th address in range
(0-F).
fo
Figure 11.9 8-word Linear Burst without Wrap Around
tCES
7? cycles for initial access shown.
2
3
tAVC
tAVDH
AVD#
4
5
d
1
CLK
6
7
de
CE#
om
m
en
tAVD
tACS
Addresses
Ac
tBACC
tACH
Data
ec
tIACC
OE#
R
ot
RDY
tCR
Hi-Z
tOE
DC
DD
DE
DF
D8
DB
tBDH
tRACC
tRACC
tRDYS
N
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for
active rising edge.
2. If any burst address occurs at “address + 1”, “address + 2”, or “address + 3”, additional clock delay cycles are inserted, and are indicated by RDY.
3. The device is in asynchronous mode with out wrap around.
4. DC–D13 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 1st address in range
(c-13).
Document Number: 002-01825 Rev. *B
Page 57 of 79
S29WS256N
S29WS128N
Figure 11.10 Linear Burst with RDY Set One Cycle Before Data
tCES
6
7
~
~
tAVC
5
~
~
~
~
1
CLK
tCEZ
6 wait cycles for initial access shown.
~
~
CE#
tAVDH
AVD#
tAVD
tACS
Addresses
Aa
tBACC
tACH
Hi-Z
Data
tIACC
Da
tCR
tOE
Da+3
Da + n
tOEZ
Hi-Z
es
Hi-Z
Da+2
ig
n
tRACC
OE#
RDY
Da+1
tBDH
tRDYS
D
Notes:
1. Figure assumes 6 wait states for initial access and synchronous read.
rN
ew
2. The Set Configuration Register command sequence has been written with CR8=0; device outputs RDY one cycle before valid data.
AC Characteristics—Asynchronous Read
fo
11.8.4
Parameter
Description
Access Time from CE# Low
de
tCE
d
Standard
Unit
Max
80
ns
Min
8
ns
4
AVD# Low Time
tAAVDS
Address Setup Time to Rising Edge of AVD#
Min
tAAVDH
Address Hold Time from Rising Edge of AVD#
Min
Output Enable to Output Valid
om
m
en
80 MHz
ns
Asynchronous Access Time
ec
66 MHz
80
tACC
tOE
54 MHz
Max
tAVDP
7
ns
6
ns
Max
13.5
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
Max
10
ns
Min
0
ns
Output Enable Hold Time
tOEZ
Output Enable to High Z (Note 1)
tCAS
CE# Setup Time to AVD#
tPACC
Page Access Time
Max
20
ns
tOH
Output Hold Time From Addresses, CE#
or OE#, whichever occurs first (Note 2)
Min
0
ns
tCEZ
Chip Enable to Output Tristate
Max
10
ns
ot
R
tOEH
N
JEDEC
Notes:
1. Not 100% tested.
2. tOEH = 1 ns for S29WS128N.
Document Number: 002-01825 Rev. *B
Page 58 of 79
S29WS256N
S29WS128N
Figure 11.11 Asynchronous Mode Read
CE#
tOE
OE#
tOEH
WE#
tCE
tOEZ
Data
Valid RD
tACC
RA
ig
n
Addresses
tAAVDH
tCAS
es
AVD#
D
tAVDP
tAAVDS
rN
ew
Notes:
RA = Read Address, RD = Read Data.
~
~
fo
Figure 11.12 Four-Word Page-Mode Operation
A1-A0
d
~
~
om
m
en
A0
Same Page Address
de
~
~
~
~
A22-A2
A1
A2
A3
tCE
~
~
CE#
tCOEZ
tACC
~
~
tOE
tPACC
R
Data
~
~
tOEZ
~
~
WE#
tOH
~
~
N
ot
OE#
ec
AVD#
Optional
D0
tPACC
tOEZ
D1
D1
tPACC
D2
tOH
tOH
11.8.5
D3
Hardware Reset (RESET#)
Parameter
Description
JEDEC
All Speed Options
Unit
Std.
tRP
RESET# Pulse Width
Min
30
µs
tRH
Reset High Time Before Read (See Note)
Min
200
ns
Note:
Not 100% tested.
Document Number: 002-01825 Rev. *B
Page 59 of 79
S29WS256N
S29WS128N
Figure 11.13 Reset Timings
CE#, OE#
tRH
RESET#
tRP
Erase/Program Timing
ig
n
11.8.6
Parameter
Standard
tAVAV
tWC
Write Cycle Time (1)
tAVWL
tAS
Address Setup Time (2) (3)
54 MHz
80
Synchronous
Address Hold Time (2) (3)
tWHDX
tDH
Data Hold Time
tGHWL
tGHWL
Min
Min
Read Recovery Time Before Write
tCAS
CE# Setup Time to AVD#
tCH
CE# Hold Time
tWLWH
tWP
Write Pulse Width
tWHWL
tWPH
Write Pulse Width High
tSR/W
ns
5
ns
0
ns
9
ns
20
8
45
ns
20
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
0
ns
Min
30
ns
Min
20
ns
ns
Min
0
VACC Rise and Fall Time
Min
500
ns
tVIDS
VACC Setup Time (During Accelerated Programming)
Min
1
µs
tCS
CE# Setup Time to WE#
Min
5
ns
R
ec
Latency Between Read and Write Operations
tVID
tAVSW
AVD# Setup Time to WE#
Min
5
ns
tAVHW
AVD# Hold Time to WE#
Min
5
ns
ot
tELWL
Unit
tAVSC
N
tWHEH
rN
Data Setup Time
fo
AVD# Low Time
tDS
d
tAVDP
tDVWH
Min
Asynchronous
de
tAH
om
m
en
tWLAX
ew
Min
Synchronous
80 MHz
D
Min
Asynchronous
66 MHz
es
Description
JEDEC
AVD# Setup Time to CLK
Min
5
ns
tAVHC
AVD# Hold Time to CLK
Min
5
ns
tCSW
Clock Setup Time to WE#
Min
5
ns
tWEP
Noise Pulse Margin on WE#
Max
3
ns
tSEA
Sector Erase Accept Time-out
Min
50
µs
tESL
Erase Suspend Latency
Max
20
µs
tPSL
Program Suspend Latency
Max
20
µs
tASP
Toggle Time During Erase within a Protected Sector
Typ
0
µs
tPSP
Toggle Time During Programming Within a Protected Sector
Typ
0
µs
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program operation timing, addresses are latched on the
rising edge of CLK.
4. See Erase and Programming Performance on page 71 for more information.
5. Does not include the preprogramming time.
Document Number: 002-01825 Rev. *B
Page 60 of 79
S29WS256N
S29WS128N
Figure 11.14 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
VIH
CLK
Read Status Data
VIL
tAVDP
AVD#
tAH
tAS
Addresses
VA
SA
2AAh
555h for
chip erase
Data
55h
In
Progress
30h
tCH
D
ew
tWP
WE#
tWHWH2
rN
tWPH
tWC
fo
tVCS
es
CE#
OE#
Complete
ig
n
tDS
tDH
tCS
VA
10h for
chip erase
N
ot
R
ec
om
m
en
de
d
VCC
Document Number: 002-01825 Rev. *B
Page 61 of 79
S29WS256N
S29WS128N
Figure 11.15 Program Operation Timing Using AVD#
Program Command Sequence (last two cycles)
Read Status Data
VIH
CLK
VIL
tAVSW
tAVHW
tAVDP
AVD#
tAS
tAH
Addresses
555h
VA
PA
Data
A0h
In
Progress
Complete
ig
n
PD
tDS
tCAS
VA
es
tDH
D
CE#
tCH
ew
OE#
WE#
tCS
de
tVCS
d
tWC
tWHWH1
fo
tWPH
rN
tWP
VCC
om
m
en
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N) are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH.
N
ot
R
ec
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Document Number: 002-01825 Rev. *B
Page 62 of 79
S29WS256N
S29WS128N
Figure 11.16 Program Operation Timing Using CLK in Relationship to AVD#
Program Command Sequence (last two cycles)
Read Status Data
tAVCH
CLK
tAS
tAH
tAVSC
AVD#
tAVDP
VA
PA
555h
Data
In
Progress
PD
A0h
tDS
tDH
tCAS
Complete
OE#
D
es
CE#
VA
ig
n
Addresses
tCH
ew
tCSW
tWP
tWPH
fo
tWC
tWHWH1
rN
WE#
de
d
tVCS
VCC
om
m
en
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. A23–A14 for the WS256N (A22–A14 for the WS128N) are don’t care during command sequence unlock cycles.
4. Addresses are latched on the first rising edge of CLK.
ec
5. Either CE# or AVD# is required to go from low to high in between programming command sequences.
R
6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register. The Configuration Register must be set to the
Synchronous Read Mode.
ot
Figure 11.17 Accelerated Unlock Bypass Programming Timing
N
CE#
AVD#
WE#
Addresses
PA
Data
Don't Care
OE#
tVIDS
ACC
A0h
Don't Care
PD
Don't Care
VID
tVID
VIL or VIH
Note:
Use setup and hold times from conventional program operation.
Document Number: 002-01825 Rev. *B
Page 63 of 79
S29WS256N
S29WS128N
Figure 11.18 Data# Polling Timings (During Embedded Algorithm)
AVD#
tCEZ
tCE
CE#
tCH
tOEZ
tOE
OE#
tOEH
WE#
tACC
Addresses
VA
High Z
VA
High Z
Status Data
ig
n
Status Data
Data
es
Notes:
1. Status reads in figure are shown as asynchronous.
D
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling outputs true data.
ew
Figure 11.19 Toggle Bit Timings (During Embedded Algorithm)
rN
AVD#
tCE
tOE
de
OE#
tOEH
om
m
en
WE#
tOEZ
d
tCH
fo
CE#
tCEZ
tACC
Addresses
VA
Data
High Z
Status Data
ec
Status Data
High Z
VA
R
Notes:
1. Status reads in figure are shown as asynchronous.
N
ot
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits stop toggling.
Document Number: 002-01825 Rev. *B
Page 64 of 79
S29WS256N
S29WS128N
Figure 11.20 Synchronous Data Polling Timings/Toggle Bit Timings
CE#
CLK
AVD#
Addresses
VA
VA
OE#
tIACC
tIACC
Data
es
RDY
Status Data
ig
n
Status Data
D
Notes:
1. The timings are similar to synchronous read timings.
ew
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits stop toggling.
rN
3. RDY is active with data (D8 = 1 in the Configuration Register). When D8 = 0 in the Configuration Register, RDY is active one clock cycle before data.
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
d
0ns
fo
Figure 11.21 Conditions for Incorrect DQ2 Polling During Erase Suspend
de
ADDR
om
m
en
CE#
AVD#
OE#
ec
Note:
DQ2 does not toggle correctly during erase suspend if AVD# or CE# are held low after valid address.
N
ot
R
Figure 11.22 Correct DQ2 Polling during Erase Suspend #1
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
2
ADDR
CE#
AVD#
OE#
Note:
DQ2 polling during erase suspend behaves normally if CE# pulses low at or after valid Address, even if AVD# does not.
Document Number: 002-01825 Rev. *B
Page 65 of 79
S29WS256N
S29WS128N
Figure 11.23 Correct DQ2 Polling during Erase Suspend #2
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ADDR
CE#
AVD#
OE#
Note:
DQ2 polling during erase suspend behaves normally if AVD# pulses low at or after valid Address, even if CE# does not.
Figure 11.24 Correct DQ2 Polling during Erase Suspend #3
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
200ns
ig
n
0ns
ADDR
es
CE#
D
AVD#
ew
OE#
rN
Note:
DQ2 polling during erase suspend behaves normally if both AVD# and CE# pulse low at or after valid Address.
Erase
Erase Suspend
Read
om
m
en
WE#
Enter Erase
Suspend Program
d
Erase
Suspend
de
Enter
Embedded
Erasing
fo
Figure 11.25 DQ2 vs. DQ6
DQ6
DQ2
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
N
ot
R
ec
Note:
DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6
Document Number: 002-01825 Rev. *B
Page 66 of 79
S29WS256N
S29WS128N
Figure 11.26 Latency with Boundary Crossing when Frequency > 66 MHz
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
C126
7C
7D
7E
C127
C127
C128
C129
7F
7F
80
81
C130
C131
CLK
Address (hex)
AVD#
82
83
(stays high)
tRACC
tRACC
RDY(1)
ig
n
latency
tRACC
Data
D125
D126
D127
D128
D129
D130
OE#,
CE#
rN
ew
D124
D
latency
es
tRACC
RDY(2)
(stays low)
fo
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
d
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
de
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device not crossing a bank in the process of performing an erase or program.
N
ot
R
ec
om
m
en
5. RDY does not go low and no additional wait states are required for WS 5.
Document Number: 002-01825 Rev. *B
Page 67 of 79
S29WS256N
S29WS128N
Figure 11.27 Latency with Boundary Crossing into Program/Erase Bank
Address boundary occurs every 128 words, beginning at address
00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing.
C124
C125
C126
7C
7D
7E
C127
C127
7F
7F
CLK
Address (hex)
AVD#
(stays high)
tRACC
tRACC
ig
n
RDY(1)
latency
tRACC
es
tRACC
RDY(2)
Data
D125
D126
D127
Read Status
d
(stays low)
Notes:
1. RDY(1) active with data (D8 = 1 in the Configuration Register).
de
OE#,
CE#
fo
rN
D124
ew
D
latency
om
m
en
2. RDY(2) active one clock cycle before data (D8 = 0 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60.
4. Figure shows the device crossing a bank in the process of performing an erase or program.
5. RDY does not go low and no additional wait states are required for WS 5.
ec
Figure 11.28 Example of Wait States Insertion
D0
D1
ot
R
Data
Rising edge of next clock cycle
following last wait state triggers
next burst data
N
AVD#
total number of clock cycles
following addresses being latched
OE#
1
2
3
0
1
4
5
6
7
3
4
5
CLK
2
number of clock cycles
programmed
Wait State Configuration Register Setup:
D13, D12, D11 = “111” Reserved
D13, D12, D11 = “110” Reserved
D13, D12, D11 = “101” 5 programmed, 7 total
D13, D12, D11 = “100” 4 programmed, 6 total
D13, D12, D11 = “011” 3 programmed, 5 total
Document Number: 002-01825 Rev. *B
Page 68 of 79
S29WS256N
S29WS128N
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
n
Note:
Figure assumes address D0 is not at an address boundary, and wait state is set to “101”.
Document Number: 002-01825 Rev. *B
Page 69 of 79
S29WS256N
S29WS128N
Figure 11.29 Back-to-Back Read/Write Cycle Timings
Last Cycle in
Program or
Sector Erase
Command Sequence
Read status (at least two cycles) in same bank
and/or array data from other bank
tWrite Cycle
Begin another
write or program
command sequence
tWrite Cycle
tRead Cycle
tRead Cycle
CE#
OE#
tOE
tOEH
ig
n
tGHWL
WE#
Data
tWP
tDS
tOEZ
es
tACC
tOEH
tDH
PD/30h
PA/SA
RA
RA
555h
tAH
de
AVD#
d
fo
tAS
rN
tSR/W
Addresses
AAh
RD
ew
RD
D
tWPH
N
ot
R
ec
om
m
en
Note:
Breakpoints in waveforms indicate that system may alternately read array data from the “non-busy bank” while checking the status of the program or erase operation in the
“busy” bank. The system should read status twice to ensure valid information.
Document Number: 002-01825 Rev. *B
Page 70 of 79
S29WS256N
S29WS128N
Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
64 Kword
VCC
0.6
3.5
16 Kword
VCC
工商网监
湘ICP备2023018690号
