TLD11141EPXUMA1

TLD1114-1EP LITIX™ Basic+ Features • Single channel device with integrated and protected output stage (current source), optimized to drive LEDs as additional low cost current source • Easy direct control without external component from other LITIX Basic+ LED Drivers • High output current (up to 360 mA) • Possibility to off-load power consumption to allow maximum current driving capability via low cost external components (Power Shift) • Very low current consumption in sleep mode • Very low output leakage when channel is “off” • Low current consumption during fault • Output currents’ control via external low power resistor • Easy delivery of additional current/power demand via other LITIX™ Basic+ family members with direct drive • Reverse polarity protection allows reduction of external components and improves system performance at low battery/input voltages • Overload protection • Wide temperature range: -40°C < TJ < 150°C • Output current control via external low power resistor • Green product (RoHS compliant) Potential applications • Cost effective “stop”/ “tail” function implementation with shared and separated LEDs per function • Turn indicators • Position, fog, rear lights and side markers • Animated light functions like wiping indicators and “welcome/goodbye” functions • Day Running Light • Interior lighting functions like ambient lighting (including RGB color control), illumination and dash board lighting • LED indicators for industrial applications and instrumentation Product validation Qualified for Automotive Applications. Product Validation according to AEC-Q100/101. Datasheet www.infineon.com 1 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Description The LITIX™ Basic+ TLD1114-1EP is a single channel high-side driver IC with integrated output stage. It is designed to control LEDs with a current up to 360 mA. In typical automotive applications the device is capable of driving 3 red LEDs with a current up to 180 mA and even above, if not limited by the overall system thermal properties. Practically, the output current is controlled by an external resistor or reference source, independently from load and supply voltage changes. Table 1 Product summary Parameter Symbol Values Operating voltage VS(nom) 5.5 V … 40 V Maximum voltage VS(max) VOUT(max) 40 V Nominal output (load) current IOUT(nom) 180 mA (nominal) when using the automotive supply voltage range 8 V - 18 V. Currents up to IOUT(max) are possible with low thermal resistance RthJA Maximum output (load) current IOUT(max) 360 mA depending on RthJA Current accuracy at RSET = 10 kΩ KRT 900±3.33% Current consumption in sleep mode IS(sleep, typ) 0.1 µA Maximum current consumption during IS(fault, ERRN) fault 850 µA or less when fault is detected from another device (disabled via ERRN) Type Package Marking TLD1114-1EP PG-TSDSO-14 TLD1114 Datasheet 2 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Table of Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 2.1 2.2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.3 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 Internal supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics internal supply and EN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 5.1 5.2 5.2.1 5.2.2 5.3 5.3.1 5.3.2 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.5 5.6 Power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Programmable output current accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power shift feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power shift via external MOSFET control and power resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power shift components calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output configuration via IN_SET, OUT_SET and PWMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IN_SET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output current adjustment via RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output control via IN_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 IN_SET pin behavior during device overload management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 OUT_SET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Direct control of PWMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Electrical characteristics power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Electrical characteristics IN_SET, OUT_SET, PWR_SHS, PWM_SHG and PWMI pins for output settings 26 6 6.1 6.1.1 6.2 6.3 Overload diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error management via ERRN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ERRN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics: Overload management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Datasheet 3 7 7 8 9 28 28 28 29 30 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Block diagram 1 Block diagram 9 8 6 4 EN PWMI IN_SET Internal supply Thermal protection Current reference TLD1114-1EP Figure 1 Datasheet Output control & protection VS ERRN 14 PWR_SHG 10 PWR_SHS 11 OUTH 12 OUTL 13 CFG 5 OUT_SET 2 GND 7 Block diagram 4 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Pin configuration 2 Pin configuration 2.1 Pin assignment n.c. OUT_SET n.c. IN_SET CFG PWMI GND 1 2 3 4 5 6 7 EP ex posed pad (bott om) TLD1114-1EP 14 13 12 11 10 9 8 ERRN OUTL OUTH PWR_SHS PWR_SHG VS EN Figure 2 Pin configuration 2.2 Pin definitions and functions Pin Symbol Function 9 VS Supply voltage; Connected to battery or supply control switch, with EMC filter 7 GND Ground; Signal ground 4 IN_SET Control input for OUT channel; Connect to a low power resistor to adjust OUT output current. Alternatively, a different current reference (i.e. the OUT_SET of another LITIX™ Basic+ LED Driver) may be connected 2 OUT_SET Control output for additional current source; If an additional channel or output current with same input control is needed, connect this pin to the IN_SET pin of the additional LED driver. If not used, leave the pin open 5 CFG Configuration input for OUT current accuracy; If higher current accuracy is required to drive the target load, leave this pin open, else connect it to GND (see Chapter 5 for further details) 6 PWMI PWM input; Connect to an external PWM controller. If not used, connect to GND 14 ERRN ERROR flag I/O; Open drain, active low. Connect to a pull-up resistor 8 EN Output enable control input; Connect to a control input or VS via a resistor divider or Zener diode 12 OUTH Channel output; Connect to the target load when low VPS drop at higher output current is required, otherwise leave the pin open 13 OUTL Channel output; Connect to the target load when high resolution at lower output current is required, otherwise leave the pin open Datasheet 5 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Pin configuration Pin Symbol Function 11 PWR_SHS Power shift source control output; Connect to a power resistor or to the source of an external NMOS to allow power shift control. If not used, leave the pin open 10 PWR_SHG Power shift gate control output; Connect to the gate of an external NMOS to allow power shift control. If not used, leave the pin open 1, 3 n.c. Not connected; Leave these pins open Exposed Pad EP Exposed Pad; Connected to GND-pin in application Datasheet 6 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ General product characteristics 3 General product characteristics 3.1 Absolute maximum ratings Table 2 Absolute maximum ratings1) TJ = -40°C to +150°C; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Voltage Supply voltage VS -18 – 40 V – P_4.1.1 EN voltage VEN -18 – 40 V – P_4.1.3 -40 – 18 V – P_4.1.4 EN voltage related to VOUT: VEN - VEN(VOUT) -18 VOUT – 40 V – P_4.1.5 EN voltage related to VS: VEN - VS VEN(VS) PWR_SHG voltage VPWR_SHG -1 – 40 V – P_4.1.6 PWR_SHS voltage related to VOUTH: VPWR_SHIFTS - VOUTH VPWR_SHS( -0.4 – 0.4 V – P_4.1.7 – 0.8 V – P_4.1.46 – 40 V – P_4.1.8 – 6 V – P_4.1.9 -1 – 40 V – P_4.1.10 Output voltage related to VS: VS - VOUT(VS) VOUT -18 – 40 V – P_4.1.11 IN_SET voltage VIN_SET -0.3 – 6 V – P_4.1.12 OUT_SET voltage VOUT_SET -0.3 – 6 V – P_4.1.13 CFG voltage VCFG -0.3 – 6 V – P_4.1.20 PWMI voltage VPWMI -0.3 – 6 V – P_4.1.14 ERRN voltage VERRN -0.3 – 40 V – P_4.1.18 Output current IOUTH 0 – 370 mA – P_4.1.22 Output current IOUTL 0 – 200 mA – P_4.1.41 PWMI current IPWMI -0.5 – 0.5 mA – P_4.1.26 IN_SET current IIN_SET 0 – 800 µA – P_4.1.48 OUT_SET current IOUT_SET 0 – 0.5 mA – P_4.1.32 TJ -40 – 150 °C – P_4.1.33 OUTH) VPWR_SHG( -0.8 PWR_SHS voltage related to VOUTL: VPWR_SHIFTS - VOUTL OUTL) PWR_SHS voltage VPWR_SHIF -1 TS VPWR_SHIF -0.3 PWR_SHG voltage related to PWR_SHS: VPWR_SHIFTG - VPWR_SHS T(GS) Output voltage VOUTL/H Current Temperature Junction temperature Datasheet 7 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ General product characteristics Table 2 Absolute maximum ratings1) (cont’d) TJ = -40°C to +150°C; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Tstg -55 – 150 °C – P_4.1.34 ESD susceptibility all pins to GND VESD -2 – 2 kV HBM2) P_4.1.36 ESD susceptibility all pins to GND VESD -500 – 500 V CDM3) P_4.1.37 ESD susceptibility Pin 1, 7, 8, 14 VESD1,7,8,1 -750 (corner pins) to GND 4 – 750 V CDM3) P_4.1.38 Storage temperature ESD susceptibility 1) Not subject to production test, specified by design 2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF) 3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101 Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. 3.2 Functional range Table 3 Functional range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. 5.5 – 18 V – P_4.2.1 Extended supply voltage for VS(ext) functional range VSUV(ON) – 40 V – P_4.2.2 Junction temperature -40 150 °C – P_4.2.4 Voltage range for normal operation Note: Datasheet VS(nom) TJ – Within the Normal Operation range, the IC operates as described in the circuit description. Within the Extended Operation range, parameters deviations are possible. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 8 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ General product characteristics 3.3 Thermal resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 4 Thermal resistance1) Parameter Junction to Case Symbol RthJC Junction to Ambient 1s0p board RthJA1 Junction to Ambient 2s2p board RthJA2 Values Min. Typ. Max. – – 10 – – 61 56 Unit Note or Test Condition Number K/W 1)2) P_4.3.1 K/W 1)3) P_4.3.3 – – TA = 85°C TA = 135°C K/W – – 45 43 – – 1)4) P_4.3.4 TA = 85°C TA = 135°C 1) Not subject to production test, specified by design 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and exposed pad are fixed to ambient temperature). TA = 85°C. Total power dissipation = 1.5 W 3) Specified RthJA value is according to Jedec JESD51-3 at natural convection on FR4 1s0p board. The product (chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 70 µm Cu, 300 mm2 cooling area. Total power dissipation 1.5 W distributed statically and homogenously over all power stages 4) Specified RthJA value is according to Jedec JESD51-5,-7 at natural convection on FR4 2s2p board; The product (chip+package) was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. Total power dissipation 1.5 W distributed statically and homogenously over all power stages Datasheet 9 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Internal supply 4 Internal supply This chapter describes the internal supply in its main parameters and functionality. 4.1 Description The internal supply principle is highlighted in the concept diagram of Figure 3. If the voltage applied at the EN pin is below VEN(th) the device enters sleep mode. In this state all internal functions are switched off and the current consumption is reduced to IS(sleep) . As soon as the voltage applied at the supply pin VS is above VSUV(ON) and the voltage applied at the EN pin is above VEN(th), after the power-on reset time tPOR, the device is ready to deliver output current from the output stage. The power on reset time tPOR has to be taken into account also in relevant application conditions, i. e. with PWM control from VS or EN lines. VSUV - VS + Internal Supply VEN(th) OUTx Control EN Figure 3 + Internal supply Furthermore, as soon as the voltage applied at the supply pin VS is above VSUV(ON) and the voltage applied to the EN pin VEN is above VEN(th), the device is ready to detect and report overtemperature condition via ERRN (error network pin) as described in Chapter 6. To program output enable via EN pin there are several possibilities, like a resistor divider from VS to GND, a Zener diode from EN to VS and also a logic control pin (e.g. from a microcontroller output). Datasheet 10 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Internal supply 4.2 Table 5 Electrical characteristics internal supply and EN pin Electrical characteristics: Internal supply and EN pin TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Current consumption, sleep IS(sleep) mode – 0.1 2 µA 1) VEN = 0 V TJ < 85°C VS = 18 V VOUT = 3.6 V P_5.2.1 Current consumption, active IS(active) mode (no fault) – 1.5 3 mA VEN = 5.5 V IIN_SET = 0 µA TJ < 105°C VS = 18 V VOUT = 3.6 V P_5.2.3 Current consumption during IS(fault, ERRN) fault condition triggered from another device sharing ERRN bus – – 850 µA VEN = 5.5 V TJ < 105°C VS = 18 V VERRN = 0 V VOUT = 3.6 V P_5.2.4 Required supply voltage for VSUV(ON) output activation – – 5.5 V VEN = VS P_5.2.5 VOUT = 3 V RIN_SET = 6.8 kΩ IOUT > 50% IOUT(nom) Required supply voltage for VSUV(OFF) output deactivation 4.5 – – V VEN = VS P_5.2.6 VOUT = 3 V RIN_SET = 6.8 kΩ IOUT < 50% IOUT(nom) VSUV(hys) Supply voltage activation hysteresis: VSUV(ON) - VSUV(OFF) – 200 – mV 1) EN output enable threshold VEN(th) 1.4 1.65 1.8 V VS = 5.5 V P_5.2.9 VPS = 2 V RIN_SET = 6.8 kΩ IOUT = 50% IOUT(nom) EN pull-down current IEN(PD) – – 15 µA 1) VS > 8 V VEN = 2.8 V P_5.2.17 EN pull-down current IEN(PD) – – 35 µA 1) VS > 8 V VEN = 5.5 V P_5.2.14 EN pull-down current IEN(PD) – – 150 µA 1) P_5.2.15 Supply thresholds Datasheet 11 VEN > VEN(th) VS > 8 V VEN = VS P_5.2.8 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Internal supply Table 5 Electrical characteristics: Internal supply and EN pin (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. – – 25 Unit Note or Test Condition µs 1) Number Timing Power on reset delay time tPOR VS rising from 0 V P_5.2.13 to 13.5 V VOUT = 3.6 V RIN_SET = 6.8 kΩ IOUT = 80% IOUT(nom) 1) Not subjected to production test: specified by design Datasheet 12 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage 5 Power stage The output stage is realized as high-side current source with an output current up to 360mA. During off state the leakage current at the output stage is minimized in order to prevent a slightly glowing LED. The maximum output current is limited by the power dissipation and used PCB cooling areas. For an operating output current control loop, the supply and output voltage have to be considered according to the following parameters: • Required supply voltage for current control VS(CC) • Voltage drop over through the output stage during current control VPS(CC) • Required output voltage for current control VOUT(CC) 5.1 Programmable output current accuracy In many rear light functions, a significant cost reduction is achieved increasing the number of LEDs per OUT (typically in series of three): this system implementation implies the need for low output voltage drop at low battery operative range, together with very high output current accuracy. As high output current accuracy needs an internal shunt voltage drop measurement in series to the output stage (the highest drop on the internal implies the highest accuracy), these two system requirements often result in a trade-off where, within a certain maximum output voltage drop, only a reduced range of output current can achieve the desired accuracy. To provide high accuracy at low output currents and low output voltage drop (VPSH/L) at high currents, the TLD1114-1EP offers the capability to select alternative output accuracy settings via the CFG output configuration pin. In this way, choosing the proper connection of the output load between OUTH and OUTL, the highest current accuracy with low drop VPSH/L can be achieved. When CFG is connected to GND, the device provides low VPSH drop and high accuracy for the highest current ranges, provided that OUTH pin is used as output. When CFG pin is left open and the load is connected to OUTL pin, the highest current accuracy is also provided in the lowest current range. Table 6 shows the configuration options to achieve the best system targets. Further implementation details are shown in Chapter 7. Table 6 Output current accuracy configuration overview1) CFG OUTL OUTH Output current accuracy Output voltage drop Connected to GND Open Connected to load 4% or better for 160 mA < IOUTH(typ) < 360 mA2) VPSH < 650 mV for 360 mA > IOUTH > 88% IOUTH(typ)3) Open Connected to load Open 4% or better for 30 mA < IOUTL(typ) < 180 mA2) VPSL < 650 mV for 180 mA > IOUTL > 88% IOUTL(typ)3) 1) The table shows the recommended application configuration. For detailed test conditions refer to electrical characteristics (Table 7) 2) TJ = 25°C, refer to parameters P_6.5.3 and P_6.5.8 3) TJ = -40°C, refer to parameters P_6.5.49 and P_6.5.50 Datasheet 13 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage VS Supply Protection 9 8 6 EN PWMI VS ERRN Internal supply Thermal protection PWR_SHG Output control & protection PWR_SHS OUTH OUTL IN_SET RSET 4 CFG Current reference TLD1114-1EP OUT_SET 14 10 11 12 13 5 2 GND 7 Configuration example with low VPS drop at high current accuracy (CFG connected to GND) Figure 4 VS Supply Protection 9 8 6 EN PWMI ERRN Internal supply Thermal protection VS PWR_SHG Output control & protection PWR_SHS OUTH OUTL RSET 4 IN_SET Current reference TLD1114-1EP Figure 5 5.2 CFG OUT_SET 14 10 11 12 13 5 2 GND 7 Configuration example with high accuracy at low current range (CFG open) Power shift feature Furthermore, the device provides the possibility of managing high power dissipation (higher than allowed by the thermal impedance RthJA of the application) by controlling the current flow on a few external, low cost, discrete components. Datasheet 14 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage 5.2.1 Power shift via external MOSFET control and power resistors The control of power dissipation can be done via usage of PWR_SHG and PWR_SHS control pins: when VPS output voltage drop exceeds the activation voltage threshold of an external switch, the voltage between PWR_SHG and PWR_SHS allows to turn it on (usually a low power external NMOS) and, in conjunction with the usage of limiting power resistors, routes most of the configured output current (in a percentage depending on external components values) outside the TLD1114-1EP. Figure 6 shows an embodiment example of the power shift feature. VS Supply Protection 9 8 6 EN PWMI ERRN Internal supply Thermal protection VS PWR_SHG Output control & protection PWR_SHS OUTH OUTL RSET 4 IN_SET CFG Current reference OUT_SET 14 10 11 12 13 5 2 GND TLD1114-1EP 7 IOUT IOUT = IOUTS + IPS k*IIN_SET IPS IOUTS VS VFLED(IOUT) Figure 6 5.2.2 VFLED(IOUT) + VGS(th) External MOSFET control concept Power shift components calculation Referring to the diagram example of Figure 6, in order to properly dimension the resistors values, the following parameters have to be considered: • Minimum current IOUT(int, min) intended to flow through the TLD1114-1EP output stage at maximum operative supply voltage VS(OP,max) • Maximum current from power shift path IOUT(int, max) (e.g. through external NMOS and dissipation resistors) at maximum overvoltage battery stress VS(OV,max) in the application Datasheet 15 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage • External NMOS voltage threshold VGS • Forward voltage VF(LED) of the output LED load and forward voltage VF(D) of the reverse polarity diode D (when used). For a safe drive of the external NMOS switch, when the OUT voltage drop VPS reaches a voltage greater than VGS(CL), the PWR_SHG voltage is automatically limited (see P_6.6.16). 5.3 Protection The device provides embedded protective functions, which are designed to prevent IC damage under fault conditions described in this datasheet. Fault conditions are considered as “outside” normal operating range. Protective functions are not designed for continuous nor for repetitive operations. 5.3.1 Thermal protection A thermal protection circuitry is integrated in the device. It is realized by a temperature monitoring of the output stages. As soon as the junction temperature exceeds the overtemperature threshold TJSD the output current is disabled and the IN_SET pin goes in a weak pull-down state with a current consumption IIN_SET(fault). If the junction temperature cools down below TJSD - TJ(hys), the IN_SET pin rise again to VIN_SET(ref) (within an additional time tIN_SET(del)) and consequently, the output current rise again (see Chapter 6 for a detailed description of fault management). Tj TjS D TjS D(hys ) t Over temperature disappear Over temperature occurs Figure 7 Overtemperature shut down auto-restart thresholds As long as the device remains into overtemperature condition, ERRN pin remains low. 5.3.2 Reverse battery protection The device has an integrated reverse battery protection feature. This feature protects the driver IC itself and, potentially, also connected LEDs. The output reverse current is limited to IOUT(REV) by the reverse battery protection. Datasheet 16 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage 5.4 Output configuration via IN_SET, OUT_SET and PWMI pins Outputs current can be defined via IN_SET and OUT_SET (to drive additional devices without further external components) pin. 5.4.1 IN_SET pin The IN_SET pin is a multiple function pin for the output current definition and input control. Output current definition and analog dimming control can be done defining accordingly the IN_SET current. ref/fault selection logic IN_SET IIN_SET VIN_SET(ref) IIN_SET(faul t) GND Figure 8 5.4.2 IN_SET pin block diagram Output current adjustment via RSET The output current for the channel can be defined connecting a low power resistor (RSET) between the IN_SET pin and GND. The dimensioning of the resistor can be done using the formula: (5.1) I OUT = k ⋅ I IN _ SET = k ⋅ VIN _ SET ( ref ) / RSET The gain factor k (defined as the ratio IOUT/IIN_SET) is graphically described in Figure 9. The current through the RSET is defined by the resistor itself and the reference voltage VIN_SET(ref), which is applied to the IN_SET pin when the device is supplied and the channel enabled. 5.4.3 Output control via IN_SET The IN_SET pin can be connected via RSET to the open-drain output of a microcontroller or to an external NMOS transistor as described in Figure 11. This signal can be used to turn off the relative output stages of the IC. A minimum IN_SET current of IIN_SET(ACT) is required to turn on the output stages. This feature is implemented to prevent glowing of LEDs caused by leakage currents on the IN_SET pin, see again Figure 9 for details. Datasheet 17 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage IOUT [mA] k = IOUT / IIN_SET IOUT IIN_SET(ACT) Figure 9 IIN_SET IIN_SET [µA] IOUT vs IIN_SET k/k(typ) OUTL 105% 100% 95% 33 66 k/k(typ) 100 122 200 IIN_SET [μA] 400 IIN_SET2 [μA] OUTH 105% 100% 95% 122 133 Figure 10 Datasheet 178 200 Typical output current accuracy IOUT / IIN_SET at TJ = 25°C 18 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage VS Supply Protection Microcontroller OUT RSET EN VS LITIX™ Basic+ (*) IN_SET OUT PWMI GND (*) The drawing refers to a generic LITIX™ BASIC+ device, and does not represent a specific device pinout (only the relevant connections for microcontroller IN_SET control are shown) Figure 11 5.4.4 Output control via IN_SET pin and open-drain microcontroller out (simplified diagram) IN_SET pin behavior during device overload management If a fault condition arises on the channel controlled by the IN_SET pin, the IN_SET pin is reduced to IIN_SET(fault), in order to minimise the current consumption of the whole device under fault condition. 5.4.5 OUT_SET pin The OUT_SET pin, mirroring the IN_SET current defined by the external resistor RSET, can be used to define the IN_SET current of an additional companion device. If minimum IN_SET activation current IIN_SET(act) is not reached the OUT_SET current is reduced to IOUT_SET(OFF). This allows to drive other devices via OUT_SET, even when digital dimming is required, without external components (see application drawing example in Chapter 7). Datasheet 19 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage LOGIC OUT_SET IOUT_SET IOUT_SET(OFF) IOUT_SET(ON) GND Figure 12 OUT_SET pin block diagram LITIX™ Basic+ (*) RSET IN_SET OUT_SET OUT PWMI GND LITIX™ Basic+ (*) IN_SET OUT_SET OUT PWMI GND EN VS EN VS EN Supply Protection VS VS LITIX™ Basic+ (*) IN_SET OUT_SET OUT PWMI GND (*) The drawing refers to a generic LITIX™ BASIC+ device, and does not represent a specific device pinout (only the relevant connections are shown) Figure 13 5.4.6 IN_SET to OUT_SET serial connection example Direct control of PWMI PWMI input can be controlled by the PWMO output of another device of LITIX™ Basic+ family or, alternatively, a push-pull output stage of a microcontroller: the host device decides the digital dimming characteristics by applying the proper control cycle in order to set the “on”/“off” timing, according to the chosen dimming function. 5.4.7 Timing diagrams In the following diagram (Figure 14, Figure 16) the influences of inputs on output activation delays are shown. Datasheet 20 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage I IN_SET IOUT tON(IN_SET ) t tOFF(IN_SET ) 100% 90% 10% t Figure 14 IN_SET turn on and turn off delay timing diagram IIN _SET I OUT_SET tdel ( OUT _SET ,H) tdel( OUT _SET ,L) t 100% 90% 10% t Figure 15 IN_SET to OUT_SET activation and deactivation delay timing diagram V PWMI IOUT tOFF (PWMI ) tON(PWMI ) t 100% 90% 10% t Figure 16 Datasheet PWMI turn on and turn off timing diagram 21 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage 5.5 Table 7 Electrical characteristics power stage Electrical characteristics: Power stage and CGF pin TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Output leakage current IOUT(leak) – – 9 µA 1) VEN = 5.5 V IIN_SET = 0 µA VOUT = 2.5 V TJ = 85°C P_6.5.51 Output leakage current IOUT(leak) – – 21 µA 1) VEN = 5.5 V IIN_SET = 0 µA VOUT = 2.5 V TJ = 150°C P_6.5.60 Reverse output current IOUT(rev) – – 3 µA 1) VEN = Vs VS = -18 V Output load: LED with break down voltage < - 0.6 V P_6.5.2 Output current accuracy IOUTL/IIN_SET KRT 870 900 930 – 1) TJ = 25°C VS = 12.8 V VPSL = 2 V CFG open OUTH open IIN_SET = 66 µA P_6.5.3 Output current accuracy IOUTL/IIN_SET KLT 846 900 954 – 1) TJ = 25... 150°C VS = 8... 18 V VPSL = 2 V CFG open OUTH open IIN_SET = 66 µA P_6.5.4 Output current accuracy IOUTL/IIN_SET KALL 837 900 963 – 1) TJ = -40... 150°C VS = 8... 18 V VPSL = 2 V CFG open OUTH open IIN_SET = 66 µA P_6.5.5 Output current accuracy IOUTL/IIN_SET KLT 855 900 945 – 1) P_6.5.6 Output current accuracy Datasheet 22 TJ = 25... 150°C VS = 8... 18 V VPSL = 2 V CFG open OUTH open IIN_SET = 100 ... 200 µA Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage Table 7 Electrical characteristics: Power stage and CGF pin (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Output current accuracy IOUTL/IIN_SET KALL 842 900 958 – 1) TJ = -40... 150°C VS = 8... 18 V VPSL = 2 V CFG open OUTH open IIN_SET = 100... 200 µA P_6.5.7 Output current accuracy IOUTH/IIN_SET KRT 861 890 919 – 1) TJ = 25°C VS = 12.8 V VPSH = 2 V VCFG = 0 V OUTL open IIN_SET = 133 µA P_6.5.8 Output current accuracy IOUTH/IIN_SET KLT 837 890 943 – 1) TJ = 25... 150°C VS = 8... 18 V VPSH = 2 V VCFG = 0 V OUTL open IIN_SET = 133 µA P_6.5.9 Output current accuracy IOUTH/IIN_SET KALL 828 890 952 – 1) TJ = -40... 150°C VS = 8... 18 V VPS = 2 V VCFG = 0 V OUTL open IIN_SET = 133 µA P_6.5.10 Output current accuracy IOUTH/IIN_SET KLT 855 890 925 – 1) TJ = 25... 150°C VS = 8... 18 V VPSH = 2 V VCFG = 0 V OUTL open IIN_SET = 200... 400 µA P_6.5.11 Output current accuracy IOUTH/IIN_SET KALL 846 890 934 – 1) TJ = -40... 150°C VS = 8... 18 V VPSH = 2 V VCFG = 0 V OUTL open IIN_SET = 200... 400 µA P_6.5.12 Required voltage drop during current control VPS(CC) = VS - VOUT VPS(CC) 1.0 – – V 2) P_6.5.36 Datasheet 23 VS = 8... 18 V IOUT > 90% of K(typ)*IIN_SET Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage Table 7 Electrical characteristics: Power stage and CGF pin (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Required voltage drop during high current control VPSH(CC) = VS - VOUTH VPSH(CC) 0.65 – – V VS = 8... 18 V VCFG = 0 V OUTL open IIN_SET = 400 µA IOUTH > 90% of K(typ)*IIN_SET TJ = -40°C P_6.5.49 Required voltage drop during high current control VPSH(CC) = VS - VOUTH VPSH(CC) 0.75 – – V VS = 8... 18 V VCFG = 0 V OUTL open IIN_SET = 400 µA IOUTH > 90% of K(typ)*IIN_SET TJ = 25°C P_6.5.61 Required voltage drop during high current control VPSH(CC) = VS - VOUTH VPSH(CC) 0.85 – – V VS = 8... 18 V VCFG = 0 V OUTL open IIN_SET = 400 µA IOUTH > 90% of K(typ)*IIN_SET TJ = 150°C P_6.5.62 Required voltage drop during low current control VPSL(CC) = VS - VOUTL VPSL(CC) 0.65 – – V VS = 8... 18 V CFG open OUTH open IIN_SET = 200 µA IOUTL > 90% of K(typ)*IIN_SET TJ = -40°C P_6.5.50 Required voltage drop during low current control VPSL(CC) = VS - VOUTL VPSL(CC) 0.75 – – V VS = 8... 18 V CFG open OUTH open IIN_SET = 200 µA IOUTL > 90% of K(typ)*IIN_SET TJ = 25°C P_6.5.63 Required voltage drop during low current control VPSL(CC) = VS - VOUTL VPSL(CC) 0.85 – – V VS = 8... 18 V CFG open OUTH open IIN_SET = 200 µA IOUTL > 90% of K(typ)*IIN_SET TJ = 150°C P_6.5.64 Datasheet 24 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage Table 7 Electrical characteristics: Power stage and CGF pin (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Required supply voltage for VS(CC) current control 5.5 – – V VEN = 5.5 V VOUT = 3 V RIN_SET = 6.8 kΩ IOUT > 90% of K*IIN_SET P_6.5.40 Required output voltage for VOUT(CC) current control 1.4 – – V VS = 8... 18 V IOUT > 90% of K*IIN_SET P_6.5.41 CFG required voltage for low VCFG(L) drop at high current – – 1.35 V VS = 8 V to 18 V VEN = 5.5 V P_6.5.46 CFG required voltage for VCFG(H) high accuracy at low output current range 2 – – V VS = 8 V to 18 V VEN = 5.5 V P_6.5.47 CFG pull-up current 20 35 50 µA VS = 8 V to 18 V VEN = 5.5 V P_6.5.48 Overtemperature shutdown TJSD threshold 150 175 190 °C 1) P_6.5.42 Overtemperature hysteresis TJ(hys) – 10 – °C 1) P_6.5.43 ICFG(PU) 1) Not subjected to production test: specified by design 2) In these test conditions, the parameter K(typ) represents the typical value of output current accuracy. Datasheet 25 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage 5.6 Table 8 Electrical characteristics IN_SET, OUT_SET, PWR_SHS, PWM_SHG and PWMI pins for output settings Electrical characteristics: IN_SET, OUT_SET, PWR_SHS, PWM_SHG and PWMI pins TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number IN_SET reference voltage VIN_SET(ref) 1.195 1.22 1.245 V 1) VEN = 5.5 V TJ = 25°C P_6.6.1 IN_SET reference voltage VIN_SET(ref) 1.184 1.22 1.256 V 1) VEN = 5.5 V P_6.6.17 IN_SET output activation current IIN_SET(ACT) – – 15 µA VEN = 5.5 V VPS = 3 V IOUT > 50% of K(typ)*IIN_SET P_6.6.2 OUT_SET output current matching ∆IOUT_SET(ON)/II -4 – 4 % P_6.6.3 N_SET VS = 8 V to 18 V VOUT_SET = 1.2V IIN_SET = 267 µA PWR_SHG pull up current IPWR_SHG(PU) 100 180 260 µA VS = 8 V to 18 V VEN = 5.5 V VPWMI = 1.5 V VPS = 3 V VPWR_SHG - VPWR_SHS =2V P_6.6.14 PWR_SHG pull-down current IPWR_SHG(PD) 1.5 2.1 3 mA VS = 8 V to 18 V VEN = 5.5 V VPWMI = 3 V VPS = 3 V VPWR_SHG - VPWR_SHS = 0.8 V P_6.6.15 PWR_SHG clamping voltage VGS(PWR_SH) VPWR_SHG - VPWR_SHS 4.5 – 6 V VS = 12 V to 18 V VEN = 5.5 V VPSL/H > 7 V P_6.6.16 PWMI low threshold VPWMI(L) 1.5 1.7 2 V VS = 8 V to 18 V VEN = 5.5 V P_6.6.6 PWMI high threshold VPWMI(H) 2.5 2.7 3 V VS = 8 V to 18 V VEN = 5.5 V P_6.6.7 tON(IN_SET) – – 20 µs 1)2) Timing IN_SET turn on time Datasheet 26 VS = 13.5 V P_6.6.8 VPS = 4 V IIN_SET rising from 0 to 180 µA IOUT = 90% of K*IIN_SET Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Power stage Table 8 Electrical characteristics: IN_SET, OUT_SET, PWR_SHS, PWM_SHG and PWMI pins (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number 1)2) P_6.6.9 IN_SET turn off time tOFF(IN_SET) – – 10 µs VS = 13.5 V VPS = 4 V IIN_SET falling from 180 to 0 µA IOUT = 10% of K*IIN_SET OUT_SET activation time tdel(OUT_SET,H) – – 5 µs 1)3) VS = 13.5 V P_6.6.10 IIN_SET rising from 0 to 180 µA IOUT_SET = 90% of IIN_SET OUT_SET deactivation time tdel(OUT_SET,L) – – 5 µs 1)3) VS = 13.5 V IIN_SET falling from 180 to 0 µA IOUT_SET = 10% of IIN_SET P_6.6.11 PWMI turn on time tON(PWMI) – – 15 µs 1)4) VS = 8 V to 18 V VEN = 5.5 V VPWMI falling from 5 V to 0 V IOUT = 90% of K*IIN_SET P_6.6.12 PWMI turn off time tOFF(PWMI) – – 10 µs 1)4) P_6.6.13 1) 2) 3) 4) VS = 8 V to 18 V VEN = 5.5 V VPWMI = 0 rising from 0 V to 5 V IOUT = 10% of K*IIN_SET Not subjected to production test: specified by design Refer to Figure 14 Refer to Figure 15 Refer to Figure 16 Datasheet 27 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Overload diagnosis 6 Overload diagnosis 6.1 Error management via ERRN 6.1.1 ERRN pin ERRN + fault Output control no fault VERR N(th) IERR N(faul t) Figure 17 ERRN pin (block diagram) The device is able to report an overtemperature failure in its driven load and react to a fault detected by another LED driver in the system if a shared error network is implemented (i. e. driving LED chains of the same light function). This is possible with the usage of an external pull-up resistor, allowing multiple devices to share the open drain diagnosis output pin ERRN. All devices sharing the common error network are capable to detect the fault from any of the channels driven by the LITIX™ Basic+ LED drivers and, if desired, to switch multiple loads off. Datasheet 28 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Overload diagnosis ERRN OUT LITIX™ Basic+ (*) IN_SET RSET RSET IN_SET PWMI GND ERRN Connection to further devices LITIX™ Basic+ (*) EN EN VS Supply Protection VS RERRN VS PWMI GND OUT (*) The drawing refers to a generic LITIX™ BASIC+ device, and does not represent a specific device pinout (only the relevant connections are shown) Figure 18 Shared error network principle between LITIX™ Basic+ family devices When the channel is detected to be under fault conditions (for, at least, a filter time tfault), the open-drain ERRN pin sinks a pull-down current IERRN(fault) toward GND. Therefore an active low state can be detected at ERRN pin when VERRN < VERRN(fault) and if this condition is reached, the channel is switched off. Similarly, when the fault is removed, ERRN pin is put back in high impedance state, and the channels reactivation procedure can be completed as illustrated in the timing diagrams in this chapter. 6.2 Fault management Under overtemperature condition the ERRN pin starts sinking a current, IERRN(PD) to ground and the voltage level on this pin will drop below VERRN(fault) if the external pull-up resistor is properly dimensioned. The ERRN low voltage can also be used as input signal for a µC to perform the desired diagnosis policy. The IN_SET pin goes in a weak pull-down state with a current consumption IN_SET(fault) after an additional latency time tIN_SET(del). The fault status is not latched: as soon as the overtemperature condition is no longer present (at least for a filter time tfault), ERRN goes back to high impedance and, when its voltage is above VERRN(fault), the IN_SET voltage goes up to VSET(ref), again after a time tIN_SET(del). Finally the output stage will be activated again after a time tERR(reset), which takes into account also the additional latency which depends on the external ERRN circuitry. An example of error diagnosis conditions is shown in the timing diagram of Figure 19. Datasheet 29 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Overload diagnosis VIN _SE T V IN_SE T(re f) tIN _SE T(del) tIN _SE T(del) t VERRN V ER RN (fa u l t) T J SD (H YST ) Tj t tfault tfault T J SD T J SD - T J SD (H YST ) t over temp. occurs Figure 19 6.3 Table 9 over temp. disappear Overtemperature condition timing diagram example Electrical characteristics: Overload management Electrical Characteristics: Fault management TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number IN_SET fault current IIN_SET(fault) – – 10 µA 1) VS > 8 V VOUT = 3.6 V VERRN = 0 V VIN_SET = 1 V VEN > VEN(th,max) P_7.5.1 ERRN fault current IERRN(fault) 2 – – mA 1) P_7.5.2 Datasheet 30 VS > 8 V VERRN = 0.8 V Overtemperature condition VEN > VEN(th,max) Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Overload diagnosis Table 9 Electrical Characteristics: Fault management (cont’d) TJ = -40°C to +150°C; VS =5.5 V to 18 V; RIN_SET = 10 kΩ; all voltages with respect to GND, positive current flowing into input and I/O pins, positive current flowing out from output pins (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number P_7.5.3 Min. Typ. Max. VERRN(th) 0.8 – 2.0 V 1) Fault deactivation delay tfault 40 – 150 µs 1) VS > 8 V VOUT falling from 5 V to 0 V or overtemperature condition VEN > VEN(th, max) P_7.5.19 Fault appearance/removal to IN_SET deactivation/activation delay tIN_SET(del) – – 10 µs 1) P_7.5.4 ERRN input threshold VS > 8 V Timing 2) VS > 8 V ERRN falling from 5 V to 0 V VEN > VEN(th, max) 1) Not subjected to production test: specified by design. 2) ERRN status only changed during overtemperature condition Datasheet 31 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Application information 7 Application information Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. ERRN EN TLD1114-1EP IN_SET OUT_SET IN_SET OUT_SET CFG PWMI GND PWR_SHG CFG PWMI GND PWR_SHG PWR_SHS OUTH OUTL PWR_SHS OUTH COUT* OUTL RSET RSET TLD1114-1EP VS CVS* ERRN EN VS CVS* Supply Protection REN2 REN1 RERRN VS * For EMI improvement, if required (e.g. 4,7 or 10nF) Figure 20 Application diagram example Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Datasheet 32 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Package outline &  & [ 6($7,1* &23/$1$5,7< 3/$1( s s  ' [   $% & [ %27720 9,(: $ ,1'(; 0$5.,1*         %  s s s   [ *$8*( 3/$1(  [  s ' rr  0$;  s  s 67$1'2)) Package outline  8   ' $%  '2(6 127 ,1&/8'( 3/$67,& 25 0(7$/ 3527586,21 2)  0$; 3(5 6,'(  '$0%$5 352786,21 6+$// %( 0$;,080 00 727$/ ,1 (;&(66 2) /($' :,'7+ $// ',0(16,216 $5( ,1 81,76 00 7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62  352-(&7,21 0(7+2'  > @ Figure 21 PG-TSDSO-14 Green product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). Further information on packages https://www.infineon.com/packages Datasheet 33 Rev. 1.20 2021-06-15 TLD1114-1EP LITIX™ Basic+ Revision History 9 Revision History Revision Date Changes 1.20 2021-06-15 Updated P_5.2.17, P_5.2.14, P_5.2.15 1.10 2019-09-26 Corrected copper dimensions in footnote4) in Table 4 1.00 2018-10-09 Initial datasheet created Datasheet 34 Rev. 1.20 2021-06-15 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2021-06-15 Published by Infineon Technologies AG 81726 Munich, Germany © 2021 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? Email: erratum@infineon.com Document reference LITIX™ Basic+ TLD1114-1EP IMPORTANT NOTICE The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.